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9e263131 SB |
1 | /* |
2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/bug.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/export.h> | |
20 | #include <linux/clk-provider.h> | |
21 | #include <linux/regmap.h> | |
22 | ||
23 | #include <asm/div64.h> | |
24 | ||
25 | #include "clk-pll.h" | |
26 | ||
27 | #define PLL_OUTCTRL BIT(0) | |
28 | #define PLL_BYPASSNL BIT(1) | |
29 | #define PLL_RESET_N BIT(2) | |
30 | #define PLL_LOCK_COUNT_SHIFT 8 | |
31 | #define PLL_LOCK_COUNT_MASK 0x3f | |
32 | #define PLL_BIAS_COUNT_SHIFT 14 | |
33 | #define PLL_BIAS_COUNT_MASK 0x3f | |
34 | #define PLL_VOTE_FSM_ENA BIT(20) | |
35 | #define PLL_VOTE_FSM_RESET BIT(21) | |
36 | ||
37 | static int clk_pll_enable(struct clk_hw *hw) | |
38 | { | |
39 | struct clk_pll *pll = to_clk_pll(hw); | |
40 | int ret; | |
41 | u32 mask, val; | |
42 | ||
43 | mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; | |
44 | ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); | |
45 | if (ret) | |
46 | return ret; | |
47 | ||
48 | /* Skip if already enabled or in FSM mode */ | |
49 | if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA) | |
50 | return 0; | |
51 | ||
52 | /* Disable PLL bypass mode. */ | |
53 | ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, | |
54 | PLL_BYPASSNL); | |
55 | if (ret) | |
56 | return ret; | |
57 | ||
58 | /* | |
59 | * H/W requires a 5us delay between disabling the bypass and | |
60 | * de-asserting the reset. Delay 10us just to be safe. | |
61 | */ | |
62 | udelay(10); | |
63 | ||
64 | /* De-assert active-low PLL reset. */ | |
65 | ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, | |
66 | PLL_RESET_N); | |
67 | if (ret) | |
68 | return ret; | |
69 | ||
70 | /* Wait until PLL is locked. */ | |
71 | udelay(50); | |
72 | ||
73 | /* Enable PLL output. */ | |
d41bd923 | 74 | return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, |
9e263131 | 75 | PLL_OUTCTRL); |
9e263131 SB |
76 | } |
77 | ||
78 | static void clk_pll_disable(struct clk_hw *hw) | |
79 | { | |
80 | struct clk_pll *pll = to_clk_pll(hw); | |
81 | u32 mask; | |
82 | u32 val; | |
83 | ||
84 | regmap_read(pll->clkr.regmap, pll->mode_reg, &val); | |
85 | /* Skip if in FSM mode */ | |
86 | if (val & PLL_VOTE_FSM_ENA) | |
87 | return; | |
88 | mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; | |
89 | regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); | |
90 | } | |
91 | ||
92 | static unsigned long | |
93 | clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) | |
94 | { | |
95 | struct clk_pll *pll = to_clk_pll(hw); | |
ae3669ac | 96 | u32 l, m, n, config; |
9e263131 SB |
97 | unsigned long rate; |
98 | u64 tmp; | |
99 | ||
100 | regmap_read(pll->clkr.regmap, pll->l_reg, &l); | |
101 | regmap_read(pll->clkr.regmap, pll->m_reg, &m); | |
102 | regmap_read(pll->clkr.regmap, pll->n_reg, &n); | |
103 | ||
104 | l &= 0x3ff; | |
105 | m &= 0x7ffff; | |
106 | n &= 0x7ffff; | |
107 | ||
108 | rate = parent_rate * l; | |
109 | if (n) { | |
110 | tmp = parent_rate; | |
111 | tmp *= m; | |
112 | do_div(tmp, n); | |
113 | rate += tmp; | |
114 | } | |
ae3669ac SB |
115 | if (pll->post_div_width) { |
116 | regmap_read(pll->clkr.regmap, pll->config_reg, &config); | |
117 | config >>= pll->post_div_shift; | |
118 | config &= BIT(pll->post_div_width) - 1; | |
119 | rate /= config + 1; | |
120 | } | |
121 | ||
9e263131 SB |
122 | return rate; |
123 | } | |
124 | ||
ae3669ac SB |
125 | static const |
126 | struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate) | |
127 | { | |
128 | if (!f) | |
129 | return NULL; | |
130 | ||
131 | for (; f->freq; f++) | |
132 | if (rate <= f->freq) | |
133 | return f; | |
134 | ||
135 | return NULL; | |
136 | } | |
137 | ||
0817b62c BB |
138 | static int |
139 | clk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) | |
ae3669ac | 140 | { |
0817b62c | 141 | struct clk *parent = __clk_get_parent(hw->clk); |
ae3669ac SB |
142 | struct clk_pll *pll = to_clk_pll(hw); |
143 | const struct pll_freq_tbl *f; | |
144 | ||
0817b62c BB |
145 | req->best_parent_hw = __clk_get_hw(parent); |
146 | req->best_parent_rate = __clk_get_rate(parent); | |
147 | ||
148 | f = find_freq(pll->freq_tbl, req->rate); | |
ae3669ac | 149 | if (!f) |
0817b62c BB |
150 | req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate); |
151 | else | |
152 | req->rate = f->freq; | |
ae3669ac | 153 | |
0817b62c | 154 | return 0; |
ae3669ac SB |
155 | } |
156 | ||
157 | static int | |
158 | clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate) | |
159 | { | |
160 | struct clk_pll *pll = to_clk_pll(hw); | |
161 | const struct pll_freq_tbl *f; | |
162 | bool enabled; | |
163 | u32 mode; | |
164 | u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; | |
165 | ||
166 | f = find_freq(pll->freq_tbl, rate); | |
167 | if (!f) | |
168 | return -EINVAL; | |
169 | ||
170 | regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); | |
171 | enabled = (mode & enable_mask) == enable_mask; | |
172 | ||
173 | if (enabled) | |
174 | clk_pll_disable(hw); | |
175 | ||
176 | regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l); | |
177 | regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m); | |
178 | regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n); | |
179 | regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits); | |
180 | ||
181 | if (enabled) | |
182 | clk_pll_enable(hw); | |
183 | ||
184 | return 0; | |
185 | } | |
186 | ||
9e263131 SB |
187 | const struct clk_ops clk_pll_ops = { |
188 | .enable = clk_pll_enable, | |
189 | .disable = clk_pll_disable, | |
190 | .recalc_rate = clk_pll_recalc_rate, | |
ae3669ac SB |
191 | .determine_rate = clk_pll_determine_rate, |
192 | .set_rate = clk_pll_set_rate, | |
9e263131 SB |
193 | }; |
194 | EXPORT_SYMBOL_GPL(clk_pll_ops); | |
195 | ||
196 | static int wait_for_pll(struct clk_pll *pll) | |
197 | { | |
198 | u32 val; | |
199 | int count; | |
200 | int ret; | |
201 | const char *name = __clk_get_name(pll->clkr.hw.clk); | |
202 | ||
203 | /* Wait for pll to enable. */ | |
204 | for (count = 200; count > 0; count--) { | |
205 | ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val); | |
206 | if (ret) | |
207 | return ret; | |
208 | if (val & BIT(pll->status_bit)) | |
209 | return 0; | |
210 | udelay(1); | |
211 | } | |
212 | ||
213 | WARN(1, "%s didn't enable after voting for it!\n", name); | |
214 | return -ETIMEDOUT; | |
215 | } | |
216 | ||
217 | static int clk_pll_vote_enable(struct clk_hw *hw) | |
218 | { | |
219 | int ret; | |
220 | struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk))); | |
221 | ||
222 | ret = clk_enable_regmap(hw); | |
223 | if (ret) | |
224 | return ret; | |
225 | ||
226 | return wait_for_pll(p); | |
227 | } | |
228 | ||
229 | const struct clk_ops clk_pll_vote_ops = { | |
230 | .enable = clk_pll_vote_enable, | |
231 | .disable = clk_disable_regmap, | |
232 | }; | |
233 | EXPORT_SYMBOL_GPL(clk_pll_vote_ops); | |
234 | ||
235 | static void | |
d8c25d3a | 236 | clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count) |
9e263131 SB |
237 | { |
238 | u32 val; | |
239 | u32 mask; | |
240 | ||
241 | /* De-assert reset to FSM */ | |
242 | regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0); | |
243 | ||
244 | /* Program bias count and lock count */ | |
d8c25d3a | 245 | val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT; |
9e263131 SB |
246 | mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; |
247 | mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; | |
248 | regmap_update_bits(regmap, pll->mode_reg, mask, val); | |
249 | ||
250 | /* Enable PLL FSM voting */ | |
251 | regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA, | |
252 | PLL_VOTE_FSM_ENA); | |
253 | } | |
254 | ||
255 | static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, | |
256 | const struct pll_config *config) | |
257 | { | |
258 | u32 val; | |
259 | u32 mask; | |
260 | ||
261 | regmap_write(regmap, pll->l_reg, config->l); | |
262 | regmap_write(regmap, pll->m_reg, config->m); | |
263 | regmap_write(regmap, pll->n_reg, config->n); | |
264 | ||
265 | val = config->vco_val; | |
266 | val |= config->pre_div_val; | |
267 | val |= config->post_div_val; | |
268 | val |= config->mn_ena_mask; | |
269 | val |= config->main_output_mask; | |
270 | val |= config->aux_output_mask; | |
271 | ||
272 | mask = config->vco_mask; | |
273 | mask |= config->pre_div_mask; | |
274 | mask |= config->post_div_mask; | |
275 | mask |= config->mn_ena_mask; | |
276 | mask |= config->main_output_mask; | |
277 | mask |= config->aux_output_mask; | |
278 | ||
279 | regmap_update_bits(regmap, pll->config_reg, mask, val); | |
280 | } | |
281 | ||
d8c25d3a SB |
282 | void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, |
283 | const struct pll_config *config, bool fsm_mode) | |
284 | { | |
285 | clk_pll_configure(pll, regmap, config); | |
286 | if (fsm_mode) | |
287 | clk_pll_set_fsm_mode(pll, regmap, 8); | |
288 | } | |
289 | EXPORT_SYMBOL_GPL(clk_pll_configure_sr); | |
290 | ||
9e263131 SB |
291 | void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, |
292 | const struct pll_config *config, bool fsm_mode) | |
293 | { | |
294 | clk_pll_configure(pll, regmap, config); | |
295 | if (fsm_mode) | |
d8c25d3a | 296 | clk_pll_set_fsm_mode(pll, regmap, 0); |
9e263131 SB |
297 | } |
298 | EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp); |