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9d9f78ed MT |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> | |
4 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Adjustable divider clock implementation | |
11 | */ | |
12 | ||
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/string.h> | |
1a3cd184 | 19 | #include <linux/log2.h> |
9d9f78ed MT |
20 | |
21 | /* | |
22 | * DOC: basic adjustable divider clock that cannot gate | |
23 | * | |
24 | * Traits of this clock: | |
25 | * prepare - clk_prepare only ensures that parents are prepared | |
26 | * enable - clk_enable only ensures that parents are enabled | |
27 | * rate - rate is adjustable. clk->rate = parent->rate / divisor | |
28 | * parent - fixed parent. No clk_set_parent support | |
29 | */ | |
30 | ||
31 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) | |
32 | ||
1a3cd184 | 33 | #define div_mask(d) ((1 << ((d)->width)) - 1) |
6d9252bd | 34 | |
357c3f0a RN |
35 | static unsigned int _get_table_maxdiv(const struct clk_div_table *table) |
36 | { | |
37 | unsigned int maxdiv = 0; | |
38 | const struct clk_div_table *clkt; | |
39 | ||
40 | for (clkt = table; clkt->div; clkt++) | |
41 | if (clkt->div > maxdiv) | |
42 | maxdiv = clkt->div; | |
43 | return maxdiv; | |
44 | } | |
45 | ||
6d9252bd RN |
46 | static unsigned int _get_maxdiv(struct clk_divider *divider) |
47 | { | |
48 | if (divider->flags & CLK_DIVIDER_ONE_BASED) | |
49 | return div_mask(divider); | |
50 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
51 | return 1 << div_mask(divider); | |
357c3f0a RN |
52 | if (divider->table) |
53 | return _get_table_maxdiv(divider->table); | |
6d9252bd RN |
54 | return div_mask(divider) + 1; |
55 | } | |
56 | ||
357c3f0a RN |
57 | static unsigned int _get_table_div(const struct clk_div_table *table, |
58 | unsigned int val) | |
59 | { | |
60 | const struct clk_div_table *clkt; | |
61 | ||
62 | for (clkt = table; clkt->div; clkt++) | |
63 | if (clkt->val == val) | |
64 | return clkt->div; | |
65 | return 0; | |
66 | } | |
67 | ||
6d9252bd RN |
68 | static unsigned int _get_div(struct clk_divider *divider, unsigned int val) |
69 | { | |
70 | if (divider->flags & CLK_DIVIDER_ONE_BASED) | |
71 | return val; | |
72 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
73 | return 1 << val; | |
357c3f0a RN |
74 | if (divider->table) |
75 | return _get_table_div(divider->table, val); | |
6d9252bd RN |
76 | return val + 1; |
77 | } | |
78 | ||
357c3f0a RN |
79 | static unsigned int _get_table_val(const struct clk_div_table *table, |
80 | unsigned int div) | |
81 | { | |
82 | const struct clk_div_table *clkt; | |
83 | ||
84 | for (clkt = table; clkt->div; clkt++) | |
85 | if (clkt->div == div) | |
86 | return clkt->val; | |
87 | return 0; | |
88 | } | |
89 | ||
f783d8b1 | 90 | static unsigned int _get_val(struct clk_divider *divider, unsigned int div) |
6d9252bd RN |
91 | { |
92 | if (divider->flags & CLK_DIVIDER_ONE_BASED) | |
93 | return div; | |
94 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
95 | return __ffs(div); | |
357c3f0a RN |
96 | if (divider->table) |
97 | return _get_table_val(divider->table, div); | |
6d9252bd RN |
98 | return div - 1; |
99 | } | |
9d9f78ed MT |
100 | |
101 | static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, | |
102 | unsigned long parent_rate) | |
103 | { | |
104 | struct clk_divider *divider = to_clk_divider(hw); | |
6d9252bd | 105 | unsigned int div, val; |
9d9f78ed | 106 | |
6d9252bd RN |
107 | val = readl(divider->reg) >> divider->shift; |
108 | val &= div_mask(divider); | |
9d9f78ed | 109 | |
6d9252bd RN |
110 | div = _get_div(divider, val); |
111 | if (!div) { | |
056b2053 SB |
112 | WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), |
113 | "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", | |
114 | __clk_get_name(hw->clk)); | |
6d9252bd RN |
115 | return parent_rate; |
116 | } | |
9d9f78ed MT |
117 | |
118 | return parent_rate / div; | |
119 | } | |
9d9f78ed MT |
120 | |
121 | /* | |
122 | * The reverse of DIV_ROUND_UP: The maximum number which | |
123 | * divided by m is r | |
124 | */ | |
125 | #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1) | |
126 | ||
357c3f0a RN |
127 | static bool _is_valid_table_div(const struct clk_div_table *table, |
128 | unsigned int div) | |
129 | { | |
130 | const struct clk_div_table *clkt; | |
131 | ||
132 | for (clkt = table; clkt->div; clkt++) | |
133 | if (clkt->div == div) | |
134 | return true; | |
135 | return false; | |
136 | } | |
137 | ||
138 | static bool _is_valid_div(struct clk_divider *divider, unsigned int div) | |
139 | { | |
140 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
1a3cd184 | 141 | return is_power_of_2(div); |
357c3f0a RN |
142 | if (divider->table) |
143 | return _is_valid_table_div(divider->table, div); | |
144 | return true; | |
145 | } | |
146 | ||
9d9f78ed MT |
147 | static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, |
148 | unsigned long *best_parent_rate) | |
149 | { | |
150 | struct clk_divider *divider = to_clk_divider(hw); | |
151 | int i, bestdiv = 0; | |
152 | unsigned long parent_rate, best = 0, now, maxdiv; | |
153 | ||
154 | if (!rate) | |
155 | rate = 1; | |
156 | ||
6d9252bd | 157 | maxdiv = _get_maxdiv(divider); |
9d9f78ed | 158 | |
81536e07 SG |
159 | if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { |
160 | parent_rate = *best_parent_rate; | |
9d9f78ed MT |
161 | bestdiv = DIV_ROUND_UP(parent_rate, rate); |
162 | bestdiv = bestdiv == 0 ? 1 : bestdiv; | |
163 | bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; | |
164 | return bestdiv; | |
165 | } | |
166 | ||
167 | /* | |
168 | * The maximum divider we can use without overflowing | |
169 | * unsigned long in rate * i below | |
170 | */ | |
171 | maxdiv = min(ULONG_MAX / rate, maxdiv); | |
172 | ||
173 | for (i = 1; i <= maxdiv; i++) { | |
357c3f0a | 174 | if (!_is_valid_div(divider, i)) |
6d9252bd | 175 | continue; |
9d9f78ed MT |
176 | parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), |
177 | MULT_ROUND_UP(rate, i)); | |
178 | now = parent_rate / i; | |
179 | if (now <= rate && now > best) { | |
180 | bestdiv = i; | |
181 | best = now; | |
182 | *best_parent_rate = parent_rate; | |
183 | } | |
184 | } | |
185 | ||
186 | if (!bestdiv) { | |
6d9252bd | 187 | bestdiv = _get_maxdiv(divider); |
9d9f78ed MT |
188 | *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1); |
189 | } | |
190 | ||
191 | return bestdiv; | |
192 | } | |
193 | ||
194 | static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, | |
195 | unsigned long *prate) | |
196 | { | |
197 | int div; | |
198 | div = clk_divider_bestdiv(hw, rate, prate); | |
199 | ||
81536e07 | 200 | return *prate / div; |
9d9f78ed | 201 | } |
9d9f78ed | 202 | |
1c0035d7 SG |
203 | static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, |
204 | unsigned long parent_rate) | |
9d9f78ed MT |
205 | { |
206 | struct clk_divider *divider = to_clk_divider(hw); | |
6d9252bd | 207 | unsigned int div, value; |
9d9f78ed MT |
208 | unsigned long flags = 0; |
209 | u32 val; | |
210 | ||
1c0035d7 | 211 | div = parent_rate / rate; |
6d9252bd | 212 | value = _get_val(divider, div); |
9d9f78ed | 213 | |
6d9252bd RN |
214 | if (value > div_mask(divider)) |
215 | value = div_mask(divider); | |
9d9f78ed MT |
216 | |
217 | if (divider->lock) | |
218 | spin_lock_irqsave(divider->lock, flags); | |
219 | ||
220 | val = readl(divider->reg); | |
221 | val &= ~(div_mask(divider) << divider->shift); | |
6d9252bd | 222 | val |= value << divider->shift; |
9d9f78ed MT |
223 | writel(val, divider->reg); |
224 | ||
225 | if (divider->lock) | |
226 | spin_unlock_irqrestore(divider->lock, flags); | |
227 | ||
228 | return 0; | |
229 | } | |
9d9f78ed | 230 | |
822c250e | 231 | const struct clk_ops clk_divider_ops = { |
9d9f78ed MT |
232 | .recalc_rate = clk_divider_recalc_rate, |
233 | .round_rate = clk_divider_round_rate, | |
234 | .set_rate = clk_divider_set_rate, | |
235 | }; | |
236 | EXPORT_SYMBOL_GPL(clk_divider_ops); | |
237 | ||
357c3f0a | 238 | static struct clk *_register_divider(struct device *dev, const char *name, |
9d9f78ed MT |
239 | const char *parent_name, unsigned long flags, |
240 | void __iomem *reg, u8 shift, u8 width, | |
357c3f0a RN |
241 | u8 clk_divider_flags, const struct clk_div_table *table, |
242 | spinlock_t *lock) | |
9d9f78ed MT |
243 | { |
244 | struct clk_divider *div; | |
245 | struct clk *clk; | |
0197b3ea | 246 | struct clk_init_data init; |
9d9f78ed | 247 | |
27d54591 | 248 | /* allocate the divider */ |
9d9f78ed | 249 | div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); |
9d9f78ed MT |
250 | if (!div) { |
251 | pr_err("%s: could not allocate divider clk\n", __func__); | |
27d54591 | 252 | return ERR_PTR(-ENOMEM); |
9d9f78ed MT |
253 | } |
254 | ||
0197b3ea SK |
255 | init.name = name; |
256 | init.ops = &clk_divider_ops; | |
f7d8caad | 257 | init.flags = flags | CLK_IS_BASIC; |
0197b3ea SK |
258 | init.parent_names = (parent_name ? &parent_name: NULL); |
259 | init.num_parents = (parent_name ? 1 : 0); | |
260 | ||
9d9f78ed MT |
261 | /* struct clk_divider assignments */ |
262 | div->reg = reg; | |
263 | div->shift = shift; | |
264 | div->width = width; | |
265 | div->flags = clk_divider_flags; | |
266 | div->lock = lock; | |
0197b3ea | 267 | div->hw.init = &init; |
357c3f0a | 268 | div->table = table; |
9d9f78ed | 269 | |
27d54591 | 270 | /* register the clock */ |
0197b3ea | 271 | clk = clk_register(dev, &div->hw); |
9d9f78ed | 272 | |
27d54591 MT |
273 | if (IS_ERR(clk)) |
274 | kfree(div); | |
9d9f78ed | 275 | |
27d54591 | 276 | return clk; |
9d9f78ed | 277 | } |
357c3f0a RN |
278 | |
279 | /** | |
280 | * clk_register_divider - register a divider clock with the clock framework | |
281 | * @dev: device registering this clock | |
282 | * @name: name of this clock | |
283 | * @parent_name: name of clock's parent | |
284 | * @flags: framework-specific flags | |
285 | * @reg: register address to adjust divider | |
286 | * @shift: number of bits to shift the bitfield | |
287 | * @width: width of the bitfield | |
288 | * @clk_divider_flags: divider-specific flags for this clock | |
289 | * @lock: shared register lock for this clock | |
290 | */ | |
291 | struct clk *clk_register_divider(struct device *dev, const char *name, | |
292 | const char *parent_name, unsigned long flags, | |
293 | void __iomem *reg, u8 shift, u8 width, | |
294 | u8 clk_divider_flags, spinlock_t *lock) | |
295 | { | |
296 | return _register_divider(dev, name, parent_name, flags, reg, shift, | |
297 | width, clk_divider_flags, NULL, lock); | |
298 | } | |
299 | ||
300 | /** | |
301 | * clk_register_divider_table - register a table based divider clock with | |
302 | * the clock framework | |
303 | * @dev: device registering this clock | |
304 | * @name: name of this clock | |
305 | * @parent_name: name of clock's parent | |
306 | * @flags: framework-specific flags | |
307 | * @reg: register address to adjust divider | |
308 | * @shift: number of bits to shift the bitfield | |
309 | * @width: width of the bitfield | |
310 | * @clk_divider_flags: divider-specific flags for this clock | |
311 | * @table: array of divider/value pairs ending with a div set to 0 | |
312 | * @lock: shared register lock for this clock | |
313 | */ | |
314 | struct clk *clk_register_divider_table(struct device *dev, const char *name, | |
315 | const char *parent_name, unsigned long flags, | |
316 | void __iomem *reg, u8 shift, u8 width, | |
317 | u8 clk_divider_flags, const struct clk_div_table *table, | |
318 | spinlock_t *lock) | |
319 | { | |
320 | return _register_divider(dev, name, parent_name, flags, reg, shift, | |
321 | width, clk_divider_flags, table, lock); | |
322 | } |