[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / vr41xx_giu.c

/*
 *  Driver for NEC VR4100 series General-purpose I/O Unit.
 *
 *  Copyright (C) 2002 MontaVista Software Inc.
 *	Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
 *  Copyright (C) 2003-2007  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/smp_lock.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#include <asm/io.h>
#include <asm/vr41xx/giu.h>
#include <asm/vr41xx/irq.h>
#include <asm/vr41xx/vr41xx.h>

MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
MODULE_LICENSE("GPL");

static int major;	/* default is dynamic major device number */
module_param(major, int, 0);
MODULE_PARM_DESC(major, "Major device number");

#define GIUIOSELL	0x00
#define GIUIOSELH	0x02
#define GIUPIODL	0x04
#define GIUPIODH	0x06
#define GIUINTSTATL	0x08
#define GIUINTSTATH	0x0a
#define GIUINTENL	0x0c
#define GIUINTENH	0x0e
#define GIUINTTYPL	0x10
#define GIUINTTYPH	0x12
#define GIUINTALSELL	0x14
#define GIUINTALSELH	0x16
#define GIUINTHTSELL	0x18
#define GIUINTHTSELH	0x1a
#define GIUPODATL	0x1c
#define GIUPODATEN	0x1c
#define GIUPODATH	0x1e
 #define PIOEN0		0x0100
 #define PIOEN1		0x0200
#define GIUPODAT	0x1e
#define GIUFEDGEINHL	0x20
#define GIUFEDGEINHH	0x22
#define GIUREDGEINHL	0x24
#define GIUREDGEINHH	0x26

#define GIUUSEUPDN	0x1e0
#define GIUTERMUPDN	0x1e2

#define GPIO_HAS_PULLUPDOWN_IO		0x0001
#define GPIO_HAS_OUTPUT_ENABLE		0x0002
#define GPIO_HAS_INTERRUPT_EDGE_SELECT	0x0100

static spinlock_t giu_lock;
static unsigned long giu_flags;
static unsigned int giu_nr_pins;

static void __iomem *giu_base;

#define giu_read(offset)		readw(giu_base + (offset))
#define giu_write(offset, value)	writew((value), giu_base + (offset))

#define GPIO_PIN_OF_IRQ(irq)	((irq) - GIU_IRQ_BASE)
#define GIUINT_HIGH_OFFSET	16
#define GIUINT_HIGH_MAX		32

static inline uint16_t giu_set(uint16_t offset, uint16_t set)
{
	uint16_t data;

	data = giu_read(offset);
	data |= set;
	giu_write(offset, data);

	return data;
}

static inline uint16_t giu_clear(uint16_t offset, uint16_t clear)
{
	uint16_t data;

	data = giu_read(offset);
	data &= ~clear;
	giu_write(offset, data);

	return data;
}

static void ack_giuint_low(unsigned int irq)
{
	giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq));
}

static void mask_giuint_low(unsigned int irq)
{
	giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
}

static void mask_ack_giuint_low(unsigned int irq)
{
	unsigned int pin;

	pin = GPIO_PIN_OF_IRQ(irq);
	giu_clear(GIUINTENL, 1 << pin);
	giu_write(GIUINTSTATL, 1 << pin);
}

static void unmask_giuint_low(unsigned int irq)
{
	giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
}

static struct irq_chip giuint_low_irq_chip = {
	.name		= "GIUINTL",
	.ack		= ack_giuint_low,
	.mask		= mask_giuint_low,
	.mask_ack	= mask_ack_giuint_low,
	.unmask		= unmask_giuint_low,
};

static void ack_giuint_high(unsigned int irq)
{
	giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
}

static void mask_giuint_high(unsigned int irq)
{
	giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
}

static void mask_ack_giuint_high(unsigned int irq)
{
	unsigned int pin;

	pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
	giu_clear(GIUINTENH, 1 << pin);
	giu_write(GIUINTSTATH, 1 << pin);
}

static void unmask_giuint_high(unsigned int irq)
{
	giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
}

static struct irq_chip giuint_high_irq_chip = {
	.name		= "GIUINTH",
	.ack		= ack_giuint_high,
	.mask		= mask_giuint_high,
	.mask_ack	= mask_ack_giuint_high,
	.unmask		= unmask_giuint_high,
};

static int giu_get_irq(unsigned int irq)
{
	uint16_t pendl, pendh, maskl, maskh;
	int i;

	pendl = giu_read(GIUINTSTATL);
	pendh = giu_read(GIUINTSTATH);
	maskl = giu_read(GIUINTENL);
	maskh = giu_read(GIUINTENH);

	maskl &= pendl;
	maskh &= pendh;

	if (maskl) {
		for (i = 0; i < 16; i++) {
			if (maskl & (1 << i))
				return GIU_IRQ(i);
		}
	} else if (maskh) {
		for (i = 0; i < 16; i++) {
			if (maskh & (1 << i))
				return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
		}
	}

	printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
	       maskl, pendl, maskh, pendh);

	atomic_inc(&irq_err_count);

	return -EINVAL;
}

void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal)
{
	uint16_t mask;

	if (pin < GIUINT_HIGH_OFFSET) {
		mask = 1 << pin;
		if (trigger != IRQ_TRIGGER_LEVEL) {
        		giu_set(GIUINTTYPL, mask);
			if (signal == IRQ_SIGNAL_HOLD)
				giu_set(GIUINTHTSELL, mask);
			else
				giu_clear(GIUINTHTSELL, mask);
			if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
				switch (trigger) {
				case IRQ_TRIGGER_EDGE_FALLING:
					giu_set(GIUFEDGEINHL, mask);
					giu_clear(GIUREDGEINHL, mask);
					break;
				case IRQ_TRIGGER_EDGE_RISING:
					giu_clear(GIUFEDGEINHL, mask);
					giu_set(GIUREDGEINHL, mask);
					break;
				default:
					giu_set(GIUFEDGEINHL, mask);
					giu_set(GIUREDGEINHL, mask);
					break;
				}
			}
			set_irq_chip_and_handler(GIU_IRQ(pin),
			                         &giuint_low_irq_chip,
			                         handle_edge_irq);
		} else {
			giu_clear(GIUINTTYPL, mask);
			giu_clear(GIUINTHTSELL, mask);
			set_irq_chip_and_handler(GIU_IRQ(pin),
			                         &giuint_low_irq_chip,
			                         handle_level_irq);
		}
		giu_write(GIUINTSTATL, mask);
	} else if (pin < GIUINT_HIGH_MAX) {
		mask = 1 << (pin - GIUINT_HIGH_OFFSET);
		if (trigger != IRQ_TRIGGER_LEVEL) {
			giu_set(GIUINTTYPH, mask);
			if (signal == IRQ_SIGNAL_HOLD)
				giu_set(GIUINTHTSELH, mask);
			else
				giu_clear(GIUINTHTSELH, mask);
			if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
				switch (trigger) {
				case IRQ_TRIGGER_EDGE_FALLING:
					giu_set(GIUFEDGEINHH, mask);
					giu_clear(GIUREDGEINHH, mask);
					break;
				case IRQ_TRIGGER_EDGE_RISING:
					giu_clear(GIUFEDGEINHH, mask);
					giu_set(GIUREDGEINHH, mask);
					break;
				default:
					giu_set(GIUFEDGEINHH, mask);
					giu_set(GIUREDGEINHH, mask);
					break;
				}
			}
			set_irq_chip_and_handler(GIU_IRQ(pin),
			                         &giuint_high_irq_chip,
			                         handle_edge_irq);
		} else {
			giu_clear(GIUINTTYPH, mask);
			giu_clear(GIUINTHTSELH, mask);
			set_irq_chip_and_handler(GIU_IRQ(pin),
			                         &giuint_high_irq_chip,
			                         handle_level_irq);
		}
		giu_write(GIUINTSTATH, mask);
	}
}
EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);

void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
{
	uint16_t mask;

	if (pin < GIUINT_HIGH_OFFSET) {
		mask = 1 << pin;
		if (level == IRQ_LEVEL_HIGH)
			giu_set(GIUINTALSELL, mask);
		else
			giu_clear(GIUINTALSELL, mask);
		giu_write(GIUINTSTATL, mask);
	} else if (pin < GIUINT_HIGH_MAX) {
		mask = 1 << (pin - GIUINT_HIGH_OFFSET);
		if (level == IRQ_LEVEL_HIGH)
			giu_set(GIUINTALSELH, mask);
		else
			giu_clear(GIUINTALSELH, mask);
		giu_write(GIUINTSTATH, mask);
	}
}
EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);

gpio_data_t vr41xx_gpio_get_pin(unsigned int pin)
{
	uint16_t reg, mask;

	if (pin >= giu_nr_pins)
		return GPIO_DATA_INVAL;

	if (pin < 16) {
		reg = giu_read(GIUPIODL);
		mask = (uint16_t)1 << pin;
	} else if (pin < 32) {
		reg = giu_read(GIUPIODH);
		mask = (uint16_t)1 << (pin - 16);
	} else if (pin < 48) {
		reg = giu_read(GIUPODATL);
		mask = (uint16_t)1 << (pin - 32);
	} else {
		reg = giu_read(GIUPODATH);
		mask = (uint16_t)1 << (pin - 48);
	}

	if (reg & mask)
		return GPIO_DATA_HIGH;

	return GPIO_DATA_LOW;
}
EXPORT_SYMBOL_GPL(vr41xx_gpio_get_pin);

int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data)
{
	uint16_t offset, mask, reg;
	unsigned long flags;

	if (pin >= giu_nr_pins)
		return -EINVAL;

	if (pin < 16) {
		offset = GIUPIODL;
		mask = (uint16_t)1 << pin;
	} else if (pin < 32) {
		offset = GIUPIODH;
		mask = (uint16_t)1 << (pin - 16);
	} else if (pin < 48) {
		offset = GIUPODATL;
		mask = (uint16_t)1 << (pin - 32);
	} else {
		offset = GIUPODATH;
		mask = (uint16_t)1 << (pin - 48);
	}

	spin_lock_irqsave(&giu_lock, flags);

	reg = giu_read(offset);
	if (data == GPIO_DATA_HIGH)
		reg |= mask;
	else
		reg &= ~mask;
	giu_write(offset, reg);

	spin_unlock_irqrestore(&giu_lock, flags);

	return 0;
}
EXPORT_SYMBOL_GPL(vr41xx_gpio_set_pin);

int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir)
{
	uint16_t offset, mask, reg;
	unsigned long flags;

	if (pin >= giu_nr_pins)
		return -EINVAL;

	if (pin < 16) {
		offset = GIUIOSELL;
		mask = (uint16_t)1 << pin;
	} else if (pin < 32) {
		offset = GIUIOSELH;
		mask = (uint16_t)1 << (pin - 16);
	} else {
		if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
			offset = GIUPODATEN;
			mask = (uint16_t)1 << (pin - 32);
		} else {
			switch (pin) {
			case 48:
				offset = GIUPODATH;
				mask = PIOEN0;
				break;
			case 49:
				offset = GIUPODATH;
				mask = PIOEN1;
				break;
			default:
				return -EINVAL;
			}
		}
	}

	spin_lock_irqsave(&giu_lock, flags);

	reg = giu_read(offset);
	if (dir == GPIO_OUTPUT)
		reg |= mask;
	else
		reg &= ~mask;
	giu_write(offset, reg);

	spin_unlock_irqrestore(&giu_lock, flags);

	return 0;
}
EXPORT_SYMBOL_GPL(vr41xx_gpio_set_direction);

int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
{
	uint16_t reg, mask;
	unsigned long flags;

	if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
		return -EPERM;

	if (pin >= 15)
		return -EINVAL;

	mask = (uint16_t)1 << pin;

	spin_lock_irqsave(&giu_lock, flags);

	if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
		reg = giu_read(GIUTERMUPDN);
		if (pull == GPIO_PULL_UP)
			reg |= mask;
		else
			reg &= ~mask;
		giu_write(GIUTERMUPDN, reg);

		reg = giu_read(GIUUSEUPDN);
		reg |= mask;
		giu_write(GIUUSEUPDN, reg);
	} else {
		reg = giu_read(GIUUSEUPDN);
		reg &= ~mask;
		giu_write(GIUUSEUPDN, reg);
	}

	spin_unlock_irqrestore(&giu_lock, flags);

	return 0;
}
EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);

static ssize_t gpio_read(struct file *file, char __user *buf, size_t len,
                         loff_t *ppos)
{
	unsigned int pin;
	char value = '0';

	pin = iminor(file->f_path.dentry->d_inode);
	if (pin >= giu_nr_pins)
		return -EBADF;

	if (vr41xx_gpio_get_pin(pin) == GPIO_DATA_HIGH)
		value = '1';

	if (len <= 0)
		return -EFAULT;

	if (put_user(value, buf))
		return -EFAULT;

	return 1;
}

static ssize_t gpio_write(struct file *file, const char __user *data,
                          size_t len, loff_t *ppos)
{
	unsigned int pin;
	size_t i;
	char c;
	int retval = 0;

	pin = iminor(file->f_path.dentry->d_inode);
	if (pin >= giu_nr_pins)
		return -EBADF;

	for (i = 0; i < len; i++) {
		if (get_user(c, data + i))
			return -EFAULT;

		switch (c) {
		case '0':
			retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_LOW);
			break;
		case '1':
			retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_HIGH);
			break;
		case 'D':
			printk(KERN_INFO "GPIO%d: pull down\n", pin);
			retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DOWN);
			break;
		case 'd':
			printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
			retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
			break;
		case 'I':
			printk(KERN_INFO "GPIO%d: input\n", pin);
			retval = vr41xx_gpio_set_direction(pin, GPIO_INPUT);
			break;
		case 'O':
			printk(KERN_INFO "GPIO%d: output\n", pin);
			retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT);
			break;
		case 'o':
			printk(KERN_INFO "GPIO%d: output disable\n", pin);
			retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT_DISABLE);
			break;
		case 'P':
			printk(KERN_INFO "GPIO%d: pull up\n", pin);
			retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_UP);
			break;
		case 'p':
			printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
			retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
			break;
		default:
			break;
		}

		if (retval < 0)
			break;
	}

	return i;
}

static int gpio_open(struct inode *inode, struct file *file)
{
	unsigned int pin;

	cycle_kernel_lock();
	pin = iminor(inode);
	if (pin >= giu_nr_pins)
		return -EBADF;

	return nonseekable_open(inode, file);
}

static int gpio_release(struct inode *inode, struct file *file)
{
	unsigned int pin;

	pin = iminor(inode);
	if (pin >= giu_nr_pins)
		return -EBADF;

	return 0;
}

static const struct file_operations gpio_fops = {
	.owner		= THIS_MODULE,
	.read		= gpio_read,
	.write		= gpio_write,
	.open		= gpio_open,
	.release	= gpio_release,
};

static int __devinit giu_probe(struct platform_device *dev)
{
	struct resource *res;
	unsigned int trigger, i, pin;
	struct irq_chip *chip;
	int irq, retval;

	switch (dev->id) {
	case GPIO_50PINS_PULLUPDOWN:
		giu_flags = GPIO_HAS_PULLUPDOWN_IO;
		giu_nr_pins = 50;
		break;
	case GPIO_36PINS:
		giu_nr_pins = 36;
		break;
	case GPIO_48PINS_EDGE_SELECT:
		giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
		giu_nr_pins = 48;
		break;
	default:
		printk(KERN_ERR "GIU: unknown ID %d\n", dev->id);
		return -ENODEV;
	}

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res)
		return -EBUSY;

	giu_base = ioremap(res->start, res->end - res->start + 1);
	if (!giu_base)
		return -ENOMEM;

	retval = register_chrdev(major, "GIU", &gpio_fops);
	if (retval < 0) {
		iounmap(giu_base);
		giu_base = NULL;
		return retval;
	}

	if (major == 0) {
		major = retval;
		printk(KERN_INFO "GIU: major number %d\n", major);
	}

	spin_lock_init(&giu_lock);

	giu_write(GIUINTENL, 0);
	giu_write(GIUINTENH, 0);

	trigger = giu_read(GIUINTTYPH) << 16;
	trigger |= giu_read(GIUINTTYPL);
	for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
		pin = GPIO_PIN_OF_IRQ(i);
		if (pin < GIUINT_HIGH_OFFSET)
			chip = &giuint_low_irq_chip;
		else
			chip = &giuint_high_irq_chip;

		if (trigger & (1 << pin))
			set_irq_chip_and_handler(i, chip, handle_edge_irq);
		else
			set_irq_chip_and_handler(i, chip, handle_level_irq);

	}

	irq = platform_get_irq(dev, 0);
	if (irq < 0 || irq >= NR_IRQS)
		return -EBUSY;

	return cascade_irq(irq, giu_get_irq);
}

static int __devexit giu_remove(struct platform_device *dev)
{
	if (giu_base) {
		iounmap(giu_base);
		giu_base = NULL;
	}

	return 0;
}

static struct platform_driver giu_device_driver = {
	.probe		= giu_probe,
	.remove		= __devexit_p(giu_remove),
	.driver		= {
		.name	= "GIU",
		.owner	= THIS_MODULE,
	},
};

static int __init vr41xx_giu_init(void)
{
	return platform_driver_register(&giu_device_driver);
}

static void __exit vr41xx_giu_exit(void)
{
	platform_driver_unregister(&giu_device_driver);
}

module_init(vr41xx_giu_init);
module_exit(vr41xx_giu_exit);
Commit	Line	Data
e400bae9 YY	1	/*
	2	* Driver for NEC VR4100 series General-purpose I/O Unit.
	3	*
	4	* Copyright (C) 2002 MontaVista Software Inc.
	5	* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
364ca8a8	6	* Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
e400bae9 YY	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
e400bae9 YY	22	#include <linux/errno.h>
	23	#include <linux/fs.h>
	24	#include <linux/init.h>
e400bae9	25	#include <linux/interrupt.h>
44173fb2	26	#include <linux/irq.h>
e400bae9 YY	27	#include <linux/kernel.h>
e400bae9 YY	28	#include <linux/module.h>
44173fb2	29	#include <linux/platform_device.h>
f2b9857e	30	#include <linux/smp_lock.h>
e400bae9 YY	31	#include <linux/spinlock.h>
	32	#include <linux/types.h>
	33
e400bae9 YY	34	#include <asm/io.h>
e400bae9 YY	35	#include <asm/vr41xx/giu.h>
66151bbd	36	#include <asm/vr41xx/irq.h>
e400bae9 YY	37	#include <asm/vr41xx/vr41xx.h>
e400bae9 YY	38
29ce2c76	39	MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
e400bae9 YY	40	MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
	41	MODULE_LICENSE("GPL");
	42
	43	static int major; /* default is dynamic major device number */
	44	module_param(major, int, 0);
	45	MODULE_PARM_DESC(major, "Major device number");
	46
e400bae9 YY	47	#define GIUIOSELL 0x00
	48	#define GIUIOSELH 0x02
	49	#define GIUPIODL 0x04
	50	#define GIUPIODH 0x06
	51	#define GIUINTSTATL 0x08
	52	#define GIUINTSTATH 0x0a
	53	#define GIUINTENL 0x0c
	54	#define GIUINTENH 0x0e
	55	#define GIUINTTYPL 0x10
	56	#define GIUINTTYPH 0x12
	57	#define GIUINTALSELL 0x14
	58	#define GIUINTALSELH 0x16
	59	#define GIUINTHTSELL 0x18
	60	#define GIUINTHTSELH 0x1a
	61	#define GIUPODATL 0x1c
	62	#define GIUPODATEN 0x1c
	63	#define GIUPODATH 0x1e
	64	#define PIOEN0 0x0100
	65	#define PIOEN1 0x0200
	66	#define GIUPODAT 0x1e
	67	#define GIUFEDGEINHL 0x20
	68	#define GIUFEDGEINHH 0x22
	69	#define GIUREDGEINHL 0x24
	70	#define GIUREDGEINHH 0x26
	71
	72	#define GIUUSEUPDN 0x1e0
	73	#define GIUTERMUPDN 0x1e2
	74
	75	#define GPIO_HAS_PULLUPDOWN_IO 0x0001
	76	#define GPIO_HAS_OUTPUT_ENABLE 0x0002
	77	#define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
	78
	79	static spinlock_t giu_lock;
e400bae9 YY	80	static unsigned long giu_flags;
	81	static unsigned int giu_nr_pins;
	82
	83	static void __iomem *giu_base;
	84
	85	#define giu_read(offset) readw(giu_base + (offset))
	86	#define giu_write(offset, value) writew((value), giu_base + (offset))
	87
	88	#define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
	89	#define GIUINT_HIGH_OFFSET 16
	90	#define GIUINT_HIGH_MAX 32
	91
	92	static inline uint16_t giu_set(uint16_t offset, uint16_t set)
	93	{
	94	uint16_t data;
	95
	96	data = giu_read(offset);
	97	data \|= set;
	98	giu_write(offset, data);
	99
	100	return data;
	101	}
	102
	103	static inline uint16_t giu_clear(uint16_t offset, uint16_t clear)
	104	{
	105	uint16_t data;
	106
	107	data = giu_read(offset);
	108	data &= ~clear;
	109	giu_write(offset, data);
	110
	111	return data;
	112	}
	113
364ca8a8	114	static void ack_giuint_low(unsigned int irq)
e400bae9	115	{
364ca8a8	116	giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq));
e400bae9 YY	117	}
e400bae9 YY	118
364ca8a8	119	static void mask_giuint_low(unsigned int irq)
e400bae9 YY	120	{
	121	giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
	122	}
	123
364ca8a8	124	static void mask_ack_giuint_low(unsigned int irq)
e400bae9 YY	125	{
	126	unsigned int pin;
	127
	128	pin = GPIO_PIN_OF_IRQ(irq);
	129	giu_clear(GIUINTENL, 1 << pin);
	130	giu_write(GIUINTSTATL, 1 << pin);
	131	}
	132
364ca8a8	133	static void unmask_giuint_low(unsigned int irq)
e400bae9	134	{
364ca8a8	135	giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
e400bae9 YY	136	}
e400bae9 YY	137
364ca8a8 YY	138	static struct irq_chip giuint_low_irq_chip = {
	139	.name = "GIUINTL",
	140	.ack = ack_giuint_low,
	141	.mask = mask_giuint_low,
	142	.mask_ack = mask_ack_giuint_low,
	143	.unmask = unmask_giuint_low,
e400bae9 YY	144	};
e400bae9 YY	145
364ca8a8	146	static void ack_giuint_high(unsigned int irq)
e400bae9	147	{
364ca8a8	148	giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
e400bae9 YY	149	}
e400bae9 YY	150
364ca8a8	151	static void mask_giuint_high(unsigned int irq)
e400bae9 YY	152	{
	153	giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
	154	}
	155
364ca8a8	156	static void mask_ack_giuint_high(unsigned int irq)
e400bae9 YY	157	{
	158	unsigned int pin;
	159
	160	pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
	161	giu_clear(GIUINTENH, 1 << pin);
	162	giu_write(GIUINTSTATH, 1 << pin);
	163	}
	164
364ca8a8	165	static void unmask_giuint_high(unsigned int irq)
e400bae9	166	{
364ca8a8	167	giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
e400bae9 YY	168	}
e400bae9 YY	169
364ca8a8 YY	170	static struct irq_chip giuint_high_irq_chip = {
	171	.name = "GIUINTH",
	172	.ack = ack_giuint_high,
	173	.mask = mask_giuint_high,
	174	.mask_ack = mask_ack_giuint_high,
	175	.unmask = unmask_giuint_high,
e400bae9 YY	176	};
e400bae9 YY	177
7d12e780	178	static int giu_get_irq(unsigned int irq)
e400bae9 YY	179	{
	180	uint16_t pendl, pendh, maskl, maskh;
	181	int i;
	182
	183	pendl = giu_read(GIUINTSTATL);
	184	pendh = giu_read(GIUINTSTATH);
	185	maskl = giu_read(GIUINTENL);
	186	maskh = giu_read(GIUINTENH);
	187
	188	maskl &= pendl;
	189	maskh &= pendh;
	190
	191	if (maskl) {
	192	for (i = 0; i < 16; i++) {
	193	if (maskl & (1 << i))
	194	return GIU_IRQ(i);
	195	}
	196	} else if (maskh) {
	197	for (i = 0; i < 16; i++) {
	198	if (maskh & (1 << i))
	199	return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
	200	}
	201	}
	202
	203	printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
	204	maskl, pendl, maskh, pendh);
	205
	206	atomic_inc(&irq_err_count);
	207
	208	return -EINVAL;
	209	}
	210
	211	void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal)
	212	{
	213	uint16_t mask;
	214
	215	if (pin < GIUINT_HIGH_OFFSET) {
	216	mask = 1 << pin;
	217	if (trigger != IRQ_TRIGGER_LEVEL) {
	218	giu_set(GIUINTTYPL, mask);
	219	if (signal == IRQ_SIGNAL_HOLD)
	220	giu_set(GIUINTHTSELL, mask);
	221	else
	222	giu_clear(GIUINTHTSELL, mask);
44173fb2	223	if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
e400bae9 YY	224	switch (trigger) {
	225	case IRQ_TRIGGER_EDGE_FALLING:
	226	giu_set(GIUFEDGEINHL, mask);
	227	giu_clear(GIUREDGEINHL, mask);
	228	break;
	229	case IRQ_TRIGGER_EDGE_RISING:
	230	giu_clear(GIUFEDGEINHL, mask);
	231	giu_set(GIUREDGEINHL, mask);
	232	break;
	233	default:
	234	giu_set(GIUFEDGEINHL, mask);
	235	giu_set(GIUREDGEINHL, mask);
	236	break;
	237	}
	238	}
364ca8a8 YY	239	set_irq_chip_and_handler(GIU_IRQ(pin),
	240	&giuint_low_irq_chip,
	241	handle_edge_irq);
e400bae9 YY	242	} else {
	243	giu_clear(GIUINTTYPL, mask);
	244	giu_clear(GIUINTHTSELL, mask);
364ca8a8 YY	245	set_irq_chip_and_handler(GIU_IRQ(pin),
	246	&giuint_low_irq_chip,
	247	handle_level_irq);
e400bae9 YY	248	}
	249	giu_write(GIUINTSTATL, mask);
	250	} else if (pin < GIUINT_HIGH_MAX) {
	251	mask = 1 << (pin - GIUINT_HIGH_OFFSET);
	252	if (trigger != IRQ_TRIGGER_LEVEL) {
	253	giu_set(GIUINTTYPH, mask);
	254	if (signal == IRQ_SIGNAL_HOLD)
	255	giu_set(GIUINTHTSELH, mask);
	256	else
	257	giu_clear(GIUINTHTSELH, mask);
44173fb2	258	if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
e400bae9 YY	259	switch (trigger) {
	260	case IRQ_TRIGGER_EDGE_FALLING:
	261	giu_set(GIUFEDGEINHH, mask);
	262	giu_clear(GIUREDGEINHH, mask);
	263	break;
	264	case IRQ_TRIGGER_EDGE_RISING:
	265	giu_clear(GIUFEDGEINHH, mask);
	266	giu_set(GIUREDGEINHH, mask);
	267	break;
	268	default:
	269	giu_set(GIUFEDGEINHH, mask);
	270	giu_set(GIUREDGEINHH, mask);
	271	break;
	272	}
	273	}
364ca8a8 YY	274	set_irq_chip_and_handler(GIU_IRQ(pin),
	275	&giuint_high_irq_chip,
	276	handle_edge_irq);
e400bae9 YY	277	} else {
	278	giu_clear(GIUINTTYPH, mask);
	279	giu_clear(GIUINTHTSELH, mask);
364ca8a8 YY	280	set_irq_chip_and_handler(GIU_IRQ(pin),
	281	&giuint_high_irq_chip,
	282	handle_level_irq);
e400bae9 YY	283	}
	284	giu_write(GIUINTSTATH, mask);
	285	}
	286	}
e400bae9 YY	287	EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
	288
	289	void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
	290	{
	291	uint16_t mask;
	292
	293	if (pin < GIUINT_HIGH_OFFSET) {
	294	mask = 1 << pin;
	295	if (level == IRQ_LEVEL_HIGH)
	296	giu_set(GIUINTALSELL, mask);
	297	else
	298	giu_clear(GIUINTALSELL, mask);
	299	giu_write(GIUINTSTATL, mask);
	300	} else if (pin < GIUINT_HIGH_MAX) {
	301	mask = 1 << (pin - GIUINT_HIGH_OFFSET);
	302	if (level == IRQ_LEVEL_HIGH)
	303	giu_set(GIUINTALSELH, mask);
	304	else
	305	giu_clear(GIUINTALSELH, mask);
	306	giu_write(GIUINTSTATH, mask);
	307	}
	308	}
e400bae9 YY	309	EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
	310
	311	gpio_data_t vr41xx_gpio_get_pin(unsigned int pin)
	312	{
	313	uint16_t reg, mask;
	314
	315	if (pin >= giu_nr_pins)
	316	return GPIO_DATA_INVAL;
	317
	318	if (pin < 16) {
	319	reg = giu_read(GIUPIODL);
	320	mask = (uint16_t)1 << pin;
	321	} else if (pin < 32) {
	322	reg = giu_read(GIUPIODH);
	323	mask = (uint16_t)1 << (pin - 16);
	324	} else if (pin < 48) {
	325	reg = giu_read(GIUPODATL);
	326	mask = (uint16_t)1 << (pin - 32);
	327	} else {
	328	reg = giu_read(GIUPODATH);
	329	mask = (uint16_t)1 << (pin - 48);
	330	}
	331
	332	if (reg & mask)
	333	return GPIO_DATA_HIGH;
	334
	335	return GPIO_DATA_LOW;
	336	}
e400bae9 YY	337	EXPORT_SYMBOL_GPL(vr41xx_gpio_get_pin);
	338
	339	int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data)
	340	{
	341	uint16_t offset, mask, reg;
	342	unsigned long flags;
	343
	344	if (pin >= giu_nr_pins)
	345	return -EINVAL;
	346
	347	if (pin < 16) {
	348	offset = GIUPIODL;
	349	mask = (uint16_t)1 << pin;
	350	} else if (pin < 32) {
	351	offset = GIUPIODH;
	352	mask = (uint16_t)1 << (pin - 16);
	353	} else if (pin < 48) {
	354	offset = GIUPODATL;
	355	mask = (uint16_t)1 << (pin - 32);
	356	} else {
	357	offset = GIUPODATH;
	358	mask = (uint16_t)1 << (pin - 48);
	359	}
	360
	361	spin_lock_irqsave(&giu_lock, flags);
	362
	363	reg = giu_read(offset);
	364	if (data == GPIO_DATA_HIGH)
	365	reg \|= mask;
	366	else
	367	reg &= ~mask;
	368	giu_write(offset, reg);
	369
	370	spin_unlock_irqrestore(&giu_lock, flags);
	371
	372	return 0;
	373	}
e400bae9 YY	374	EXPORT_SYMBOL_GPL(vr41xx_gpio_set_pin);
	375
	376	int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir)
	377	{
	378	uint16_t offset, mask, reg;
	379	unsigned long flags;
	380
	381	if (pin >= giu_nr_pins)
	382	return -EINVAL;
	383
	384	if (pin < 16) {
	385	offset = GIUIOSELL;
	386	mask = (uint16_t)1 << pin;
	387	} else if (pin < 32) {
	388	offset = GIUIOSELH;
	389	mask = (uint16_t)1 << (pin - 16);
	390	} else {
	391	if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
	392	offset = GIUPODATEN;
	393	mask = (uint16_t)1 << (pin - 32);
	394	} else {
	395	switch (pin) {
	396	case 48:
	397	offset = GIUPODATH;
	398	mask = PIOEN0;
	399	break;
	400	case 49:
	401	offset = GIUPODATH;
	402	mask = PIOEN1;
	403	break;
	404	default:
	405	return -EINVAL;
	406	}
	407	}
	408	}
	409
	410	spin_lock_irqsave(&giu_lock, flags);
	411
	412	reg = giu_read(offset);
	413	if (dir == GPIO_OUTPUT)
	414	reg \|= mask;
	415	else
	416	reg &= ~mask;
	417	giu_write(offset, reg);
	418
	419	spin_unlock_irqrestore(&giu_lock, flags);
	420
	421	return 0;
	422	}
e400bae9 YY	423	EXPORT_SYMBOL_GPL(vr41xx_gpio_set_direction);
	424
	425	int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
	426	{
	427	uint16_t reg, mask;
	428	unsigned long flags;
	429
	430	if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
	431	return -EPERM;
	432
	433	if (pin >= 15)
	434	return -EINVAL;
	435
	436	mask = (uint16_t)1 << pin;
	437
	438	spin_lock_irqsave(&giu_lock, flags);
	439
	440	if (pull == GPIO_PULL_UP \|\| pull == GPIO_PULL_DOWN) {
	441	reg = giu_read(GIUTERMUPDN);
	442	if (pull == GPIO_PULL_UP)
	443	reg \|= mask;
	444	else
	445	reg &= ~mask;
	446	giu_write(GIUTERMUPDN, reg);
	447
	448	reg = giu_read(GIUUSEUPDN);
	449	reg \|= mask;
	450	giu_write(GIUUSEUPDN, reg);
	451	} else {
	452	reg = giu_read(GIUUSEUPDN);
	453	reg &= ~mask;
	454	giu_write(GIUUSEUPDN, reg);
	455	}
	456
	457	spin_unlock_irqrestore(&giu_lock, flags);
	458
	459	return 0;
	460	}
e400bae9 YY	461	EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
	462
	463	static ssize_t gpio_read(struct file file, char __user buf, size_t len,
	464	loff_t *ppos)
	465	{
	466	unsigned int pin;
	467	char value = '0';
	468
a7113a96	469	pin = iminor(file->f_path.dentry->d_inode);
e400bae9 YY	470	if (pin >= giu_nr_pins)
	471	return -EBADF;
	472
	473	if (vr41xx_gpio_get_pin(pin) == GPIO_DATA_HIGH)
	474	value = '1';
	475
	476	if (len <= 0)
	477	return -EFAULT;
	478
	479	if (put_user(value, buf))
	480	return -EFAULT;
	481
	482	return 1;
	483	}
	484
	485	static ssize_t gpio_write(struct file file, const char __user data,
	486	size_t len, loff_t *ppos)
	487	{
	488	unsigned int pin;
	489	size_t i;
	490	char c;
	491	int retval = 0;
	492
a7113a96	493	pin = iminor(file->f_path.dentry->d_inode);
e400bae9 YY	494	if (pin >= giu_nr_pins)
	495	return -EBADF;
	496
	497	for (i = 0; i < len; i++) {
	498	if (get_user(c, data + i))
	499	return -EFAULT;
	500
	501	switch (c) {
	502	case '0':
	503	retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_LOW);
	504	break;
	505	case '1':
	506	retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_HIGH);
	507	break;
	508	case 'D':
	509	printk(KERN_INFO "GPIO%d: pull down\n", pin);
	510	retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DOWN);
	511	break;
	512	case 'd':
	513	printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
	514	retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
	515	break;
	516	case 'I':
	517	printk(KERN_INFO "GPIO%d: input\n", pin);
	518	retval = vr41xx_gpio_set_direction(pin, GPIO_INPUT);
	519	break;
	520	case 'O':
	521	printk(KERN_INFO "GPIO%d: output\n", pin);
	522	retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT);
	523	break;
	524	case 'o':
	525	printk(KERN_INFO "GPIO%d: output disable\n", pin);
	526	retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT_DISABLE);
	527	break;
	528	case 'P':
	529	printk(KERN_INFO "GPIO%d: pull up\n", pin);
	530	retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_UP);
	531	break;
	532	case 'p':
	533	printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
	534	retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
	535	break;
	536	default:
	537	break;
	538	}
	539
	540	if (retval < 0)
	541	break;
	542	}
	543
	544	return i;
	545	}
	546
	547	static int gpio_open(struct inode inode, struct file file)
	548	{
	549	unsigned int pin;
	550
f2b9857e	551	cycle_kernel_lock();
e400bae9 YY	552	pin = iminor(inode);
	553	if (pin >= giu_nr_pins)
	554	return -EBADF;
	555
	556	return nonseekable_open(inode, file);
	557	}
	558
	559	static int gpio_release(struct inode inode, struct file file)
	560	{
	561	unsigned int pin;
	562
	563	pin = iminor(inode);
	564	if (pin >= giu_nr_pins)
	565	return -EBADF;
	566
	567	return 0;
	568	}
	569
62322d25	570	static const struct file_operations gpio_fops = {
e400bae9 YY	571	.owner = THIS_MODULE,
	572	.read = gpio_read,
	573	.write = gpio_write,
	574	.open = gpio_open,
	575	.release = gpio_release,
	576	};
	577
d39b6cfe	578	static int __devinit giu_probe(struct platform_device *dev)
e400bae9	579	{
44173fb2 YY	580	struct resource *res;
44173fb2 YY	581	unsigned int trigger, i, pin;
364ca8a8	582	struct irq_chip *chip;
44173fb2 YY	583	int irq, retval;
	584
	585	switch (dev->id) {
	586	case GPIO_50PINS_PULLUPDOWN:
	587	giu_flags = GPIO_HAS_PULLUPDOWN_IO;
	588	giu_nr_pins = 50;
e400bae9	589	break;
44173fb2 YY	590	case GPIO_36PINS:
44173fb2 YY	591	giu_nr_pins = 36;
e400bae9	592	break;
44173fb2 YY	593	case GPIO_48PINS_EDGE_SELECT:
	594	giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
	595	giu_nr_pins = 48;
e400bae9 YY	596	break;
e400bae9 YY	597	default:
44173fb2	598	printk(KERN_ERR "GIU: unknown ID %d\n", dev->id);
e400bae9 YY	599	return -ENODEV;
	600	}
	601
44173fb2 YY	602	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
44173fb2 YY	603	if (!res)
e400bae9 YY	604	return -EBUSY;
e400bae9 YY	605
44173fb2 YY	606	giu_base = ioremap(res->start, res->end - res->start + 1);
44173fb2 YY	607	if (!giu_base)
e400bae9	608	return -ENOMEM;
e400bae9 YY	609
	610	retval = register_chrdev(major, "GIU", &gpio_fops);
	611	if (retval < 0) {
44173fb2 YY	612	iounmap(giu_base);
44173fb2 YY	613	giu_base = NULL;
e400bae9 YY	614	return retval;
	615	}
	616
	617	if (major == 0) {
	618	major = retval;
	619	printk(KERN_INFO "GIU: major number %d\n", major);
	620	}
	621
	622	spin_lock_init(&giu_lock);
e400bae9 YY	623
	624	giu_write(GIUINTENL, 0);
	625	giu_write(GIUINTENH, 0);
	626
364ca8a8 YY	627	trigger = giu_read(GIUINTTYPH) << 16;
364ca8a8 YY	628	trigger \|= giu_read(GIUINTTYPL);
e400bae9	629	for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
364ca8a8 YY	630	pin = GPIO_PIN_OF_IRQ(i);
	631	if (pin < GIUINT_HIGH_OFFSET)
	632	chip = &giuint_low_irq_chip;
e400bae9	633	else
364ca8a8 YY	634	chip = &giuint_high_irq_chip;
	635
	636	if (trigger & (1 << pin))
	637	set_irq_chip_and_handler(i, chip, handle_edge_irq);
	638	else
	639	set_irq_chip_and_handler(i, chip, handle_level_irq);
	640
e400bae9 YY	641	}
e400bae9 YY	642
44173fb2 YY	643	irq = platform_get_irq(dev, 0);
	644	if (irq < 0 \|\| irq >= NR_IRQS)
	645	return -EBUSY;
	646
	647	return cascade_irq(irq, giu_get_irq);
e400bae9 YY	648	}
e400bae9 YY	649
d39b6cfe	650	static int __devexit giu_remove(struct platform_device *dev)
e400bae9	651	{
44173fb2 YY	652	if (giu_base) {
	653	iounmap(giu_base);
	654	giu_base = NULL;
	655	}
e400bae9 YY	656
	657	return 0;
	658	}
	659
3ae5eaec	660	static struct platform_driver giu_device_driver = {
e400bae9	661	.probe = giu_probe,
d39b6cfe	662	.remove = __devexit_p(giu_remove),
3ae5eaec RK	663	.driver = {
3ae5eaec RK	664	.name = "GIU",
d39b6cfe	665	.owner = THIS_MODULE,
3ae5eaec	666	},
e400bae9 YY	667	};
e400bae9 YY	668
e701e85b	669	static int __init vr41xx_giu_init(void)
e400bae9	670	{
44173fb2	671	return platform_driver_register(&giu_device_driver);
e400bae9 YY	672	}
e400bae9 YY	673
e701e85b	674	static void __exit vr41xx_giu_exit(void)
e400bae9	675	{
3ae5eaec	676	platform_driver_unregister(&giu_device_driver);
e400bae9 YY	677	}
	678
	679	module_init(vr41xx_giu_init);
	680	module_exit(vr41xx_giu_exit);