Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2004 IBM Corporation | |
3 | * | |
4 | * Authors: | |
5 | * Leendert van Doorn <leendert@watson.ibm.com> | |
6 | * Dave Safford <safford@watson.ibm.com> | |
7 | * Reiner Sailer <sailer@watson.ibm.com> | |
8 | * Kylene Hall <kjhall@us.ibm.com> | |
9 | * | |
8e81cc13 | 10 | * Maintained by: <tpmdd-devel@lists.sourceforge.net> |
1da177e4 LT |
11 | * |
12 | * Device driver for TCG/TCPA TPM (trusted platform module). | |
13 | * Specifications at www.trustedcomputinggroup.org | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation, version 2 of the | |
18 | * License. | |
19 | * | |
20 | */ | |
21 | ||
faba278f | 22 | #include <linux/platform_device.h> |
1da177e4 LT |
23 | #include "tpm.h" |
24 | ||
25 | /* National definitions */ | |
e1a23c66 | 26 | enum tpm_nsc_addr{ |
e1a23c66 KH |
27 | TPM_NSC_IRQ = 0x07, |
28 | TPM_NSC_BASE0_HI = 0x60, | |
29 | TPM_NSC_BASE0_LO = 0x61, | |
30 | TPM_NSC_BASE1_HI = 0x62, | |
31 | TPM_NSC_BASE1_LO = 0x63 | |
3122a88a | 32 | }; |
1da177e4 | 33 | |
3122a88a KH |
34 | enum tpm_nsc_index { |
35 | NSC_LDN_INDEX = 0x07, | |
36 | NSC_SID_INDEX = 0x20, | |
37 | NSC_LDC_INDEX = 0x30, | |
38 | NSC_DIO_INDEX = 0x60, | |
39 | NSC_CIO_INDEX = 0x62, | |
40 | NSC_IRQ_INDEX = 0x70, | |
41 | NSC_ITS_INDEX = 0x71 | |
42 | }; | |
1da177e4 | 43 | |
3122a88a KH |
44 | enum tpm_nsc_status_loc { |
45 | NSC_STATUS = 0x01, | |
46 | NSC_COMMAND = 0x01, | |
47 | NSC_DATA = 0x00 | |
48 | }; | |
1da177e4 LT |
49 | |
50 | /* status bits */ | |
e1a23c66 | 51 | enum tpm_nsc_status { |
3122a88a KH |
52 | NSC_STATUS_OBF = 0x01, /* output buffer full */ |
53 | NSC_STATUS_IBF = 0x02, /* input buffer full */ | |
54 | NSC_STATUS_F0 = 0x04, /* F0 */ | |
55 | NSC_STATUS_A2 = 0x08, /* A2 */ | |
56 | NSC_STATUS_RDY = 0x10, /* ready to receive command */ | |
57 | NSC_STATUS_IBR = 0x20 /* ready to receive data */ | |
58 | }; | |
daacdfa6 | 59 | |
1da177e4 | 60 | /* command bits */ |
3122a88a KH |
61 | enum tpm_nsc_cmd_mode { |
62 | NSC_COMMAND_NORMAL = 0x01, /* normal mode */ | |
63 | NSC_COMMAND_EOC = 0x03, | |
64 | NSC_COMMAND_CANCEL = 0x22 | |
65 | }; | |
1da177e4 LT |
66 | /* |
67 | * Wait for a certain status to appear | |
68 | */ | |
69 | static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data) | |
70 | { | |
700d8bdc | 71 | unsigned long stop; |
1da177e4 LT |
72 | |
73 | /* status immediately available check */ | |
90dda520 | 74 | *data = inb(chip->vendor.base + NSC_STATUS); |
1da177e4 LT |
75 | if ((*data & mask) == val) |
76 | return 0; | |
77 | ||
78 | /* wait for status */ | |
700d8bdc | 79 | stop = jiffies + 10 * HZ; |
1da177e4 | 80 | do { |
700d8bdc | 81 | msleep(TPM_TIMEOUT); |
90dda520 | 82 | *data = inb(chip->vendor.base + 1); |
700d8bdc | 83 | if ((*data & mask) == val) |
1da177e4 | 84 | return 0; |
1da177e4 | 85 | } |
700d8bdc | 86 | while (time_before(jiffies, stop)); |
1da177e4 LT |
87 | |
88 | return -EBUSY; | |
89 | } | |
90 | ||
91 | static int nsc_wait_for_ready(struct tpm_chip *chip) | |
92 | { | |
93 | int status; | |
700d8bdc | 94 | unsigned long stop; |
1da177e4 LT |
95 | |
96 | /* status immediately available check */ | |
90dda520 | 97 | status = inb(chip->vendor.base + NSC_STATUS); |
1da177e4 | 98 | if (status & NSC_STATUS_OBF) |
90dda520 | 99 | status = inb(chip->vendor.base + NSC_DATA); |
1da177e4 LT |
100 | if (status & NSC_STATUS_RDY) |
101 | return 0; | |
102 | ||
103 | /* wait for status */ | |
700d8bdc | 104 | stop = jiffies + 100; |
1da177e4 | 105 | do { |
700d8bdc | 106 | msleep(TPM_TIMEOUT); |
90dda520 | 107 | status = inb(chip->vendor.base + NSC_STATUS); |
1da177e4 | 108 | if (status & NSC_STATUS_OBF) |
90dda520 | 109 | status = inb(chip->vendor.base + NSC_DATA); |
700d8bdc | 110 | if (status & NSC_STATUS_RDY) |
1da177e4 | 111 | return 0; |
1da177e4 | 112 | } |
700d8bdc | 113 | while (time_before(jiffies, stop)); |
1da177e4 | 114 | |
e659a3fe | 115 | dev_info(chip->dev, "wait for ready failed\n"); |
1da177e4 LT |
116 | return -EBUSY; |
117 | } | |
118 | ||
119 | ||
120 | static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count) | |
121 | { | |
122 | u8 *buffer = buf; | |
123 | u8 data, *p; | |
124 | u32 size; | |
125 | __be32 *native_size; | |
126 | ||
127 | if (count < 6) | |
128 | return -EIO; | |
129 | ||
130 | if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) { | |
e659a3fe | 131 | dev_err(chip->dev, "F0 timeout\n"); |
1da177e4 LT |
132 | return -EIO; |
133 | } | |
134 | if ((data = | |
90dda520 | 135 | inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) { |
e659a3fe | 136 | dev_err(chip->dev, "not in normal mode (0x%x)\n", |
1da177e4 LT |
137 | data); |
138 | return -EIO; | |
139 | } | |
140 | ||
141 | /* read the whole packet */ | |
142 | for (p = buffer; p < &buffer[count]; p++) { | |
143 | if (wait_for_stat | |
144 | (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) { | |
e659a3fe | 145 | dev_err(chip->dev, |
1da177e4 LT |
146 | "OBF timeout (while reading data)\n"); |
147 | return -EIO; | |
148 | } | |
149 | if (data & NSC_STATUS_F0) | |
150 | break; | |
90dda520 | 151 | *p = inb(chip->vendor.base + NSC_DATA); |
1da177e4 LT |
152 | } |
153 | ||
daacdfa6 KJH |
154 | if ((data & NSC_STATUS_F0) == 0 && |
155 | (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) { | |
e659a3fe | 156 | dev_err(chip->dev, "F0 not set\n"); |
1da177e4 LT |
157 | return -EIO; |
158 | } | |
90dda520 | 159 | if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) { |
e659a3fe | 160 | dev_err(chip->dev, |
1da177e4 LT |
161 | "expected end of command(0x%x)\n", data); |
162 | return -EIO; | |
163 | } | |
164 | ||
165 | native_size = (__force __be32 *) (buf + 2); | |
166 | size = be32_to_cpu(*native_size); | |
167 | ||
168 | if (count < size) | |
169 | return -EIO; | |
170 | ||
171 | return size; | |
172 | } | |
173 | ||
174 | static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count) | |
175 | { | |
176 | u8 data; | |
177 | int i; | |
178 | ||
179 | /* | |
180 | * If we hit the chip with back to back commands it locks up | |
181 | * and never set IBF. Hitting it with this "hammer" seems to | |
182 | * fix it. Not sure why this is needed, we followed the flow | |
183 | * chart in the manual to the letter. | |
184 | */ | |
90dda520 | 185 | outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND); |
1da177e4 LT |
186 | |
187 | if (nsc_wait_for_ready(chip) != 0) | |
188 | return -EIO; | |
189 | ||
190 | if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { | |
e659a3fe | 191 | dev_err(chip->dev, "IBF timeout\n"); |
1da177e4 LT |
192 | return -EIO; |
193 | } | |
194 | ||
90dda520 | 195 | outb(NSC_COMMAND_NORMAL, chip->vendor.base + NSC_COMMAND); |
1da177e4 | 196 | if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) { |
e659a3fe | 197 | dev_err(chip->dev, "IBR timeout\n"); |
1da177e4 LT |
198 | return -EIO; |
199 | } | |
200 | ||
201 | for (i = 0; i < count; i++) { | |
202 | if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { | |
e659a3fe | 203 | dev_err(chip->dev, |
1da177e4 LT |
204 | "IBF timeout (while writing data)\n"); |
205 | return -EIO; | |
206 | } | |
90dda520 | 207 | outb(buf[i], chip->vendor.base + NSC_DATA); |
1da177e4 LT |
208 | } |
209 | ||
210 | if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { | |
e659a3fe | 211 | dev_err(chip->dev, "IBF timeout\n"); |
1da177e4 LT |
212 | return -EIO; |
213 | } | |
90dda520 | 214 | outb(NSC_COMMAND_EOC, chip->vendor.base + NSC_COMMAND); |
1da177e4 LT |
215 | |
216 | return count; | |
217 | } | |
218 | ||
219 | static void tpm_nsc_cancel(struct tpm_chip *chip) | |
220 | { | |
90dda520 | 221 | outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND); |
1da177e4 LT |
222 | } |
223 | ||
b4ed3e3c KJH |
224 | static u8 tpm_nsc_status(struct tpm_chip *chip) |
225 | { | |
90dda520 | 226 | return inb(chip->vendor.base + NSC_STATUS); |
b4ed3e3c KJH |
227 | } |
228 | ||
62322d25 | 229 | static const struct file_operations nsc_ops = { |
1da177e4 LT |
230 | .owner = THIS_MODULE, |
231 | .llseek = no_llseek, | |
232 | .open = tpm_open, | |
233 | .read = tpm_read, | |
234 | .write = tpm_write, | |
235 | .release = tpm_release, | |
236 | }; | |
237 | ||
6659ca2a KH |
238 | static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL); |
239 | static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL); | |
240 | static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL); | |
241 | static DEVICE_ATTR(cancel, S_IWUSR|S_IWGRP, NULL, tpm_store_cancel); | |
242 | ||
243 | static struct attribute * nsc_attrs[] = { | |
244 | &dev_attr_pubek.attr, | |
245 | &dev_attr_pcrs.attr, | |
246 | &dev_attr_caps.attr, | |
247 | &dev_attr_cancel.attr, | |
874ec33f | 248 | NULL, |
6659ca2a KH |
249 | }; |
250 | ||
251 | static struct attribute_group nsc_attr_grp = { .attrs = nsc_attrs }; | |
252 | ||
e0dd03ca | 253 | static const struct tpm_vendor_specific tpm_nsc = { |
1da177e4 LT |
254 | .recv = tpm_nsc_recv, |
255 | .send = tpm_nsc_send, | |
256 | .cancel = tpm_nsc_cancel, | |
b4ed3e3c | 257 | .status = tpm_nsc_status, |
1da177e4 LT |
258 | .req_complete_mask = NSC_STATUS_OBF, |
259 | .req_complete_val = NSC_STATUS_OBF, | |
d9e5b6bf | 260 | .req_canceled = NSC_STATUS_RDY, |
6659ca2a | 261 | .attr_group = &nsc_attr_grp, |
1da177e4 | 262 | .miscdev = { .fops = &nsc_ops, }, |
1da177e4 LT |
263 | }; |
264 | ||
570302a3 KJH |
265 | static struct platform_device *pdev = NULL; |
266 | ||
4821cd11 | 267 | static void tpm_nsc_remove(struct device *dev) |
570302a3 KJH |
268 | { |
269 | struct tpm_chip *chip = dev_get_drvdata(dev); | |
270 | if ( chip ) { | |
90dda520 | 271 | release_region(chip->vendor.base, 2); |
570302a3 KJH |
272 | tpm_remove_hardware(chip->dev); |
273 | } | |
274 | } | |
275 | ||
09f50c95 DS |
276 | static int tpm_nsc_suspend(struct platform_device *dev, pm_message_t msg) |
277 | { | |
278 | return tpm_pm_suspend(&dev->dev, msg); | |
279 | } | |
280 | ||
281 | static int tpm_nsc_resume(struct platform_device *dev) | |
282 | { | |
283 | return tpm_pm_resume(&dev->dev); | |
284 | } | |
285 | ||
286 | static struct platform_driver nsc_drv = { | |
287 | .suspend = tpm_nsc_suspend, | |
288 | .resume = tpm_nsc_resume, | |
289 | .driver = { | |
290 | .name = "tpm_nsc", | |
291 | .owner = THIS_MODULE, | |
292 | }, | |
570302a3 KJH |
293 | }; |
294 | ||
295 | static int __init init_nsc(void) | |
1da177e4 LT |
296 | { |
297 | int rc = 0; | |
f33d9bd5 | 298 | int lo, hi, err; |
daacdfa6 | 299 | int nscAddrBase = TPM_ADDR; |
e0dd03ca KJH |
300 | struct tpm_chip *chip; |
301 | unsigned long base; | |
daacdfa6 | 302 | |
1da177e4 | 303 | /* verify that it is a National part (SID) */ |
daacdfa6 KJH |
304 | if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) { |
305 | nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)| | |
306 | (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE); | |
570302a3 KJH |
307 | if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6) |
308 | return -ENODEV; | |
1da177e4 LT |
309 | } |
310 | ||
09f50c95 | 311 | err = platform_driver_register(&nsc_drv); |
f33d9bd5 JG |
312 | if (err) |
313 | return err; | |
e2a8f7a1 | 314 | |
daacdfa6 KJH |
315 | hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI); |
316 | lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO); | |
e0dd03ca | 317 | base = (hi<<8) | lo; |
daacdfa6 | 318 | |
570302a3 KJH |
319 | /* enable the DPM module */ |
320 | tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01); | |
321 | ||
09f50c95 | 322 | pdev = platform_device_alloc("tpm_nscl0", -1); |
e2a8f7a1 KJH |
323 | if (!pdev) { |
324 | rc = -ENOMEM; | |
325 | goto err_unreg_drv; | |
326 | } | |
570302a3 | 327 | |
570302a3 | 328 | pdev->num_resources = 0; |
09f50c95 | 329 | pdev->dev.driver = &nsc_drv.driver; |
570302a3 | 330 | pdev->dev.release = tpm_nsc_remove; |
570302a3 | 331 | |
e2a8f7a1 KJH |
332 | if ((rc = platform_device_register(pdev)) < 0) |
333 | goto err_free_dev; | |
570302a3 | 334 | |
e0dd03ca | 335 | if (request_region(base, 2, "tpm_nsc0") == NULL ) { |
e2a8f7a1 KJH |
336 | rc = -EBUSY; |
337 | goto err_unreg_dev; | |
570302a3 KJH |
338 | } |
339 | ||
e0dd03ca KJH |
340 | if (!(chip = tpm_register_hardware(&pdev->dev, &tpm_nsc))) { |
341 | rc = -ENODEV; | |
e2a8f7a1 | 342 | goto err_rel_reg; |
e0dd03ca | 343 | } |
570302a3 KJH |
344 | |
345 | dev_dbg(&pdev->dev, "NSC TPM detected\n"); | |
346 | dev_dbg(&pdev->dev, | |
1da177e4 | 347 | "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n", |
daacdfa6 KJH |
348 | tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20), |
349 | tpm_read_index(nscAddrBase,0x27)); | |
570302a3 | 350 | dev_dbg(&pdev->dev, |
1da177e4 | 351 | "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n", |
daacdfa6 KJH |
352 | tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25), |
353 | tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28)); | |
570302a3 | 354 | dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n", |
daacdfa6 | 355 | (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61)); |
570302a3 | 356 | dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n", |
daacdfa6 | 357 | (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63)); |
570302a3 | 358 | dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n", |
daacdfa6 | 359 | tpm_read_index(nscAddrBase,0x70)); |
570302a3 | 360 | dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n", |
daacdfa6 | 361 | tpm_read_index(nscAddrBase,0x71)); |
570302a3 | 362 | dev_dbg(&pdev->dev, |
1da177e4 | 363 | "NSC DMA channel select0 0x%x, select1 0x%x\n", |
daacdfa6 | 364 | tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75)); |
570302a3 | 365 | dev_dbg(&pdev->dev, |
1da177e4 LT |
366 | "NSC Config " |
367 | "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", | |
daacdfa6 KJH |
368 | tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1), |
369 | tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3), | |
370 | tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5), | |
371 | tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7), | |
372 | tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9)); | |
1da177e4 | 373 | |
570302a3 | 374 | dev_info(&pdev->dev, |
daacdfa6 KJH |
375 | "NSC TPM revision %d\n", |
376 | tpm_read_index(nscAddrBase, 0x27) & 0x1F); | |
1da177e4 | 377 | |
e0dd03ca KJH |
378 | chip->vendor.base = base; |
379 | ||
1da177e4 | 380 | return 0; |
e2a8f7a1 KJH |
381 | |
382 | err_rel_reg: | |
e0dd03ca | 383 | release_region(base, 2); |
e2a8f7a1 KJH |
384 | err_unreg_dev: |
385 | platform_device_unregister(pdev); | |
386 | err_free_dev: | |
387 | kfree(pdev); | |
388 | err_unreg_drv: | |
09f50c95 | 389 | platform_driver_unregister(&nsc_drv); |
e2a8f7a1 | 390 | return rc; |
1da177e4 LT |
391 | } |
392 | ||
393 | static void __exit cleanup_nsc(void) | |
394 | { | |
570302a3 KJH |
395 | if (pdev) { |
396 | tpm_nsc_remove(&pdev->dev); | |
397 | platform_device_unregister(pdev); | |
398 | kfree(pdev); | |
399 | pdev = NULL; | |
400 | } | |
401 | ||
09f50c95 | 402 | platform_driver_unregister(&nsc_drv); |
1da177e4 LT |
403 | } |
404 | ||
405 | module_init(init_nsc); | |
406 | module_exit(cleanup_nsc); | |
407 | ||
408 | MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)"); | |
409 | MODULE_DESCRIPTION("TPM Driver"); | |
410 | MODULE_VERSION("2.0"); | |
411 | MODULE_LICENSE("GPL"); |