Commit | Line | Data |
---|---|---|
705b6c7b | 1 | /* |
705b6c7b PF |
2 | * Device driver for Microgate SyncLink GT serial adapters. |
3 | * | |
4 | * written by Paul Fulghum for Microgate Corporation | |
5 | * paulkf@microgate.com | |
6 | * | |
7 | * Microgate and SyncLink are trademarks of Microgate Corporation | |
8 | * | |
9 | * This code is released under the GNU General Public License (GPL) | |
10 | * | |
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
13 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
14 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |
15 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
16 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
17 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
18 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
19 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
20 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
21 | * OF THE POSSIBILITY OF SUCH DAMAGE. | |
22 | */ | |
23 | ||
24 | /* | |
25 | * DEBUG OUTPUT DEFINITIONS | |
26 | * | |
27 | * uncomment lines below to enable specific types of debug output | |
28 | * | |
29 | * DBGINFO information - most verbose output | |
30 | * DBGERR serious errors | |
31 | * DBGBH bottom half service routine debugging | |
32 | * DBGISR interrupt service routine debugging | |
33 | * DBGDATA output receive and transmit data | |
34 | * DBGTBUF output transmit DMA buffers and registers | |
35 | * DBGRBUF output receive DMA buffers and registers | |
36 | */ | |
37 | ||
38 | #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt | |
39 | #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt | |
40 | #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt | |
41 | #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt | |
42 | #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) | |
f602501d AC |
43 | /*#define DBGTBUF(info) dump_tbufs(info)*/ |
44 | /*#define DBGRBUF(info) dump_rbufs(info)*/ | |
705b6c7b PF |
45 | |
46 | ||
705b6c7b | 47 | #include <linux/module.h> |
705b6c7b PF |
48 | #include <linux/errno.h> |
49 | #include <linux/signal.h> | |
50 | #include <linux/sched.h> | |
51 | #include <linux/timer.h> | |
52 | #include <linux/interrupt.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/tty.h> | |
55 | #include <linux/tty_flip.h> | |
56 | #include <linux/serial.h> | |
57 | #include <linux/major.h> | |
58 | #include <linux/string.h> | |
59 | #include <linux/fcntl.h> | |
60 | #include <linux/ptrace.h> | |
61 | #include <linux/ioport.h> | |
62 | #include <linux/mm.h> | |
a18c56e5 | 63 | #include <linux/seq_file.h> |
705b6c7b PF |
64 | #include <linux/slab.h> |
65 | #include <linux/netdevice.h> | |
66 | #include <linux/vmalloc.h> | |
67 | #include <linux/init.h> | |
68 | #include <linux/delay.h> | |
69 | #include <linux/ioctl.h> | |
70 | #include <linux/termios.h> | |
71 | #include <linux/bitops.h> | |
72 | #include <linux/workqueue.h> | |
73 | #include <linux/hdlc.h> | |
3dd1247f | 74 | #include <linux/synclink.h> |
705b6c7b | 75 | |
705b6c7b PF |
76 | #include <asm/system.h> |
77 | #include <asm/io.h> | |
78 | #include <asm/irq.h> | |
79 | #include <asm/dma.h> | |
80 | #include <asm/types.h> | |
81 | #include <asm/uaccess.h> | |
82 | ||
af69c7f9 PF |
83 | #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE)) |
84 | #define SYNCLINK_GENERIC_HDLC 1 | |
85 | #else | |
86 | #define SYNCLINK_GENERIC_HDLC 0 | |
705b6c7b PF |
87 | #endif |
88 | ||
89 | /* | |
90 | * module identification | |
91 | */ | |
92 | static char *driver_name = "SyncLink GT"; | |
705b6c7b PF |
93 | static char *tty_driver_name = "synclink_gt"; |
94 | static char *tty_dev_prefix = "ttySLG"; | |
95 | MODULE_LICENSE("GPL"); | |
96 | #define MGSL_MAGIC 0x5401 | |
a077c1a0 | 97 | #define MAX_DEVICES 32 |
705b6c7b PF |
98 | |
99 | static struct pci_device_id pci_table[] = { | |
100 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
6f84be84 | 101 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
705b6c7b PF |
102 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
103 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
104 | {0,}, /* terminate list */ | |
105 | }; | |
106 | MODULE_DEVICE_TABLE(pci, pci_table); | |
107 | ||
108 | static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); | |
109 | static void remove_one(struct pci_dev *dev); | |
110 | static struct pci_driver pci_driver = { | |
111 | .name = "synclink_gt", | |
112 | .id_table = pci_table, | |
113 | .probe = init_one, | |
114 | .remove = __devexit_p(remove_one), | |
115 | }; | |
116 | ||
0fab6de0 | 117 | static bool pci_registered; |
705b6c7b PF |
118 | |
119 | /* | |
120 | * module configuration and status | |
121 | */ | |
122 | static struct slgt_info *slgt_device_list; | |
123 | static int slgt_device_count; | |
124 | ||
125 | static int ttymajor; | |
126 | static int debug_level; | |
127 | static int maxframe[MAX_DEVICES]; | |
705b6c7b PF |
128 | |
129 | module_param(ttymajor, int, 0); | |
130 | module_param(debug_level, int, 0); | |
131 | module_param_array(maxframe, int, NULL, 0); | |
705b6c7b PF |
132 | |
133 | MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); | |
134 | MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); | |
135 | MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); | |
705b6c7b PF |
136 | |
137 | /* | |
138 | * tty support and callbacks | |
139 | */ | |
705b6c7b PF |
140 | static struct tty_driver *serial_driver; |
141 | ||
142 | static int open(struct tty_struct *tty, struct file * filp); | |
143 | static void close(struct tty_struct *tty, struct file * filp); | |
144 | static void hangup(struct tty_struct *tty); | |
606d099c | 145 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); |
705b6c7b PF |
146 | |
147 | static int write(struct tty_struct *tty, const unsigned char *buf, int count); | |
55da7789 | 148 | static int put_char(struct tty_struct *tty, unsigned char ch); |
705b6c7b PF |
149 | static void send_xchar(struct tty_struct *tty, char ch); |
150 | static void wait_until_sent(struct tty_struct *tty, int timeout); | |
151 | static int write_room(struct tty_struct *tty); | |
152 | static void flush_chars(struct tty_struct *tty); | |
153 | static void flush_buffer(struct tty_struct *tty); | |
154 | static void tx_hold(struct tty_struct *tty); | |
155 | static void tx_release(struct tty_struct *tty); | |
156 | ||
157 | static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg); | |
705b6c7b PF |
158 | static int chars_in_buffer(struct tty_struct *tty); |
159 | static void throttle(struct tty_struct * tty); | |
160 | static void unthrottle(struct tty_struct * tty); | |
9e98966c | 161 | static int set_break(struct tty_struct *tty, int break_state); |
705b6c7b PF |
162 | |
163 | /* | |
164 | * generic HDLC support and callbacks | |
165 | */ | |
af69c7f9 | 166 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
167 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) |
168 | static void hdlcdev_tx_done(struct slgt_info *info); | |
169 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size); | |
170 | static int hdlcdev_init(struct slgt_info *info); | |
171 | static void hdlcdev_exit(struct slgt_info *info); | |
172 | #endif | |
173 | ||
174 | ||
175 | /* | |
176 | * device specific structures, macros and functions | |
177 | */ | |
178 | ||
179 | #define SLGT_MAX_PORTS 4 | |
180 | #define SLGT_REG_SIZE 256 | |
181 | ||
0080b7aa PF |
182 | /* |
183 | * conditional wait facility | |
184 | */ | |
185 | struct cond_wait { | |
186 | struct cond_wait *next; | |
187 | wait_queue_head_t q; | |
188 | wait_queue_t wait; | |
189 | unsigned int data; | |
190 | }; | |
191 | static void init_cond_wait(struct cond_wait *w, unsigned int data); | |
192 | static void add_cond_wait(struct cond_wait **head, struct cond_wait *w); | |
193 | static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w); | |
194 | static void flush_cond_wait(struct cond_wait **head); | |
195 | ||
705b6c7b PF |
196 | /* |
197 | * DMA buffer descriptor and access macros | |
198 | */ | |
199 | struct slgt_desc | |
200 | { | |
51ef9c57 AV |
201 | __le16 count; |
202 | __le16 status; | |
203 | __le32 pbuf; /* physical address of data buffer */ | |
204 | __le32 next; /* physical address of next descriptor */ | |
705b6c7b PF |
205 | |
206 | /* driver book keeping */ | |
207 | char *buf; /* virtual address of data buffer */ | |
208 | unsigned int pdesc; /* physical address of this descriptor */ | |
209 | dma_addr_t buf_dma_addr; | |
403214d0 | 210 | unsigned short buf_count; |
705b6c7b PF |
211 | }; |
212 | ||
213 | #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) | |
214 | #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) | |
215 | #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) | |
216 | #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) | |
5ba5a5d2 | 217 | #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b)) |
705b6c7b PF |
218 | #define desc_count(a) (le16_to_cpu((a).count)) |
219 | #define desc_status(a) (le16_to_cpu((a).status)) | |
220 | #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) | |
221 | #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) | |
222 | #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) | |
223 | #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) | |
224 | #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) | |
225 | ||
226 | struct _input_signal_events { | |
227 | int ri_up; | |
228 | int ri_down; | |
229 | int dsr_up; | |
230 | int dsr_down; | |
231 | int dcd_up; | |
232 | int dcd_down; | |
233 | int cts_up; | |
234 | int cts_down; | |
235 | }; | |
236 | ||
237 | /* | |
238 | * device instance data structure | |
239 | */ | |
240 | struct slgt_info { | |
241 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | |
8fb06c77 | 242 | struct tty_port port; |
705b6c7b PF |
243 | |
244 | struct slgt_info *next_device; /* device list link */ | |
245 | ||
246 | int magic; | |
705b6c7b PF |
247 | |
248 | char device_name[25]; | |
249 | struct pci_dev *pdev; | |
250 | ||
251 | int port_count; /* count of ports on adapter */ | |
252 | int adapter_num; /* adapter instance number */ | |
253 | int port_num; /* port instance number */ | |
254 | ||
255 | /* array of pointers to port contexts on this adapter */ | |
256 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
257 | ||
705b6c7b | 258 | int line; /* tty line instance number */ |
705b6c7b PF |
259 | |
260 | struct mgsl_icount icount; | |
261 | ||
705b6c7b PF |
262 | int timeout; |
263 | int x_char; /* xon/xoff character */ | |
705b6c7b PF |
264 | unsigned int read_status_mask; |
265 | unsigned int ignore_status_mask; | |
266 | ||
705b6c7b PF |
267 | wait_queue_head_t status_event_wait_q; |
268 | wait_queue_head_t event_wait_q; | |
269 | struct timer_list tx_timer; | |
270 | struct timer_list rx_timer; | |
271 | ||
0080b7aa PF |
272 | unsigned int gpio_present; |
273 | struct cond_wait *gpio_wait_q; | |
274 | ||
705b6c7b PF |
275 | spinlock_t lock; /* spinlock for synchronizing with ISR */ |
276 | ||
277 | struct work_struct task; | |
278 | u32 pending_bh; | |
0fab6de0 JP |
279 | bool bh_requested; |
280 | bool bh_running; | |
705b6c7b PF |
281 | |
282 | int isr_overflow; | |
0fab6de0 JP |
283 | bool irq_requested; /* true if IRQ requested */ |
284 | bool irq_occurred; /* for diagnostics use */ | |
705b6c7b PF |
285 | |
286 | /* device configuration */ | |
287 | ||
288 | unsigned int bus_type; | |
289 | unsigned int irq_level; | |
290 | unsigned long irq_flags; | |
291 | ||
292 | unsigned char __iomem * reg_addr; /* memory mapped registers address */ | |
293 | u32 phys_reg_addr; | |
0fab6de0 | 294 | bool reg_addr_requested; |
705b6c7b PF |
295 | |
296 | MGSL_PARAMS params; /* communications parameters */ | |
297 | u32 idle_mode; | |
298 | u32 max_frame_size; /* as set by device config */ | |
299 | ||
814dae03 | 300 | unsigned int rbuf_fill_level; |
5ba5a5d2 | 301 | unsigned int rx_pio; |
705b6c7b | 302 | unsigned int if_mode; |
1f80769f | 303 | unsigned int base_clock; |
705b6c7b PF |
304 | |
305 | /* device status */ | |
306 | ||
0fab6de0 JP |
307 | bool rx_enabled; |
308 | bool rx_restart; | |
705b6c7b | 309 | |
0fab6de0 JP |
310 | bool tx_enabled; |
311 | bool tx_active; | |
705b6c7b PF |
312 | |
313 | unsigned char signals; /* serial signal states */ | |
2641dfd9 | 314 | int init_error; /* initialization error */ |
705b6c7b PF |
315 | |
316 | unsigned char *tx_buf; | |
317 | int tx_count; | |
318 | ||
319 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; | |
320 | char char_buf[MAX_ASYNC_BUFFER_SIZE]; | |
0fab6de0 | 321 | bool drop_rts_on_tx_done; |
705b6c7b PF |
322 | struct _input_signal_events input_signal_events; |
323 | ||
324 | int dcd_chkcount; /* check counts to prevent */ | |
325 | int cts_chkcount; /* too many IRQs if a signal */ | |
326 | int dsr_chkcount; /* is floating */ | |
327 | int ri_chkcount; | |
328 | ||
329 | char *bufs; /* virtual address of DMA buffer lists */ | |
330 | dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ | |
331 | ||
332 | unsigned int rbuf_count; | |
333 | struct slgt_desc *rbufs; | |
334 | unsigned int rbuf_current; | |
335 | unsigned int rbuf_index; | |
5ba5a5d2 PF |
336 | unsigned int rbuf_fill_index; |
337 | unsigned short rbuf_fill_count; | |
705b6c7b PF |
338 | |
339 | unsigned int tbuf_count; | |
340 | struct slgt_desc *tbufs; | |
341 | unsigned int tbuf_current; | |
342 | unsigned int tbuf_start; | |
343 | ||
344 | unsigned char *tmp_rbuf; | |
345 | unsigned int tmp_rbuf_count; | |
346 | ||
347 | /* SPPP/Cisco HDLC device parts */ | |
348 | ||
349 | int netcount; | |
705b6c7b | 350 | spinlock_t netlock; |
af69c7f9 | 351 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
352 | struct net_device *netdev; |
353 | #endif | |
354 | ||
355 | }; | |
356 | ||
357 | static MGSL_PARAMS default_params = { | |
358 | .mode = MGSL_MODE_HDLC, | |
359 | .loopback = 0, | |
360 | .flags = HDLC_FLAG_UNDERRUN_ABORT15, | |
361 | .encoding = HDLC_ENCODING_NRZI_SPACE, | |
362 | .clock_speed = 0, | |
363 | .addr_filter = 0xff, | |
364 | .crc_type = HDLC_CRC_16_CCITT, | |
365 | .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, | |
366 | .preamble = HDLC_PREAMBLE_PATTERN_NONE, | |
367 | .data_rate = 9600, | |
368 | .data_bits = 8, | |
369 | .stop_bits = 1, | |
370 | .parity = ASYNC_PARITY_NONE | |
371 | }; | |
372 | ||
373 | ||
374 | #define BH_RECEIVE 1 | |
375 | #define BH_TRANSMIT 2 | |
376 | #define BH_STATUS 4 | |
377 | #define IO_PIN_SHUTDOWN_LIMIT 100 | |
378 | ||
379 | #define DMABUFSIZE 256 | |
380 | #define DESC_LIST_SIZE 4096 | |
381 | ||
382 | #define MASK_PARITY BIT1 | |
202af6d5 PF |
383 | #define MASK_FRAMING BIT0 |
384 | #define MASK_BREAK BIT14 | |
705b6c7b PF |
385 | #define MASK_OVERRUN BIT4 |
386 | ||
387 | #define GSR 0x00 /* global status */ | |
0080b7aa PF |
388 | #define JCR 0x04 /* JTAG control */ |
389 | #define IODR 0x08 /* GPIO direction */ | |
390 | #define IOER 0x0c /* GPIO interrupt enable */ | |
391 | #define IOVR 0x10 /* GPIO value */ | |
392 | #define IOSR 0x14 /* GPIO interrupt status */ | |
705b6c7b PF |
393 | #define TDR 0x80 /* tx data */ |
394 | #define RDR 0x80 /* rx data */ | |
395 | #define TCR 0x82 /* tx control */ | |
396 | #define TIR 0x84 /* tx idle */ | |
397 | #define TPR 0x85 /* tx preamble */ | |
398 | #define RCR 0x86 /* rx control */ | |
399 | #define VCR 0x88 /* V.24 control */ | |
400 | #define CCR 0x89 /* clock control */ | |
401 | #define BDR 0x8a /* baud divisor */ | |
402 | #define SCR 0x8c /* serial control */ | |
403 | #define SSR 0x8e /* serial status */ | |
404 | #define RDCSR 0x90 /* rx DMA control/status */ | |
405 | #define TDCSR 0x94 /* tx DMA control/status */ | |
406 | #define RDDAR 0x98 /* rx DMA descriptor address */ | |
407 | #define TDDAR 0x9c /* tx DMA descriptor address */ | |
408 | ||
409 | #define RXIDLE BIT14 | |
410 | #define RXBREAK BIT14 | |
411 | #define IRQ_TXDATA BIT13 | |
412 | #define IRQ_TXIDLE BIT12 | |
413 | #define IRQ_TXUNDER BIT11 /* HDLC */ | |
414 | #define IRQ_RXDATA BIT10 | |
415 | #define IRQ_RXIDLE BIT9 /* HDLC */ | |
416 | #define IRQ_RXBREAK BIT9 /* async */ | |
417 | #define IRQ_RXOVER BIT8 | |
418 | #define IRQ_DSR BIT7 | |
419 | #define IRQ_CTS BIT6 | |
420 | #define IRQ_DCD BIT5 | |
421 | #define IRQ_RI BIT4 | |
422 | #define IRQ_ALL 0x3ff0 | |
423 | #define IRQ_MASTER BIT0 | |
424 | ||
425 | #define slgt_irq_on(info, mask) \ | |
426 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) | |
427 | #define slgt_irq_off(info, mask) \ | |
428 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) | |
429 | ||
430 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); | |
431 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); | |
432 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); | |
433 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); | |
434 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); | |
435 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); | |
436 | ||
437 | static void msc_set_vcr(struct slgt_info *info); | |
438 | ||
439 | static int startup(struct slgt_info *info); | |
440 | static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); | |
441 | static void shutdown(struct slgt_info *info); | |
442 | static void program_hw(struct slgt_info *info); | |
443 | static void change_params(struct slgt_info *info); | |
444 | ||
445 | static int register_test(struct slgt_info *info); | |
446 | static int irq_test(struct slgt_info *info); | |
447 | static int loopback_test(struct slgt_info *info); | |
448 | static int adapter_test(struct slgt_info *info); | |
449 | ||
450 | static void reset_adapter(struct slgt_info *info); | |
451 | static void reset_port(struct slgt_info *info); | |
452 | static void async_mode(struct slgt_info *info); | |
cb10dc9a | 453 | static void sync_mode(struct slgt_info *info); |
705b6c7b PF |
454 | |
455 | static void rx_stop(struct slgt_info *info); | |
456 | static void rx_start(struct slgt_info *info); | |
457 | static void reset_rbufs(struct slgt_info *info); | |
458 | static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); | |
459 | static void rdma_reset(struct slgt_info *info); | |
0fab6de0 JP |
460 | static bool rx_get_frame(struct slgt_info *info); |
461 | static bool rx_get_buf(struct slgt_info *info); | |
705b6c7b PF |
462 | |
463 | static void tx_start(struct slgt_info *info); | |
464 | static void tx_stop(struct slgt_info *info); | |
465 | static void tx_set_idle(struct slgt_info *info); | |
466 | static unsigned int free_tbuf_count(struct slgt_info *info); | |
403214d0 | 467 | static unsigned int tbuf_bytes(struct slgt_info *info); |
705b6c7b PF |
468 | static void reset_tbufs(struct slgt_info *info); |
469 | static void tdma_reset(struct slgt_info *info); | |
de538eb3 | 470 | static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count); |
705b6c7b PF |
471 | |
472 | static void get_signals(struct slgt_info *info); | |
473 | static void set_signals(struct slgt_info *info); | |
474 | static void enable_loopback(struct slgt_info *info); | |
475 | static void set_rate(struct slgt_info *info, u32 data_rate); | |
476 | ||
477 | static int bh_action(struct slgt_info *info); | |
c4028958 | 478 | static void bh_handler(struct work_struct *work); |
705b6c7b PF |
479 | static void bh_transmit(struct slgt_info *info); |
480 | static void isr_serial(struct slgt_info *info); | |
481 | static void isr_rdma(struct slgt_info *info); | |
482 | static void isr_txeom(struct slgt_info *info, unsigned short status); | |
483 | static void isr_tdma(struct slgt_info *info); | |
705b6c7b PF |
484 | |
485 | static int alloc_dma_bufs(struct slgt_info *info); | |
486 | static void free_dma_bufs(struct slgt_info *info); | |
487 | static int alloc_desc(struct slgt_info *info); | |
488 | static void free_desc(struct slgt_info *info); | |
489 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
490 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
491 | ||
492 | static int alloc_tmp_rbuf(struct slgt_info *info); | |
493 | static void free_tmp_rbuf(struct slgt_info *info); | |
494 | ||
495 | static void tx_timeout(unsigned long context); | |
496 | static void rx_timeout(unsigned long context); | |
497 | ||
498 | /* | |
499 | * ioctl handlers | |
500 | */ | |
501 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); | |
502 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
503 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
504 | static int get_txidle(struct slgt_info *info, int __user *idle_mode); | |
505 | static int set_txidle(struct slgt_info *info, int idle_mode); | |
506 | static int tx_enable(struct slgt_info *info, int enable); | |
507 | static int tx_abort(struct slgt_info *info); | |
508 | static int rx_enable(struct slgt_info *info, int enable); | |
509 | static int modem_input_wait(struct slgt_info *info,int arg); | |
510 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); | |
511 | static int tiocmget(struct tty_struct *tty, struct file *file); | |
512 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
513 | unsigned int set, unsigned int clear); | |
9e98966c | 514 | static int set_break(struct tty_struct *tty, int break_state); |
705b6c7b PF |
515 | static int get_interface(struct slgt_info *info, int __user *if_mode); |
516 | static int set_interface(struct slgt_info *info, int if_mode); | |
0080b7aa PF |
517 | static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); |
518 | static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); | |
519 | static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); | |
705b6c7b PF |
520 | |
521 | /* | |
522 | * driver functions | |
523 | */ | |
524 | static void add_device(struct slgt_info *info); | |
525 | static void device_init(int adapter_num, struct pci_dev *pdev); | |
526 | static int claim_resources(struct slgt_info *info); | |
527 | static void release_resources(struct slgt_info *info); | |
528 | ||
529 | /* | |
530 | * DEBUG OUTPUT CODE | |
531 | */ | |
532 | #ifndef DBGINFO | |
533 | #define DBGINFO(fmt) | |
534 | #endif | |
535 | #ifndef DBGERR | |
536 | #define DBGERR(fmt) | |
537 | #endif | |
538 | #ifndef DBGBH | |
539 | #define DBGBH(fmt) | |
540 | #endif | |
541 | #ifndef DBGISR | |
542 | #define DBGISR(fmt) | |
543 | #endif | |
544 | ||
545 | #ifdef DBGDATA | |
546 | static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) | |
547 | { | |
548 | int i; | |
549 | int linecount; | |
550 | printk("%s %s data:\n",info->device_name, label); | |
551 | while(count) { | |
552 | linecount = (count > 16) ? 16 : count; | |
553 | for(i=0; i < linecount; i++) | |
554 | printk("%02X ",(unsigned char)data[i]); | |
555 | for(;i<17;i++) | |
556 | printk(" "); | |
557 | for(i=0;i<linecount;i++) { | |
558 | if (data[i]>=040 && data[i]<=0176) | |
559 | printk("%c",data[i]); | |
560 | else | |
561 | printk("."); | |
562 | } | |
563 | printk("\n"); | |
564 | data += linecount; | |
565 | count -= linecount; | |
566 | } | |
567 | } | |
568 | #else | |
569 | #define DBGDATA(info, buf, size, label) | |
570 | #endif | |
571 | ||
572 | #ifdef DBGTBUF | |
573 | static void dump_tbufs(struct slgt_info *info) | |
574 | { | |
575 | int i; | |
576 | printk("tbuf_current=%d\n", info->tbuf_current); | |
577 | for (i=0 ; i < info->tbuf_count ; i++) { | |
578 | printk("%d: count=%04X status=%04X\n", | |
579 | i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); | |
580 | } | |
581 | } | |
582 | #else | |
583 | #define DBGTBUF(info) | |
584 | #endif | |
585 | ||
586 | #ifdef DBGRBUF | |
587 | static void dump_rbufs(struct slgt_info *info) | |
588 | { | |
589 | int i; | |
590 | printk("rbuf_current=%d\n", info->rbuf_current); | |
591 | for (i=0 ; i < info->rbuf_count ; i++) { | |
592 | printk("%d: count=%04X status=%04X\n", | |
593 | i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); | |
594 | } | |
595 | } | |
596 | #else | |
597 | #define DBGRBUF(info) | |
598 | #endif | |
599 | ||
600 | static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) | |
601 | { | |
602 | #ifdef SANITY_CHECK | |
603 | if (!info) { | |
604 | printk("null struct slgt_info for (%s) in %s\n", devname, name); | |
605 | return 1; | |
606 | } | |
607 | if (info->magic != MGSL_MAGIC) { | |
608 | printk("bad magic number struct slgt_info (%s) in %s\n", devname, name); | |
609 | return 1; | |
610 | } | |
611 | #else | |
612 | if (!info) | |
613 | return 1; | |
614 | #endif | |
615 | return 0; | |
616 | } | |
617 | ||
618 | /** | |
619 | * line discipline callback wrappers | |
620 | * | |
621 | * The wrappers maintain line discipline references | |
622 | * while calling into the line discipline. | |
623 | * | |
624 | * ldisc_receive_buf - pass receive data to line discipline | |
625 | */ | |
626 | static void ldisc_receive_buf(struct tty_struct *tty, | |
627 | const __u8 *data, char *flags, int count) | |
628 | { | |
629 | struct tty_ldisc *ld; | |
630 | if (!tty) | |
631 | return; | |
632 | ld = tty_ldisc_ref(tty); | |
633 | if (ld) { | |
a352def2 AC |
634 | if (ld->ops->receive_buf) |
635 | ld->ops->receive_buf(tty, data, flags, count); | |
705b6c7b PF |
636 | tty_ldisc_deref(ld); |
637 | } | |
638 | } | |
639 | ||
640 | /* tty callbacks */ | |
641 | ||
642 | static int open(struct tty_struct *tty, struct file *filp) | |
643 | { | |
644 | struct slgt_info *info; | |
645 | int retval, line; | |
646 | unsigned long flags; | |
647 | ||
648 | line = tty->index; | |
649 | if ((line < 0) || (line >= slgt_device_count)) { | |
650 | DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); | |
651 | return -ENODEV; | |
652 | } | |
653 | ||
654 | info = slgt_device_list; | |
655 | while(info && info->line != line) | |
656 | info = info->next_device; | |
657 | if (sanity_check(info, tty->name, "open")) | |
658 | return -ENODEV; | |
659 | if (info->init_error) { | |
660 | DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); | |
661 | return -ENODEV; | |
662 | } | |
663 | ||
664 | tty->driver_data = info; | |
8fb06c77 | 665 | info->port.tty = tty; |
705b6c7b | 666 | |
8fb06c77 | 667 | DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count)); |
705b6c7b PF |
668 | |
669 | /* If port is closing, signal caller to try again */ | |
8fb06c77 AC |
670 | if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){ |
671 | if (info->port.flags & ASYNC_CLOSING) | |
672 | interruptible_sleep_on(&info->port.close_wait); | |
673 | retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ? | |
705b6c7b PF |
674 | -EAGAIN : -ERESTARTSYS); |
675 | goto cleanup; | |
676 | } | |
677 | ||
8fb06c77 | 678 | info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; |
705b6c7b PF |
679 | |
680 | spin_lock_irqsave(&info->netlock, flags); | |
681 | if (info->netcount) { | |
682 | retval = -EBUSY; | |
683 | spin_unlock_irqrestore(&info->netlock, flags); | |
684 | goto cleanup; | |
685 | } | |
8fb06c77 | 686 | info->port.count++; |
705b6c7b PF |
687 | spin_unlock_irqrestore(&info->netlock, flags); |
688 | ||
8fb06c77 | 689 | if (info->port.count == 1) { |
705b6c7b PF |
690 | /* 1st open on this device, init hardware */ |
691 | retval = startup(info); | |
692 | if (retval < 0) | |
693 | goto cleanup; | |
694 | } | |
695 | ||
696 | retval = block_til_ready(tty, filp, info); | |
697 | if (retval) { | |
698 | DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); | |
699 | goto cleanup; | |
700 | } | |
701 | ||
702 | retval = 0; | |
703 | ||
704 | cleanup: | |
705 | if (retval) { | |
706 | if (tty->count == 1) | |
8fb06c77 AC |
707 | info->port.tty = NULL; /* tty layer will release tty struct */ |
708 | if(info->port.count) | |
709 | info->port.count--; | |
705b6c7b PF |
710 | } |
711 | ||
712 | DBGINFO(("%s open rc=%d\n", info->device_name, retval)); | |
713 | return retval; | |
714 | } | |
715 | ||
716 | static void close(struct tty_struct *tty, struct file *filp) | |
717 | { | |
718 | struct slgt_info *info = tty->driver_data; | |
719 | ||
720 | if (sanity_check(info, tty->name, "close")) | |
721 | return; | |
8fb06c77 | 722 | DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count)); |
705b6c7b | 723 | |
a6614999 | 724 | if (tty_port_close_start(&info->port, tty, filp) == 0) |
705b6c7b PF |
725 | goto cleanup; |
726 | ||
8fb06c77 | 727 | if (info->port.flags & ASYNC_INITIALIZED) |
705b6c7b | 728 | wait_until_sent(tty, info->timeout); |
978e595f | 729 | flush_buffer(tty); |
705b6c7b PF |
730 | tty_ldisc_flush(tty); |
731 | ||
732 | shutdown(info); | |
733 | ||
a6614999 | 734 | tty_port_close_end(&info->port, tty); |
8fb06c77 | 735 | info->port.tty = NULL; |
705b6c7b | 736 | cleanup: |
8fb06c77 | 737 | DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count)); |
705b6c7b PF |
738 | } |
739 | ||
740 | static void hangup(struct tty_struct *tty) | |
741 | { | |
742 | struct slgt_info *info = tty->driver_data; | |
743 | ||
744 | if (sanity_check(info, tty->name, "hangup")) | |
745 | return; | |
746 | DBGINFO(("%s hangup\n", info->device_name)); | |
747 | ||
748 | flush_buffer(tty); | |
749 | shutdown(info); | |
750 | ||
8fb06c77 AC |
751 | info->port.count = 0; |
752 | info->port.flags &= ~ASYNC_NORMAL_ACTIVE; | |
753 | info->port.tty = NULL; | |
705b6c7b | 754 | |
8fb06c77 | 755 | wake_up_interruptible(&info->port.open_wait); |
705b6c7b PF |
756 | } |
757 | ||
606d099c | 758 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
705b6c7b PF |
759 | { |
760 | struct slgt_info *info = tty->driver_data; | |
761 | unsigned long flags; | |
762 | ||
763 | DBGINFO(("%s set_termios\n", tty->driver->name)); | |
764 | ||
705b6c7b PF |
765 | change_params(info); |
766 | ||
767 | /* Handle transition to B0 status */ | |
768 | if (old_termios->c_cflag & CBAUD && | |
769 | !(tty->termios->c_cflag & CBAUD)) { | |
770 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
771 | spin_lock_irqsave(&info->lock,flags); | |
772 | set_signals(info); | |
773 | spin_unlock_irqrestore(&info->lock,flags); | |
774 | } | |
775 | ||
776 | /* Handle transition away from B0 status */ | |
777 | if (!(old_termios->c_cflag & CBAUD) && | |
778 | tty->termios->c_cflag & CBAUD) { | |
779 | info->signals |= SerialSignal_DTR; | |
780 | if (!(tty->termios->c_cflag & CRTSCTS) || | |
781 | !test_bit(TTY_THROTTLED, &tty->flags)) { | |
782 | info->signals |= SerialSignal_RTS; | |
783 | } | |
784 | spin_lock_irqsave(&info->lock,flags); | |
785 | set_signals(info); | |
786 | spin_unlock_irqrestore(&info->lock,flags); | |
787 | } | |
788 | ||
789 | /* Handle turning off CRTSCTS */ | |
790 | if (old_termios->c_cflag & CRTSCTS && | |
791 | !(tty->termios->c_cflag & CRTSCTS)) { | |
792 | tty->hw_stopped = 0; | |
793 | tx_release(tty); | |
794 | } | |
795 | } | |
796 | ||
ce89294c PF |
797 | static void update_tx_timer(struct slgt_info *info) |
798 | { | |
799 | /* | |
800 | * use worst case speed of 1200bps to calculate transmit timeout | |
801 | * based on data in buffers (tbuf_bytes) and FIFO (128 bytes) | |
802 | */ | |
803 | if (info->params.mode == MGSL_MODE_HDLC) { | |
804 | int timeout = (tbuf_bytes(info) * 7) + 1000; | |
805 | mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout)); | |
806 | } | |
807 | } | |
808 | ||
705b6c7b PF |
809 | static int write(struct tty_struct *tty, |
810 | const unsigned char *buf, int count) | |
811 | { | |
812 | int ret = 0; | |
813 | struct slgt_info *info = tty->driver_data; | |
814 | unsigned long flags; | |
815 | ||
816 | if (sanity_check(info, tty->name, "write")) | |
de538eb3 PF |
817 | return -EIO; |
818 | ||
705b6c7b PF |
819 | DBGINFO(("%s write count=%d\n", info->device_name, count)); |
820 | ||
de538eb3 PF |
821 | if (!info->tx_buf || (count > info->max_frame_size)) |
822 | return -EIO; | |
705b6c7b | 823 | |
de538eb3 PF |
824 | if (!count || tty->stopped || tty->hw_stopped) |
825 | return 0; | |
705b6c7b | 826 | |
de538eb3 | 827 | spin_lock_irqsave(&info->lock, flags); |
705b6c7b | 828 | |
de538eb3 | 829 | if (info->tx_count) { |
8a38c285 | 830 | /* send accumulated data from send_char() */ |
de538eb3 PF |
831 | if (!tx_load(info, info->tx_buf, info->tx_count)) |
832 | goto cleanup; | |
833 | info->tx_count = 0; | |
705b6c7b PF |
834 | } |
835 | ||
de538eb3 PF |
836 | if (tx_load(info, buf, count)) |
837 | ret = count; | |
705b6c7b PF |
838 | |
839 | cleanup: | |
de538eb3 | 840 | spin_unlock_irqrestore(&info->lock, flags); |
705b6c7b PF |
841 | DBGINFO(("%s write rc=%d\n", info->device_name, ret)); |
842 | return ret; | |
843 | } | |
844 | ||
55da7789 | 845 | static int put_char(struct tty_struct *tty, unsigned char ch) |
705b6c7b PF |
846 | { |
847 | struct slgt_info *info = tty->driver_data; | |
848 | unsigned long flags; | |
6c82c415 | 849 | int ret = 0; |
705b6c7b PF |
850 | |
851 | if (sanity_check(info, tty->name, "put_char")) | |
55da7789 | 852 | return 0; |
705b6c7b | 853 | DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); |
326f28e9 | 854 | if (!info->tx_buf) |
55da7789 | 855 | return 0; |
705b6c7b | 856 | spin_lock_irqsave(&info->lock,flags); |
de538eb3 | 857 | if (info->tx_count < info->max_frame_size) { |
705b6c7b | 858 | info->tx_buf[info->tx_count++] = ch; |
55da7789 AC |
859 | ret = 1; |
860 | } | |
705b6c7b | 861 | spin_unlock_irqrestore(&info->lock,flags); |
55da7789 | 862 | return ret; |
705b6c7b PF |
863 | } |
864 | ||
865 | static void send_xchar(struct tty_struct *tty, char ch) | |
866 | { | |
867 | struct slgt_info *info = tty->driver_data; | |
868 | unsigned long flags; | |
869 | ||
870 | if (sanity_check(info, tty->name, "send_xchar")) | |
871 | return; | |
872 | DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); | |
873 | info->x_char = ch; | |
874 | if (ch) { | |
875 | spin_lock_irqsave(&info->lock,flags); | |
876 | if (!info->tx_enabled) | |
877 | tx_start(info); | |
878 | spin_unlock_irqrestore(&info->lock,flags); | |
879 | } | |
880 | } | |
881 | ||
882 | static void wait_until_sent(struct tty_struct *tty, int timeout) | |
883 | { | |
884 | struct slgt_info *info = tty->driver_data; | |
885 | unsigned long orig_jiffies, char_time; | |
886 | ||
887 | if (!info ) | |
888 | return; | |
889 | if (sanity_check(info, tty->name, "wait_until_sent")) | |
890 | return; | |
891 | DBGINFO(("%s wait_until_sent entry\n", info->device_name)); | |
8fb06c77 | 892 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
705b6c7b PF |
893 | goto exit; |
894 | ||
895 | orig_jiffies = jiffies; | |
896 | ||
897 | /* Set check interval to 1/5 of estimated time to | |
898 | * send a character, and make it at least 1. The check | |
899 | * interval should also be less than the timeout. | |
900 | * Note: use tight timings here to satisfy the NIST-PCTS. | |
901 | */ | |
902 | ||
903 | if (info->params.data_rate) { | |
904 | char_time = info->timeout/(32 * 5); | |
905 | if (!char_time) | |
906 | char_time++; | |
907 | } else | |
908 | char_time = 1; | |
909 | ||
910 | if (timeout) | |
911 | char_time = min_t(unsigned long, char_time, timeout); | |
912 | ||
913 | while (info->tx_active) { | |
914 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
915 | if (signal_pending(current)) | |
916 | break; | |
917 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
918 | break; | |
919 | } | |
705b6c7b PF |
920 | exit: |
921 | DBGINFO(("%s wait_until_sent exit\n", info->device_name)); | |
922 | } | |
923 | ||
924 | static int write_room(struct tty_struct *tty) | |
925 | { | |
926 | struct slgt_info *info = tty->driver_data; | |
927 | int ret; | |
928 | ||
929 | if (sanity_check(info, tty->name, "write_room")) | |
930 | return 0; | |
931 | ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; | |
932 | DBGINFO(("%s write_room=%d\n", info->device_name, ret)); | |
933 | return ret; | |
934 | } | |
935 | ||
936 | static void flush_chars(struct tty_struct *tty) | |
937 | { | |
938 | struct slgt_info *info = tty->driver_data; | |
939 | unsigned long flags; | |
940 | ||
941 | if (sanity_check(info, tty->name, "flush_chars")) | |
942 | return; | |
943 | DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); | |
944 | ||
945 | if (info->tx_count <= 0 || tty->stopped || | |
946 | tty->hw_stopped || !info->tx_buf) | |
947 | return; | |
948 | ||
949 | DBGINFO(("%s flush_chars start transmit\n", info->device_name)); | |
950 | ||
951 | spin_lock_irqsave(&info->lock,flags); | |
de538eb3 PF |
952 | if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) |
953 | info->tx_count = 0; | |
705b6c7b PF |
954 | spin_unlock_irqrestore(&info->lock,flags); |
955 | } | |
956 | ||
957 | static void flush_buffer(struct tty_struct *tty) | |
958 | { | |
959 | struct slgt_info *info = tty->driver_data; | |
960 | unsigned long flags; | |
961 | ||
962 | if (sanity_check(info, tty->name, "flush_buffer")) | |
963 | return; | |
964 | DBGINFO(("%s flush_buffer\n", info->device_name)); | |
965 | ||
de538eb3 PF |
966 | spin_lock_irqsave(&info->lock, flags); |
967 | info->tx_count = 0; | |
968 | spin_unlock_irqrestore(&info->lock, flags); | |
705b6c7b | 969 | |
705b6c7b PF |
970 | tty_wakeup(tty); |
971 | } | |
972 | ||
973 | /* | |
974 | * throttle (stop) transmitter | |
975 | */ | |
976 | static void tx_hold(struct tty_struct *tty) | |
977 | { | |
978 | struct slgt_info *info = tty->driver_data; | |
979 | unsigned long flags; | |
980 | ||
981 | if (sanity_check(info, tty->name, "tx_hold")) | |
982 | return; | |
983 | DBGINFO(("%s tx_hold\n", info->device_name)); | |
984 | spin_lock_irqsave(&info->lock,flags); | |
985 | if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) | |
986 | tx_stop(info); | |
987 | spin_unlock_irqrestore(&info->lock,flags); | |
988 | } | |
989 | ||
990 | /* | |
991 | * release (start) transmitter | |
992 | */ | |
993 | static void tx_release(struct tty_struct *tty) | |
994 | { | |
995 | struct slgt_info *info = tty->driver_data; | |
996 | unsigned long flags; | |
997 | ||
998 | if (sanity_check(info, tty->name, "tx_release")) | |
999 | return; | |
1000 | DBGINFO(("%s tx_release\n", info->device_name)); | |
de538eb3 PF |
1001 | spin_lock_irqsave(&info->lock, flags); |
1002 | if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) | |
1003 | info->tx_count = 0; | |
1004 | spin_unlock_irqrestore(&info->lock, flags); | |
705b6c7b PF |
1005 | } |
1006 | ||
1007 | /* | |
1008 | * Service an IOCTL request | |
1009 | * | |
1010 | * Arguments | |
1011 | * | |
1012 | * tty pointer to tty instance data | |
1013 | * file pointer to associated file object for device | |
1014 | * cmd IOCTL command code | |
1015 | * arg command argument/context | |
1016 | * | |
1017 | * Return 0 if success, otherwise error code | |
1018 | */ | |
1019 | static int ioctl(struct tty_struct *tty, struct file *file, | |
1020 | unsigned int cmd, unsigned long arg) | |
1021 | { | |
1022 | struct slgt_info *info = tty->driver_data; | |
1023 | struct mgsl_icount cnow; /* kernel counter temps */ | |
1024 | struct serial_icounter_struct __user *p_cuser; /* user space */ | |
1025 | unsigned long flags; | |
1026 | void __user *argp = (void __user *)arg; | |
1f8cabb7 | 1027 | int ret; |
705b6c7b PF |
1028 | |
1029 | if (sanity_check(info, tty->name, "ioctl")) | |
1030 | return -ENODEV; | |
1031 | DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); | |
1032 | ||
1033 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
1034 | (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { | |
1035 | if (tty->flags & (1 << TTY_IO_ERROR)) | |
1036 | return -EIO; | |
1037 | } | |
1038 | ||
f602501d AC |
1039 | switch (cmd) { |
1040 | case MGSL_IOCWAITEVENT: | |
1041 | return wait_mgsl_event(info, argp); | |
1042 | case TIOCMIWAIT: | |
1043 | return modem_input_wait(info,(int)arg); | |
1044 | case TIOCGICOUNT: | |
1045 | spin_lock_irqsave(&info->lock,flags); | |
1046 | cnow = info->icount; | |
1047 | spin_unlock_irqrestore(&info->lock,flags); | |
1048 | p_cuser = argp; | |
1049 | if (put_user(cnow.cts, &p_cuser->cts) || | |
1050 | put_user(cnow.dsr, &p_cuser->dsr) || | |
1051 | put_user(cnow.rng, &p_cuser->rng) || | |
1052 | put_user(cnow.dcd, &p_cuser->dcd) || | |
1053 | put_user(cnow.rx, &p_cuser->rx) || | |
1054 | put_user(cnow.tx, &p_cuser->tx) || | |
1055 | put_user(cnow.frame, &p_cuser->frame) || | |
1056 | put_user(cnow.overrun, &p_cuser->overrun) || | |
1057 | put_user(cnow.parity, &p_cuser->parity) || | |
1058 | put_user(cnow.brk, &p_cuser->brk) || | |
1059 | put_user(cnow.buf_overrun, &p_cuser->buf_overrun)) | |
1060 | return -EFAULT; | |
1061 | return 0; | |
1062 | case MGSL_IOCSGPIO: | |
1063 | return set_gpio(info, argp); | |
1064 | case MGSL_IOCGGPIO: | |
1065 | return get_gpio(info, argp); | |
1066 | case MGSL_IOCWAITGPIO: | |
1067 | return wait_gpio(info, argp); | |
1068 | } | |
1069 | mutex_lock(&info->port.mutex); | |
705b6c7b PF |
1070 | switch (cmd) { |
1071 | case MGSL_IOCGPARAMS: | |
1f8cabb7 AC |
1072 | ret = get_params(info, argp); |
1073 | break; | |
705b6c7b | 1074 | case MGSL_IOCSPARAMS: |
1f8cabb7 AC |
1075 | ret = set_params(info, argp); |
1076 | break; | |
705b6c7b | 1077 | case MGSL_IOCGTXIDLE: |
1f8cabb7 AC |
1078 | ret = get_txidle(info, argp); |
1079 | break; | |
705b6c7b | 1080 | case MGSL_IOCSTXIDLE: |
1f8cabb7 AC |
1081 | ret = set_txidle(info, (int)arg); |
1082 | break; | |
705b6c7b | 1083 | case MGSL_IOCTXENABLE: |
1f8cabb7 AC |
1084 | ret = tx_enable(info, (int)arg); |
1085 | break; | |
705b6c7b | 1086 | case MGSL_IOCRXENABLE: |
1f8cabb7 AC |
1087 | ret = rx_enable(info, (int)arg); |
1088 | break; | |
705b6c7b | 1089 | case MGSL_IOCTXABORT: |
1f8cabb7 AC |
1090 | ret = tx_abort(info); |
1091 | break; | |
705b6c7b | 1092 | case MGSL_IOCGSTATS: |
1f8cabb7 AC |
1093 | ret = get_stats(info, argp); |
1094 | break; | |
705b6c7b | 1095 | case MGSL_IOCGIF: |
1f8cabb7 AC |
1096 | ret = get_interface(info, argp); |
1097 | break; | |
705b6c7b | 1098 | case MGSL_IOCSIF: |
1f8cabb7 AC |
1099 | ret = set_interface(info,(int)arg); |
1100 | break; | |
705b6c7b | 1101 | default: |
1f8cabb7 | 1102 | ret = -ENOIOCTLCMD; |
705b6c7b | 1103 | } |
f602501d | 1104 | mutex_unlock(&info->port.mutex); |
1f8cabb7 | 1105 | return ret; |
705b6c7b PF |
1106 | } |
1107 | ||
2acdb169 PF |
1108 | /* |
1109 | * support for 32 bit ioctl calls on 64 bit systems | |
1110 | */ | |
1111 | #ifdef CONFIG_COMPAT | |
1112 | static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params) | |
1113 | { | |
1114 | struct MGSL_PARAMS32 tmp_params; | |
1115 | ||
1116 | DBGINFO(("%s get_params32\n", info->device_name)); | |
1117 | tmp_params.mode = (compat_ulong_t)info->params.mode; | |
1118 | tmp_params.loopback = info->params.loopback; | |
1119 | tmp_params.flags = info->params.flags; | |
1120 | tmp_params.encoding = info->params.encoding; | |
1121 | tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; | |
1122 | tmp_params.addr_filter = info->params.addr_filter; | |
1123 | tmp_params.crc_type = info->params.crc_type; | |
1124 | tmp_params.preamble_length = info->params.preamble_length; | |
1125 | tmp_params.preamble = info->params.preamble; | |
1126 | tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; | |
1127 | tmp_params.data_bits = info->params.data_bits; | |
1128 | tmp_params.stop_bits = info->params.stop_bits; | |
1129 | tmp_params.parity = info->params.parity; | |
1130 | if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32))) | |
1131 | return -EFAULT; | |
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params) | |
1136 | { | |
1137 | struct MGSL_PARAMS32 tmp_params; | |
1138 | ||
1139 | DBGINFO(("%s set_params32\n", info->device_name)); | |
1140 | if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32))) | |
1141 | return -EFAULT; | |
1142 | ||
1143 | spin_lock(&info->lock); | |
1f80769f PF |
1144 | if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) { |
1145 | info->base_clock = tmp_params.clock_speed; | |
1146 | } else { | |
1147 | info->params.mode = tmp_params.mode; | |
1148 | info->params.loopback = tmp_params.loopback; | |
1149 | info->params.flags = tmp_params.flags; | |
1150 | info->params.encoding = tmp_params.encoding; | |
1151 | info->params.clock_speed = tmp_params.clock_speed; | |
1152 | info->params.addr_filter = tmp_params.addr_filter; | |
1153 | info->params.crc_type = tmp_params.crc_type; | |
1154 | info->params.preamble_length = tmp_params.preamble_length; | |
1155 | info->params.preamble = tmp_params.preamble; | |
1156 | info->params.data_rate = tmp_params.data_rate; | |
1157 | info->params.data_bits = tmp_params.data_bits; | |
1158 | info->params.stop_bits = tmp_params.stop_bits; | |
1159 | info->params.parity = tmp_params.parity; | |
1160 | } | |
2acdb169 PF |
1161 | spin_unlock(&info->lock); |
1162 | ||
1f80769f | 1163 | program_hw(info); |
2acdb169 PF |
1164 | |
1165 | return 0; | |
1166 | } | |
1167 | ||
1168 | static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file, | |
1169 | unsigned int cmd, unsigned long arg) | |
1170 | { | |
1171 | struct slgt_info *info = tty->driver_data; | |
1172 | int rc = -ENOIOCTLCMD; | |
1173 | ||
1174 | if (sanity_check(info, tty->name, "compat_ioctl")) | |
1175 | return -ENODEV; | |
1176 | DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd)); | |
1177 | ||
1178 | switch (cmd) { | |
1179 | ||
1180 | case MGSL_IOCSPARAMS32: | |
1181 | rc = set_params32(info, compat_ptr(arg)); | |
1182 | break; | |
1183 | ||
1184 | case MGSL_IOCGPARAMS32: | |
1185 | rc = get_params32(info, compat_ptr(arg)); | |
1186 | break; | |
1187 | ||
1188 | case MGSL_IOCGPARAMS: | |
1189 | case MGSL_IOCSPARAMS: | |
1190 | case MGSL_IOCGTXIDLE: | |
1191 | case MGSL_IOCGSTATS: | |
1192 | case MGSL_IOCWAITEVENT: | |
1193 | case MGSL_IOCGIF: | |
1194 | case MGSL_IOCSGPIO: | |
1195 | case MGSL_IOCGGPIO: | |
1196 | case MGSL_IOCWAITGPIO: | |
1197 | case TIOCGICOUNT: | |
1198 | rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg))); | |
1199 | break; | |
1200 | ||
1201 | case MGSL_IOCSTXIDLE: | |
1202 | case MGSL_IOCTXENABLE: | |
1203 | case MGSL_IOCRXENABLE: | |
1204 | case MGSL_IOCTXABORT: | |
1205 | case TIOCMIWAIT: | |
1206 | case MGSL_IOCSIF: | |
1207 | rc = ioctl(tty, file, cmd, arg); | |
1208 | break; | |
1209 | } | |
1210 | ||
1211 | DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc)); | |
1212 | return rc; | |
1213 | } | |
1214 | #else | |
1215 | #define slgt_compat_ioctl NULL | |
1216 | #endif /* ifdef CONFIG_COMPAT */ | |
1217 | ||
705b6c7b PF |
1218 | /* |
1219 | * proc fs support | |
1220 | */ | |
a18c56e5 | 1221 | static inline void line_info(struct seq_file *m, struct slgt_info *info) |
705b6c7b PF |
1222 | { |
1223 | char stat_buf[30]; | |
705b6c7b PF |
1224 | unsigned long flags; |
1225 | ||
a18c56e5 | 1226 | seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", |
705b6c7b PF |
1227 | info->device_name, info->phys_reg_addr, |
1228 | info->irq_level, info->max_frame_size); | |
1229 | ||
1230 | /* output current serial signal states */ | |
1231 | spin_lock_irqsave(&info->lock,flags); | |
1232 | get_signals(info); | |
1233 | spin_unlock_irqrestore(&info->lock,flags); | |
1234 | ||
1235 | stat_buf[0] = 0; | |
1236 | stat_buf[1] = 0; | |
1237 | if (info->signals & SerialSignal_RTS) | |
1238 | strcat(stat_buf, "|RTS"); | |
1239 | if (info->signals & SerialSignal_CTS) | |
1240 | strcat(stat_buf, "|CTS"); | |
1241 | if (info->signals & SerialSignal_DTR) | |
1242 | strcat(stat_buf, "|DTR"); | |
1243 | if (info->signals & SerialSignal_DSR) | |
1244 | strcat(stat_buf, "|DSR"); | |
1245 | if (info->signals & SerialSignal_DCD) | |
1246 | strcat(stat_buf, "|CD"); | |
1247 | if (info->signals & SerialSignal_RI) | |
1248 | strcat(stat_buf, "|RI"); | |
1249 | ||
1250 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
a18c56e5 | 1251 | seq_printf(m, "\tHDLC txok:%d rxok:%d", |
705b6c7b PF |
1252 | info->icount.txok, info->icount.rxok); |
1253 | if (info->icount.txunder) | |
a18c56e5 | 1254 | seq_printf(m, " txunder:%d", info->icount.txunder); |
705b6c7b | 1255 | if (info->icount.txabort) |
a18c56e5 | 1256 | seq_printf(m, " txabort:%d", info->icount.txabort); |
705b6c7b | 1257 | if (info->icount.rxshort) |
a18c56e5 | 1258 | seq_printf(m, " rxshort:%d", info->icount.rxshort); |
705b6c7b | 1259 | if (info->icount.rxlong) |
a18c56e5 | 1260 | seq_printf(m, " rxlong:%d", info->icount.rxlong); |
705b6c7b | 1261 | if (info->icount.rxover) |
a18c56e5 | 1262 | seq_printf(m, " rxover:%d", info->icount.rxover); |
705b6c7b | 1263 | if (info->icount.rxcrc) |
a18c56e5 | 1264 | seq_printf(m, " rxcrc:%d", info->icount.rxcrc); |
705b6c7b | 1265 | } else { |
a18c56e5 | 1266 | seq_printf(m, "\tASYNC tx:%d rx:%d", |
705b6c7b PF |
1267 | info->icount.tx, info->icount.rx); |
1268 | if (info->icount.frame) | |
a18c56e5 | 1269 | seq_printf(m, " fe:%d", info->icount.frame); |
705b6c7b | 1270 | if (info->icount.parity) |
a18c56e5 | 1271 | seq_printf(m, " pe:%d", info->icount.parity); |
705b6c7b | 1272 | if (info->icount.brk) |
a18c56e5 | 1273 | seq_printf(m, " brk:%d", info->icount.brk); |
705b6c7b | 1274 | if (info->icount.overrun) |
a18c56e5 | 1275 | seq_printf(m, " oe:%d", info->icount.overrun); |
705b6c7b PF |
1276 | } |
1277 | ||
1278 | /* Append serial signal status to end */ | |
a18c56e5 | 1279 | seq_printf(m, " %s\n", stat_buf+1); |
705b6c7b | 1280 | |
a18c56e5 | 1281 | seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", |
705b6c7b PF |
1282 | info->tx_active,info->bh_requested,info->bh_running, |
1283 | info->pending_bh); | |
705b6c7b PF |
1284 | } |
1285 | ||
1286 | /* Called to print information about devices | |
1287 | */ | |
a18c56e5 | 1288 | static int synclink_gt_proc_show(struct seq_file *m, void *v) |
705b6c7b | 1289 | { |
705b6c7b PF |
1290 | struct slgt_info *info; |
1291 | ||
a18c56e5 | 1292 | seq_puts(m, "synclink_gt driver\n"); |
705b6c7b PF |
1293 | |
1294 | info = slgt_device_list; | |
1295 | while( info ) { | |
a18c56e5 | 1296 | line_info(m, info); |
705b6c7b PF |
1297 | info = info->next_device; |
1298 | } | |
a18c56e5 AD |
1299 | return 0; |
1300 | } | |
705b6c7b | 1301 | |
a18c56e5 AD |
1302 | static int synclink_gt_proc_open(struct inode *inode, struct file *file) |
1303 | { | |
1304 | return single_open(file, synclink_gt_proc_show, NULL); | |
705b6c7b PF |
1305 | } |
1306 | ||
a18c56e5 AD |
1307 | static const struct file_operations synclink_gt_proc_fops = { |
1308 | .owner = THIS_MODULE, | |
1309 | .open = synclink_gt_proc_open, | |
1310 | .read = seq_read, | |
1311 | .llseek = seq_lseek, | |
1312 | .release = single_release, | |
1313 | }; | |
1314 | ||
705b6c7b PF |
1315 | /* |
1316 | * return count of bytes in transmit buffer | |
1317 | */ | |
1318 | static int chars_in_buffer(struct tty_struct *tty) | |
1319 | { | |
1320 | struct slgt_info *info = tty->driver_data; | |
403214d0 | 1321 | int count; |
705b6c7b PF |
1322 | if (sanity_check(info, tty->name, "chars_in_buffer")) |
1323 | return 0; | |
403214d0 PF |
1324 | count = tbuf_bytes(info); |
1325 | DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count)); | |
1326 | return count; | |
705b6c7b PF |
1327 | } |
1328 | ||
1329 | /* | |
1330 | * signal remote device to throttle send data (our receive data) | |
1331 | */ | |
1332 | static void throttle(struct tty_struct * tty) | |
1333 | { | |
1334 | struct slgt_info *info = tty->driver_data; | |
1335 | unsigned long flags; | |
1336 | ||
1337 | if (sanity_check(info, tty->name, "throttle")) | |
1338 | return; | |
1339 | DBGINFO(("%s throttle\n", info->device_name)); | |
1340 | if (I_IXOFF(tty)) | |
1341 | send_xchar(tty, STOP_CHAR(tty)); | |
1342 | if (tty->termios->c_cflag & CRTSCTS) { | |
1343 | spin_lock_irqsave(&info->lock,flags); | |
1344 | info->signals &= ~SerialSignal_RTS; | |
1345 | set_signals(info); | |
1346 | spin_unlock_irqrestore(&info->lock,flags); | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | /* | |
1351 | * signal remote device to stop throttling send data (our receive data) | |
1352 | */ | |
1353 | static void unthrottle(struct tty_struct * tty) | |
1354 | { | |
1355 | struct slgt_info *info = tty->driver_data; | |
1356 | unsigned long flags; | |
1357 | ||
1358 | if (sanity_check(info, tty->name, "unthrottle")) | |
1359 | return; | |
1360 | DBGINFO(("%s unthrottle\n", info->device_name)); | |
1361 | if (I_IXOFF(tty)) { | |
1362 | if (info->x_char) | |
1363 | info->x_char = 0; | |
1364 | else | |
1365 | send_xchar(tty, START_CHAR(tty)); | |
1366 | } | |
1367 | if (tty->termios->c_cflag & CRTSCTS) { | |
1368 | spin_lock_irqsave(&info->lock,flags); | |
1369 | info->signals |= SerialSignal_RTS; | |
1370 | set_signals(info); | |
1371 | spin_unlock_irqrestore(&info->lock,flags); | |
1372 | } | |
1373 | } | |
1374 | ||
1375 | /* | |
1376 | * set or clear transmit break condition | |
1377 | * break_state -1=set break condition, 0=clear | |
1378 | */ | |
9e98966c | 1379 | static int set_break(struct tty_struct *tty, int break_state) |
705b6c7b PF |
1380 | { |
1381 | struct slgt_info *info = tty->driver_data; | |
1382 | unsigned short value; | |
1383 | unsigned long flags; | |
1384 | ||
1385 | if (sanity_check(info, tty->name, "set_break")) | |
9e98966c | 1386 | return -EINVAL; |
705b6c7b PF |
1387 | DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); |
1388 | ||
1389 | spin_lock_irqsave(&info->lock,flags); | |
1390 | value = rd_reg16(info, TCR); | |
1391 | if (break_state == -1) | |
1392 | value |= BIT6; | |
1393 | else | |
1394 | value &= ~BIT6; | |
1395 | wr_reg16(info, TCR, value); | |
1396 | spin_unlock_irqrestore(&info->lock,flags); | |
9e98966c | 1397 | return 0; |
705b6c7b PF |
1398 | } |
1399 | ||
af69c7f9 | 1400 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
1401 | |
1402 | /** | |
1403 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) | |
1404 | * set encoding and frame check sequence (FCS) options | |
1405 | * | |
1406 | * dev pointer to network device structure | |
1407 | * encoding serial encoding setting | |
1408 | * parity FCS setting | |
1409 | * | |
1410 | * returns 0 if success, otherwise error code | |
1411 | */ | |
1412 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, | |
1413 | unsigned short parity) | |
1414 | { | |
1415 | struct slgt_info *info = dev_to_port(dev); | |
1416 | unsigned char new_encoding; | |
1417 | unsigned short new_crctype; | |
1418 | ||
1419 | /* return error if TTY interface open */ | |
8fb06c77 | 1420 | if (info->port.count) |
705b6c7b PF |
1421 | return -EBUSY; |
1422 | ||
1423 | DBGINFO(("%s hdlcdev_attach\n", info->device_name)); | |
1424 | ||
1425 | switch (encoding) | |
1426 | { | |
1427 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; | |
1428 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; | |
1429 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; | |
1430 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; | |
1431 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; | |
1432 | default: return -EINVAL; | |
1433 | } | |
1434 | ||
1435 | switch (parity) | |
1436 | { | |
1437 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; | |
1438 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; | |
1439 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; | |
1440 | default: return -EINVAL; | |
1441 | } | |
1442 | ||
1443 | info->params.encoding = new_encoding; | |
53b3531b | 1444 | info->params.crc_type = new_crctype; |
705b6c7b PF |
1445 | |
1446 | /* if network interface up, reprogram hardware */ | |
1447 | if (info->netcount) | |
1448 | program_hw(info); | |
1449 | ||
1450 | return 0; | |
1451 | } | |
1452 | ||
1453 | /** | |
1454 | * called by generic HDLC layer to send frame | |
1455 | * | |
1456 | * skb socket buffer containing HDLC frame | |
1457 | * dev pointer to network device structure | |
705b6c7b | 1458 | */ |
4c5d502d SH |
1459 | static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, |
1460 | struct net_device *dev) | |
705b6c7b PF |
1461 | { |
1462 | struct slgt_info *info = dev_to_port(dev); | |
705b6c7b PF |
1463 | unsigned long flags; |
1464 | ||
1465 | DBGINFO(("%s hdlc_xmit\n", dev->name)); | |
1466 | ||
de538eb3 PF |
1467 | if (!skb->len) |
1468 | return NETDEV_TX_OK; | |
1469 | ||
705b6c7b PF |
1470 | /* stop sending until this frame completes */ |
1471 | netif_stop_queue(dev); | |
1472 | ||
705b6c7b | 1473 | /* update network statistics */ |
198191c4 KH |
1474 | dev->stats.tx_packets++; |
1475 | dev->stats.tx_bytes += skb->len; | |
705b6c7b | 1476 | |
705b6c7b PF |
1477 | /* save start time for transmit timeout detection */ |
1478 | dev->trans_start = jiffies; | |
1479 | ||
de538eb3 PF |
1480 | spin_lock_irqsave(&info->lock, flags); |
1481 | tx_load(info, skb->data, skb->len); | |
1482 | spin_unlock_irqrestore(&info->lock, flags); | |
1483 | ||
1484 | /* done with socket buffer, so free it */ | |
1485 | dev_kfree_skb(skb); | |
705b6c7b | 1486 | |
4c5d502d | 1487 | return NETDEV_TX_OK; |
705b6c7b PF |
1488 | } |
1489 | ||
1490 | /** | |
1491 | * called by network layer when interface enabled | |
1492 | * claim resources and initialize hardware | |
1493 | * | |
1494 | * dev pointer to network device structure | |
1495 | * | |
1496 | * returns 0 if success, otherwise error code | |
1497 | */ | |
1498 | static int hdlcdev_open(struct net_device *dev) | |
1499 | { | |
1500 | struct slgt_info *info = dev_to_port(dev); | |
1501 | int rc; | |
1502 | unsigned long flags; | |
1503 | ||
d4c63b7c PF |
1504 | if (!try_module_get(THIS_MODULE)) |
1505 | return -EBUSY; | |
1506 | ||
705b6c7b PF |
1507 | DBGINFO(("%s hdlcdev_open\n", dev->name)); |
1508 | ||
1509 | /* generic HDLC layer open processing */ | |
1510 | if ((rc = hdlc_open(dev))) | |
1511 | return rc; | |
1512 | ||
1513 | /* arbitrate between network and tty opens */ | |
1514 | spin_lock_irqsave(&info->netlock, flags); | |
8fb06c77 | 1515 | if (info->port.count != 0 || info->netcount != 0) { |
705b6c7b PF |
1516 | DBGINFO(("%s hdlc_open busy\n", dev->name)); |
1517 | spin_unlock_irqrestore(&info->netlock, flags); | |
1518 | return -EBUSY; | |
1519 | } | |
1520 | info->netcount=1; | |
1521 | spin_unlock_irqrestore(&info->netlock, flags); | |
1522 | ||
1523 | /* claim resources and init adapter */ | |
1524 | if ((rc = startup(info)) != 0) { | |
1525 | spin_lock_irqsave(&info->netlock, flags); | |
1526 | info->netcount=0; | |
1527 | spin_unlock_irqrestore(&info->netlock, flags); | |
1528 | return rc; | |
1529 | } | |
1530 | ||
1531 | /* assert DTR and RTS, apply hardware settings */ | |
1532 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
1533 | program_hw(info); | |
1534 | ||
1535 | /* enable network layer transmit */ | |
1536 | dev->trans_start = jiffies; | |
1537 | netif_start_queue(dev); | |
1538 | ||
1539 | /* inform generic HDLC layer of current DCD status */ | |
1540 | spin_lock_irqsave(&info->lock, flags); | |
1541 | get_signals(info); | |
1542 | spin_unlock_irqrestore(&info->lock, flags); | |
fbeff3c1 KH |
1543 | if (info->signals & SerialSignal_DCD) |
1544 | netif_carrier_on(dev); | |
1545 | else | |
1546 | netif_carrier_off(dev); | |
705b6c7b PF |
1547 | return 0; |
1548 | } | |
1549 | ||
1550 | /** | |
1551 | * called by network layer when interface is disabled | |
1552 | * shutdown hardware and release resources | |
1553 | * | |
1554 | * dev pointer to network device structure | |
1555 | * | |
1556 | * returns 0 if success, otherwise error code | |
1557 | */ | |
1558 | static int hdlcdev_close(struct net_device *dev) | |
1559 | { | |
1560 | struct slgt_info *info = dev_to_port(dev); | |
1561 | unsigned long flags; | |
1562 | ||
1563 | DBGINFO(("%s hdlcdev_close\n", dev->name)); | |
1564 | ||
1565 | netif_stop_queue(dev); | |
1566 | ||
1567 | /* shutdown adapter and release resources */ | |
1568 | shutdown(info); | |
1569 | ||
1570 | hdlc_close(dev); | |
1571 | ||
1572 | spin_lock_irqsave(&info->netlock, flags); | |
1573 | info->netcount=0; | |
1574 | spin_unlock_irqrestore(&info->netlock, flags); | |
1575 | ||
d4c63b7c | 1576 | module_put(THIS_MODULE); |
705b6c7b PF |
1577 | return 0; |
1578 | } | |
1579 | ||
1580 | /** | |
1581 | * called by network layer to process IOCTL call to network device | |
1582 | * | |
1583 | * dev pointer to network device structure | |
1584 | * ifr pointer to network interface request structure | |
1585 | * cmd IOCTL command code | |
1586 | * | |
1587 | * returns 0 if success, otherwise error code | |
1588 | */ | |
1589 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1590 | { | |
1591 | const size_t size = sizeof(sync_serial_settings); | |
1592 | sync_serial_settings new_line; | |
1593 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
1594 | struct slgt_info *info = dev_to_port(dev); | |
1595 | unsigned int flags; | |
1596 | ||
1597 | DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); | |
1598 | ||
1599 | /* return error if TTY interface open */ | |
8fb06c77 | 1600 | if (info->port.count) |
705b6c7b PF |
1601 | return -EBUSY; |
1602 | ||
1603 | if (cmd != SIOCWANDEV) | |
1604 | return hdlc_ioctl(dev, ifr, cmd); | |
1605 | ||
1606 | switch(ifr->ifr_settings.type) { | |
1607 | case IF_GET_IFACE: /* return current sync_serial_settings */ | |
1608 | ||
1609 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
1610 | if (ifr->ifr_settings.size < size) { | |
1611 | ifr->ifr_settings.size = size; /* data size wanted */ | |
1612 | return -ENOBUFS; | |
1613 | } | |
1614 | ||
1615 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1616 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1617 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1618 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1619 | ||
1620 | switch (flags){ | |
1621 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; | |
1622 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; | |
1623 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; | |
1624 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; | |
1625 | default: new_line.clock_type = CLOCK_DEFAULT; | |
1626 | } | |
1627 | ||
1628 | new_line.clock_rate = info->params.clock_speed; | |
1629 | new_line.loopback = info->params.loopback ? 1:0; | |
1630 | ||
1631 | if (copy_to_user(line, &new_line, size)) | |
1632 | return -EFAULT; | |
1633 | return 0; | |
1634 | ||
1635 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ | |
1636 | ||
1637 | if(!capable(CAP_NET_ADMIN)) | |
1638 | return -EPERM; | |
1639 | if (copy_from_user(&new_line, line, size)) | |
1640 | return -EFAULT; | |
1641 | ||
1642 | switch (new_line.clock_type) | |
1643 | { | |
1644 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; | |
1645 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; | |
1646 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; | |
1647 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; | |
1648 | case CLOCK_DEFAULT: flags = info->params.flags & | |
1649 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1650 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1651 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1652 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; | |
1653 | default: return -EINVAL; | |
1654 | } | |
1655 | ||
1656 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
1657 | return -EINVAL; | |
1658 | ||
1659 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1660 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1661 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1662 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1663 | info->params.flags |= flags; | |
1664 | ||
1665 | info->params.loopback = new_line.loopback; | |
1666 | ||
1667 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) | |
1668 | info->params.clock_speed = new_line.clock_rate; | |
1669 | else | |
1670 | info->params.clock_speed = 0; | |
1671 | ||
1672 | /* if network interface up, reprogram hardware */ | |
1673 | if (info->netcount) | |
1674 | program_hw(info); | |
1675 | return 0; | |
1676 | ||
1677 | default: | |
1678 | return hdlc_ioctl(dev, ifr, cmd); | |
1679 | } | |
1680 | } | |
1681 | ||
1682 | /** | |
1683 | * called by network layer when transmit timeout is detected | |
1684 | * | |
1685 | * dev pointer to network device structure | |
1686 | */ | |
1687 | static void hdlcdev_tx_timeout(struct net_device *dev) | |
1688 | { | |
1689 | struct slgt_info *info = dev_to_port(dev); | |
705b6c7b PF |
1690 | unsigned long flags; |
1691 | ||
1692 | DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); | |
1693 | ||
198191c4 KH |
1694 | dev->stats.tx_errors++; |
1695 | dev->stats.tx_aborted_errors++; | |
705b6c7b PF |
1696 | |
1697 | spin_lock_irqsave(&info->lock,flags); | |
1698 | tx_stop(info); | |
1699 | spin_unlock_irqrestore(&info->lock,flags); | |
1700 | ||
1701 | netif_wake_queue(dev); | |
1702 | } | |
1703 | ||
1704 | /** | |
1705 | * called by device driver when transmit completes | |
1706 | * reenable network layer transmit if stopped | |
1707 | * | |
1708 | * info pointer to device instance information | |
1709 | */ | |
1710 | static void hdlcdev_tx_done(struct slgt_info *info) | |
1711 | { | |
1712 | if (netif_queue_stopped(info->netdev)) | |
1713 | netif_wake_queue(info->netdev); | |
1714 | } | |
1715 | ||
1716 | /** | |
1717 | * called by device driver when frame received | |
1718 | * pass frame to network layer | |
1719 | * | |
1720 | * info pointer to device instance information | |
1721 | * buf pointer to buffer contianing frame data | |
1722 | * size count of data bytes in buf | |
1723 | */ | |
1724 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) | |
1725 | { | |
1726 | struct sk_buff *skb = dev_alloc_skb(size); | |
1727 | struct net_device *dev = info->netdev; | |
705b6c7b PF |
1728 | |
1729 | DBGINFO(("%s hdlcdev_rx\n", dev->name)); | |
1730 | ||
1731 | if (skb == NULL) { | |
1732 | DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); | |
198191c4 | 1733 | dev->stats.rx_dropped++; |
705b6c7b PF |
1734 | return; |
1735 | } | |
1736 | ||
198191c4 | 1737 | memcpy(skb_put(skb, size), buf, size); |
705b6c7b | 1738 | |
198191c4 | 1739 | skb->protocol = hdlc_type_trans(skb, dev); |
705b6c7b | 1740 | |
198191c4 KH |
1741 | dev->stats.rx_packets++; |
1742 | dev->stats.rx_bytes += size; | |
705b6c7b PF |
1743 | |
1744 | netif_rx(skb); | |
705b6c7b PF |
1745 | } |
1746 | ||
991990a1 KH |
1747 | static const struct net_device_ops hdlcdev_ops = { |
1748 | .ndo_open = hdlcdev_open, | |
1749 | .ndo_stop = hdlcdev_close, | |
1750 | .ndo_change_mtu = hdlc_change_mtu, | |
1751 | .ndo_start_xmit = hdlc_start_xmit, | |
1752 | .ndo_do_ioctl = hdlcdev_ioctl, | |
1753 | .ndo_tx_timeout = hdlcdev_tx_timeout, | |
1754 | }; | |
1755 | ||
705b6c7b PF |
1756 | /** |
1757 | * called by device driver when adding device instance | |
1758 | * do generic HDLC initialization | |
1759 | * | |
1760 | * info pointer to device instance information | |
1761 | * | |
1762 | * returns 0 if success, otherwise error code | |
1763 | */ | |
1764 | static int hdlcdev_init(struct slgt_info *info) | |
1765 | { | |
1766 | int rc; | |
1767 | struct net_device *dev; | |
1768 | hdlc_device *hdlc; | |
1769 | ||
1770 | /* allocate and initialize network and HDLC layer objects */ | |
1771 | ||
1772 | if (!(dev = alloc_hdlcdev(info))) { | |
1773 | printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); | |
1774 | return -ENOMEM; | |
1775 | } | |
1776 | ||
1777 | /* for network layer reporting purposes only */ | |
1778 | dev->mem_start = info->phys_reg_addr; | |
1779 | dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; | |
1780 | dev->irq = info->irq_level; | |
1781 | ||
1782 | /* network layer callbacks and settings */ | |
991990a1 KH |
1783 | dev->netdev_ops = &hdlcdev_ops; |
1784 | dev->watchdog_timeo = 10 * HZ; | |
705b6c7b PF |
1785 | dev->tx_queue_len = 50; |
1786 | ||
1787 | /* generic HDLC layer callbacks and settings */ | |
1788 | hdlc = dev_to_hdlc(dev); | |
1789 | hdlc->attach = hdlcdev_attach; | |
1790 | hdlc->xmit = hdlcdev_xmit; | |
1791 | ||
1792 | /* register objects with HDLC layer */ | |
1793 | if ((rc = register_hdlc_device(dev))) { | |
1794 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); | |
1795 | free_netdev(dev); | |
1796 | return rc; | |
1797 | } | |
1798 | ||
1799 | info->netdev = dev; | |
1800 | return 0; | |
1801 | } | |
1802 | ||
1803 | /** | |
1804 | * called by device driver when removing device instance | |
1805 | * do generic HDLC cleanup | |
1806 | * | |
1807 | * info pointer to device instance information | |
1808 | */ | |
1809 | static void hdlcdev_exit(struct slgt_info *info) | |
1810 | { | |
1811 | unregister_hdlc_device(info->netdev); | |
1812 | free_netdev(info->netdev); | |
1813 | info->netdev = NULL; | |
1814 | } | |
1815 | ||
1816 | #endif /* ifdef CONFIG_HDLC */ | |
1817 | ||
1818 | /* | |
1819 | * get async data from rx DMA buffers | |
1820 | */ | |
1821 | static void rx_async(struct slgt_info *info) | |
1822 | { | |
8fb06c77 | 1823 | struct tty_struct *tty = info->port.tty; |
705b6c7b PF |
1824 | struct mgsl_icount *icount = &info->icount; |
1825 | unsigned int start, end; | |
1826 | unsigned char *p; | |
1827 | unsigned char status; | |
1828 | struct slgt_desc *bufs = info->rbufs; | |
1829 | int i, count; | |
33f0f88f AC |
1830 | int chars = 0; |
1831 | int stat; | |
1832 | unsigned char ch; | |
705b6c7b PF |
1833 | |
1834 | start = end = info->rbuf_current; | |
1835 | ||
1836 | while(desc_complete(bufs[end])) { | |
1837 | count = desc_count(bufs[end]) - info->rbuf_index; | |
1838 | p = bufs[end].buf + info->rbuf_index; | |
1839 | ||
1840 | DBGISR(("%s rx_async count=%d\n", info->device_name, count)); | |
1841 | DBGDATA(info, p, count, "rx"); | |
1842 | ||
1843 | for(i=0 ; i < count; i+=2, p+=2) { | |
33f0f88f | 1844 | ch = *p; |
705b6c7b PF |
1845 | icount->rx++; |
1846 | ||
33f0f88f AC |
1847 | stat = 0; |
1848 | ||
202af6d5 PF |
1849 | if ((status = *(p+1) & (BIT1 + BIT0))) { |
1850 | if (status & BIT1) | |
705b6c7b | 1851 | icount->parity++; |
202af6d5 | 1852 | else if (status & BIT0) |
705b6c7b PF |
1853 | icount->frame++; |
1854 | /* discard char if tty control flags say so */ | |
1855 | if (status & info->ignore_status_mask) | |
1856 | continue; | |
202af6d5 | 1857 | if (status & BIT1) |
33f0f88f | 1858 | stat = TTY_PARITY; |
202af6d5 | 1859 | else if (status & BIT0) |
33f0f88f | 1860 | stat = TTY_FRAME; |
705b6c7b PF |
1861 | } |
1862 | if (tty) { | |
33f0f88f AC |
1863 | tty_insert_flip_char(tty, ch, stat); |
1864 | chars++; | |
705b6c7b PF |
1865 | } |
1866 | } | |
1867 | ||
1868 | if (i < count) { | |
1869 | /* receive buffer not completed */ | |
1870 | info->rbuf_index += i; | |
40565f19 | 1871 | mod_timer(&info->rx_timer, jiffies + 1); |
705b6c7b PF |
1872 | break; |
1873 | } | |
1874 | ||
1875 | info->rbuf_index = 0; | |
1876 | free_rbufs(info, end, end); | |
1877 | ||
1878 | if (++end == info->rbuf_count) | |
1879 | end = 0; | |
1880 | ||
1881 | /* if entire list searched then no frame available */ | |
1882 | if (end == start) | |
1883 | break; | |
1884 | } | |
1885 | ||
33f0f88f | 1886 | if (tty && chars) |
705b6c7b PF |
1887 | tty_flip_buffer_push(tty); |
1888 | } | |
1889 | ||
1890 | /* | |
1891 | * return next bottom half action to perform | |
1892 | */ | |
1893 | static int bh_action(struct slgt_info *info) | |
1894 | { | |
1895 | unsigned long flags; | |
1896 | int rc; | |
1897 | ||
1898 | spin_lock_irqsave(&info->lock,flags); | |
1899 | ||
1900 | if (info->pending_bh & BH_RECEIVE) { | |
1901 | info->pending_bh &= ~BH_RECEIVE; | |
1902 | rc = BH_RECEIVE; | |
1903 | } else if (info->pending_bh & BH_TRANSMIT) { | |
1904 | info->pending_bh &= ~BH_TRANSMIT; | |
1905 | rc = BH_TRANSMIT; | |
1906 | } else if (info->pending_bh & BH_STATUS) { | |
1907 | info->pending_bh &= ~BH_STATUS; | |
1908 | rc = BH_STATUS; | |
1909 | } else { | |
1910 | /* Mark BH routine as complete */ | |
0fab6de0 JP |
1911 | info->bh_running = false; |
1912 | info->bh_requested = false; | |
705b6c7b PF |
1913 | rc = 0; |
1914 | } | |
1915 | ||
1916 | spin_unlock_irqrestore(&info->lock,flags); | |
1917 | ||
1918 | return rc; | |
1919 | } | |
1920 | ||
1921 | /* | |
1922 | * perform bottom half processing | |
1923 | */ | |
c4028958 | 1924 | static void bh_handler(struct work_struct *work) |
705b6c7b | 1925 | { |
c4028958 | 1926 | struct slgt_info *info = container_of(work, struct slgt_info, task); |
705b6c7b PF |
1927 | int action; |
1928 | ||
1929 | if (!info) | |
1930 | return; | |
0fab6de0 | 1931 | info->bh_running = true; |
705b6c7b PF |
1932 | |
1933 | while((action = bh_action(info))) { | |
1934 | switch (action) { | |
1935 | case BH_RECEIVE: | |
1936 | DBGBH(("%s bh receive\n", info->device_name)); | |
1937 | switch(info->params.mode) { | |
1938 | case MGSL_MODE_ASYNC: | |
1939 | rx_async(info); | |
1940 | break; | |
1941 | case MGSL_MODE_HDLC: | |
1942 | while(rx_get_frame(info)); | |
1943 | break; | |
1944 | case MGSL_MODE_RAW: | |
cb10dc9a PF |
1945 | case MGSL_MODE_MONOSYNC: |
1946 | case MGSL_MODE_BISYNC: | |
705b6c7b PF |
1947 | while(rx_get_buf(info)); |
1948 | break; | |
1949 | } | |
1950 | /* restart receiver if rx DMA buffers exhausted */ | |
1951 | if (info->rx_restart) | |
1952 | rx_start(info); | |
1953 | break; | |
1954 | case BH_TRANSMIT: | |
1955 | bh_transmit(info); | |
1956 | break; | |
1957 | case BH_STATUS: | |
1958 | DBGBH(("%s bh status\n", info->device_name)); | |
1959 | info->ri_chkcount = 0; | |
1960 | info->dsr_chkcount = 0; | |
1961 | info->dcd_chkcount = 0; | |
1962 | info->cts_chkcount = 0; | |
1963 | break; | |
1964 | default: | |
1965 | DBGBH(("%s unknown action\n", info->device_name)); | |
1966 | break; | |
1967 | } | |
1968 | } | |
1969 | DBGBH(("%s bh_handler exit\n", info->device_name)); | |
1970 | } | |
1971 | ||
1972 | static void bh_transmit(struct slgt_info *info) | |
1973 | { | |
8fb06c77 | 1974 | struct tty_struct *tty = info->port.tty; |
705b6c7b PF |
1975 | |
1976 | DBGBH(("%s bh_transmit\n", info->device_name)); | |
b963a844 | 1977 | if (tty) |
705b6c7b | 1978 | tty_wakeup(tty); |
705b6c7b PF |
1979 | } |
1980 | ||
ed8485fb | 1981 | static void dsr_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 1982 | { |
ed8485fb PF |
1983 | if (status & BIT3) { |
1984 | info->signals |= SerialSignal_DSR; | |
1985 | info->input_signal_events.dsr_up++; | |
1986 | } else { | |
1987 | info->signals &= ~SerialSignal_DSR; | |
1988 | info->input_signal_events.dsr_down++; | |
1989 | } | |
705b6c7b PF |
1990 | DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); |
1991 | if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
1992 | slgt_irq_off(info, IRQ_DSR); | |
1993 | return; | |
1994 | } | |
1995 | info->icount.dsr++; | |
705b6c7b PF |
1996 | wake_up_interruptible(&info->status_event_wait_q); |
1997 | wake_up_interruptible(&info->event_wait_q); | |
1998 | info->pending_bh |= BH_STATUS; | |
1999 | } | |
2000 | ||
ed8485fb | 2001 | static void cts_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2002 | { |
ed8485fb PF |
2003 | if (status & BIT2) { |
2004 | info->signals |= SerialSignal_CTS; | |
2005 | info->input_signal_events.cts_up++; | |
2006 | } else { | |
2007 | info->signals &= ~SerialSignal_CTS; | |
2008 | info->input_signal_events.cts_down++; | |
2009 | } | |
705b6c7b PF |
2010 | DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); |
2011 | if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2012 | slgt_irq_off(info, IRQ_CTS); | |
2013 | return; | |
2014 | } | |
2015 | info->icount.cts++; | |
705b6c7b PF |
2016 | wake_up_interruptible(&info->status_event_wait_q); |
2017 | wake_up_interruptible(&info->event_wait_q); | |
2018 | info->pending_bh |= BH_STATUS; | |
2019 | ||
8fb06c77 AC |
2020 | if (info->port.flags & ASYNC_CTS_FLOW) { |
2021 | if (info->port.tty) { | |
2022 | if (info->port.tty->hw_stopped) { | |
705b6c7b | 2023 | if (info->signals & SerialSignal_CTS) { |
8fb06c77 | 2024 | info->port.tty->hw_stopped = 0; |
705b6c7b PF |
2025 | info->pending_bh |= BH_TRANSMIT; |
2026 | return; | |
2027 | } | |
2028 | } else { | |
2029 | if (!(info->signals & SerialSignal_CTS)) | |
8fb06c77 | 2030 | info->port.tty->hw_stopped = 1; |
705b6c7b PF |
2031 | } |
2032 | } | |
2033 | } | |
2034 | } | |
2035 | ||
ed8485fb | 2036 | static void dcd_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2037 | { |
ed8485fb PF |
2038 | if (status & BIT1) { |
2039 | info->signals |= SerialSignal_DCD; | |
2040 | info->input_signal_events.dcd_up++; | |
2041 | } else { | |
2042 | info->signals &= ~SerialSignal_DCD; | |
2043 | info->input_signal_events.dcd_down++; | |
2044 | } | |
705b6c7b PF |
2045 | DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); |
2046 | if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2047 | slgt_irq_off(info, IRQ_DCD); | |
2048 | return; | |
2049 | } | |
2050 | info->icount.dcd++; | |
af69c7f9 | 2051 | #if SYNCLINK_GENERIC_HDLC |
fbeff3c1 KH |
2052 | if (info->netcount) { |
2053 | if (info->signals & SerialSignal_DCD) | |
2054 | netif_carrier_on(info->netdev); | |
2055 | else | |
2056 | netif_carrier_off(info->netdev); | |
2057 | } | |
705b6c7b PF |
2058 | #endif |
2059 | wake_up_interruptible(&info->status_event_wait_q); | |
2060 | wake_up_interruptible(&info->event_wait_q); | |
2061 | info->pending_bh |= BH_STATUS; | |
2062 | ||
8fb06c77 | 2063 | if (info->port.flags & ASYNC_CHECK_CD) { |
705b6c7b | 2064 | if (info->signals & SerialSignal_DCD) |
8fb06c77 | 2065 | wake_up_interruptible(&info->port.open_wait); |
705b6c7b | 2066 | else { |
8fb06c77 AC |
2067 | if (info->port.tty) |
2068 | tty_hangup(info->port.tty); | |
705b6c7b PF |
2069 | } |
2070 | } | |
2071 | } | |
2072 | ||
ed8485fb | 2073 | static void ri_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2074 | { |
ed8485fb PF |
2075 | if (status & BIT0) { |
2076 | info->signals |= SerialSignal_RI; | |
2077 | info->input_signal_events.ri_up++; | |
2078 | } else { | |
2079 | info->signals &= ~SerialSignal_RI; | |
2080 | info->input_signal_events.ri_down++; | |
2081 | } | |
705b6c7b PF |
2082 | DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); |
2083 | if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2084 | slgt_irq_off(info, IRQ_RI); | |
2085 | return; | |
2086 | } | |
ed8485fb | 2087 | info->icount.rng++; |
705b6c7b PF |
2088 | wake_up_interruptible(&info->status_event_wait_q); |
2089 | wake_up_interruptible(&info->event_wait_q); | |
2090 | info->pending_bh |= BH_STATUS; | |
2091 | } | |
2092 | ||
5ba5a5d2 PF |
2093 | static void isr_rxdata(struct slgt_info *info) |
2094 | { | |
2095 | unsigned int count = info->rbuf_fill_count; | |
2096 | unsigned int i = info->rbuf_fill_index; | |
2097 | unsigned short reg; | |
2098 | ||
2099 | while (rd_reg16(info, SSR) & IRQ_RXDATA) { | |
2100 | reg = rd_reg16(info, RDR); | |
2101 | DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg)); | |
2102 | if (desc_complete(info->rbufs[i])) { | |
2103 | /* all buffers full */ | |
2104 | rx_stop(info); | |
2105 | info->rx_restart = 1; | |
2106 | continue; | |
2107 | } | |
2108 | info->rbufs[i].buf[count++] = (unsigned char)reg; | |
2109 | /* async mode saves status byte to buffer for each data byte */ | |
2110 | if (info->params.mode == MGSL_MODE_ASYNC) | |
2111 | info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8); | |
2112 | if (count == info->rbuf_fill_level || (reg & BIT10)) { | |
2113 | /* buffer full or end of frame */ | |
2114 | set_desc_count(info->rbufs[i], count); | |
2115 | set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); | |
2116 | info->rbuf_fill_count = count = 0; | |
2117 | if (++i == info->rbuf_count) | |
2118 | i = 0; | |
2119 | info->pending_bh |= BH_RECEIVE; | |
2120 | } | |
2121 | } | |
2122 | ||
2123 | info->rbuf_fill_index = i; | |
2124 | info->rbuf_fill_count = count; | |
2125 | } | |
2126 | ||
705b6c7b PF |
2127 | static void isr_serial(struct slgt_info *info) |
2128 | { | |
2129 | unsigned short status = rd_reg16(info, SSR); | |
2130 | ||
2131 | DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); | |
2132 | ||
2133 | wr_reg16(info, SSR, status); /* clear pending */ | |
2134 | ||
0fab6de0 | 2135 | info->irq_occurred = true; |
705b6c7b PF |
2136 | |
2137 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
2138 | if (status & IRQ_TXIDLE) { | |
de538eb3 | 2139 | if (info->tx_active) |
705b6c7b PF |
2140 | isr_txeom(info, status); |
2141 | } | |
5ba5a5d2 PF |
2142 | if (info->rx_pio && (status & IRQ_RXDATA)) |
2143 | isr_rxdata(info); | |
705b6c7b PF |
2144 | if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { |
2145 | info->icount.brk++; | |
2146 | /* process break detection if tty control allows */ | |
8fb06c77 | 2147 | if (info->port.tty) { |
705b6c7b PF |
2148 | if (!(status & info->ignore_status_mask)) { |
2149 | if (info->read_status_mask & MASK_BREAK) { | |
8fb06c77 AC |
2150 | tty_insert_flip_char(info->port.tty, 0, TTY_BREAK); |
2151 | if (info->port.flags & ASYNC_SAK) | |
2152 | do_SAK(info->port.tty); | |
705b6c7b PF |
2153 | } |
2154 | } | |
2155 | } | |
2156 | } | |
2157 | } else { | |
2158 | if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) | |
2159 | isr_txeom(info, status); | |
5ba5a5d2 PF |
2160 | if (info->rx_pio && (status & IRQ_RXDATA)) |
2161 | isr_rxdata(info); | |
705b6c7b PF |
2162 | if (status & IRQ_RXIDLE) { |
2163 | if (status & RXIDLE) | |
2164 | info->icount.rxidle++; | |
2165 | else | |
2166 | info->icount.exithunt++; | |
2167 | wake_up_interruptible(&info->event_wait_q); | |
2168 | } | |
2169 | ||
2170 | if (status & IRQ_RXOVER) | |
2171 | rx_start(info); | |
2172 | } | |
2173 | ||
2174 | if (status & IRQ_DSR) | |
ed8485fb | 2175 | dsr_change(info, status); |
705b6c7b | 2176 | if (status & IRQ_CTS) |
ed8485fb | 2177 | cts_change(info, status); |
705b6c7b | 2178 | if (status & IRQ_DCD) |
ed8485fb | 2179 | dcd_change(info, status); |
705b6c7b | 2180 | if (status & IRQ_RI) |
ed8485fb | 2181 | ri_change(info, status); |
705b6c7b PF |
2182 | } |
2183 | ||
2184 | static void isr_rdma(struct slgt_info *info) | |
2185 | { | |
2186 | unsigned int status = rd_reg32(info, RDCSR); | |
2187 | ||
2188 | DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); | |
2189 | ||
2190 | /* RDCSR (rx DMA control/status) | |
2191 | * | |
2192 | * 31..07 reserved | |
2193 | * 06 save status byte to DMA buffer | |
2194 | * 05 error | |
2195 | * 04 eol (end of list) | |
2196 | * 03 eob (end of buffer) | |
2197 | * 02 IRQ enable | |
2198 | * 01 reset | |
2199 | * 00 enable | |
2200 | */ | |
2201 | wr_reg32(info, RDCSR, status); /* clear pending */ | |
2202 | ||
2203 | if (status & (BIT5 + BIT4)) { | |
2204 | DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); | |
0fab6de0 | 2205 | info->rx_restart = true; |
705b6c7b PF |
2206 | } |
2207 | info->pending_bh |= BH_RECEIVE; | |
2208 | } | |
2209 | ||
2210 | static void isr_tdma(struct slgt_info *info) | |
2211 | { | |
2212 | unsigned int status = rd_reg32(info, TDCSR); | |
2213 | ||
2214 | DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); | |
2215 | ||
2216 | /* TDCSR (tx DMA control/status) | |
2217 | * | |
2218 | * 31..06 reserved | |
2219 | * 05 error | |
2220 | * 04 eol (end of list) | |
2221 | * 03 eob (end of buffer) | |
2222 | * 02 IRQ enable | |
2223 | * 01 reset | |
2224 | * 00 enable | |
2225 | */ | |
2226 | wr_reg32(info, TDCSR, status); /* clear pending */ | |
2227 | ||
2228 | if (status & (BIT5 + BIT4 + BIT3)) { | |
2229 | // another transmit buffer has completed | |
2230 | // run bottom half to get more send data from user | |
2231 | info->pending_bh |= BH_TRANSMIT; | |
2232 | } | |
2233 | } | |
2234 | ||
de538eb3 PF |
2235 | /* |
2236 | * return true if there are unsent tx DMA buffers, otherwise false | |
2237 | * | |
2238 | * if there are unsent buffers then info->tbuf_start | |
2239 | * is set to index of first unsent buffer | |
2240 | */ | |
2241 | static bool unsent_tbufs(struct slgt_info *info) | |
2242 | { | |
2243 | unsigned int i = info->tbuf_current; | |
2244 | bool rc = false; | |
2245 | ||
2246 | /* | |
2247 | * search backwards from last loaded buffer (precedes tbuf_current) | |
2248 | * for first unsent buffer (desc_count > 0) | |
2249 | */ | |
2250 | ||
2251 | do { | |
2252 | if (i) | |
2253 | i--; | |
2254 | else | |
2255 | i = info->tbuf_count - 1; | |
2256 | if (!desc_count(info->tbufs[i])) | |
2257 | break; | |
2258 | info->tbuf_start = i; | |
2259 | rc = true; | |
2260 | } while (i != info->tbuf_current); | |
2261 | ||
2262 | return rc; | |
2263 | } | |
2264 | ||
705b6c7b PF |
2265 | static void isr_txeom(struct slgt_info *info, unsigned short status) |
2266 | { | |
2267 | DBGISR(("%s txeom status=%04x\n", info->device_name, status)); | |
2268 | ||
2269 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
2270 | tdma_reset(info); | |
705b6c7b PF |
2271 | if (status & IRQ_TXUNDER) { |
2272 | unsigned short val = rd_reg16(info, TCR); | |
2273 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
2274 | wr_reg16(info, TCR, val); /* clear reset bit */ | |
2275 | } | |
2276 | ||
2277 | if (info->tx_active) { | |
2278 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
2279 | if (status & IRQ_TXUNDER) | |
2280 | info->icount.txunder++; | |
2281 | else if (status & IRQ_TXIDLE) | |
2282 | info->icount.txok++; | |
2283 | } | |
2284 | ||
de538eb3 PF |
2285 | if (unsent_tbufs(info)) { |
2286 | tx_start(info); | |
2287 | update_tx_timer(info); | |
2288 | return; | |
2289 | } | |
0fab6de0 | 2290 | info->tx_active = false; |
705b6c7b PF |
2291 | |
2292 | del_timer(&info->tx_timer); | |
2293 | ||
2294 | if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { | |
2295 | info->signals &= ~SerialSignal_RTS; | |
0fab6de0 | 2296 | info->drop_rts_on_tx_done = false; |
705b6c7b PF |
2297 | set_signals(info); |
2298 | } | |
2299 | ||
af69c7f9 | 2300 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
2301 | if (info->netcount) |
2302 | hdlcdev_tx_done(info); | |
2303 | else | |
2304 | #endif | |
2305 | { | |
8fb06c77 | 2306 | if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { |
705b6c7b PF |
2307 | tx_stop(info); |
2308 | return; | |
2309 | } | |
2310 | info->pending_bh |= BH_TRANSMIT; | |
2311 | } | |
2312 | } | |
2313 | } | |
2314 | ||
0080b7aa PF |
2315 | static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state) |
2316 | { | |
2317 | struct cond_wait *w, *prev; | |
2318 | ||
2319 | /* wake processes waiting for specific transitions */ | |
2320 | for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) { | |
2321 | if (w->data & changed) { | |
2322 | w->data = state; | |
2323 | wake_up_interruptible(&w->q); | |
2324 | if (prev != NULL) | |
2325 | prev->next = w->next; | |
2326 | else | |
2327 | info->gpio_wait_q = w->next; | |
2328 | } else | |
2329 | prev = w; | |
2330 | } | |
2331 | } | |
2332 | ||
705b6c7b PF |
2333 | /* interrupt service routine |
2334 | * | |
2335 | * irq interrupt number | |
2336 | * dev_id device ID supplied during interrupt registration | |
705b6c7b | 2337 | */ |
a6f97b29 | 2338 | static irqreturn_t slgt_interrupt(int dummy, void *dev_id) |
705b6c7b | 2339 | { |
a6f97b29 | 2340 | struct slgt_info *info = dev_id; |
705b6c7b PF |
2341 | unsigned int gsr; |
2342 | unsigned int i; | |
2343 | ||
a6f97b29 | 2344 | DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level)); |
705b6c7b PF |
2345 | |
2346 | spin_lock(&info->lock); | |
2347 | ||
2348 | while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { | |
2349 | DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); | |
0fab6de0 | 2350 | info->irq_occurred = true; |
705b6c7b PF |
2351 | for(i=0; i < info->port_count ; i++) { |
2352 | if (info->port_array[i] == NULL) | |
2353 | continue; | |
2354 | if (gsr & (BIT8 << i)) | |
2355 | isr_serial(info->port_array[i]); | |
2356 | if (gsr & (BIT16 << (i*2))) | |
2357 | isr_rdma(info->port_array[i]); | |
2358 | if (gsr & (BIT17 << (i*2))) | |
2359 | isr_tdma(info->port_array[i]); | |
2360 | } | |
2361 | } | |
2362 | ||
0080b7aa PF |
2363 | if (info->gpio_present) { |
2364 | unsigned int state; | |
2365 | unsigned int changed; | |
2366 | while ((changed = rd_reg32(info, IOSR)) != 0) { | |
2367 | DBGISR(("%s iosr=%08x\n", info->device_name, changed)); | |
2368 | /* read latched state of GPIO signals */ | |
2369 | state = rd_reg32(info, IOVR); | |
2370 | /* clear pending GPIO interrupt bits */ | |
2371 | wr_reg32(info, IOSR, changed); | |
2372 | for (i=0 ; i < info->port_count ; i++) { | |
2373 | if (info->port_array[i] != NULL) | |
2374 | isr_gpio(info->port_array[i], changed, state); | |
2375 | } | |
2376 | } | |
2377 | } | |
2378 | ||
705b6c7b PF |
2379 | for(i=0; i < info->port_count ; i++) { |
2380 | struct slgt_info *port = info->port_array[i]; | |
2381 | ||
8fb06c77 | 2382 | if (port && (port->port.count || port->netcount) && |
705b6c7b PF |
2383 | port->pending_bh && !port->bh_running && |
2384 | !port->bh_requested) { | |
2385 | DBGISR(("%s bh queued\n", port->device_name)); | |
2386 | schedule_work(&port->task); | |
0fab6de0 | 2387 | port->bh_requested = true; |
705b6c7b PF |
2388 | } |
2389 | } | |
2390 | ||
2391 | spin_unlock(&info->lock); | |
2392 | ||
a6f97b29 | 2393 | DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level)); |
705b6c7b PF |
2394 | return IRQ_HANDLED; |
2395 | } | |
2396 | ||
2397 | static int startup(struct slgt_info *info) | |
2398 | { | |
2399 | DBGINFO(("%s startup\n", info->device_name)); | |
2400 | ||
8fb06c77 | 2401 | if (info->port.flags & ASYNC_INITIALIZED) |
705b6c7b PF |
2402 | return 0; |
2403 | ||
2404 | if (!info->tx_buf) { | |
2405 | info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); | |
2406 | if (!info->tx_buf) { | |
2407 | DBGERR(("%s can't allocate tx buffer\n", info->device_name)); | |
2408 | return -ENOMEM; | |
2409 | } | |
2410 | } | |
2411 | ||
2412 | info->pending_bh = 0; | |
2413 | ||
2414 | memset(&info->icount, 0, sizeof(info->icount)); | |
2415 | ||
2416 | /* program hardware for current parameters */ | |
2417 | change_params(info); | |
2418 | ||
8fb06c77 AC |
2419 | if (info->port.tty) |
2420 | clear_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
705b6c7b | 2421 | |
8fb06c77 | 2422 | info->port.flags |= ASYNC_INITIALIZED; |
705b6c7b PF |
2423 | |
2424 | return 0; | |
2425 | } | |
2426 | ||
2427 | /* | |
2428 | * called by close() and hangup() to shutdown hardware | |
2429 | */ | |
2430 | static void shutdown(struct slgt_info *info) | |
2431 | { | |
2432 | unsigned long flags; | |
2433 | ||
8fb06c77 | 2434 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
705b6c7b PF |
2435 | return; |
2436 | ||
2437 | DBGINFO(("%s shutdown\n", info->device_name)); | |
2438 | ||
2439 | /* clear status wait queue because status changes */ | |
2440 | /* can't happen after shutting down the hardware */ | |
2441 | wake_up_interruptible(&info->status_event_wait_q); | |
2442 | wake_up_interruptible(&info->event_wait_q); | |
2443 | ||
2444 | del_timer_sync(&info->tx_timer); | |
2445 | del_timer_sync(&info->rx_timer); | |
2446 | ||
2447 | kfree(info->tx_buf); | |
2448 | info->tx_buf = NULL; | |
2449 | ||
2450 | spin_lock_irqsave(&info->lock,flags); | |
2451 | ||
2452 | tx_stop(info); | |
2453 | rx_stop(info); | |
2454 | ||
2455 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
2456 | ||
8fb06c77 | 2457 | if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) { |
705b6c7b PF |
2458 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); |
2459 | set_signals(info); | |
2460 | } | |
2461 | ||
0080b7aa PF |
2462 | flush_cond_wait(&info->gpio_wait_q); |
2463 | ||
705b6c7b PF |
2464 | spin_unlock_irqrestore(&info->lock,flags); |
2465 | ||
8fb06c77 AC |
2466 | if (info->port.tty) |
2467 | set_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
705b6c7b | 2468 | |
8fb06c77 | 2469 | info->port.flags &= ~ASYNC_INITIALIZED; |
705b6c7b PF |
2470 | } |
2471 | ||
2472 | static void program_hw(struct slgt_info *info) | |
2473 | { | |
2474 | unsigned long flags; | |
2475 | ||
2476 | spin_lock_irqsave(&info->lock,flags); | |
2477 | ||
2478 | rx_stop(info); | |
2479 | tx_stop(info); | |
2480 | ||
cb10dc9a | 2481 | if (info->params.mode != MGSL_MODE_ASYNC || |
705b6c7b | 2482 | info->netcount) |
cb10dc9a | 2483 | sync_mode(info); |
705b6c7b PF |
2484 | else |
2485 | async_mode(info); | |
2486 | ||
2487 | set_signals(info); | |
2488 | ||
2489 | info->dcd_chkcount = 0; | |
2490 | info->cts_chkcount = 0; | |
2491 | info->ri_chkcount = 0; | |
2492 | info->dsr_chkcount = 0; | |
2493 | ||
a6b2f87b | 2494 | slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI); |
705b6c7b PF |
2495 | get_signals(info); |
2496 | ||
2497 | if (info->netcount || | |
8fb06c77 | 2498 | (info->port.tty && info->port.tty->termios->c_cflag & CREAD)) |
705b6c7b PF |
2499 | rx_start(info); |
2500 | ||
2501 | spin_unlock_irqrestore(&info->lock,flags); | |
2502 | } | |
2503 | ||
2504 | /* | |
2505 | * reconfigure adapter based on new parameters | |
2506 | */ | |
2507 | static void change_params(struct slgt_info *info) | |
2508 | { | |
2509 | unsigned cflag; | |
2510 | int bits_per_char; | |
2511 | ||
8fb06c77 | 2512 | if (!info->port.tty || !info->port.tty->termios) |
705b6c7b PF |
2513 | return; |
2514 | DBGINFO(("%s change_params\n", info->device_name)); | |
2515 | ||
8fb06c77 | 2516 | cflag = info->port.tty->termios->c_cflag; |
705b6c7b PF |
2517 | |
2518 | /* if B0 rate (hangup) specified then negate DTR and RTS */ | |
2519 | /* otherwise assert DTR and RTS */ | |
2520 | if (cflag & CBAUD) | |
2521 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
2522 | else | |
2523 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
2524 | ||
2525 | /* byte size and parity */ | |
2526 | ||
2527 | switch (cflag & CSIZE) { | |
2528 | case CS5: info->params.data_bits = 5; break; | |
2529 | case CS6: info->params.data_bits = 6; break; | |
2530 | case CS7: info->params.data_bits = 7; break; | |
2531 | case CS8: info->params.data_bits = 8; break; | |
2532 | default: info->params.data_bits = 7; break; | |
2533 | } | |
2534 | ||
2535 | info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; | |
2536 | ||
2537 | if (cflag & PARENB) | |
2538 | info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; | |
2539 | else | |
2540 | info->params.parity = ASYNC_PARITY_NONE; | |
2541 | ||
2542 | /* calculate number of jiffies to transmit a full | |
2543 | * FIFO (32 bytes) at specified data rate | |
2544 | */ | |
2545 | bits_per_char = info->params.data_bits + | |
2546 | info->params.stop_bits + 1; | |
2547 | ||
8fb06c77 | 2548 | info->params.data_rate = tty_get_baud_rate(info->port.tty); |
705b6c7b PF |
2549 | |
2550 | if (info->params.data_rate) { | |
2551 | info->timeout = (32*HZ*bits_per_char) / | |
2552 | info->params.data_rate; | |
2553 | } | |
2554 | info->timeout += HZ/50; /* Add .02 seconds of slop */ | |
2555 | ||
2556 | if (cflag & CRTSCTS) | |
8fb06c77 | 2557 | info->port.flags |= ASYNC_CTS_FLOW; |
705b6c7b | 2558 | else |
8fb06c77 | 2559 | info->port.flags &= ~ASYNC_CTS_FLOW; |
705b6c7b PF |
2560 | |
2561 | if (cflag & CLOCAL) | |
8fb06c77 | 2562 | info->port.flags &= ~ASYNC_CHECK_CD; |
705b6c7b | 2563 | else |
8fb06c77 | 2564 | info->port.flags |= ASYNC_CHECK_CD; |
705b6c7b PF |
2565 | |
2566 | /* process tty input control flags */ | |
2567 | ||
2568 | info->read_status_mask = IRQ_RXOVER; | |
8fb06c77 | 2569 | if (I_INPCK(info->port.tty)) |
705b6c7b | 2570 | info->read_status_mask |= MASK_PARITY | MASK_FRAMING; |
8fb06c77 | 2571 | if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) |
705b6c7b | 2572 | info->read_status_mask |= MASK_BREAK; |
8fb06c77 | 2573 | if (I_IGNPAR(info->port.tty)) |
705b6c7b | 2574 | info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; |
8fb06c77 | 2575 | if (I_IGNBRK(info->port.tty)) { |
705b6c7b PF |
2576 | info->ignore_status_mask |= MASK_BREAK; |
2577 | /* If ignoring parity and break indicators, ignore | |
2578 | * overruns too. (For real raw support). | |
2579 | */ | |
8fb06c77 | 2580 | if (I_IGNPAR(info->port.tty)) |
705b6c7b PF |
2581 | info->ignore_status_mask |= MASK_OVERRUN; |
2582 | } | |
2583 | ||
2584 | program_hw(info); | |
2585 | } | |
2586 | ||
2587 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) | |
2588 | { | |
2589 | DBGINFO(("%s get_stats\n", info->device_name)); | |
2590 | if (!user_icount) { | |
2591 | memset(&info->icount, 0, sizeof(info->icount)); | |
2592 | } else { | |
2593 | if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) | |
2594 | return -EFAULT; | |
2595 | } | |
2596 | return 0; | |
2597 | } | |
2598 | ||
2599 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) | |
2600 | { | |
2601 | DBGINFO(("%s get_params\n", info->device_name)); | |
2602 | if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) | |
2603 | return -EFAULT; | |
2604 | return 0; | |
2605 | } | |
2606 | ||
2607 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) | |
2608 | { | |
2609 | unsigned long flags; | |
2610 | MGSL_PARAMS tmp_params; | |
2611 | ||
2612 | DBGINFO(("%s set_params\n", info->device_name)); | |
2613 | if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) | |
2614 | return -EFAULT; | |
2615 | ||
2616 | spin_lock_irqsave(&info->lock, flags); | |
1f80769f PF |
2617 | if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) |
2618 | info->base_clock = tmp_params.clock_speed; | |
2619 | else | |
2620 | memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); | |
705b6c7b PF |
2621 | spin_unlock_irqrestore(&info->lock, flags); |
2622 | ||
1f80769f | 2623 | program_hw(info); |
705b6c7b PF |
2624 | |
2625 | return 0; | |
2626 | } | |
2627 | ||
2628 | static int get_txidle(struct slgt_info *info, int __user *idle_mode) | |
2629 | { | |
2630 | DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); | |
2631 | if (put_user(info->idle_mode, idle_mode)) | |
2632 | return -EFAULT; | |
2633 | return 0; | |
2634 | } | |
2635 | ||
2636 | static int set_txidle(struct slgt_info *info, int idle_mode) | |
2637 | { | |
2638 | unsigned long flags; | |
2639 | DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); | |
2640 | spin_lock_irqsave(&info->lock,flags); | |
2641 | info->idle_mode = idle_mode; | |
643f3319 PF |
2642 | if (info->params.mode != MGSL_MODE_ASYNC) |
2643 | tx_set_idle(info); | |
705b6c7b PF |
2644 | spin_unlock_irqrestore(&info->lock,flags); |
2645 | return 0; | |
2646 | } | |
2647 | ||
2648 | static int tx_enable(struct slgt_info *info, int enable) | |
2649 | { | |
2650 | unsigned long flags; | |
2651 | DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); | |
2652 | spin_lock_irqsave(&info->lock,flags); | |
2653 | if (enable) { | |
2654 | if (!info->tx_enabled) | |
2655 | tx_start(info); | |
2656 | } else { | |
2657 | if (info->tx_enabled) | |
2658 | tx_stop(info); | |
2659 | } | |
2660 | spin_unlock_irqrestore(&info->lock,flags); | |
2661 | return 0; | |
2662 | } | |
2663 | ||
2664 | /* | |
2665 | * abort transmit HDLC frame | |
2666 | */ | |
2667 | static int tx_abort(struct slgt_info *info) | |
2668 | { | |
2669 | unsigned long flags; | |
2670 | DBGINFO(("%s tx_abort\n", info->device_name)); | |
2671 | spin_lock_irqsave(&info->lock,flags); | |
2672 | tdma_reset(info); | |
2673 | spin_unlock_irqrestore(&info->lock,flags); | |
2674 | return 0; | |
2675 | } | |
2676 | ||
2677 | static int rx_enable(struct slgt_info *info, int enable) | |
2678 | { | |
2679 | unsigned long flags; | |
814dae03 PF |
2680 | unsigned int rbuf_fill_level; |
2681 | DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable)); | |
705b6c7b | 2682 | spin_lock_irqsave(&info->lock,flags); |
814dae03 PF |
2683 | /* |
2684 | * enable[31..16] = receive DMA buffer fill level | |
2685 | * 0 = noop (leave fill level unchanged) | |
2686 | * fill level must be multiple of 4 and <= buffer size | |
2687 | */ | |
2688 | rbuf_fill_level = ((unsigned int)enable) >> 16; | |
2689 | if (rbuf_fill_level) { | |
c68a99cd PF |
2690 | if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) { |
2691 | spin_unlock_irqrestore(&info->lock, flags); | |
814dae03 | 2692 | return -EINVAL; |
c68a99cd | 2693 | } |
814dae03 | 2694 | info->rbuf_fill_level = rbuf_fill_level; |
5ba5a5d2 PF |
2695 | if (rbuf_fill_level < 128) |
2696 | info->rx_pio = 1; /* PIO mode */ | |
2697 | else | |
2698 | info->rx_pio = 0; /* DMA mode */ | |
814dae03 PF |
2699 | rx_stop(info); /* restart receiver to use new fill level */ |
2700 | } | |
2701 | ||
2702 | /* | |
2703 | * enable[1..0] = receiver enable command | |
2704 | * 0 = disable | |
2705 | * 1 = enable | |
2706 | * 2 = enable or force hunt mode if already enabled | |
2707 | */ | |
2708 | enable &= 3; | |
705b6c7b PF |
2709 | if (enable) { |
2710 | if (!info->rx_enabled) | |
2711 | rx_start(info); | |
cb10dc9a PF |
2712 | else if (enable == 2) { |
2713 | /* force hunt mode (write 1 to RCR[3]) */ | |
2714 | wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); | |
2715 | } | |
705b6c7b PF |
2716 | } else { |
2717 | if (info->rx_enabled) | |
2718 | rx_stop(info); | |
2719 | } | |
2720 | spin_unlock_irqrestore(&info->lock,flags); | |
2721 | return 0; | |
2722 | } | |
2723 | ||
2724 | /* | |
2725 | * wait for specified event to occur | |
2726 | */ | |
2727 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) | |
2728 | { | |
2729 | unsigned long flags; | |
2730 | int s; | |
2731 | int rc=0; | |
2732 | struct mgsl_icount cprev, cnow; | |
2733 | int events; | |
2734 | int mask; | |
2735 | struct _input_signal_events oldsigs, newsigs; | |
2736 | DECLARE_WAITQUEUE(wait, current); | |
2737 | ||
2738 | if (get_user(mask, mask_ptr)) | |
2739 | return -EFAULT; | |
2740 | ||
2741 | DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); | |
2742 | ||
2743 | spin_lock_irqsave(&info->lock,flags); | |
2744 | ||
2745 | /* return immediately if state matches requested events */ | |
2746 | get_signals(info); | |
2747 | s = info->signals; | |
2748 | ||
2749 | events = mask & | |
2750 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + | |
2751 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + | |
2752 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + | |
2753 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); | |
2754 | if (events) { | |
2755 | spin_unlock_irqrestore(&info->lock,flags); | |
2756 | goto exit; | |
2757 | } | |
2758 | ||
2759 | /* save current irq counts */ | |
2760 | cprev = info->icount; | |
2761 | oldsigs = info->input_signal_events; | |
2762 | ||
2763 | /* enable hunt and idle irqs if needed */ | |
2764 | if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { | |
2765 | unsigned short val = rd_reg16(info, SCR); | |
2766 | if (!(val & IRQ_RXIDLE)) | |
2767 | wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); | |
2768 | } | |
2769 | ||
2770 | set_current_state(TASK_INTERRUPTIBLE); | |
2771 | add_wait_queue(&info->event_wait_q, &wait); | |
2772 | ||
2773 | spin_unlock_irqrestore(&info->lock,flags); | |
2774 | ||
2775 | for(;;) { | |
2776 | schedule(); | |
2777 | if (signal_pending(current)) { | |
2778 | rc = -ERESTARTSYS; | |
2779 | break; | |
2780 | } | |
2781 | ||
2782 | /* get current irq counts */ | |
2783 | spin_lock_irqsave(&info->lock,flags); | |
2784 | cnow = info->icount; | |
2785 | newsigs = info->input_signal_events; | |
2786 | set_current_state(TASK_INTERRUPTIBLE); | |
2787 | spin_unlock_irqrestore(&info->lock,flags); | |
2788 | ||
2789 | /* if no change, wait aborted for some reason */ | |
2790 | if (newsigs.dsr_up == oldsigs.dsr_up && | |
2791 | newsigs.dsr_down == oldsigs.dsr_down && | |
2792 | newsigs.dcd_up == oldsigs.dcd_up && | |
2793 | newsigs.dcd_down == oldsigs.dcd_down && | |
2794 | newsigs.cts_up == oldsigs.cts_up && | |
2795 | newsigs.cts_down == oldsigs.cts_down && | |
2796 | newsigs.ri_up == oldsigs.ri_up && | |
2797 | newsigs.ri_down == oldsigs.ri_down && | |
2798 | cnow.exithunt == cprev.exithunt && | |
2799 | cnow.rxidle == cprev.rxidle) { | |
2800 | rc = -EIO; | |
2801 | break; | |
2802 | } | |
2803 | ||
2804 | events = mask & | |
2805 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + | |
2806 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + | |
2807 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + | |
2808 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + | |
2809 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + | |
2810 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + | |
2811 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + | |
2812 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + | |
2813 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + | |
2814 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); | |
2815 | if (events) | |
2816 | break; | |
2817 | ||
2818 | cprev = cnow; | |
2819 | oldsigs = newsigs; | |
2820 | } | |
2821 | ||
2822 | remove_wait_queue(&info->event_wait_q, &wait); | |
2823 | set_current_state(TASK_RUNNING); | |
2824 | ||
2825 | ||
2826 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { | |
2827 | spin_lock_irqsave(&info->lock,flags); | |
2828 | if (!waitqueue_active(&info->event_wait_q)) { | |
2829 | /* disable enable exit hunt mode/idle rcvd IRQs */ | |
2830 | wr_reg16(info, SCR, | |
2831 | (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); | |
2832 | } | |
2833 | spin_unlock_irqrestore(&info->lock,flags); | |
2834 | } | |
2835 | exit: | |
2836 | if (rc == 0) | |
2837 | rc = put_user(events, mask_ptr); | |
2838 | return rc; | |
2839 | } | |
2840 | ||
2841 | static int get_interface(struct slgt_info *info, int __user *if_mode) | |
2842 | { | |
2843 | DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); | |
2844 | if (put_user(info->if_mode, if_mode)) | |
2845 | return -EFAULT; | |
2846 | return 0; | |
2847 | } | |
2848 | ||
2849 | static int set_interface(struct slgt_info *info, int if_mode) | |
2850 | { | |
2851 | unsigned long flags; | |
35fbd397 | 2852 | unsigned short val; |
705b6c7b PF |
2853 | |
2854 | DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); | |
2855 | spin_lock_irqsave(&info->lock,flags); | |
2856 | info->if_mode = if_mode; | |
2857 | ||
2858 | msc_set_vcr(info); | |
2859 | ||
2860 | /* TCR (tx control) 07 1=RTS driver control */ | |
2861 | val = rd_reg16(info, TCR); | |
2862 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
2863 | val |= BIT7; | |
2864 | else | |
2865 | val &= ~BIT7; | |
2866 | wr_reg16(info, TCR, val); | |
2867 | ||
2868 | spin_unlock_irqrestore(&info->lock,flags); | |
2869 | return 0; | |
2870 | } | |
2871 | ||
0080b7aa PF |
2872 | /* |
2873 | * set general purpose IO pin state and direction | |
2874 | * | |
2875 | * user_gpio fields: | |
2876 | * state each bit indicates a pin state | |
2877 | * smask set bit indicates pin state to set | |
2878 | * dir each bit indicates a pin direction (0=input, 1=output) | |
2879 | * dmask set bit indicates pin direction to set | |
2880 | */ | |
2881 | static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2882 | { | |
2883 | unsigned long flags; | |
2884 | struct gpio_desc gpio; | |
2885 | __u32 data; | |
2886 | ||
2887 | if (!info->gpio_present) | |
2888 | return -EINVAL; | |
2889 | if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) | |
2890 | return -EFAULT; | |
2891 | DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n", | |
2892 | info->device_name, gpio.state, gpio.smask, | |
2893 | gpio.dir, gpio.dmask)); | |
2894 | ||
2895 | spin_lock_irqsave(&info->lock,flags); | |
2896 | if (gpio.dmask) { | |
2897 | data = rd_reg32(info, IODR); | |
2898 | data |= gpio.dmask & gpio.dir; | |
2899 | data &= ~(gpio.dmask & ~gpio.dir); | |
2900 | wr_reg32(info, IODR, data); | |
2901 | } | |
2902 | if (gpio.smask) { | |
2903 | data = rd_reg32(info, IOVR); | |
2904 | data |= gpio.smask & gpio.state; | |
2905 | data &= ~(gpio.smask & ~gpio.state); | |
2906 | wr_reg32(info, IOVR, data); | |
2907 | } | |
2908 | spin_unlock_irqrestore(&info->lock,flags); | |
2909 | ||
2910 | return 0; | |
2911 | } | |
2912 | ||
2913 | /* | |
2914 | * get general purpose IO pin state and direction | |
2915 | */ | |
2916 | static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2917 | { | |
2918 | struct gpio_desc gpio; | |
2919 | if (!info->gpio_present) | |
2920 | return -EINVAL; | |
2921 | gpio.state = rd_reg32(info, IOVR); | |
2922 | gpio.smask = 0xffffffff; | |
2923 | gpio.dir = rd_reg32(info, IODR); | |
2924 | gpio.dmask = 0xffffffff; | |
2925 | if (copy_to_user(user_gpio, &gpio, sizeof(gpio))) | |
2926 | return -EFAULT; | |
2927 | DBGINFO(("%s get_gpio state=%08x dir=%08x\n", | |
2928 | info->device_name, gpio.state, gpio.dir)); | |
2929 | return 0; | |
2930 | } | |
2931 | ||
2932 | /* | |
2933 | * conditional wait facility | |
2934 | */ | |
2935 | static void init_cond_wait(struct cond_wait *w, unsigned int data) | |
2936 | { | |
2937 | init_waitqueue_head(&w->q); | |
2938 | init_waitqueue_entry(&w->wait, current); | |
2939 | w->data = data; | |
2940 | } | |
2941 | ||
2942 | static void add_cond_wait(struct cond_wait **head, struct cond_wait *w) | |
2943 | { | |
2944 | set_current_state(TASK_INTERRUPTIBLE); | |
2945 | add_wait_queue(&w->q, &w->wait); | |
2946 | w->next = *head; | |
2947 | *head = w; | |
2948 | } | |
2949 | ||
2950 | static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw) | |
2951 | { | |
2952 | struct cond_wait *w, *prev; | |
2953 | remove_wait_queue(&cw->q, &cw->wait); | |
2954 | set_current_state(TASK_RUNNING); | |
2955 | for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) { | |
2956 | if (w == cw) { | |
2957 | if (prev != NULL) | |
2958 | prev->next = w->next; | |
2959 | else | |
2960 | *head = w->next; | |
2961 | break; | |
2962 | } | |
2963 | } | |
2964 | } | |
2965 | ||
2966 | static void flush_cond_wait(struct cond_wait **head) | |
2967 | { | |
2968 | while (*head != NULL) { | |
2969 | wake_up_interruptible(&(*head)->q); | |
2970 | *head = (*head)->next; | |
2971 | } | |
2972 | } | |
2973 | ||
2974 | /* | |
2975 | * wait for general purpose I/O pin(s) to enter specified state | |
2976 | * | |
2977 | * user_gpio fields: | |
2978 | * state - bit indicates target pin state | |
2979 | * smask - set bit indicates watched pin | |
2980 | * | |
2981 | * The wait ends when at least one watched pin enters the specified | |
2982 | * state. When 0 (no error) is returned, user_gpio->state is set to the | |
2983 | * state of all GPIO pins when the wait ends. | |
2984 | * | |
2985 | * Note: Each pin may be a dedicated input, dedicated output, or | |
2986 | * configurable input/output. The number and configuration of pins | |
2987 | * varies with the specific adapter model. Only input pins (dedicated | |
2988 | * or configured) can be monitored with this function. | |
2989 | */ | |
2990 | static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2991 | { | |
2992 | unsigned long flags; | |
2993 | int rc = 0; | |
2994 | struct gpio_desc gpio; | |
2995 | struct cond_wait wait; | |
2996 | u32 state; | |
2997 | ||
2998 | if (!info->gpio_present) | |
2999 | return -EINVAL; | |
3000 | if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) | |
3001 | return -EFAULT; | |
3002 | DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n", | |
3003 | info->device_name, gpio.state, gpio.smask)); | |
3004 | /* ignore output pins identified by set IODR bit */ | |
3005 | if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0) | |
3006 | return -EINVAL; | |
3007 | init_cond_wait(&wait, gpio.smask); | |
3008 | ||
3009 | spin_lock_irqsave(&info->lock, flags); | |
3010 | /* enable interrupts for watched pins */ | |
3011 | wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); | |
3012 | /* get current pin states */ | |
3013 | state = rd_reg32(info, IOVR); | |
3014 | ||
3015 | if (gpio.smask & ~(state ^ gpio.state)) { | |
3016 | /* already in target state */ | |
3017 | gpio.state = state; | |
3018 | } else { | |
3019 | /* wait for target state */ | |
3020 | add_cond_wait(&info->gpio_wait_q, &wait); | |
3021 | spin_unlock_irqrestore(&info->lock, flags); | |
3022 | schedule(); | |
3023 | if (signal_pending(current)) | |
3024 | rc = -ERESTARTSYS; | |
3025 | else | |
3026 | gpio.state = wait.data; | |
3027 | spin_lock_irqsave(&info->lock, flags); | |
3028 | remove_cond_wait(&info->gpio_wait_q, &wait); | |
3029 | } | |
3030 | ||
3031 | /* disable all GPIO interrupts if no waiting processes */ | |
3032 | if (info->gpio_wait_q == NULL) | |
3033 | wr_reg32(info, IOER, 0); | |
3034 | spin_unlock_irqrestore(&info->lock,flags); | |
3035 | ||
3036 | if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio))) | |
3037 | rc = -EFAULT; | |
3038 | return rc; | |
3039 | } | |
3040 | ||
705b6c7b PF |
3041 | static int modem_input_wait(struct slgt_info *info,int arg) |
3042 | { | |
3043 | unsigned long flags; | |
3044 | int rc; | |
3045 | struct mgsl_icount cprev, cnow; | |
3046 | DECLARE_WAITQUEUE(wait, current); | |
3047 | ||
3048 | /* save current irq counts */ | |
3049 | spin_lock_irqsave(&info->lock,flags); | |
3050 | cprev = info->icount; | |
3051 | add_wait_queue(&info->status_event_wait_q, &wait); | |
3052 | set_current_state(TASK_INTERRUPTIBLE); | |
3053 | spin_unlock_irqrestore(&info->lock,flags); | |
3054 | ||
3055 | for(;;) { | |
3056 | schedule(); | |
3057 | if (signal_pending(current)) { | |
3058 | rc = -ERESTARTSYS; | |
3059 | break; | |
3060 | } | |
3061 | ||
3062 | /* get new irq counts */ | |
3063 | spin_lock_irqsave(&info->lock,flags); | |
3064 | cnow = info->icount; | |
3065 | set_current_state(TASK_INTERRUPTIBLE); | |
3066 | spin_unlock_irqrestore(&info->lock,flags); | |
3067 | ||
3068 | /* if no change, wait aborted for some reason */ | |
3069 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && | |
3070 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { | |
3071 | rc = -EIO; | |
3072 | break; | |
3073 | } | |
3074 | ||
3075 | /* check for change in caller specified modem input */ | |
3076 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || | |
3077 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || | |
3078 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || | |
3079 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { | |
3080 | rc = 0; | |
3081 | break; | |
3082 | } | |
3083 | ||
3084 | cprev = cnow; | |
3085 | } | |
3086 | remove_wait_queue(&info->status_event_wait_q, &wait); | |
3087 | set_current_state(TASK_RUNNING); | |
3088 | return rc; | |
3089 | } | |
3090 | ||
3091 | /* | |
3092 | * return state of serial control and status signals | |
3093 | */ | |
3094 | static int tiocmget(struct tty_struct *tty, struct file *file) | |
3095 | { | |
3096 | struct slgt_info *info = tty->driver_data; | |
3097 | unsigned int result; | |
3098 | unsigned long flags; | |
3099 | ||
3100 | spin_lock_irqsave(&info->lock,flags); | |
3101 | get_signals(info); | |
3102 | spin_unlock_irqrestore(&info->lock,flags); | |
3103 | ||
3104 | result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + | |
3105 | ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + | |
3106 | ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + | |
3107 | ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + | |
3108 | ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + | |
3109 | ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); | |
3110 | ||
3111 | DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); | |
3112 | return result; | |
3113 | } | |
3114 | ||
3115 | /* | |
3116 | * set modem control signals (DTR/RTS) | |
3117 | * | |
3118 | * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit | |
3119 | * TIOCMSET = set/clear signal values | |
3120 | * value bit mask for command | |
3121 | */ | |
3122 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
3123 | unsigned int set, unsigned int clear) | |
3124 | { | |
3125 | struct slgt_info *info = tty->driver_data; | |
3126 | unsigned long flags; | |
3127 | ||
3128 | DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); | |
3129 | ||
3130 | if (set & TIOCM_RTS) | |
3131 | info->signals |= SerialSignal_RTS; | |
3132 | if (set & TIOCM_DTR) | |
3133 | info->signals |= SerialSignal_DTR; | |
3134 | if (clear & TIOCM_RTS) | |
3135 | info->signals &= ~SerialSignal_RTS; | |
3136 | if (clear & TIOCM_DTR) | |
3137 | info->signals &= ~SerialSignal_DTR; | |
3138 | ||
3139 | spin_lock_irqsave(&info->lock,flags); | |
3140 | set_signals(info); | |
3141 | spin_unlock_irqrestore(&info->lock,flags); | |
3142 | return 0; | |
3143 | } | |
3144 | ||
31f35939 AC |
3145 | static int carrier_raised(struct tty_port *port) |
3146 | { | |
3147 | unsigned long flags; | |
3148 | struct slgt_info *info = container_of(port, struct slgt_info, port); | |
3149 | ||
3150 | spin_lock_irqsave(&info->lock,flags); | |
3151 | get_signals(info); | |
3152 | spin_unlock_irqrestore(&info->lock,flags); | |
3153 | return (info->signals & SerialSignal_DCD) ? 1 : 0; | |
3154 | } | |
3155 | ||
fcc8ac18 | 3156 | static void dtr_rts(struct tty_port *port, int on) |
5d951fb4 AC |
3157 | { |
3158 | unsigned long flags; | |
3159 | struct slgt_info *info = container_of(port, struct slgt_info, port); | |
3160 | ||
3161 | spin_lock_irqsave(&info->lock,flags); | |
fcc8ac18 AC |
3162 | if (on) |
3163 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
3164 | else | |
3165 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
5d951fb4 AC |
3166 | set_signals(info); |
3167 | spin_unlock_irqrestore(&info->lock,flags); | |
3168 | } | |
3169 | ||
3170 | ||
705b6c7b PF |
3171 | /* |
3172 | * block current process until the device is ready to open | |
3173 | */ | |
3174 | static int block_til_ready(struct tty_struct *tty, struct file *filp, | |
3175 | struct slgt_info *info) | |
3176 | { | |
3177 | DECLARE_WAITQUEUE(wait, current); | |
3178 | int retval; | |
0fab6de0 JP |
3179 | bool do_clocal = false; |
3180 | bool extra_count = false; | |
705b6c7b | 3181 | unsigned long flags; |
31f35939 AC |
3182 | int cd; |
3183 | struct tty_port *port = &info->port; | |
705b6c7b PF |
3184 | |
3185 | DBGINFO(("%s block_til_ready\n", tty->driver->name)); | |
3186 | ||
3187 | if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ | |
3188 | /* nonblock mode is set or port is not enabled */ | |
31f35939 | 3189 | port->flags |= ASYNC_NORMAL_ACTIVE; |
705b6c7b PF |
3190 | return 0; |
3191 | } | |
3192 | ||
3193 | if (tty->termios->c_cflag & CLOCAL) | |
0fab6de0 | 3194 | do_clocal = true; |
705b6c7b PF |
3195 | |
3196 | /* Wait for carrier detect and the line to become | |
3197 | * free (i.e., not in use by the callout). While we are in | |
31f35939 | 3198 | * this loop, port->count is dropped by one, so that |
705b6c7b PF |
3199 | * close() knows when to free things. We restore it upon |
3200 | * exit, either normal or abnormal. | |
3201 | */ | |
3202 | ||
3203 | retval = 0; | |
31f35939 | 3204 | add_wait_queue(&port->open_wait, &wait); |
705b6c7b PF |
3205 | |
3206 | spin_lock_irqsave(&info->lock, flags); | |
3207 | if (!tty_hung_up_p(filp)) { | |
0fab6de0 | 3208 | extra_count = true; |
31f35939 | 3209 | port->count--; |
705b6c7b PF |
3210 | } |
3211 | spin_unlock_irqrestore(&info->lock, flags); | |
31f35939 | 3212 | port->blocked_open++; |
705b6c7b PF |
3213 | |
3214 | while (1) { | |
5d951fb4 AC |
3215 | if ((tty->termios->c_cflag & CBAUD)) |
3216 | tty_port_raise_dtr_rts(port); | |
705b6c7b PF |
3217 | |
3218 | set_current_state(TASK_INTERRUPTIBLE); | |
3219 | ||
31f35939 AC |
3220 | if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ |
3221 | retval = (port->flags & ASYNC_HUP_NOTIFY) ? | |
705b6c7b PF |
3222 | -EAGAIN : -ERESTARTSYS; |
3223 | break; | |
3224 | } | |
3225 | ||
31f35939 | 3226 | cd = tty_port_carrier_raised(port); |
705b6c7b | 3227 | |
31f35939 | 3228 | if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd )) |
705b6c7b | 3229 | break; |
705b6c7b PF |
3230 | |
3231 | if (signal_pending(current)) { | |
3232 | retval = -ERESTARTSYS; | |
3233 | break; | |
3234 | } | |
3235 | ||
3236 | DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); | |
3237 | schedule(); | |
3238 | } | |
3239 | ||
3240 | set_current_state(TASK_RUNNING); | |
31f35939 | 3241 | remove_wait_queue(&port->open_wait, &wait); |
705b6c7b PF |
3242 | |
3243 | if (extra_count) | |
31f35939 AC |
3244 | port->count++; |
3245 | port->blocked_open--; | |
705b6c7b PF |
3246 | |
3247 | if (!retval) | |
31f35939 | 3248 | port->flags |= ASYNC_NORMAL_ACTIVE; |
705b6c7b PF |
3249 | |
3250 | DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); | |
3251 | return retval; | |
3252 | } | |
3253 | ||
3254 | static int alloc_tmp_rbuf(struct slgt_info *info) | |
3255 | { | |
04b374d0 | 3256 | info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL); |
705b6c7b PF |
3257 | if (info->tmp_rbuf == NULL) |
3258 | return -ENOMEM; | |
3259 | return 0; | |
3260 | } | |
3261 | ||
3262 | static void free_tmp_rbuf(struct slgt_info *info) | |
3263 | { | |
3264 | kfree(info->tmp_rbuf); | |
3265 | info->tmp_rbuf = NULL; | |
3266 | } | |
3267 | ||
3268 | /* | |
3269 | * allocate DMA descriptor lists. | |
3270 | */ | |
3271 | static int alloc_desc(struct slgt_info *info) | |
3272 | { | |
3273 | unsigned int i; | |
3274 | unsigned int pbufs; | |
3275 | ||
3276 | /* allocate memory to hold descriptor lists */ | |
3277 | info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr); | |
3278 | if (info->bufs == NULL) | |
3279 | return -ENOMEM; | |
3280 | ||
3281 | memset(info->bufs, 0, DESC_LIST_SIZE); | |
3282 | ||
3283 | info->rbufs = (struct slgt_desc*)info->bufs; | |
3284 | info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; | |
3285 | ||
3286 | pbufs = (unsigned int)info->bufs_dma_addr; | |
3287 | ||
3288 | /* | |
3289 | * Build circular lists of descriptors | |
3290 | */ | |
3291 | ||
3292 | for (i=0; i < info->rbuf_count; i++) { | |
3293 | /* physical address of this descriptor */ | |
3294 | info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); | |
3295 | ||
3296 | /* physical address of next descriptor */ | |
3297 | if (i == info->rbuf_count - 1) | |
3298 | info->rbufs[i].next = cpu_to_le32(pbufs); | |
3299 | else | |
3300 | info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); | |
3301 | set_desc_count(info->rbufs[i], DMABUFSIZE); | |
3302 | } | |
3303 | ||
3304 | for (i=0; i < info->tbuf_count; i++) { | |
3305 | /* physical address of this descriptor */ | |
3306 | info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); | |
3307 | ||
3308 | /* physical address of next descriptor */ | |
3309 | if (i == info->tbuf_count - 1) | |
3310 | info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); | |
3311 | else | |
3312 | info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); | |
3313 | } | |
3314 | ||
3315 | return 0; | |
3316 | } | |
3317 | ||
3318 | static void free_desc(struct slgt_info *info) | |
3319 | { | |
3320 | if (info->bufs != NULL) { | |
3321 | pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr); | |
3322 | info->bufs = NULL; | |
3323 | info->rbufs = NULL; | |
3324 | info->tbufs = NULL; | |
3325 | } | |
3326 | } | |
3327 | ||
3328 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
3329 | { | |
3330 | int i; | |
3331 | for (i=0; i < count; i++) { | |
3332 | if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL) | |
3333 | return -ENOMEM; | |
3334 | bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); | |
3335 | } | |
3336 | return 0; | |
3337 | } | |
3338 | ||
3339 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
3340 | { | |
3341 | int i; | |
3342 | for (i=0; i < count; i++) { | |
3343 | if (bufs[i].buf == NULL) | |
3344 | continue; | |
3345 | pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr); | |
3346 | bufs[i].buf = NULL; | |
3347 | } | |
3348 | } | |
3349 | ||
3350 | static int alloc_dma_bufs(struct slgt_info *info) | |
3351 | { | |
3352 | info->rbuf_count = 32; | |
3353 | info->tbuf_count = 32; | |
3354 | ||
3355 | if (alloc_desc(info) < 0 || | |
3356 | alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || | |
3357 | alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || | |
3358 | alloc_tmp_rbuf(info) < 0) { | |
3359 | DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); | |
3360 | return -ENOMEM; | |
3361 | } | |
3362 | reset_rbufs(info); | |
3363 | return 0; | |
3364 | } | |
3365 | ||
3366 | static void free_dma_bufs(struct slgt_info *info) | |
3367 | { | |
3368 | if (info->bufs) { | |
3369 | free_bufs(info, info->rbufs, info->rbuf_count); | |
3370 | free_bufs(info, info->tbufs, info->tbuf_count); | |
3371 | free_desc(info); | |
3372 | } | |
3373 | free_tmp_rbuf(info); | |
3374 | } | |
3375 | ||
3376 | static int claim_resources(struct slgt_info *info) | |
3377 | { | |
3378 | if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { | |
3379 | DBGERR(("%s reg addr conflict, addr=%08X\n", | |
3380 | info->device_name, info->phys_reg_addr)); | |
3381 | info->init_error = DiagStatus_AddressConflict; | |
3382 | goto errout; | |
3383 | } | |
3384 | else | |
0fab6de0 | 3385 | info->reg_addr_requested = true; |
705b6c7b | 3386 | |
24cb2335 | 3387 | info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE); |
705b6c7b PF |
3388 | if (!info->reg_addr) { |
3389 | DBGERR(("%s cant map device registers, addr=%08X\n", | |
3390 | info->device_name, info->phys_reg_addr)); | |
3391 | info->init_error = DiagStatus_CantAssignPciResources; | |
3392 | goto errout; | |
3393 | } | |
705b6c7b PF |
3394 | return 0; |
3395 | ||
3396 | errout: | |
3397 | release_resources(info); | |
3398 | return -ENODEV; | |
3399 | } | |
3400 | ||
3401 | static void release_resources(struct slgt_info *info) | |
3402 | { | |
3403 | if (info->irq_requested) { | |
3404 | free_irq(info->irq_level, info); | |
0fab6de0 | 3405 | info->irq_requested = false; |
705b6c7b PF |
3406 | } |
3407 | ||
3408 | if (info->reg_addr_requested) { | |
3409 | release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); | |
0fab6de0 | 3410 | info->reg_addr_requested = false; |
705b6c7b PF |
3411 | } |
3412 | ||
3413 | if (info->reg_addr) { | |
0c8365ec | 3414 | iounmap(info->reg_addr); |
705b6c7b PF |
3415 | info->reg_addr = NULL; |
3416 | } | |
3417 | } | |
3418 | ||
3419 | /* Add the specified device instance data structure to the | |
3420 | * global linked list of devices and increment the device count. | |
3421 | */ | |
3422 | static void add_device(struct slgt_info *info) | |
3423 | { | |
3424 | char *devstr; | |
3425 | ||
3426 | info->next_device = NULL; | |
3427 | info->line = slgt_device_count; | |
3428 | sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); | |
3429 | ||
3430 | if (info->line < MAX_DEVICES) { | |
3431 | if (maxframe[info->line]) | |
3432 | info->max_frame_size = maxframe[info->line]; | |
705b6c7b PF |
3433 | } |
3434 | ||
3435 | slgt_device_count++; | |
3436 | ||
3437 | if (!slgt_device_list) | |
3438 | slgt_device_list = info; | |
3439 | else { | |
3440 | struct slgt_info *current_dev = slgt_device_list; | |
3441 | while(current_dev->next_device) | |
3442 | current_dev = current_dev->next_device; | |
3443 | current_dev->next_device = info; | |
3444 | } | |
3445 | ||
3446 | if (info->max_frame_size < 4096) | |
3447 | info->max_frame_size = 4096; | |
3448 | else if (info->max_frame_size > 65535) | |
3449 | info->max_frame_size = 65535; | |
3450 | ||
3451 | switch(info->pdev->device) { | |
3452 | case SYNCLINK_GT_DEVICE_ID: | |
3453 | devstr = "GT"; | |
3454 | break; | |
6f84be84 PF |
3455 | case SYNCLINK_GT2_DEVICE_ID: |
3456 | devstr = "GT2"; | |
3457 | break; | |
705b6c7b PF |
3458 | case SYNCLINK_GT4_DEVICE_ID: |
3459 | devstr = "GT4"; | |
3460 | break; | |
3461 | case SYNCLINK_AC_DEVICE_ID: | |
3462 | devstr = "AC"; | |
3463 | info->params.mode = MGSL_MODE_ASYNC; | |
3464 | break; | |
3465 | default: | |
3466 | devstr = "(unknown model)"; | |
3467 | } | |
3468 | printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", | |
3469 | devstr, info->device_name, info->phys_reg_addr, | |
3470 | info->irq_level, info->max_frame_size); | |
3471 | ||
af69c7f9 | 3472 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
3473 | hdlcdev_init(info); |
3474 | #endif | |
3475 | } | |
3476 | ||
31f35939 AC |
3477 | static const struct tty_port_operations slgt_port_ops = { |
3478 | .carrier_raised = carrier_raised, | |
fcc8ac18 | 3479 | .dtr_rts = dtr_rts, |
31f35939 AC |
3480 | }; |
3481 | ||
705b6c7b PF |
3482 | /* |
3483 | * allocate device instance structure, return NULL on failure | |
3484 | */ | |
3485 | static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) | |
3486 | { | |
3487 | struct slgt_info *info; | |
3488 | ||
dd00cc48 | 3489 | info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL); |
705b6c7b PF |
3490 | |
3491 | if (!info) { | |
3492 | DBGERR(("%s device alloc failed adapter=%d port=%d\n", | |
3493 | driver_name, adapter_num, port_num)); | |
3494 | } else { | |
44b7d1b3 | 3495 | tty_port_init(&info->port); |
31f35939 | 3496 | info->port.ops = &slgt_port_ops; |
705b6c7b | 3497 | info->magic = MGSL_MAGIC; |
c4028958 | 3498 | INIT_WORK(&info->task, bh_handler); |
705b6c7b | 3499 | info->max_frame_size = 4096; |
1f80769f | 3500 | info->base_clock = 14745600; |
814dae03 | 3501 | info->rbuf_fill_level = DMABUFSIZE; |
44b7d1b3 AC |
3502 | info->port.close_delay = 5*HZ/10; |
3503 | info->port.closing_wait = 30*HZ; | |
705b6c7b PF |
3504 | init_waitqueue_head(&info->status_event_wait_q); |
3505 | init_waitqueue_head(&info->event_wait_q); | |
3506 | spin_lock_init(&info->netlock); | |
3507 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
3508 | info->idle_mode = HDLC_TXIDLE_FLAGS; | |
3509 | info->adapter_num = adapter_num; | |
3510 | info->port_num = port_num; | |
3511 | ||
40565f19 JS |
3512 | setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); |
3513 | setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info); | |
705b6c7b PF |
3514 | |
3515 | /* Copy configuration info to device instance data */ | |
3516 | info->pdev = pdev; | |
3517 | info->irq_level = pdev->irq; | |
3518 | info->phys_reg_addr = pci_resource_start(pdev,0); | |
3519 | ||
705b6c7b | 3520 | info->bus_type = MGSL_BUS_TYPE_PCI; |
0f2ed4c6 | 3521 | info->irq_flags = IRQF_SHARED; |
705b6c7b PF |
3522 | |
3523 | info->init_error = -1; /* assume error, set to 0 on successful init */ | |
3524 | } | |
3525 | ||
3526 | return info; | |
3527 | } | |
3528 | ||
3529 | static void device_init(int adapter_num, struct pci_dev *pdev) | |
3530 | { | |
3531 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
3532 | int i; | |
3533 | int port_count = 1; | |
3534 | ||
6f84be84 PF |
3535 | if (pdev->device == SYNCLINK_GT2_DEVICE_ID) |
3536 | port_count = 2; | |
3537 | else if (pdev->device == SYNCLINK_GT4_DEVICE_ID) | |
705b6c7b PF |
3538 | port_count = 4; |
3539 | ||
3540 | /* allocate device instances for all ports */ | |
3541 | for (i=0; i < port_count; ++i) { | |
3542 | port_array[i] = alloc_dev(adapter_num, i, pdev); | |
3543 | if (port_array[i] == NULL) { | |
3544 | for (--i; i >= 0; --i) | |
3545 | kfree(port_array[i]); | |
3546 | return; | |
3547 | } | |
3548 | } | |
3549 | ||
3550 | /* give copy of port_array to all ports and add to device list */ | |
3551 | for (i=0; i < port_count; ++i) { | |
3552 | memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); | |
3553 | add_device(port_array[i]); | |
3554 | port_array[i]->port_count = port_count; | |
3555 | spin_lock_init(&port_array[i]->lock); | |
3556 | } | |
3557 | ||
3558 | /* Allocate and claim adapter resources */ | |
3559 | if (!claim_resources(port_array[0])) { | |
3560 | ||
3561 | alloc_dma_bufs(port_array[0]); | |
3562 | ||
3563 | /* copy resource information from first port to others */ | |
3564 | for (i = 1; i < port_count; ++i) { | |
3565 | port_array[i]->lock = port_array[0]->lock; | |
3566 | port_array[i]->irq_level = port_array[0]->irq_level; | |
3567 | port_array[i]->reg_addr = port_array[0]->reg_addr; | |
3568 | alloc_dma_bufs(port_array[i]); | |
3569 | } | |
3570 | ||
3571 | if (request_irq(port_array[0]->irq_level, | |
3572 | slgt_interrupt, | |
3573 | port_array[0]->irq_flags, | |
3574 | port_array[0]->device_name, | |
3575 | port_array[0]) < 0) { | |
3576 | DBGERR(("%s request_irq failed IRQ=%d\n", | |
3577 | port_array[0]->device_name, | |
3578 | port_array[0]->irq_level)); | |
3579 | } else { | |
0fab6de0 | 3580 | port_array[0]->irq_requested = true; |
705b6c7b | 3581 | adapter_test(port_array[0]); |
0080b7aa | 3582 | for (i=1 ; i < port_count ; i++) { |
705b6c7b | 3583 | port_array[i]->init_error = port_array[0]->init_error; |
0080b7aa PF |
3584 | port_array[i]->gpio_present = port_array[0]->gpio_present; |
3585 | } | |
705b6c7b PF |
3586 | } |
3587 | } | |
62eb5b1f PF |
3588 | |
3589 | for (i=0; i < port_count; ++i) | |
3590 | tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev)); | |
705b6c7b PF |
3591 | } |
3592 | ||
3593 | static int __devinit init_one(struct pci_dev *dev, | |
3594 | const struct pci_device_id *ent) | |
3595 | { | |
3596 | if (pci_enable_device(dev)) { | |
3597 | printk("error enabling pci device %p\n", dev); | |
3598 | return -EIO; | |
3599 | } | |
3600 | pci_set_master(dev); | |
3601 | device_init(slgt_device_count, dev); | |
3602 | return 0; | |
3603 | } | |
3604 | ||
3605 | static void __devexit remove_one(struct pci_dev *dev) | |
3606 | { | |
3607 | } | |
3608 | ||
b68e31d0 | 3609 | static const struct tty_operations ops = { |
705b6c7b PF |
3610 | .open = open, |
3611 | .close = close, | |
3612 | .write = write, | |
3613 | .put_char = put_char, | |
3614 | .flush_chars = flush_chars, | |
3615 | .write_room = write_room, | |
3616 | .chars_in_buffer = chars_in_buffer, | |
3617 | .flush_buffer = flush_buffer, | |
3618 | .ioctl = ioctl, | |
2acdb169 | 3619 | .compat_ioctl = slgt_compat_ioctl, |
705b6c7b PF |
3620 | .throttle = throttle, |
3621 | .unthrottle = unthrottle, | |
3622 | .send_xchar = send_xchar, | |
3623 | .break_ctl = set_break, | |
3624 | .wait_until_sent = wait_until_sent, | |
705b6c7b PF |
3625 | .set_termios = set_termios, |
3626 | .stop = tx_hold, | |
3627 | .start = tx_release, | |
3628 | .hangup = hangup, | |
3629 | .tiocmget = tiocmget, | |
3630 | .tiocmset = tiocmset, | |
a18c56e5 | 3631 | .proc_fops = &synclink_gt_proc_fops, |
705b6c7b PF |
3632 | }; |
3633 | ||
3634 | static void slgt_cleanup(void) | |
3635 | { | |
3636 | int rc; | |
3637 | struct slgt_info *info; | |
3638 | struct slgt_info *tmp; | |
3639 | ||
a6b2f87b | 3640 | printk(KERN_INFO "unload %s\n", driver_name); |
705b6c7b PF |
3641 | |
3642 | if (serial_driver) { | |
62eb5b1f PF |
3643 | for (info=slgt_device_list ; info != NULL ; info=info->next_device) |
3644 | tty_unregister_device(serial_driver, info->line); | |
705b6c7b PF |
3645 | if ((rc = tty_unregister_driver(serial_driver))) |
3646 | DBGERR(("tty_unregister_driver error=%d\n", rc)); | |
3647 | put_tty_driver(serial_driver); | |
3648 | } | |
3649 | ||
3650 | /* reset devices */ | |
3651 | info = slgt_device_list; | |
3652 | while(info) { | |
3653 | reset_port(info); | |
3654 | info = info->next_device; | |
3655 | } | |
3656 | ||
3657 | /* release devices */ | |
3658 | info = slgt_device_list; | |
3659 | while(info) { | |
af69c7f9 | 3660 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
3661 | hdlcdev_exit(info); |
3662 | #endif | |
3663 | free_dma_bufs(info); | |
3664 | free_tmp_rbuf(info); | |
3665 | if (info->port_num == 0) | |
3666 | release_resources(info); | |
3667 | tmp = info; | |
3668 | info = info->next_device; | |
3669 | kfree(tmp); | |
3670 | } | |
3671 | ||
3672 | if (pci_registered) | |
3673 | pci_unregister_driver(&pci_driver); | |
3674 | } | |
3675 | ||
3676 | /* | |
3677 | * Driver initialization entry point. | |
3678 | */ | |
3679 | static int __init slgt_init(void) | |
3680 | { | |
3681 | int rc; | |
3682 | ||
a6b2f87b | 3683 | printk(KERN_INFO "%s\n", driver_name); |
705b6c7b | 3684 | |
705b6c7b PF |
3685 | serial_driver = alloc_tty_driver(MAX_DEVICES); |
3686 | if (!serial_driver) { | |
62eb5b1f PF |
3687 | printk("%s can't allocate tty driver\n", driver_name); |
3688 | return -ENOMEM; | |
705b6c7b PF |
3689 | } |
3690 | ||
3691 | /* Initialize the tty_driver structure */ | |
3692 | ||
3693 | serial_driver->owner = THIS_MODULE; | |
3694 | serial_driver->driver_name = tty_driver_name; | |
3695 | serial_driver->name = tty_dev_prefix; | |
3696 | serial_driver->major = ttymajor; | |
3697 | serial_driver->minor_start = 64; | |
3698 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
3699 | serial_driver->subtype = SERIAL_TYPE_NORMAL; | |
3700 | serial_driver->init_termios = tty_std_termios; | |
3701 | serial_driver->init_termios.c_cflag = | |
3702 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
606d099c AC |
3703 | serial_driver->init_termios.c_ispeed = 9600; |
3704 | serial_driver->init_termios.c_ospeed = 9600; | |
62eb5b1f | 3705 | serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; |
705b6c7b PF |
3706 | tty_set_operations(serial_driver, &ops); |
3707 | if ((rc = tty_register_driver(serial_driver)) < 0) { | |
3708 | DBGERR(("%s can't register serial driver\n", driver_name)); | |
3709 | put_tty_driver(serial_driver); | |
3710 | serial_driver = NULL; | |
3711 | goto error; | |
3712 | } | |
3713 | ||
a6b2f87b PF |
3714 | printk(KERN_INFO "%s, tty major#%d\n", |
3715 | driver_name, serial_driver->major); | |
705b6c7b | 3716 | |
62eb5b1f PF |
3717 | slgt_device_count = 0; |
3718 | if ((rc = pci_register_driver(&pci_driver)) < 0) { | |
3719 | printk("%s pci_register_driver error=%d\n", driver_name, rc); | |
3720 | goto error; | |
3721 | } | |
0fab6de0 | 3722 | pci_registered = true; |
62eb5b1f PF |
3723 | |
3724 | if (!slgt_device_list) | |
3725 | printk("%s no devices found\n",driver_name); | |
3726 | ||
705b6c7b PF |
3727 | return 0; |
3728 | ||
3729 | error: | |
3730 | slgt_cleanup(); | |
3731 | return rc; | |
3732 | } | |
3733 | ||
3734 | static void __exit slgt_exit(void) | |
3735 | { | |
3736 | slgt_cleanup(); | |
3737 | } | |
3738 | ||
3739 | module_init(slgt_init); | |
3740 | module_exit(slgt_exit); | |
3741 | ||
3742 | /* | |
3743 | * register access routines | |
3744 | */ | |
3745 | ||
3746 | #define CALC_REGADDR() \ | |
3747 | unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ | |
3748 | if (addr >= 0x80) \ | |
3749 | reg_addr += (info->port_num) * 32; | |
3750 | ||
3751 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) | |
3752 | { | |
3753 | CALC_REGADDR(); | |
3754 | return readb((void __iomem *)reg_addr); | |
3755 | } | |
3756 | ||
3757 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) | |
3758 | { | |
3759 | CALC_REGADDR(); | |
3760 | writeb(value, (void __iomem *)reg_addr); | |
3761 | } | |
3762 | ||
3763 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) | |
3764 | { | |
3765 | CALC_REGADDR(); | |
3766 | return readw((void __iomem *)reg_addr); | |
3767 | } | |
3768 | ||
3769 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) | |
3770 | { | |
3771 | CALC_REGADDR(); | |
3772 | writew(value, (void __iomem *)reg_addr); | |
3773 | } | |
3774 | ||
3775 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) | |
3776 | { | |
3777 | CALC_REGADDR(); | |
3778 | return readl((void __iomem *)reg_addr); | |
3779 | } | |
3780 | ||
3781 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) | |
3782 | { | |
3783 | CALC_REGADDR(); | |
3784 | writel(value, (void __iomem *)reg_addr); | |
3785 | } | |
3786 | ||
3787 | static void rdma_reset(struct slgt_info *info) | |
3788 | { | |
3789 | unsigned int i; | |
3790 | ||
3791 | /* set reset bit */ | |
3792 | wr_reg32(info, RDCSR, BIT1); | |
3793 | ||
3794 | /* wait for enable bit cleared */ | |
3795 | for(i=0 ; i < 1000 ; i++) | |
3796 | if (!(rd_reg32(info, RDCSR) & BIT0)) | |
3797 | break; | |
3798 | } | |
3799 | ||
3800 | static void tdma_reset(struct slgt_info *info) | |
3801 | { | |
3802 | unsigned int i; | |
3803 | ||
3804 | /* set reset bit */ | |
3805 | wr_reg32(info, TDCSR, BIT1); | |
3806 | ||
3807 | /* wait for enable bit cleared */ | |
3808 | for(i=0 ; i < 1000 ; i++) | |
3809 | if (!(rd_reg32(info, TDCSR) & BIT0)) | |
3810 | break; | |
3811 | } | |
3812 | ||
3813 | /* | |
3814 | * enable internal loopback | |
3815 | * TxCLK and RxCLK are generated from BRG | |
3816 | * and TxD is looped back to RxD internally. | |
3817 | */ | |
3818 | static void enable_loopback(struct slgt_info *info) | |
3819 | { | |
3820 | /* SCR (serial control) BIT2=looopback enable */ | |
3821 | wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); | |
3822 | ||
3823 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3824 | /* CCR (clock control) | |
3825 | * 07..05 tx clock source (010 = BRG) | |
3826 | * 04..02 rx clock source (010 = BRG) | |
3827 | * 01 auxclk enable (0 = disable) | |
3828 | * 00 BRG enable (1 = enable) | |
3829 | * | |
3830 | * 0100 1001 | |
3831 | */ | |
3832 | wr_reg8(info, CCR, 0x49); | |
3833 | ||
3834 | /* set speed if available, otherwise use default */ | |
3835 | if (info->params.clock_speed) | |
3836 | set_rate(info, info->params.clock_speed); | |
3837 | else | |
3838 | set_rate(info, 3686400); | |
3839 | } | |
3840 | } | |
3841 | ||
3842 | /* | |
3843 | * set baud rate generator to specified rate | |
3844 | */ | |
3845 | static void set_rate(struct slgt_info *info, u32 rate) | |
3846 | { | |
3847 | unsigned int div; | |
1f80769f | 3848 | unsigned int osc = info->base_clock; |
705b6c7b PF |
3849 | |
3850 | /* div = osc/rate - 1 | |
3851 | * | |
3852 | * Round div up if osc/rate is not integer to | |
3853 | * force to next slowest rate. | |
3854 | */ | |
3855 | ||
3856 | if (rate) { | |
3857 | div = osc/rate; | |
3858 | if (!(osc % rate) && div) | |
3859 | div--; | |
3860 | wr_reg16(info, BDR, (unsigned short)div); | |
3861 | } | |
3862 | } | |
3863 | ||
3864 | static void rx_stop(struct slgt_info *info) | |
3865 | { | |
3866 | unsigned short val; | |
3867 | ||
3868 | /* disable and reset receiver */ | |
3869 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3870 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3871 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3872 | ||
3873 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); | |
3874 | ||
3875 | /* clear pending rx interrupts */ | |
3876 | wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); | |
3877 | ||
3878 | rdma_reset(info); | |
3879 | ||
0fab6de0 JP |
3880 | info->rx_enabled = false; |
3881 | info->rx_restart = false; | |
705b6c7b PF |
3882 | } |
3883 | ||
3884 | static void rx_start(struct slgt_info *info) | |
3885 | { | |
3886 | unsigned short val; | |
3887 | ||
3888 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); | |
3889 | ||
3890 | /* clear pending rx overrun IRQ */ | |
3891 | wr_reg16(info, SSR, IRQ_RXOVER); | |
3892 | ||
3893 | /* reset and disable receiver */ | |
3894 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3895 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3896 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3897 | ||
3898 | rdma_reset(info); | |
3899 | reset_rbufs(info); | |
3900 | ||
5ba5a5d2 PF |
3901 | if (info->rx_pio) { |
3902 | /* rx request when rx FIFO not empty */ | |
3903 | wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14)); | |
3904 | slgt_irq_on(info, IRQ_RXDATA); | |
3905 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
3906 | /* enable saving of rx status */ | |
3907 | wr_reg32(info, RDCSR, BIT6); | |
3908 | } | |
705b6c7b | 3909 | } else { |
5ba5a5d2 PF |
3910 | /* rx request when rx FIFO half full */ |
3911 | wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14)); | |
3912 | /* set 1st descriptor address */ | |
3913 | wr_reg32(info, RDDAR, info->rbufs[0].pdesc); | |
3914 | ||
3915 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3916 | /* enable rx DMA and DMA interrupt */ | |
3917 | wr_reg32(info, RDCSR, (BIT2 + BIT0)); | |
3918 | } else { | |
3919 | /* enable saving of rx status, rx DMA and DMA interrupt */ | |
3920 | wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); | |
3921 | } | |
705b6c7b PF |
3922 | } |
3923 | ||
3924 | slgt_irq_on(info, IRQ_RXOVER); | |
3925 | ||
3926 | /* enable receiver */ | |
3927 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); | |
3928 | ||
0fab6de0 JP |
3929 | info->rx_restart = false; |
3930 | info->rx_enabled = true; | |
705b6c7b PF |
3931 | } |
3932 | ||
3933 | static void tx_start(struct slgt_info *info) | |
3934 | { | |
3935 | if (!info->tx_enabled) { | |
3936 | wr_reg16(info, TCR, | |
cb10dc9a | 3937 | (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); |
0fab6de0 | 3938 | info->tx_enabled = true; |
705b6c7b PF |
3939 | } |
3940 | ||
de538eb3 | 3941 | if (desc_count(info->tbufs[info->tbuf_start])) { |
0fab6de0 | 3942 | info->drop_rts_on_tx_done = false; |
705b6c7b PF |
3943 | |
3944 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3945 | if (info->params.flags & HDLC_FLAG_AUTO_RTS) { | |
3946 | get_signals(info); | |
3947 | if (!(info->signals & SerialSignal_RTS)) { | |
3948 | info->signals |= SerialSignal_RTS; | |
3949 | set_signals(info); | |
0fab6de0 | 3950 | info->drop_rts_on_tx_done = true; |
705b6c7b PF |
3951 | } |
3952 | } | |
3953 | ||
3954 | slgt_irq_off(info, IRQ_TXDATA); | |
3955 | slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); | |
3956 | /* clear tx idle and underrun status bits */ | |
3957 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
705b6c7b | 3958 | } else { |
705b6c7b PF |
3959 | slgt_irq_off(info, IRQ_TXDATA); |
3960 | slgt_irq_on(info, IRQ_TXIDLE); | |
3961 | /* clear tx idle status bit */ | |
3962 | wr_reg16(info, SSR, IRQ_TXIDLE); | |
705b6c7b | 3963 | } |
ce89294c PF |
3964 | /* set 1st descriptor address and start DMA */ |
3965 | wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); | |
3966 | wr_reg32(info, TDCSR, BIT2 + BIT0); | |
0fab6de0 | 3967 | info->tx_active = true; |
705b6c7b PF |
3968 | } |
3969 | } | |
3970 | ||
3971 | static void tx_stop(struct slgt_info *info) | |
3972 | { | |
3973 | unsigned short val; | |
3974 | ||
3975 | del_timer(&info->tx_timer); | |
3976 | ||
3977 | tdma_reset(info); | |
3978 | ||
3979 | /* reset and disable transmitter */ | |
3980 | val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ | |
3981 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
705b6c7b PF |
3982 | |
3983 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
3984 | ||
3985 | /* clear tx idle and underrun status bit */ | |
3986 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
3987 | ||
3988 | reset_tbufs(info); | |
3989 | ||
0fab6de0 JP |
3990 | info->tx_enabled = false; |
3991 | info->tx_active = false; | |
705b6c7b PF |
3992 | } |
3993 | ||
3994 | static void reset_port(struct slgt_info *info) | |
3995 | { | |
3996 | if (!info->reg_addr) | |
3997 | return; | |
3998 | ||
3999 | tx_stop(info); | |
4000 | rx_stop(info); | |
4001 | ||
4002 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); | |
4003 | set_signals(info); | |
4004 | ||
4005 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
4006 | } | |
4007 | ||
4008 | static void reset_adapter(struct slgt_info *info) | |
4009 | { | |
4010 | int i; | |
4011 | for (i=0; i < info->port_count; ++i) { | |
4012 | if (info->port_array[i]) | |
4013 | reset_port(info->port_array[i]); | |
4014 | } | |
4015 | } | |
4016 | ||
4017 | static void async_mode(struct slgt_info *info) | |
4018 | { | |
4019 | unsigned short val; | |
4020 | ||
4021 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
4022 | tx_stop(info); | |
4023 | rx_stop(info); | |
4024 | ||
4025 | /* TCR (tx control) | |
4026 | * | |
4027 | * 15..13 mode, 010=async | |
4028 | * 12..10 encoding, 000=NRZ | |
4029 | * 09 parity enable | |
4030 | * 08 1=odd parity, 0=even parity | |
4031 | * 07 1=RTS driver control | |
4032 | * 06 1=break enable | |
4033 | * 05..04 character length | |
4034 | * 00=5 bits | |
4035 | * 01=6 bits | |
4036 | * 10=7 bits | |
4037 | * 11=8 bits | |
4038 | * 03 0=1 stop bit, 1=2 stop bits | |
4039 | * 02 reset | |
4040 | * 01 enable | |
4041 | * 00 auto-CTS enable | |
4042 | */ | |
4043 | val = 0x4000; | |
4044 | ||
4045 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
4046 | val |= BIT7; | |
4047 | ||
4048 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4049 | val |= BIT9; | |
4050 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4051 | val |= BIT8; | |
4052 | } | |
4053 | ||
4054 | switch (info->params.data_bits) | |
4055 | { | |
4056 | case 6: val |= BIT4; break; | |
4057 | case 7: val |= BIT5; break; | |
4058 | case 8: val |= BIT5 + BIT4; break; | |
4059 | } | |
4060 | ||
4061 | if (info->params.stop_bits != 1) | |
4062 | val |= BIT3; | |
4063 | ||
4064 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4065 | val |= BIT0; | |
4066 | ||
4067 | wr_reg16(info, TCR, val); | |
4068 | ||
4069 | /* RCR (rx control) | |
4070 | * | |
4071 | * 15..13 mode, 010=async | |
4072 | * 12..10 encoding, 000=NRZ | |
4073 | * 09 parity enable | |
4074 | * 08 1=odd parity, 0=even parity | |
4075 | * 07..06 reserved, must be 0 | |
4076 | * 05..04 character length | |
4077 | * 00=5 bits | |
4078 | * 01=6 bits | |
4079 | * 10=7 bits | |
4080 | * 11=8 bits | |
4081 | * 03 reserved, must be zero | |
4082 | * 02 reset | |
4083 | * 01 enable | |
4084 | * 00 auto-DCD enable | |
4085 | */ | |
4086 | val = 0x4000; | |
4087 | ||
4088 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4089 | val |= BIT9; | |
4090 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4091 | val |= BIT8; | |
4092 | } | |
4093 | ||
4094 | switch (info->params.data_bits) | |
4095 | { | |
4096 | case 6: val |= BIT4; break; | |
4097 | case 7: val |= BIT5; break; | |
4098 | case 8: val |= BIT5 + BIT4; break; | |
4099 | } | |
4100 | ||
4101 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4102 | val |= BIT0; | |
4103 | ||
4104 | wr_reg16(info, RCR, val); | |
4105 | ||
4106 | /* CCR (clock control) | |
4107 | * | |
4108 | * 07..05 011 = tx clock source is BRG/16 | |
4109 | * 04..02 010 = rx clock source is BRG | |
4110 | * 01 0 = auxclk disabled | |
4111 | * 00 1 = BRG enabled | |
4112 | * | |
4113 | * 0110 1001 | |
4114 | */ | |
4115 | wr_reg8(info, CCR, 0x69); | |
4116 | ||
4117 | msc_set_vcr(info); | |
4118 | ||
705b6c7b PF |
4119 | /* SCR (serial control) |
4120 | * | |
4121 | * 15 1=tx req on FIFO half empty | |
4122 | * 14 1=rx req on FIFO half full | |
4123 | * 13 tx data IRQ enable | |
4124 | * 12 tx idle IRQ enable | |
4125 | * 11 rx break on IRQ enable | |
4126 | * 10 rx data IRQ enable | |
4127 | * 09 rx break off IRQ enable | |
4128 | * 08 overrun IRQ enable | |
4129 | * 07 DSR IRQ enable | |
4130 | * 06 CTS IRQ enable | |
4131 | * 05 DCD IRQ enable | |
4132 | * 04 RI IRQ enable | |
1f80769f | 4133 | * 03 0=16x sampling, 1=8x sampling |
705b6c7b PF |
4134 | * 02 1=txd->rxd internal loopback enable |
4135 | * 01 reserved, must be zero | |
4136 | * 00 1=master IRQ enable | |
4137 | */ | |
4138 | val = BIT15 + BIT14 + BIT0; | |
1f80769f PF |
4139 | /* JCR[8] : 1 = x8 async mode feature available */ |
4140 | if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && | |
4141 | ((info->base_clock < (info->params.data_rate * 16)) || | |
4142 | (info->base_clock % (info->params.data_rate * 16)))) { | |
4143 | /* use 8x sampling */ | |
4144 | val |= BIT3; | |
4145 | set_rate(info, info->params.data_rate * 8); | |
4146 | } else { | |
4147 | /* use 16x sampling */ | |
4148 | set_rate(info, info->params.data_rate * 16); | |
4149 | } | |
705b6c7b PF |
4150 | wr_reg16(info, SCR, val); |
4151 | ||
4152 | slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); | |
4153 | ||
705b6c7b PF |
4154 | if (info->params.loopback) |
4155 | enable_loopback(info); | |
4156 | } | |
4157 | ||
cb10dc9a | 4158 | static void sync_mode(struct slgt_info *info) |
705b6c7b PF |
4159 | { |
4160 | unsigned short val; | |
4161 | ||
4162 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
4163 | tx_stop(info); | |
4164 | rx_stop(info); | |
4165 | ||
4166 | /* TCR (tx control) | |
4167 | * | |
cb10dc9a | 4168 | * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync |
705b6c7b PF |
4169 | * 12..10 encoding |
4170 | * 09 CRC enable | |
4171 | * 08 CRC32 | |
4172 | * 07 1=RTS driver control | |
4173 | * 06 preamble enable | |
4174 | * 05..04 preamble length | |
4175 | * 03 share open/close flag | |
4176 | * 02 reset | |
4177 | * 01 enable | |
4178 | * 00 auto-CTS enable | |
4179 | */ | |
993456cd | 4180 | val = BIT2; |
705b6c7b | 4181 | |
cb10dc9a PF |
4182 | switch(info->params.mode) { |
4183 | case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; | |
4184 | case MGSL_MODE_BISYNC: val |= BIT15; break; | |
4185 | case MGSL_MODE_RAW: val |= BIT13; break; | |
4186 | } | |
705b6c7b PF |
4187 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) |
4188 | val |= BIT7; | |
4189 | ||
4190 | switch(info->params.encoding) | |
4191 | { | |
4192 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
4193 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
4194 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
4195 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
4196 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
4197 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
4198 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
4199 | } | |
4200 | ||
04b374d0 | 4201 | switch (info->params.crc_type & HDLC_CRC_MASK) |
705b6c7b PF |
4202 | { |
4203 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
4204 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
4205 | } | |
4206 | ||
4207 | if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) | |
4208 | val |= BIT6; | |
4209 | ||
4210 | switch (info->params.preamble_length) | |
4211 | { | |
4212 | case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; | |
4213 | case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; | |
4214 | case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; | |
4215 | } | |
4216 | ||
4217 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4218 | val |= BIT0; | |
4219 | ||
4220 | wr_reg16(info, TCR, val); | |
4221 | ||
4222 | /* TPR (transmit preamble) */ | |
4223 | ||
4224 | switch (info->params.preamble) | |
4225 | { | |
4226 | case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; | |
4227 | case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; | |
4228 | case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; | |
4229 | case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; | |
4230 | case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; | |
4231 | default: val = 0x7e; break; | |
4232 | } | |
4233 | wr_reg8(info, TPR, (unsigned char)val); | |
4234 | ||
4235 | /* RCR (rx control) | |
4236 | * | |
cb10dc9a | 4237 | * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync |
705b6c7b PF |
4238 | * 12..10 encoding |
4239 | * 09 CRC enable | |
4240 | * 08 CRC32 | |
4241 | * 07..03 reserved, must be 0 | |
4242 | * 02 reset | |
4243 | * 01 enable | |
4244 | * 00 auto-DCD enable | |
4245 | */ | |
4246 | val = 0; | |
4247 | ||
cb10dc9a PF |
4248 | switch(info->params.mode) { |
4249 | case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; | |
4250 | case MGSL_MODE_BISYNC: val |= BIT15; break; | |
4251 | case MGSL_MODE_RAW: val |= BIT13; break; | |
4252 | } | |
705b6c7b PF |
4253 | |
4254 | switch(info->params.encoding) | |
4255 | { | |
4256 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
4257 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
4258 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
4259 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
4260 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
4261 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
4262 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
4263 | } | |
4264 | ||
04b374d0 | 4265 | switch (info->params.crc_type & HDLC_CRC_MASK) |
705b6c7b PF |
4266 | { |
4267 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
4268 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
4269 | } | |
4270 | ||
4271 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4272 | val |= BIT0; | |
4273 | ||
4274 | wr_reg16(info, RCR, val); | |
4275 | ||
4276 | /* CCR (clock control) | |
4277 | * | |
4278 | * 07..05 tx clock source | |
4279 | * 04..02 rx clock source | |
4280 | * 01 auxclk enable | |
4281 | * 00 BRG enable | |
4282 | */ | |
4283 | val = 0; | |
4284 | ||
4285 | if (info->params.flags & HDLC_FLAG_TXC_BRG) | |
4286 | { | |
4287 | // when RxC source is DPLL, BRG generates 16X DPLL | |
4288 | // reference clock, so take TxC from BRG/16 to get | |
4289 | // transmit clock at actual data rate | |
4290 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4291 | val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ | |
4292 | else | |
4293 | val |= BIT6; /* 010, txclk = BRG */ | |
4294 | } | |
4295 | else if (info->params.flags & HDLC_FLAG_TXC_DPLL) | |
4296 | val |= BIT7; /* 100, txclk = DPLL Input */ | |
4297 | else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) | |
4298 | val |= BIT5; /* 001, txclk = RXC Input */ | |
4299 | ||
4300 | if (info->params.flags & HDLC_FLAG_RXC_BRG) | |
4301 | val |= BIT3; /* 010, rxclk = BRG */ | |
4302 | else if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4303 | val |= BIT4; /* 100, rxclk = DPLL */ | |
4304 | else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) | |
4305 | val |= BIT2; /* 001, rxclk = TXC Input */ | |
4306 | ||
4307 | if (info->params.clock_speed) | |
4308 | val |= BIT1 + BIT0; | |
4309 | ||
4310 | wr_reg8(info, CCR, (unsigned char)val); | |
4311 | ||
4312 | if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) | |
4313 | { | |
4314 | // program DPLL mode | |
4315 | switch(info->params.encoding) | |
4316 | { | |
4317 | case HDLC_ENCODING_BIPHASE_MARK: | |
4318 | case HDLC_ENCODING_BIPHASE_SPACE: | |
4319 | val = BIT7; break; | |
4320 | case HDLC_ENCODING_BIPHASE_LEVEL: | |
4321 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: | |
4322 | val = BIT7 + BIT6; break; | |
4323 | default: val = BIT6; // NRZ encodings | |
4324 | } | |
4325 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); | |
4326 | ||
4327 | // DPLL requires a 16X reference clock from BRG | |
4328 | set_rate(info, info->params.clock_speed * 16); | |
4329 | } | |
4330 | else | |
4331 | set_rate(info, info->params.clock_speed); | |
4332 | ||
4333 | tx_set_idle(info); | |
4334 | ||
4335 | msc_set_vcr(info); | |
4336 | ||
4337 | /* SCR (serial control) | |
4338 | * | |
4339 | * 15 1=tx req on FIFO half empty | |
4340 | * 14 1=rx req on FIFO half full | |
4341 | * 13 tx data IRQ enable | |
4342 | * 12 tx idle IRQ enable | |
4343 | * 11 underrun IRQ enable | |
4344 | * 10 rx data IRQ enable | |
4345 | * 09 rx idle IRQ enable | |
4346 | * 08 overrun IRQ enable | |
4347 | * 07 DSR IRQ enable | |
4348 | * 06 CTS IRQ enable | |
4349 | * 05 DCD IRQ enable | |
4350 | * 04 RI IRQ enable | |
4351 | * 03 reserved, must be zero | |
4352 | * 02 1=txd->rxd internal loopback enable | |
4353 | * 01 reserved, must be zero | |
4354 | * 00 1=master IRQ enable | |
4355 | */ | |
4356 | wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); | |
4357 | ||
4358 | if (info->params.loopback) | |
4359 | enable_loopback(info); | |
4360 | } | |
4361 | ||
4362 | /* | |
4363 | * set transmit idle mode | |
4364 | */ | |
4365 | static void tx_set_idle(struct slgt_info *info) | |
4366 | { | |
643f3319 PF |
4367 | unsigned char val; |
4368 | unsigned short tcr; | |
705b6c7b | 4369 | |
643f3319 PF |
4370 | /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits |
4371 | * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits | |
4372 | */ | |
4373 | tcr = rd_reg16(info, TCR); | |
4374 | if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) { | |
4375 | /* disable preamble, set idle size to 16 bits */ | |
4376 | tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; | |
4377 | /* MSB of 16 bit idle specified in tx preamble register (TPR) */ | |
4378 | wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff)); | |
4379 | } else if (!(tcr & BIT6)) { | |
4380 | /* preamble is disabled, set idle size to 8 bits */ | |
4381 | tcr &= ~(BIT5 + BIT4); | |
4382 | } | |
4383 | wr_reg16(info, TCR, tcr); | |
4384 | ||
4385 | if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) { | |
4386 | /* LSB of custom tx idle specified in tx idle register */ | |
4387 | val = (unsigned char)(info->idle_mode & 0xff); | |
4388 | } else { | |
4389 | /* standard 8 bit idle patterns */ | |
4390 | switch(info->idle_mode) | |
4391 | { | |
4392 | case HDLC_TXIDLE_FLAGS: val = 0x7e; break; | |
4393 | case HDLC_TXIDLE_ALT_ZEROS_ONES: | |
4394 | case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; | |
4395 | case HDLC_TXIDLE_ZEROS: | |
4396 | case HDLC_TXIDLE_SPACE: val = 0x00; break; | |
4397 | default: val = 0xff; | |
4398 | } | |
705b6c7b PF |
4399 | } |
4400 | ||
4401 | wr_reg8(info, TIR, val); | |
4402 | } | |
4403 | ||
4404 | /* | |
4405 | * get state of V24 status (input) signals | |
4406 | */ | |
4407 | static void get_signals(struct slgt_info *info) | |
4408 | { | |
4409 | unsigned short status = rd_reg16(info, SSR); | |
4410 | ||
4411 | /* clear all serial signals except DTR and RTS */ | |
4412 | info->signals &= SerialSignal_DTR + SerialSignal_RTS; | |
4413 | ||
4414 | if (status & BIT3) | |
4415 | info->signals |= SerialSignal_DSR; | |
4416 | if (status & BIT2) | |
4417 | info->signals |= SerialSignal_CTS; | |
4418 | if (status & BIT1) | |
4419 | info->signals |= SerialSignal_DCD; | |
4420 | if (status & BIT0) | |
4421 | info->signals |= SerialSignal_RI; | |
4422 | } | |
4423 | ||
4424 | /* | |
4425 | * set V.24 Control Register based on current configuration | |
4426 | */ | |
4427 | static void msc_set_vcr(struct slgt_info *info) | |
4428 | { | |
4429 | unsigned char val = 0; | |
4430 | ||
4431 | /* VCR (V.24 control) | |
4432 | * | |
4433 | * 07..04 serial IF select | |
4434 | * 03 DTR | |
4435 | * 02 RTS | |
4436 | * 01 LL | |
4437 | * 00 RL | |
4438 | */ | |
4439 | ||
4440 | switch(info->if_mode & MGSL_INTERFACE_MASK) | |
4441 | { | |
4442 | case MGSL_INTERFACE_RS232: | |
4443 | val |= BIT5; /* 0010 */ | |
4444 | break; | |
4445 | case MGSL_INTERFACE_V35: | |
4446 | val |= BIT7 + BIT6 + BIT5; /* 1110 */ | |
4447 | break; | |
4448 | case MGSL_INTERFACE_RS422: | |
4449 | val |= BIT6; /* 0100 */ | |
4450 | break; | |
4451 | } | |
4452 | ||
e5590717 PF |
4453 | if (info->if_mode & MGSL_INTERFACE_MSB_FIRST) |
4454 | val |= BIT4; | |
705b6c7b PF |
4455 | if (info->signals & SerialSignal_DTR) |
4456 | val |= BIT3; | |
4457 | if (info->signals & SerialSignal_RTS) | |
4458 | val |= BIT2; | |
4459 | if (info->if_mode & MGSL_INTERFACE_LL) | |
4460 | val |= BIT1; | |
4461 | if (info->if_mode & MGSL_INTERFACE_RL) | |
4462 | val |= BIT0; | |
4463 | wr_reg8(info, VCR, val); | |
4464 | } | |
4465 | ||
4466 | /* | |
4467 | * set state of V24 control (output) signals | |
4468 | */ | |
4469 | static void set_signals(struct slgt_info *info) | |
4470 | { | |
4471 | unsigned char val = rd_reg8(info, VCR); | |
4472 | if (info->signals & SerialSignal_DTR) | |
4473 | val |= BIT3; | |
4474 | else | |
4475 | val &= ~BIT3; | |
4476 | if (info->signals & SerialSignal_RTS) | |
4477 | val |= BIT2; | |
4478 | else | |
4479 | val &= ~BIT2; | |
4480 | wr_reg8(info, VCR, val); | |
4481 | } | |
4482 | ||
4483 | /* | |
4484 | * free range of receive DMA buffers (i to last) | |
4485 | */ | |
4486 | static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) | |
4487 | { | |
4488 | int done = 0; | |
4489 | ||
4490 | while(!done) { | |
4491 | /* reset current buffer for reuse */ | |
4492 | info->rbufs[i].status = 0; | |
814dae03 | 4493 | set_desc_count(info->rbufs[i], info->rbuf_fill_level); |
705b6c7b PF |
4494 | if (i == last) |
4495 | done = 1; | |
4496 | if (++i == info->rbuf_count) | |
4497 | i = 0; | |
4498 | } | |
4499 | info->rbuf_current = i; | |
4500 | } | |
4501 | ||
4502 | /* | |
4503 | * mark all receive DMA buffers as free | |
4504 | */ | |
4505 | static void reset_rbufs(struct slgt_info *info) | |
4506 | { | |
4507 | free_rbufs(info, 0, info->rbuf_count - 1); | |
5ba5a5d2 PF |
4508 | info->rbuf_fill_index = 0; |
4509 | info->rbuf_fill_count = 0; | |
705b6c7b PF |
4510 | } |
4511 | ||
4512 | /* | |
4513 | * pass receive HDLC frame to upper layer | |
4514 | * | |
0fab6de0 | 4515 | * return true if frame available, otherwise false |
705b6c7b | 4516 | */ |
0fab6de0 | 4517 | static bool rx_get_frame(struct slgt_info *info) |
705b6c7b PF |
4518 | { |
4519 | unsigned int start, end; | |
4520 | unsigned short status; | |
4521 | unsigned int framesize = 0; | |
705b6c7b | 4522 | unsigned long flags; |
8fb06c77 | 4523 | struct tty_struct *tty = info->port.tty; |
705b6c7b | 4524 | unsigned char addr_field = 0xff; |
04b374d0 PF |
4525 | unsigned int crc_size = 0; |
4526 | ||
4527 | switch (info->params.crc_type & HDLC_CRC_MASK) { | |
4528 | case HDLC_CRC_16_CCITT: crc_size = 2; break; | |
4529 | case HDLC_CRC_32_CCITT: crc_size = 4; break; | |
4530 | } | |
705b6c7b PF |
4531 | |
4532 | check_again: | |
4533 | ||
4534 | framesize = 0; | |
4535 | addr_field = 0xff; | |
4536 | start = end = info->rbuf_current; | |
4537 | ||
4538 | for (;;) { | |
4539 | if (!desc_complete(info->rbufs[end])) | |
4540 | goto cleanup; | |
4541 | ||
4542 | if (framesize == 0 && info->params.addr_filter != 0xff) | |
4543 | addr_field = info->rbufs[end].buf[0]; | |
4544 | ||
4545 | framesize += desc_count(info->rbufs[end]); | |
4546 | ||
4547 | if (desc_eof(info->rbufs[end])) | |
4548 | break; | |
4549 | ||
4550 | if (++end == info->rbuf_count) | |
4551 | end = 0; | |
4552 | ||
4553 | if (end == info->rbuf_current) { | |
4554 | if (info->rx_enabled){ | |
4555 | spin_lock_irqsave(&info->lock,flags); | |
4556 | rx_start(info); | |
4557 | spin_unlock_irqrestore(&info->lock,flags); | |
4558 | } | |
4559 | goto cleanup; | |
4560 | } | |
4561 | } | |
4562 | ||
4563 | /* status | |
4564 | * | |
4565 | * 15 buffer complete | |
4566 | * 14..06 reserved | |
4567 | * 05..04 residue | |
4568 | * 02 eof (end of frame) | |
4569 | * 01 CRC error | |
4570 | * 00 abort | |
4571 | */ | |
4572 | status = desc_status(info->rbufs[end]); | |
4573 | ||
4574 | /* ignore CRC bit if not using CRC (bit is undefined) */ | |
04b374d0 | 4575 | if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE) |
705b6c7b PF |
4576 | status &= ~BIT1; |
4577 | ||
4578 | if (framesize == 0 || | |
4579 | (addr_field != 0xff && addr_field != info->params.addr_filter)) { | |
4580 | free_rbufs(info, start, end); | |
4581 | goto check_again; | |
4582 | } | |
4583 | ||
04b374d0 PF |
4584 | if (framesize < (2 + crc_size) || status & BIT0) { |
4585 | info->icount.rxshort++; | |
705b6c7b | 4586 | framesize = 0; |
04b374d0 PF |
4587 | } else if (status & BIT1) { |
4588 | info->icount.rxcrc++; | |
4589 | if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) | |
4590 | framesize = 0; | |
4591 | } | |
705b6c7b | 4592 | |
af69c7f9 | 4593 | #if SYNCLINK_GENERIC_HDLC |
04b374d0 | 4594 | if (framesize == 0) { |
198191c4 KH |
4595 | info->netdev->stats.rx_errors++; |
4596 | info->netdev->stats.rx_frame_errors++; | |
705b6c7b | 4597 | } |
04b374d0 | 4598 | #endif |
705b6c7b PF |
4599 | |
4600 | DBGBH(("%s rx frame status=%04X size=%d\n", | |
4601 | info->device_name, status, framesize)); | |
814dae03 | 4602 | DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx"); |
705b6c7b PF |
4603 | |
4604 | if (framesize) { | |
04b374d0 PF |
4605 | if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) { |
4606 | framesize -= crc_size; | |
4607 | crc_size = 0; | |
4608 | } | |
4609 | ||
4610 | if (framesize > info->max_frame_size + crc_size) | |
705b6c7b PF |
4611 | info->icount.rxlong++; |
4612 | else { | |
4613 | /* copy dma buffer(s) to contiguous temp buffer */ | |
4614 | int copy_count = framesize; | |
4615 | int i = start; | |
4616 | unsigned char *p = info->tmp_rbuf; | |
4617 | info->tmp_rbuf_count = framesize; | |
4618 | ||
4619 | info->icount.rxok++; | |
4620 | ||
4621 | while(copy_count) { | |
814dae03 | 4622 | int partial_count = min_t(int, copy_count, info->rbuf_fill_level); |
705b6c7b PF |
4623 | memcpy(p, info->rbufs[i].buf, partial_count); |
4624 | p += partial_count; | |
4625 | copy_count -= partial_count; | |
4626 | if (++i == info->rbuf_count) | |
4627 | i = 0; | |
4628 | } | |
4629 | ||
04b374d0 PF |
4630 | if (info->params.crc_type & HDLC_CRC_RETURN_EX) { |
4631 | *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; | |
4632 | framesize++; | |
4633 | } | |
4634 | ||
af69c7f9 | 4635 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
4636 | if (info->netcount) |
4637 | hdlcdev_rx(info,info->tmp_rbuf, framesize); | |
4638 | else | |
4639 | #endif | |
4640 | ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize); | |
4641 | } | |
4642 | } | |
4643 | free_rbufs(info, start, end); | |
0fab6de0 | 4644 | return true; |
705b6c7b PF |
4645 | |
4646 | cleanup: | |
0fab6de0 | 4647 | return false; |
705b6c7b PF |
4648 | } |
4649 | ||
4650 | /* | |
4651 | * pass receive buffer (RAW synchronous mode) to tty layer | |
0fab6de0 | 4652 | * return true if buffer available, otherwise false |
705b6c7b | 4653 | */ |
0fab6de0 | 4654 | static bool rx_get_buf(struct slgt_info *info) |
705b6c7b PF |
4655 | { |
4656 | unsigned int i = info->rbuf_current; | |
cb10dc9a | 4657 | unsigned int count; |
705b6c7b PF |
4658 | |
4659 | if (!desc_complete(info->rbufs[i])) | |
0fab6de0 | 4660 | return false; |
cb10dc9a PF |
4661 | count = desc_count(info->rbufs[i]); |
4662 | switch(info->params.mode) { | |
4663 | case MGSL_MODE_MONOSYNC: | |
4664 | case MGSL_MODE_BISYNC: | |
4665 | /* ignore residue in byte synchronous modes */ | |
4666 | if (desc_residue(info->rbufs[i])) | |
4667 | count--; | |
4668 | break; | |
4669 | } | |
4670 | DBGDATA(info, info->rbufs[i].buf, count, "rx"); | |
4671 | DBGINFO(("rx_get_buf size=%d\n", count)); | |
4672 | if (count) | |
8fb06c77 | 4673 | ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, |
cb10dc9a | 4674 | info->flag_buf, count); |
705b6c7b | 4675 | free_rbufs(info, i, i); |
0fab6de0 | 4676 | return true; |
705b6c7b PF |
4677 | } |
4678 | ||
4679 | static void reset_tbufs(struct slgt_info *info) | |
4680 | { | |
4681 | unsigned int i; | |
4682 | info->tbuf_current = 0; | |
4683 | for (i=0 ; i < info->tbuf_count ; i++) { | |
4684 | info->tbufs[i].status = 0; | |
4685 | info->tbufs[i].count = 0; | |
4686 | } | |
4687 | } | |
4688 | ||
4689 | /* | |
4690 | * return number of free transmit DMA buffers | |
4691 | */ | |
4692 | static unsigned int free_tbuf_count(struct slgt_info *info) | |
4693 | { | |
4694 | unsigned int count = 0; | |
4695 | unsigned int i = info->tbuf_current; | |
4696 | ||
4697 | do | |
4698 | { | |
4699 | if (desc_count(info->tbufs[i])) | |
4700 | break; /* buffer in use */ | |
4701 | ++count; | |
4702 | if (++i == info->tbuf_count) | |
4703 | i=0; | |
4704 | } while (i != info->tbuf_current); | |
4705 | ||
bb029c67 PF |
4706 | /* if tx DMA active, last zero count buffer is in use */ |
4707 | if (count && (rd_reg32(info, TDCSR) & BIT0)) | |
705b6c7b PF |
4708 | --count; |
4709 | ||
4710 | return count; | |
4711 | } | |
4712 | ||
403214d0 PF |
4713 | /* |
4714 | * return number of bytes in unsent transmit DMA buffers | |
4715 | * and the serial controller tx FIFO | |
4716 | */ | |
4717 | static unsigned int tbuf_bytes(struct slgt_info *info) | |
4718 | { | |
4719 | unsigned int total_count = 0; | |
4720 | unsigned int i = info->tbuf_current; | |
4721 | unsigned int reg_value; | |
4722 | unsigned int count; | |
4723 | unsigned int active_buf_count = 0; | |
4724 | ||
4725 | /* | |
4726 | * Add descriptor counts for all tx DMA buffers. | |
4727 | * If count is zero (cleared by DMA controller after read), | |
4728 | * the buffer is complete or is actively being read from. | |
4729 | * | |
4730 | * Record buf_count of last buffer with zero count starting | |
4731 | * from current ring position. buf_count is mirror | |
4732 | * copy of count and is not cleared by serial controller. | |
4733 | * If DMA controller is active, that buffer is actively | |
4734 | * being read so add to total. | |
4735 | */ | |
4736 | do { | |
4737 | count = desc_count(info->tbufs[i]); | |
4738 | if (count) | |
4739 | total_count += count; | |
4740 | else if (!total_count) | |
4741 | active_buf_count = info->tbufs[i].buf_count; | |
4742 | if (++i == info->tbuf_count) | |
4743 | i = 0; | |
4744 | } while (i != info->tbuf_current); | |
4745 | ||
4746 | /* read tx DMA status register */ | |
4747 | reg_value = rd_reg32(info, TDCSR); | |
4748 | ||
4749 | /* if tx DMA active, last zero count buffer is in use */ | |
4750 | if (reg_value & BIT0) | |
4751 | total_count += active_buf_count; | |
4752 | ||
4753 | /* add tx FIFO count = reg_value[15..8] */ | |
4754 | total_count += (reg_value >> 8) & 0xff; | |
4755 | ||
4756 | /* if transmitter active add one byte for shift register */ | |
4757 | if (info->tx_active) | |
4758 | total_count++; | |
4759 | ||
4760 | return total_count; | |
4761 | } | |
4762 | ||
705b6c7b | 4763 | /* |
de538eb3 PF |
4764 | * load data into transmit DMA buffer ring and start transmitter if needed |
4765 | * return true if data accepted, otherwise false (buffers full) | |
705b6c7b | 4766 | */ |
de538eb3 | 4767 | static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size) |
705b6c7b PF |
4768 | { |
4769 | unsigned short count; | |
4770 | unsigned int i; | |
4771 | struct slgt_desc *d; | |
4772 | ||
de538eb3 PF |
4773 | /* check required buffer space */ |
4774 | if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info)) | |
4775 | return false; | |
705b6c7b PF |
4776 | |
4777 | DBGDATA(info, buf, size, "tx"); | |
4778 | ||
de538eb3 PF |
4779 | /* |
4780 | * copy data to one or more DMA buffers in circular ring | |
4781 | * tbuf_start = first buffer for this data | |
4782 | * tbuf_current = next free buffer | |
4783 | * | |
4784 | * Copy all data before making data visible to DMA controller by | |
4785 | * setting descriptor count of the first buffer. | |
4786 | * This prevents an active DMA controller from reading the first DMA | |
4787 | * buffers of a frame and stopping before the final buffers are filled. | |
4788 | */ | |
4789 | ||
705b6c7b PF |
4790 | info->tbuf_start = i = info->tbuf_current; |
4791 | ||
4792 | while (size) { | |
4793 | d = &info->tbufs[i]; | |
705b6c7b PF |
4794 | |
4795 | count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); | |
4796 | memcpy(d->buf, buf, count); | |
4797 | ||
4798 | size -= count; | |
4799 | buf += count; | |
4800 | ||
cb10dc9a PF |
4801 | /* |
4802 | * set EOF bit for last buffer of HDLC frame or | |
4803 | * for every buffer in raw mode | |
4804 | */ | |
4805 | if ((!size && info->params.mode == MGSL_MODE_HDLC) || | |
4806 | info->params.mode == MGSL_MODE_RAW) | |
4807 | set_desc_eof(*d, 1); | |
705b6c7b PF |
4808 | else |
4809 | set_desc_eof(*d, 0); | |
4810 | ||
de538eb3 PF |
4811 | /* set descriptor count for all but first buffer */ |
4812 | if (i != info->tbuf_start) | |
4813 | set_desc_count(*d, count); | |
403214d0 | 4814 | d->buf_count = count; |
de538eb3 PF |
4815 | |
4816 | if (++i == info->tbuf_count) | |
4817 | i = 0; | |
705b6c7b PF |
4818 | } |
4819 | ||
4820 | info->tbuf_current = i; | |
de538eb3 PF |
4821 | |
4822 | /* set first buffer count to make new data visible to DMA controller */ | |
4823 | d = &info->tbufs[info->tbuf_start]; | |
4824 | set_desc_count(*d, d->buf_count); | |
4825 | ||
4826 | /* start transmitter if needed and update transmit timeout */ | |
4827 | if (!info->tx_active) | |
4828 | tx_start(info); | |
4829 | update_tx_timer(info); | |
4830 | ||
4831 | return true; | |
705b6c7b PF |
4832 | } |
4833 | ||
4834 | static int register_test(struct slgt_info *info) | |
4835 | { | |
4836 | static unsigned short patterns[] = | |
4837 | {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; | |
7ea7c6d5 | 4838 | static unsigned int count = ARRAY_SIZE(patterns); |
705b6c7b PF |
4839 | unsigned int i; |
4840 | int rc = 0; | |
4841 | ||
4842 | for (i=0 ; i < count ; i++) { | |
4843 | wr_reg16(info, TIR, patterns[i]); | |
4844 | wr_reg16(info, BDR, patterns[(i+1)%count]); | |
4845 | if ((rd_reg16(info, TIR) != patterns[i]) || | |
4846 | (rd_reg16(info, BDR) != patterns[(i+1)%count])) { | |
4847 | rc = -ENODEV; | |
4848 | break; | |
4849 | } | |
4850 | } | |
0080b7aa | 4851 | info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; |
705b6c7b PF |
4852 | info->init_error = rc ? 0 : DiagStatus_AddressFailure; |
4853 | return rc; | |
4854 | } | |
4855 | ||
4856 | static int irq_test(struct slgt_info *info) | |
4857 | { | |
4858 | unsigned long timeout; | |
4859 | unsigned long flags; | |
8fb06c77 | 4860 | struct tty_struct *oldtty = info->port.tty; |
705b6c7b PF |
4861 | u32 speed = info->params.data_rate; |
4862 | ||
4863 | info->params.data_rate = 921600; | |
8fb06c77 | 4864 | info->port.tty = NULL; |
705b6c7b PF |
4865 | |
4866 | spin_lock_irqsave(&info->lock, flags); | |
4867 | async_mode(info); | |
4868 | slgt_irq_on(info, IRQ_TXIDLE); | |
4869 | ||
4870 | /* enable transmitter */ | |
4871 | wr_reg16(info, TCR, | |
4872 | (unsigned short)(rd_reg16(info, TCR) | BIT1)); | |
4873 | ||
4874 | /* write one byte and wait for tx idle */ | |
4875 | wr_reg16(info, TDR, 0); | |
4876 | ||
4877 | /* assume failure */ | |
4878 | info->init_error = DiagStatus_IrqFailure; | |
0fab6de0 | 4879 | info->irq_occurred = false; |
705b6c7b PF |
4880 | |
4881 | spin_unlock_irqrestore(&info->lock, flags); | |
4882 | ||
4883 | timeout=100; | |
4884 | while(timeout-- && !info->irq_occurred) | |
4885 | msleep_interruptible(10); | |
4886 | ||
4887 | spin_lock_irqsave(&info->lock,flags); | |
4888 | reset_port(info); | |
4889 | spin_unlock_irqrestore(&info->lock,flags); | |
4890 | ||
4891 | info->params.data_rate = speed; | |
8fb06c77 | 4892 | info->port.tty = oldtty; |
705b6c7b PF |
4893 | |
4894 | info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; | |
4895 | return info->irq_occurred ? 0 : -ENODEV; | |
4896 | } | |
4897 | ||
4898 | static int loopback_test_rx(struct slgt_info *info) | |
4899 | { | |
4900 | unsigned char *src, *dest; | |
4901 | int count; | |
4902 | ||
4903 | if (desc_complete(info->rbufs[0])) { | |
4904 | count = desc_count(info->rbufs[0]); | |
4905 | src = info->rbufs[0].buf; | |
4906 | dest = info->tmp_rbuf; | |
4907 | ||
4908 | for( ; count ; count-=2, src+=2) { | |
4909 | /* src=data byte (src+1)=status byte */ | |
4910 | if (!(*(src+1) & (BIT9 + BIT8))) { | |
4911 | *dest = *src; | |
4912 | dest++; | |
4913 | info->tmp_rbuf_count++; | |
4914 | } | |
4915 | } | |
4916 | DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); | |
4917 | return 1; | |
4918 | } | |
4919 | return 0; | |
4920 | } | |
4921 | ||
4922 | static int loopback_test(struct slgt_info *info) | |
4923 | { | |
4924 | #define TESTFRAMESIZE 20 | |
4925 | ||
4926 | unsigned long timeout; | |
4927 | u16 count = TESTFRAMESIZE; | |
4928 | unsigned char buf[TESTFRAMESIZE]; | |
4929 | int rc = -ENODEV; | |
4930 | unsigned long flags; | |
4931 | ||
8fb06c77 | 4932 | struct tty_struct *oldtty = info->port.tty; |
705b6c7b PF |
4933 | MGSL_PARAMS params; |
4934 | ||
4935 | memcpy(¶ms, &info->params, sizeof(params)); | |
4936 | ||
4937 | info->params.mode = MGSL_MODE_ASYNC; | |
4938 | info->params.data_rate = 921600; | |
4939 | info->params.loopback = 1; | |
8fb06c77 | 4940 | info->port.tty = NULL; |
705b6c7b PF |
4941 | |
4942 | /* build and send transmit frame */ | |
4943 | for (count = 0; count < TESTFRAMESIZE; ++count) | |
4944 | buf[count] = (unsigned char)count; | |
4945 | ||
4946 | info->tmp_rbuf_count = 0; | |
4947 | memset(info->tmp_rbuf, 0, TESTFRAMESIZE); | |
4948 | ||
4949 | /* program hardware for HDLC and enabled receiver */ | |
4950 | spin_lock_irqsave(&info->lock,flags); | |
4951 | async_mode(info); | |
4952 | rx_start(info); | |
705b6c7b | 4953 | tx_load(info, buf, count); |
705b6c7b PF |
4954 | spin_unlock_irqrestore(&info->lock, flags); |
4955 | ||
4956 | /* wait for receive complete */ | |
4957 | for (timeout = 100; timeout; --timeout) { | |
4958 | msleep_interruptible(10); | |
4959 | if (loopback_test_rx(info)) { | |
4960 | rc = 0; | |
4961 | break; | |
4962 | } | |
4963 | } | |
4964 | ||
4965 | /* verify received frame length and contents */ | |
4966 | if (!rc && (info->tmp_rbuf_count != count || | |
4967 | memcmp(buf, info->tmp_rbuf, count))) { | |
4968 | rc = -ENODEV; | |
4969 | } | |
4970 | ||
4971 | spin_lock_irqsave(&info->lock,flags); | |
4972 | reset_adapter(info); | |
4973 | spin_unlock_irqrestore(&info->lock,flags); | |
4974 | ||
4975 | memcpy(&info->params, ¶ms, sizeof(info->params)); | |
8fb06c77 | 4976 | info->port.tty = oldtty; |
705b6c7b PF |
4977 | |
4978 | info->init_error = rc ? DiagStatus_DmaFailure : 0; | |
4979 | return rc; | |
4980 | } | |
4981 | ||
4982 | static int adapter_test(struct slgt_info *info) | |
4983 | { | |
4984 | DBGINFO(("testing %s\n", info->device_name)); | |
294dad05 | 4985 | if (register_test(info) < 0) { |
705b6c7b PF |
4986 | printk("register test failure %s addr=%08X\n", |
4987 | info->device_name, info->phys_reg_addr); | |
294dad05 | 4988 | } else if (irq_test(info) < 0) { |
705b6c7b PF |
4989 | printk("IRQ test failure %s IRQ=%d\n", |
4990 | info->device_name, info->irq_level); | |
294dad05 | 4991 | } else if (loopback_test(info) < 0) { |
705b6c7b PF |
4992 | printk("loopback test failure %s\n", info->device_name); |
4993 | } | |
4994 | return info->init_error; | |
4995 | } | |
4996 | ||
4997 | /* | |
4998 | * transmit timeout handler | |
4999 | */ | |
5000 | static void tx_timeout(unsigned long context) | |
5001 | { | |
5002 | struct slgt_info *info = (struct slgt_info*)context; | |
5003 | unsigned long flags; | |
5004 | ||
5005 | DBGINFO(("%s tx_timeout\n", info->device_name)); | |
5006 | if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { | |
5007 | info->icount.txtimeout++; | |
5008 | } | |
5009 | spin_lock_irqsave(&info->lock,flags); | |
ce89294c | 5010 | tx_stop(info); |
705b6c7b PF |
5011 | spin_unlock_irqrestore(&info->lock,flags); |
5012 | ||
af69c7f9 | 5013 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
5014 | if (info->netcount) |
5015 | hdlcdev_tx_done(info); | |
5016 | else | |
5017 | #endif | |
5018 | bh_transmit(info); | |
5019 | } | |
5020 | ||
5021 | /* | |
5022 | * receive buffer polling timer | |
5023 | */ | |
5024 | static void rx_timeout(unsigned long context) | |
5025 | { | |
5026 | struct slgt_info *info = (struct slgt_info*)context; | |
5027 | unsigned long flags; | |
5028 | ||
5029 | DBGINFO(("%s rx_timeout\n", info->device_name)); | |
5030 | spin_lock_irqsave(&info->lock, flags); | |
5031 | info->pending_bh |= BH_RECEIVE; | |
5032 | spin_unlock_irqrestore(&info->lock, flags); | |
c4028958 | 5033 | bh_handler(&info->task); |
705b6c7b PF |
5034 | } |
5035 |