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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / pcmcia / synclink_cs.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/pcmcia/synclink_cs.c
3 *
a7482a2e 4 * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
1da177e4
LT		 5 *
6 * Device driver for Microgate SyncLink PC Card
7 * multiprotocol serial adapter.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * This code is released under the GNU General Public License (GPL)
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
26 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30#if defined(__i386__)
31# define BREAKPOINT() asm(" int $3");
32#else
33# define BREAKPOINT() { }
34#endif
35
36#define MAX_DEVICE_COUNT 4
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/errno.h>
40#include <linux/signal.h>
41#include <linux/sched.h>
42#include <linux/timer.h>
43#include <linux/time.h>
44#include <linux/interrupt.h>
1da177e4
LT		 45#include <linux/tty.h>
46#include <linux/tty_flip.h>
47#include <linux/serial.h>
48#include <linux/major.h>
49#include <linux/string.h>
50#include <linux/fcntl.h>
51#include <linux/ptrace.h>
52#include <linux/ioport.h>
53#include <linux/mm.h>
87687144 54#include <linux/seq_file.h>
1da177e4
LT		 55#include <linux/slab.h>
56#include <linux/netdevice.h>
57#include <linux/vmalloc.h>
58#include <linux/init.h>
1da177e4
LT		 59#include <linux/delay.h>
60#include <linux/ioctl.h>
3dd1247f 61#include <linux/synclink.h>
1da177e4 62
1da177e4
LT		 63#include <asm/io.h>
64#include <asm/irq.h>
65#include <asm/dma.h>
66#include <linux/bitops.h>
67#include <asm/types.h>
68#include <linux/termios.h>
69#include <linux/workqueue.h>
70#include <linux/hdlc.h>
71
1da177e4
LT		 72#include <pcmcia/cistpl.h>
73#include <pcmcia/cisreg.h>
74#include <pcmcia/ds.h>
75
af69c7f9
PF		 76#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
77#define SYNCLINK_GENERIC_HDLC 1
78#else
79#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 80#endif
81
82#define GET_USER(error,value,addr) error = get_user(value,addr)
83#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
84#define PUT_USER(error,value,addr) error = put_user(value,addr)
85#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
86
87#include <asm/uaccess.h>
88
1da177e4
LT		 89static MGSL_PARAMS default_params = {
90 MGSL_MODE_HDLC, /* unsigned long mode */
91 0, /* unsigned char loopback; */
92 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
93 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
94 0, /* unsigned long clock_speed; */
95 0xff, /* unsigned char addr_filter; */
96 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
97 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
98 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
99 9600, /* unsigned long data_rate; */
100 8, /* unsigned char data_bits; */
101 1, /* unsigned char stop_bits; */
102 ASYNC_PARITY_NONE /* unsigned char parity; */
103};
104
105typedef struct
106{
107 int count;
108 unsigned char status;
109 char data[1];
110} RXBUF;
111
112/* The queue of BH actions to be performed */
113
114#define BH_RECEIVE 1
115#define BH_TRANSMIT 2
116#define BH_STATUS 4
117
118#define IO_PIN_SHUTDOWN_LIMIT 100
119
120#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
121
122struct _input_signal_events {
d12341f9 123 int ri_up;
1da177e4
LT		 124 int ri_down;
125 int dsr_up;
126 int dsr_down;
127 int dcd_up;
128 int dcd_down;
129 int cts_up;
130 int cts_down;
131};
132
133
134/*
135 * Device instance data structure
136 */
d12341f9 137
1da177e4 138typedef struct _mgslpc_info {
eeb46134 139 struct tty_port port;
1da177e4
LT		 140 void *if_ptr; /* General purpose pointer (used by SPPP) */
141 int magic;
1da177e4 142 int line;
d12341f9 143
1da177e4 144 struct mgsl_icount icount;
d12341f9 145
1da177e4
LT		 146 int timeout;
147 int x_char; /* xon/xoff character */
1da177e4 148 unsigned char read_status_mask;
d12341f9 149 unsigned char ignore_status_mask;
1da177e4
LT		 150
151 unsigned char *tx_buf;
152 int tx_put;
153 int tx_get;
154 int tx_count;
155
156 /* circular list of fixed length rx buffers */
157
158 unsigned char *rx_buf; /* memory allocated for all rx buffers */
159 int rx_buf_total_size; /* size of memory allocated for rx buffers */
160 int rx_put; /* index of next empty rx buffer */
161 int rx_get; /* index of next full rx buffer */
162 int rx_buf_size; /* size in bytes of single rx buffer */
163 int rx_buf_count; /* total number of rx buffers */
164 int rx_frame_count; /* number of full rx buffers */
d12341f9 165
1da177e4
LT		 166 wait_queue_head_t status_event_wait_q;
167 wait_queue_head_t event_wait_q;
168 struct timer_list tx_timer; /* HDLC transmit timeout timer */
169 struct _mgslpc_info *next_device; /* device list link */
170
171 unsigned short imra_value;
172 unsigned short imrb_value;
173 unsigned char pim_value;
174
175 spinlock_t lock;
176 struct work_struct task; /* task structure for scheduling bh */
177
178 u32 max_frame_size;
179
180 u32 pending_bh;
181
0fab6de0
JP		 182 bool bh_running;
183 bool bh_requested;
d12341f9 184
1da177e4
LT		 185 int dcd_chkcount; /* check counts to prevent */
186 int cts_chkcount; /* too many IRQs if a signal */
187 int dsr_chkcount; /* is floating */
188 int ri_chkcount;
189
0fab6de0
JP		 190 bool rx_enabled;
191 bool rx_overflow;
1da177e4 192
0fab6de0
JP		 193 bool tx_enabled;
194 bool tx_active;
195 bool tx_aborting;
1da177e4
LT		 196 u32 idle_mode;
197
198 int if_mode; /* serial interface selection (RS-232, v.35 etc) */
199
200 char device_name[25]; /* device instance name */
201
202 unsigned int io_base; /* base I/O address of adapter */
203 unsigned int irq_level;
d12341f9 204
1da177e4
LT		 205 MGSL_PARAMS params; /* communications parameters */
206
207 unsigned char serial_signals; /* current serial signal states */
208
0fab6de0 209 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 210 char testing_irq;
211 unsigned int init_error; /* startup error (DIAGS) */
212
a6b68a69 213 char *flag_buf;
0fab6de0 214 bool drop_rts_on_tx_done;
1da177e4
LT		 215
216 struct _input_signal_events input_signal_events;
217
218 /* PCMCIA support */
fd238232 219 struct pcmcia_device *p_dev;
1da177e4
LT		 220 int stop;
221
222 /* SPPP/Cisco HDLC device parts */
223 int netcount;
1da177e4
LT		 224 spinlock_t netlock;
225
af69c7f9 226#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 227 struct net_device *netdev;
228#endif
229
230} MGSLPC_INFO;
231
232#define MGSLPC_MAGIC 0x5402
233
234/*
235 * The size of the serial xmit buffer is 1 page, or 4096 bytes
236 */
237#define TXBUFSIZE 4096
238
d12341f9 239
1da177e4
LT		 240#define CHA 0x00 /* channel A offset */
241#define CHB 0x40 /* channel B offset */
242
243/*
244 * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
245 */
246#undef PVR
247
248#define RXFIFO 0
249#define TXFIFO 0
250#define STAR 0x20
251#define CMDR 0x20
252#define RSTA 0x21
253#define PRE 0x21
254#define MODE 0x22
255#define TIMR 0x23
256#define XAD1 0x24
257#define XAD2 0x25
258#define RAH1 0x26
259#define RAH2 0x27
260#define DAFO 0x27
261#define RAL1 0x28
262#define RFC 0x28
263#define RHCR 0x29
264#define RAL2 0x29
265#define RBCL 0x2a
266#define XBCL 0x2a
267#define RBCH 0x2b
268#define XBCH 0x2b
269#define CCR0 0x2c
270#define CCR1 0x2d
271#define CCR2 0x2e
272#define CCR3 0x2f
273#define VSTR 0x34
274#define BGR 0x34
275#define RLCR 0x35
276#define AML 0x36
277#define AMH 0x37
278#define GIS 0x38
279#define IVA 0x38
280#define IPC 0x39
281#define ISR 0x3a
282#define IMR 0x3a
283#define PVR 0x3c
284#define PIS 0x3d
285#define PIM 0x3d
286#define PCR 0x3e
287#define CCR4 0x3f
d12341f9 288
1da177e4 289// IMR/ISR
d12341f9 290
1da177e4
LT		 291#define IRQ_BREAK_ON BIT15 // rx break detected
292#define IRQ_DATAOVERRUN BIT14 // receive data overflow
293#define IRQ_ALLSENT BIT13 // all sent
294#define IRQ_UNDERRUN BIT12 // transmit data underrun
295#define IRQ_TIMER BIT11 // timer interrupt
296#define IRQ_CTS BIT10 // CTS status change
297#define IRQ_TXREPEAT BIT9 // tx message repeat
298#define IRQ_TXFIFO BIT8 // transmit pool ready
299#define IRQ_RXEOM BIT7 // receive message end
300#define IRQ_EXITHUNT BIT6 // receive frame start
301#define IRQ_RXTIME BIT6 // rx char timeout
302#define IRQ_DCD BIT2 // carrier detect status change
303#define IRQ_OVERRUN BIT1 // receive frame overflow
304#define IRQ_RXFIFO BIT0 // receive pool full
d12341f9 305
1da177e4 306// STAR
d12341f9 307
1da177e4
LT		 308#define XFW BIT6 // transmit FIFO write enable
309#define CEC BIT2 // command executing
310#define CTS BIT1 // CTS state
d12341f9 311
1da177e4
LT		 312#define PVR_DTR BIT0
313#define PVR_DSR BIT1
314#define PVR_RI BIT2
315#define PVR_AUTOCTS BIT3
316#define PVR_RS232 0x20 /* 0010b */
317#define PVR_V35 0xe0 /* 1110b */
318#define PVR_RS422 0x40 /* 0100b */
d12341f9
JG		 319
320/* Register access functions */
321
1da177e4
LT		 322#define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
323#define read_reg(info, reg) inb((info)->io_base + (reg))
324
d12341f9 325#define read_reg16(info, reg) inw((info)->io_base + (reg))
1da177e4 326#define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
d12341f9 327
1da177e4
LT		 328#define set_reg_bits(info, reg, mask) \
329 write_reg(info, (reg), \
d12341f9 330 (unsigned char) (read_reg(info, (reg)) | (mask)))
1da177e4
LT		 331#define clear_reg_bits(info, reg, mask) \
332 write_reg(info, (reg), \
d12341f9 333 (unsigned char) (read_reg(info, (reg)) & ~(mask)))
1da177e4
LT		 334/*
335 * interrupt enable/disable routines
d12341f9
JG		 336 */
337static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 338{
339 if (channel == CHA) {
340 info->imra_value |= mask;
341 write_reg16(info, CHA + IMR, info->imra_value);
342 } else {
343 info->imrb_value |= mask;
344 write_reg16(info, CHB + IMR, info->imrb_value);
345 }
346}
d12341f9 347static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 348{
349 if (channel == CHA) {
350 info->imra_value &= ~mask;
351 write_reg16(info, CHA + IMR, info->imra_value);
352 } else {
353 info->imrb_value &= ~mask;
354 write_reg16(info, CHB + IMR, info->imrb_value);
355 }
356}
357
358#define port_irq_disable(info, mask) \
359 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
360
361#define port_irq_enable(info, mask) \
362 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
363
364static void rx_start(MGSLPC_INFO *info);
365static void rx_stop(MGSLPC_INFO *info);
366
eeb46134 367static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 368static void tx_stop(MGSLPC_INFO *info);
369static void tx_set_idle(MGSLPC_INFO *info);
370
371static void get_signals(MGSLPC_INFO *info);
372static void set_signals(MGSLPC_INFO *info);
373
374static void reset_device(MGSLPC_INFO *info);
375
376static void hdlc_mode(MGSLPC_INFO *info);
377static void async_mode(MGSLPC_INFO *info);
378
379static void tx_timeout(unsigned long context);
380
eeb46134 381static int carrier_raised(struct tty_port *port);
fcc8ac18 382static void dtr_rts(struct tty_port *port, int onoff);
1da177e4 383
af69c7f9 384#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 385#define dev_to_port(D) (dev_to_hdlc(D)->priv)
386static void hdlcdev_tx_done(MGSLPC_INFO *info);
387static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
388static int hdlcdev_init(MGSLPC_INFO *info);
389static void hdlcdev_exit(MGSLPC_INFO *info);
390#endif
391
392static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
393
0fab6de0
JP		 394static bool register_test(MGSLPC_INFO *info);
395static bool irq_test(MGSLPC_INFO *info);
1da177e4
LT		 396static int adapter_test(MGSLPC_INFO *info);
397
398static int claim_resources(MGSLPC_INFO *info);
399static void release_resources(MGSLPC_INFO *info);
400static void mgslpc_add_device(MGSLPC_INFO *info);
401static void mgslpc_remove_device(MGSLPC_INFO *info);
402
eeb46134 403static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 404static void rx_reset_buffers(MGSLPC_INFO *info);
405static int rx_alloc_buffers(MGSLPC_INFO *info);
406static void rx_free_buffers(MGSLPC_INFO *info);
407
7d12e780 408static irqreturn_t mgslpc_isr(int irq, void *dev_id);
1da177e4
LT		 409
410/*
411 * Bottom half interrupt handlers
412 */
c4028958 413static void bh_handler(struct work_struct *work);
eeb46134 414static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 415static void bh_status(MGSLPC_INFO *info);
416
417/*
418 * ioctl handlers
419 */
60b33c13 420static int tiocmget(struct tty_struct *tty);
20b9d177
AC		 421static int tiocmset(struct tty_struct *tty,
422 unsigned int set, unsigned int clear);
1da177e4
LT		 423static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
424static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
eeb46134 425static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
1da177e4
LT		 426static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
427static int set_txidle(MGSLPC_INFO *info, int idle_mode);
eeb46134 428static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
1da177e4
LT		 429static int tx_abort(MGSLPC_INFO *info);
430static int set_rxenable(MGSLPC_INFO *info, int enable);
431static int wait_events(MGSLPC_INFO *info, int __user *mask);
432
433static MGSLPC_INFO *mgslpc_device_list = NULL;
434static int mgslpc_device_count = 0;
435
436/*
437 * Set this param to non-zero to load eax with the
438 * .text section address and breakpoint on module load.
439 * This is useful for use with gdb and add-symbol-file command.
440 */
90ab5ee9 441static bool break_on_load=0;
1da177e4
LT		 442
443/*
444 * Driver major number, defaults to zero to get auto
445 * assigned major number. May be forced as module parameter.
446 */
447static int ttymajor=0;
448
449static int debug_level = 0;
450static int maxframe[MAX_DEVICE_COUNT] = {0,};
1da177e4
LT		 451
452module_param(break_on_load, bool, 0);
453module_param(ttymajor, int, 0);
454module_param(debug_level, int, 0);
455module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 456
457MODULE_LICENSE("GPL");
458
459static char *driver_name = "SyncLink PC Card driver";
a7482a2e 460static char *driver_version = "$Revision: 4.34 $";
1da177e4
LT		 461
462static struct tty_driver *serial_driver;
463
464/* number of characters left in xmit buffer before we ask for more */
465#define WAKEUP_CHARS 256
466
eeb46134 467static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 468static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
469
470/* PCMCIA prototypes */
471
15b99ac1 472static int mgslpc_config(struct pcmcia_device *link);
1da177e4 473static void mgslpc_release(u_long arg);
cc3b4866 474static void mgslpc_detach(struct pcmcia_device *p_dev);
1da177e4 475
1da177e4
LT		 476/*
477 * 1st function defined in .text section. Calling this function in
478 * init_module() followed by a breakpoint allows a remote debugger
479 * (gdb) to get the .text address for the add-symbol-file command.
480 * This allows remote debugging of dynamically loadable modules.
481 */
482static void* mgslpc_get_text_ptr(void)
483{
484 return mgslpc_get_text_ptr;
485}
486
487/**
488 * line discipline callback wrappers
489 *
490 * The wrappers maintain line discipline references
491 * while calling into the line discipline.
492 *
1da177e4
LT		 493 * ldisc_receive_buf - pass receive data to line discipline
494 */
495
1da177e4
LT		 496static void ldisc_receive_buf(struct tty_struct *tty,
497 const __u8 *data, char *flags, int count)
498{
499 struct tty_ldisc *ld;
500 if (!tty)
501 return;
502 ld = tty_ldisc_ref(tty);
503 if (ld) {
a352def2
AC		 504 if (ld->ops->receive_buf)
505 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 506 tty_ldisc_deref(ld);
507 }
508}
509
eeb46134
AC		 510static const struct tty_port_operations mgslpc_port_ops = {
511 .carrier_raised = carrier_raised,
fcc8ac18 512 .dtr_rts = dtr_rts
eeb46134
AC		 513};
514
15b99ac1 515static int mgslpc_probe(struct pcmcia_device *link)
1da177e4
LT		 516{
517 MGSLPC_INFO *info;
15b99ac1 518 int ret;
fd238232 519
1da177e4
LT		 520 if (debug_level >= DEBUG_LEVEL_INFO)
521 printk("mgslpc_attach\n");
fd238232 522
dd00cc48 523 info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
1da177e4
LT		 524 if (!info) {
525 printk("Error can't allocate device instance data\n");
f8cfa618 526 return -ENOMEM;
1da177e4
LT		 527 }
528
1da177e4 529 info->magic = MGSLPC_MAGIC;
eeb46134
AC		 530 tty_port_init(&info->port);
531 info->port.ops = &mgslpc_port_ops;
c4028958 532 INIT_WORK(&info->task, bh_handler);
1da177e4 533 info->max_frame_size = 4096;
eeb46134
AC		 534 info->port.close_delay = 5*HZ/10;
535 info->port.closing_wait = 30*HZ;
1da177e4
LT		 536 init_waitqueue_head(&info->status_event_wait_q);
537 init_waitqueue_head(&info->event_wait_q);
538 spin_lock_init(&info->lock);
539 spin_lock_init(&info->netlock);
540 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
d12341f9 541 info->idle_mode = HDLC_TXIDLE_FLAGS;
1da177e4
LT		 542 info->imra_value = 0xffff;
543 info->imrb_value = 0xffff;
544 info->pim_value = 0xff;
545
fba395ee 546 info->p_dev = link;
1da177e4 547 link->priv = info;
fd238232 548
fba395ee 549 /* Initialize the struct pcmcia_device structure */
1da177e4 550
15b99ac1 551 ret = mgslpc_config(link);
191c5f10
JS		 552 if (ret) {
553 tty_port_destroy(&info->port);
15b99ac1 554 return ret;
191c5f10 555 }
1da177e4
LT		 556
557 mgslpc_add_device(info);
558
f8cfa618 559 return 0;
1da177e4
LT		 560}
561
562/* Card has been inserted.
563 */
564
00990e7c 565static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
aaa8cfda 566{
90abdc3b 567 return pcmcia_request_io(p_dev);
aaa8cfda
DB		 568}
569
15b99ac1 570static int mgslpc_config(struct pcmcia_device *link)
1da177e4 571{
1da177e4 572 MGSLPC_INFO *info = link->priv;
cbf624f0 573 int ret;
d12341f9 574
1da177e4
LT		 575 if (debug_level >= DEBUG_LEVEL_INFO)
576 printk("mgslpc_config(0x%p)\n", link);
577
00990e7c
DB		 578 link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
579
cbf624f0
DB		 580 ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
581 if (ret != 0)
582 goto failed;
1da177e4 583
7feabb64
DB		 584 link->config_index = 8;
585 link->config_regs = PRESENT_OPTION;
d12341f9 586
eb14120f 587 ret = pcmcia_request_irq(link, mgslpc_isr);
cbf624f0
DB		 588 if (ret)
589 goto failed;
1ac71e5a 590 ret = pcmcia_enable_device(link);
cbf624f0
DB		 591 if (ret)
592 goto failed;
1da177e4 593
9a017a91 594 info->io_base = link->resource[0]->start;
eb14120f 595 info->irq_level = link->irq;
15b99ac1 596 return 0;
1da177e4 597
cbf624f0 598failed:
1da177e4 599 mgslpc_release((u_long)link);
15b99ac1 600 return -ENODEV;
1da177e4
LT		 601}
602
603/* Card has been removed.
604 * Unregister device and release PCMCIA configuration.
605 * If device is open, postpone until it is closed.
606 */
607static void mgslpc_release(u_long arg)
608{
e2d40963 609 struct pcmcia_device *link = (struct pcmcia_device *)arg;
1da177e4 610
e2d40963
DB		 611 if (debug_level >= DEBUG_LEVEL_INFO)
612 printk("mgslpc_release(0x%p)\n", link);
1da177e4 613
e2d40963 614 pcmcia_disable_device(link);
1da177e4
LT		 615}
616
fba395ee 617static void mgslpc_detach(struct pcmcia_device *link)
1da177e4 618{
e2d40963
DB		 619 if (debug_level >= DEBUG_LEVEL_INFO)
620 printk("mgslpc_detach(0x%p)\n", link);
cc3b4866 621
e2d40963
DB		 622 ((MGSLPC_INFO *)link->priv)->stop = 1;
623 mgslpc_release((u_long)link);
1da177e4 624
e2d40963 625 mgslpc_remove_device((MGSLPC_INFO *)link->priv);
1da177e4
LT		 626}
627
fba395ee 628static int mgslpc_suspend(struct pcmcia_device *link)
98e4c28b 629{
98e4c28b
DB		 630 MGSLPC_INFO *info = link->priv;
631
98e4c28b 632 info->stop = 1;
98e4c28b
DB		 633
634 return 0;
635}
636
fba395ee 637static int mgslpc_resume(struct pcmcia_device *link)
98e4c28b 638{
98e4c28b
DB		 639 MGSLPC_INFO *info = link->priv;
640
98e4c28b
DB		 641 info->stop = 0;
642
643 return 0;
644}
645
646
0fab6de0 647static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
1da177e4
LT		 648 char *name, const char *routine)
649{
650#ifdef MGSLPC_PARANOIA_CHECK
651 static const char *badmagic =
652 "Warning: bad magic number for mgsl struct (%s) in %s\n";
653 static const char *badinfo =
654 "Warning: null mgslpc_info for (%s) in %s\n";
655
656 if (!info) {
657 printk(badinfo, name, routine);
0fab6de0 658 return true;
1da177e4
LT		 659 }
660 if (info->magic != MGSLPC_MAGIC) {
661 printk(badmagic, name, routine);
0fab6de0 662 return true;
1da177e4
LT		 663 }
664#else
665 if (!info)
0fab6de0 666 return true;
1da177e4 667#endif
0fab6de0 668 return false;
1da177e4
LT		 669}
670
671
672#define CMD_RXFIFO BIT7 // release current rx FIFO
673#define CMD_RXRESET BIT6 // receiver reset
674#define CMD_RXFIFO_READ BIT5
675#define CMD_START_TIMER BIT4
676#define CMD_TXFIFO BIT3 // release current tx FIFO
677#define CMD_TXEOM BIT1 // transmit end message
678#define CMD_TXRESET BIT0 // transmit reset
679
0fab6de0 680static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
1da177e4
LT		 681{
682 int i = 0;
d12341f9 683 /* wait for command completion */
1da177e4
LT		 684 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
685 udelay(1);
686 if (i++ == 1000)
0fab6de0 687 return false;
1da177e4 688 }
0fab6de0 689 return true;
1da177e4
LT		 690}
691
d12341f9 692static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
1da177e4
LT		 693{
694 wait_command_complete(info, channel);
695 write_reg(info, (unsigned char) (channel + CMDR), cmd);
696}
697
698static void tx_pause(struct tty_struct *tty)
699{
700 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
701 unsigned long flags;
d12341f9 702
1da177e4
LT		 703 if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
704 return;
705 if (debug_level >= DEBUG_LEVEL_INFO)
d12341f9
JG		 706 printk("tx_pause(%s)\n",info->device_name);
707
1da177e4
LT		 708 spin_lock_irqsave(&info->lock,flags);
709 if (info->tx_enabled)
710 tx_stop(info);
711 spin_unlock_irqrestore(&info->lock,flags);
712}
713
714static void tx_release(struct tty_struct *tty)
715{
716 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
717 unsigned long flags;
d12341f9 718
1da177e4
LT		 719 if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
720 return;
721 if (debug_level >= DEBUG_LEVEL_INFO)
d12341f9
JG		 722 printk("tx_release(%s)\n",info->device_name);
723
1da177e4
LT		 724 spin_lock_irqsave(&info->lock,flags);
725 if (!info->tx_enabled)
eeb46134 726 tx_start(info, tty);
1da177e4
LT		 727 spin_unlock_irqrestore(&info->lock,flags);
728}
729
730/* Return next bottom half action to perform.
731 * or 0 if nothing to do.
732 */
733static int bh_action(MGSLPC_INFO *info)
734{
735 unsigned long flags;
736 int rc = 0;
d12341f9 737
1da177e4
LT		 738 spin_lock_irqsave(&info->lock,flags);
739
740 if (info->pending_bh & BH_RECEIVE) {
741 info->pending_bh &= ~BH_RECEIVE;
742 rc = BH_RECEIVE;
743 } else if (info->pending_bh & BH_TRANSMIT) {
744 info->pending_bh &= ~BH_TRANSMIT;
745 rc = BH_TRANSMIT;
746 } else if (info->pending_bh & BH_STATUS) {
747 info->pending_bh &= ~BH_STATUS;
748 rc = BH_STATUS;
749 }
750
751 if (!rc) {
752 /* Mark BH routine as complete */
0fab6de0
JP		 753 info->bh_running = false;
754 info->bh_requested = false;
1da177e4 755 }
d12341f9 756
1da177e4 757 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 758
1da177e4
LT		 759 return rc;
760}
761
c4028958 762static void bh_handler(struct work_struct *work)
1da177e4 763{
c4028958 764 MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
eeb46134 765 struct tty_struct *tty;
1da177e4
LT		 766 int action;
767
768 if (!info)
769 return;
d12341f9 770
1da177e4
LT		 771 if (debug_level >= DEBUG_LEVEL_BH)
772 printk( "%s(%d):bh_handler(%s) entry\n",
773 __FILE__,__LINE__,info->device_name);
d12341f9 774
0fab6de0 775 info->bh_running = true;
eeb46134 776 tty = tty_port_tty_get(&info->port);
1da177e4
LT		 777
778 while((action = bh_action(info)) != 0) {
d12341f9 779
1da177e4
LT		 780 /* Process work item */
781 if ( debug_level >= DEBUG_LEVEL_BH )
782 printk( "%s(%d):bh_handler() work item action=%d\n",
783 __FILE__,__LINE__,action);
784
785 switch (action) {
d12341f9 786
1da177e4 787 case BH_RECEIVE:
eeb46134 788 while(rx_get_frame(info, tty));
1da177e4
LT		 789 break;
790 case BH_TRANSMIT:
eeb46134 791 bh_transmit(info, tty);
1da177e4
LT		 792 break;
793 case BH_STATUS:
794 bh_status(info);
795 break;
796 default:
797 /* unknown work item ID */
798 printk("Unknown work item ID=%08X!\n", action);
799 break;
800 }
801 }
802
eeb46134 803 tty_kref_put(tty);
1da177e4
LT		 804 if (debug_level >= DEBUG_LEVEL_BH)
805 printk( "%s(%d):bh_handler(%s) exit\n",
806 __FILE__,__LINE__,info->device_name);
807}
808
eeb46134 809static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4 810{
1da177e4
LT		 811 if (debug_level >= DEBUG_LEVEL_BH)
812 printk("bh_transmit() entry on %s\n", info->device_name);
813
b963a844 814 if (tty)
1da177e4 815 tty_wakeup(tty);
1da177e4
LT		 816}
817
cdaad343 818static void bh_status(MGSLPC_INFO *info)
1da177e4
LT		 819{
820 info->ri_chkcount = 0;
821 info->dsr_chkcount = 0;
822 info->dcd_chkcount = 0;
823 info->cts_chkcount = 0;
824}
825
d12341f9 826/* eom: non-zero = end of frame */
1da177e4
LT		 827static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
828{
829 unsigned char data[2];
830 unsigned char fifo_count, read_count, i;
831 RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
832
833 if (debug_level >= DEBUG_LEVEL_ISR)
834 printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
d12341f9 835
1da177e4
LT		 836 if (!info->rx_enabled)
837 return;
838
839 if (info->rx_frame_count >= info->rx_buf_count) {
840 /* no more free buffers */
841 issue_command(info, CHA, CMD_RXRESET);
842 info->pending_bh |= BH_RECEIVE;
0fab6de0 843 info->rx_overflow = true;
1da177e4
LT		 844 info->icount.buf_overrun++;
845 return;
846 }
847
848 if (eom) {
d12341f9 849 /* end of frame, get FIFO count from RBCL register */
1da177e4
LT		 850 if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
851 fifo_count = 32;
852 } else
853 fifo_count = 32;
d12341f9 854
1da177e4
LT		 855 do {
856 if (fifo_count == 1) {
857 read_count = 1;
858 data[0] = read_reg(info, CHA + RXFIFO);
859 } else {
860 read_count = 2;
861 *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
862 }
863 fifo_count -= read_count;
864 if (!fifo_count && eom)
865 buf->status = data[--read_count];
866
867 for (i = 0; i < read_count; i++) {
868 if (buf->count >= info->max_frame_size) {
869 /* frame too large, reset receiver and reset current buffer */
870 issue_command(info, CHA, CMD_RXRESET);
871 buf->count = 0;
872 return;
873 }
874 *(buf->data + buf->count) = data[i];
875 buf->count++;
876 }
877 } while (fifo_count);
878
879 if (eom) {
880 info->pending_bh |= BH_RECEIVE;
881 info->rx_frame_count++;
882 info->rx_put++;
883 if (info->rx_put >= info->rx_buf_count)
884 info->rx_put = 0;
885 }
886 issue_command(info, CHA, CMD_RXFIFO);
887}
888
2e124b4a 889static void rx_ready_async(MGSLPC_INFO *info, int tcd)
1da177e4 890{
227434f8 891 struct tty_port *port = &info->port;
33f0f88f 892 unsigned char data, status, flag;
1da177e4 893 int fifo_count;
33f0f88f 894 int work = 0;
1da177e4
LT		 895 struct mgsl_icount *icount = &info->icount;
896
897 if (tcd) {
d12341f9 898 /* early termination, get FIFO count from RBCL register */
1da177e4
LT		 899 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
900
901 /* Zero fifo count could mean 0 or 32 bytes available.
902 * If BIT5 of STAR is set then at least 1 byte is available.
903 */
904 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
905 fifo_count = 32;
906 } else
907 fifo_count = 32;
33f0f88f 908
227434f8 909 tty_buffer_request_room(port, fifo_count);
d12341f9 910 /* Flush received async data to receive data buffer. */
1da177e4
LT		 911 while (fifo_count) {
912 data = read_reg(info, CHA + RXFIFO);
913 status = read_reg(info, CHA + RXFIFO);
914 fifo_count -= 2;
915
1da177e4 916 icount->rx++;
33f0f88f 917 flag = TTY_NORMAL;
1da177e4
LT		 918
919 // if no frameing/crc error then save data
920 // BIT7:parity error
921 // BIT6:framing error
922
923 if (status & (BIT7 + BIT6)) {
d12341f9 924 if (status & BIT7)
1da177e4
LT		 925 icount->parity++;
926 else
927 icount->frame++;
928
929 /* discard char if tty control flags say so */
930 if (status & info->ignore_status_mask)
931 continue;
d12341f9 932
1da177e4
LT		 933 status &= info->read_status_mask;
934
935 if (status & BIT7)
33f0f88f 936 flag = TTY_PARITY;
1da177e4 937 else if (status & BIT6)
33f0f88f 938 flag = TTY_FRAME;
1da177e4 939 }
92a19f9c 940 work += tty_insert_flip_char(port, data, flag);
1da177e4
LT		 941 }
942 issue_command(info, CHA, CMD_RXFIFO);
943
944 if (debug_level >= DEBUG_LEVEL_ISR) {
33f0f88f
AC		 945 printk("%s(%d):rx_ready_async",
946 __FILE__,__LINE__);
1da177e4
LT		 947 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
948 __FILE__,__LINE__,icount->rx,icount->brk,
949 icount->parity,icount->frame,icount->overrun);
950 }
d12341f9 951
33f0f88f 952 if (work)
2e124b4a 953 tty_flip_buffer_push(port);
1da177e4
LT		 954}
955
956
eeb46134 957static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 958{
959 if (!info->tx_active)
960 return;
d12341f9 961
0fab6de0
JP		 962 info->tx_active = false;
963 info->tx_aborting = false;
1da177e4
LT		 964
965 if (info->params.mode == MGSL_MODE_ASYNC)
966 return;
967
968 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9
JG		 969 del_timer(&info->tx_timer);
970
1da177e4
LT		 971 if (info->drop_rts_on_tx_done) {
972 get_signals(info);
973 if (info->serial_signals & SerialSignal_RTS) {
974 info->serial_signals &= ~SerialSignal_RTS;
975 set_signals(info);
976 }
0fab6de0 977 info->drop_rts_on_tx_done = false;
1da177e4
LT		 978 }
979
af69c7f9 980#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 981 if (info->netcount)
982 hdlcdev_tx_done(info);
d12341f9 983 else
1da177e4
LT		 984#endif
985 {
221b7b57 986 if (tty && (tty->stopped || tty->hw_stopped)) {
1da177e4
LT		 987 tx_stop(info);
988 return;
989 }
990 info->pending_bh |= BH_TRANSMIT;
991 }
992}
993
eeb46134 994static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 995{
996 unsigned char fifo_count = 32;
997 int c;
998
999 if (debug_level >= DEBUG_LEVEL_ISR)
1000 printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
1001
1002 if (info->params.mode == MGSL_MODE_HDLC) {
1003 if (!info->tx_active)
1004 return;
1005 } else {
221b7b57 1006 if (tty && (tty->stopped || tty->hw_stopped)) {
1da177e4
LT		 1007 tx_stop(info);
1008 return;
1009 }
1010 if (!info->tx_count)
0fab6de0 1011 info->tx_active = false;
1da177e4
LT		 1012 }
1013
1014 if (!info->tx_count)
1015 return;
1016
1017 while (info->tx_count && fifo_count) {
1018 c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
d12341f9 1019
1da177e4
LT		 1020 if (c == 1) {
1021 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
1022 } else {
1023 write_reg16(info, CHA + TXFIFO,
1024 *((unsigned short*)(info->tx_buf + info->tx_get)));
1025 }
1026 info->tx_count -= c;
1027 info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
1028 fifo_count -= c;
1029 }
1030
1031 if (info->params.mode == MGSL_MODE_ASYNC) {
1032 if (info->tx_count < WAKEUP_CHARS)
1033 info->pending_bh |= BH_TRANSMIT;
1034 issue_command(info, CHA, CMD_TXFIFO);
1035 } else {
1036 if (info->tx_count)
1037 issue_command(info, CHA, CMD_TXFIFO);
1038 else
1039 issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
1040 }
1041}
1042
eeb46134 1043static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1044{
1045 get_signals(info);
1046 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1047 irq_disable(info, CHB, IRQ_CTS);
1048 info->icount.cts++;
1049 if (info->serial_signals & SerialSignal_CTS)
1050 info->input_signal_events.cts_up++;
1051 else
1052 info->input_signal_events.cts_down++;
1053 wake_up_interruptible(&info->status_event_wait_q);
1054 wake_up_interruptible(&info->event_wait_q);
1055
3498d13b 1056 if (tty && tty_port_cts_enabled(&info->port)) {
eeb46134 1057 if (tty->hw_stopped) {
1da177e4
LT		 1058 if (info->serial_signals & SerialSignal_CTS) {
1059 if (debug_level >= DEBUG_LEVEL_ISR)
1060 printk("CTS tx start...");
221b7b57 1061 tty->hw_stopped = 0;
eeb46134 1062 tx_start(info, tty);
1da177e4
LT		 1063 info->pending_bh |= BH_TRANSMIT;
1064 return;
1065 }
1066 } else {
1067 if (!(info->serial_signals & SerialSignal_CTS)) {
1068 if (debug_level >= DEBUG_LEVEL_ISR)
1069 printk("CTS tx stop...");
221b7b57 1070 tty->hw_stopped = 1;
1da177e4
LT		 1071 tx_stop(info);
1072 }
1073 }
1074 }
1075 info->pending_bh |= BH_STATUS;
1076}
1077
eeb46134 1078static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1079{
1080 get_signals(info);
1081 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1082 irq_disable(info, CHB, IRQ_DCD);
1083 info->icount.dcd++;
1084 if (info->serial_signals & SerialSignal_DCD) {
1085 info->input_signal_events.dcd_up++;
1086 }
1087 else
1088 info->input_signal_events.dcd_down++;
af69c7f9 1089#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 1090 if (info->netcount) {
1091 if (info->serial_signals & SerialSignal_DCD)
1092 netif_carrier_on(info->netdev);
1093 else
1094 netif_carrier_off(info->netdev);
1095 }
1da177e4
LT		 1096#endif
1097 wake_up_interruptible(&info->status_event_wait_q);
1098 wake_up_interruptible(&info->event_wait_q);
1099
eeb46134 1100 if (info->port.flags & ASYNC_CHECK_CD) {
1da177e4
LT		 1101 if (debug_level >= DEBUG_LEVEL_ISR)
1102 printk("%s CD now %s...", info->device_name,
1103 (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
1104 if (info->serial_signals & SerialSignal_DCD)
eeb46134 1105 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1106 else {
1107 if (debug_level >= DEBUG_LEVEL_ISR)
1108 printk("doing serial hangup...");
eeb46134
AC		 1109 if (tty)
1110 tty_hangup(tty);
1da177e4
LT		 1111 }
1112 }
1113 info->pending_bh |= BH_STATUS;
1114}
1115
1116static void dsr_change(MGSLPC_INFO *info)
1117{
1118 get_signals(info);
1119 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1120 port_irq_disable(info, PVR_DSR);
1121 info->icount.dsr++;
1122 if (info->serial_signals & SerialSignal_DSR)
1123 info->input_signal_events.dsr_up++;
1124 else
1125 info->input_signal_events.dsr_down++;
1126 wake_up_interruptible(&info->status_event_wait_q);
1127 wake_up_interruptible(&info->event_wait_q);
1128 info->pending_bh |= BH_STATUS;
1129}
1130
1131static void ri_change(MGSLPC_INFO *info)
1132{
1133 get_signals(info);
1134 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1135 port_irq_disable(info, PVR_RI);
1136 info->icount.rng++;
1137 if (info->serial_signals & SerialSignal_RI)
1138 info->input_signal_events.ri_up++;
1139 else
1140 info->input_signal_events.ri_down++;
1141 wake_up_interruptible(&info->status_event_wait_q);
1142 wake_up_interruptible(&info->event_wait_q);
1143 info->pending_bh |= BH_STATUS;
1144}
1145
1146/* Interrupt service routine entry point.
d12341f9 1147 *
1da177e4 1148 * Arguments:
d12341f9 1149 *
1da177e4
LT		 1150 * irq interrupt number that caused interrupt
1151 * dev_id device ID supplied during interrupt registration
1da177e4 1152 */
a6f97b29 1153static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
1da177e4 1154{
a6f97b29 1155 MGSLPC_INFO *info = dev_id;
eeb46134 1156 struct tty_struct *tty;
1da177e4
LT		 1157 unsigned short isr;
1158 unsigned char gis, pis;
1159 int count=0;
1160
d12341f9 1161 if (debug_level >= DEBUG_LEVEL_ISR)
a6f97b29 1162 printk("mgslpc_isr(%d) entry.\n", info->irq_level);
d12341f9 1163
e2d40963 1164 if (!(info->p_dev->_locked))
1da177e4
LT		 1165 return IRQ_HANDLED;
1166
eeb46134
AC		 1167 tty = tty_port_tty_get(&info->port);
1168
1da177e4
LT		 1169 spin_lock(&info->lock);
1170
1171 while ((gis = read_reg(info, CHA + GIS))) {
d12341f9 1172 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4
LT		 1173 printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
1174
1175 if ((gis & 0x70) || count > 1000) {
1176 printk("synclink_cs:hardware failed or ejected\n");
1177 break;
1178 }
1179 count++;
1180
1181 if (gis & (BIT1 + BIT0)) {
1182 isr = read_reg16(info, CHB + ISR);
1183 if (isr & IRQ_DCD)
eeb46134 1184 dcd_change(info, tty);
1da177e4 1185 if (isr & IRQ_CTS)
eeb46134 1186 cts_change(info, tty);
1da177e4
LT		 1187 }
1188 if (gis & (BIT3 + BIT2))
1189 {
1190 isr = read_reg16(info, CHA + ISR);
1191 if (isr & IRQ_TIMER) {
0fab6de0 1192 info->irq_occurred = true;
1da177e4
LT		 1193 irq_disable(info, CHA, IRQ_TIMER);
1194 }
1195
d12341f9 1196 /* receive IRQs */
1da177e4
LT		 1197 if (isr & IRQ_EXITHUNT) {
1198 info->icount.exithunt++;
1199 wake_up_interruptible(&info->event_wait_q);
1200 }
1201 if (isr & IRQ_BREAK_ON) {
1202 info->icount.brk++;
eeb46134
AC		 1203 if (info->port.flags & ASYNC_SAK)
1204 do_SAK(tty);
1da177e4
LT		 1205 }
1206 if (isr & IRQ_RXTIME) {
1207 issue_command(info, CHA, CMD_RXFIFO_READ);
1208 }
1209 if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
1210 if (info->params.mode == MGSL_MODE_HDLC)
d12341f9 1211 rx_ready_hdlc(info, isr & IRQ_RXEOM);
1da177e4 1212 else
2e124b4a 1213 rx_ready_async(info, isr & IRQ_RXEOM);
1da177e4
LT		 1214 }
1215
d12341f9 1216 /* transmit IRQs */
1da177e4
LT		 1217 if (isr & IRQ_UNDERRUN) {
1218 if (info->tx_aborting)
1219 info->icount.txabort++;
1220 else
1221 info->icount.txunder++;
eeb46134 1222 tx_done(info, tty);
1da177e4
LT		 1223 }
1224 else if (isr & IRQ_ALLSENT) {
1225 info->icount.txok++;
eeb46134 1226 tx_done(info, tty);
1da177e4
LT		 1227 }
1228 else if (isr & IRQ_TXFIFO)
eeb46134 1229 tx_ready(info, tty);
1da177e4
LT		 1230 }
1231 if (gis & BIT7) {
1232 pis = read_reg(info, CHA + PIS);
1233 if (pis & BIT1)
1234 dsr_change(info);
1235 if (pis & BIT2)
1236 ri_change(info);
1237 }
1238 }
d12341f9
JG		 1239
1240 /* Request bottom half processing if there's something
1da177e4
LT		 1241 * for it to do and the bh is not already running
1242 */
1243
1244 if (info->pending_bh && !info->bh_running && !info->bh_requested) {
d12341f9 1245 if ( debug_level >= DEBUG_LEVEL_ISR )
1da177e4
LT		 1246 printk("%s(%d):%s queueing bh task.\n",
1247 __FILE__,__LINE__,info->device_name);
1248 schedule_work(&info->task);
0fab6de0 1249 info->bh_requested = true;
1da177e4
LT		 1250 }
1251
1252 spin_unlock(&info->lock);
eeb46134 1253 tty_kref_put(tty);
d12341f9
JG		 1254
1255 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4 1256 printk("%s(%d):mgslpc_isr(%d)exit.\n",
a6f97b29 1257 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 1258
1259 return IRQ_HANDLED;
1260}
1261
1262/* Initialize and start device.
1263 */
eeb46134 1264static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1265{
1266 int retval = 0;
d12341f9 1267
1da177e4
LT		 1268 if (debug_level >= DEBUG_LEVEL_INFO)
1269 printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
d12341f9 1270
eeb46134 1271 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4 1272 return 0;
d12341f9 1273
1da177e4
LT		 1274 if (!info->tx_buf) {
1275 /* allocate a page of memory for a transmit buffer */
1276 info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1277 if (!info->tx_buf) {
1278 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1279 __FILE__,__LINE__,info->device_name);
1280 return -ENOMEM;
1281 }
1282 }
1283
1284 info->pending_bh = 0;
d12341f9 1285
a7482a2e
PF		 1286 memset(&info->icount, 0, sizeof(info->icount));
1287
40565f19 1288 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
1da177e4
LT		 1289
1290 /* Allocate and claim adapter resources */
1291 retval = claim_resources(info);
d12341f9 1292
25985edc 1293 /* perform existence check and diagnostics */
1da177e4
LT		 1294 if ( !retval )
1295 retval = adapter_test(info);
d12341f9 1296
1da177e4 1297 if ( retval ) {
eeb46134
AC		 1298 if (capable(CAP_SYS_ADMIN) && tty)
1299 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4
LT		 1300 release_resources(info);
1301 return retval;
1302 }
1303
1304 /* program hardware for current parameters */
eeb46134 1305 mgslpc_change_params(info, tty);
d12341f9 1306
eeb46134
AC		 1307 if (tty)
1308 clear_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1309
eeb46134 1310 info->port.flags |= ASYNC_INITIALIZED;
d12341f9 1311
1da177e4
LT		 1312 return 0;
1313}
1314
1315/* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
1316 */
eeb46134 1317static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1318{
1319 unsigned long flags;
d12341f9 1320
eeb46134 1321 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 1322 return;
1323
1324 if (debug_level >= DEBUG_LEVEL_INFO)
1325 printk("%s(%d):mgslpc_shutdown(%s)\n",
1326 __FILE__,__LINE__, info->device_name );
1327
1328 /* clear status wait queue because status changes */
1329 /* can't happen after shutting down the hardware */
1330 wake_up_interruptible(&info->status_event_wait_q);
1331 wake_up_interruptible(&info->event_wait_q);
1332
40565f19 1333 del_timer_sync(&info->tx_timer);
1da177e4
LT		 1334
1335 if (info->tx_buf) {
1336 free_page((unsigned long) info->tx_buf);
1337 info->tx_buf = NULL;
1338 }
1339
1340 spin_lock_irqsave(&info->lock,flags);
1341
1342 rx_stop(info);
1343 tx_stop(info);
1344
1345 /* TODO:disable interrupts instead of reset to preserve signal states */
1346 reset_device(info);
d12341f9 1347
373f5aed 1348 if (!tty || tty->termios.c_cflag & HUPCL) {
1da177e4
LT		 1349 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1350 set_signals(info);
1351 }
d12341f9 1352
1da177e4
LT		 1353 spin_unlock_irqrestore(&info->lock,flags);
1354
d12341f9
JG		 1355 release_resources(info);
1356
eeb46134
AC		 1357 if (tty)
1358 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1359
eeb46134 1360 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4
LT		 1361}
1362
eeb46134 1363static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1364{
1365 unsigned long flags;
1366
1367 spin_lock_irqsave(&info->lock,flags);
d12341f9 1368
1da177e4
LT		 1369 rx_stop(info);
1370 tx_stop(info);
1371 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1372
1da177e4
LT		 1373 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
1374 hdlc_mode(info);
1375 else
1376 async_mode(info);
d12341f9 1377
1da177e4 1378 set_signals(info);
d12341f9 1379
1da177e4
LT		 1380 info->dcd_chkcount = 0;
1381 info->cts_chkcount = 0;
1382 info->ri_chkcount = 0;
1383 info->dsr_chkcount = 0;
1384
1385 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
1386 port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
1387 get_signals(info);
d12341f9 1388
373f5aed 1389 if (info->netcount || (tty && (tty->termios.c_cflag & CREAD)))
1da177e4 1390 rx_start(info);
d12341f9 1391
1da177e4
LT		 1392 spin_unlock_irqrestore(&info->lock,flags);
1393}
1394
1395/* Reconfigure adapter based on new parameters
1396 */
eeb46134 1397static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1398{
1399 unsigned cflag;
1400 int bits_per_char;
1401
373f5aed 1402 if (!tty)
1da177e4 1403 return;
d12341f9 1404
1da177e4
LT		 1405 if (debug_level >= DEBUG_LEVEL_INFO)
1406 printk("%s(%d):mgslpc_change_params(%s)\n",
1407 __FILE__,__LINE__, info->device_name );
d12341f9 1408
373f5aed 1409 cflag = tty->termios.c_cflag;
1da177e4
LT		 1410
1411 /* if B0 rate (hangup) specified then negate DTR and RTS */
1412 /* otherwise assert DTR and RTS */
1413 if (cflag & CBAUD)
1414 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1415 else
1416 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
d12341f9 1417
1da177e4 1418 /* byte size and parity */
d12341f9 1419
1da177e4
LT		 1420 switch (cflag & CSIZE) {
1421 case CS5: info->params.data_bits = 5; break;
1422 case CS6: info->params.data_bits = 6; break;
1423 case CS7: info->params.data_bits = 7; break;
1424 case CS8: info->params.data_bits = 8; break;
1425 default: info->params.data_bits = 7; break;
1426 }
d12341f9 1427
1da177e4
LT		 1428 if (cflag & CSTOPB)
1429 info->params.stop_bits = 2;
1430 else
1431 info->params.stop_bits = 1;
1432
1433 info->params.parity = ASYNC_PARITY_NONE;
1434 if (cflag & PARENB) {
1435 if (cflag & PARODD)
1436 info->params.parity = ASYNC_PARITY_ODD;
1437 else
1438 info->params.parity = ASYNC_PARITY_EVEN;
1439#ifdef CMSPAR
1440 if (cflag & CMSPAR)
1441 info->params.parity = ASYNC_PARITY_SPACE;
1442#endif
1443 }
1444
1445 /* calculate number of jiffies to transmit a full
1446 * FIFO (32 bytes) at specified data rate
1447 */
d12341f9 1448 bits_per_char = info->params.data_bits +
1da177e4
LT		 1449 info->params.stop_bits + 1;
1450
1451 /* if port data rate is set to 460800 or less then
1452 * allow tty settings to override, otherwise keep the
1453 * current data rate.
1454 */
1455 if (info->params.data_rate <= 460800) {
eeb46134 1456 info->params.data_rate = tty_get_baud_rate(tty);
1da177e4 1457 }
d12341f9 1458
1da177e4 1459 if ( info->params.data_rate ) {
d12341f9 1460 info->timeout = (32*HZ*bits_per_char) /
1da177e4
LT		 1461 info->params.data_rate;
1462 }
1463 info->timeout += HZ/50; /* Add .02 seconds of slop */
1464
1465 if (cflag & CRTSCTS)
eeb46134 1466 info->port.flags |= ASYNC_CTS_FLOW;
1da177e4 1467 else
eeb46134 1468 info->port.flags &= ~ASYNC_CTS_FLOW;
d12341f9 1469
1da177e4 1470 if (cflag & CLOCAL)
eeb46134 1471 info->port.flags &= ~ASYNC_CHECK_CD;
1da177e4 1472 else
eeb46134 1473 info->port.flags |= ASYNC_CHECK_CD;
1da177e4
LT		 1474
1475 /* process tty input control flags */
d12341f9 1476
1da177e4 1477 info->read_status_mask = 0;
eeb46134 1478 if (I_INPCK(tty))
1da177e4 1479 info->read_status_mask |= BIT7 | BIT6;
eeb46134 1480 if (I_IGNPAR(tty))
1da177e4
LT		 1481 info->ignore_status_mask |= BIT7 | BIT6;
1482
eeb46134 1483 mgslpc_program_hw(info, tty);
1da177e4
LT		 1484}
1485
1486/* Add a character to the transmit buffer
1487 */
d7e752e2 1488static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4
LT		 1489{
1490 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1491 unsigned long flags;
1492
1493 if (debug_level >= DEBUG_LEVEL_INFO) {
1494 printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
1495 __FILE__,__LINE__,ch,info->device_name);
1496 }
1497
1498 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
d7e752e2 1499 return 0;
1da177e4 1500
326f28e9 1501 if (!info->tx_buf)
d7e752e2 1502 return 0;
1da177e4
LT		 1503
1504 spin_lock_irqsave(&info->lock,flags);
d12341f9 1505
1da177e4
LT		 1506 if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
1507 if (info->tx_count < TXBUFSIZE - 1) {
1508 info->tx_buf[info->tx_put++] = ch;
1509 info->tx_put &= TXBUFSIZE-1;
1510 info->tx_count++;
1511 }
1512 }
d12341f9 1513
1da177e4 1514 spin_unlock_irqrestore(&info->lock,flags);
d7e752e2 1515 return 1;
1da177e4
LT		 1516}
1517
1518/* Enable transmitter so remaining characters in the
1519 * transmit buffer are sent.
1520 */
1521static void mgslpc_flush_chars(struct tty_struct *tty)
1522{
1523 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1524 unsigned long flags;
d12341f9 1525
1da177e4
LT		 1526 if (debug_level >= DEBUG_LEVEL_INFO)
1527 printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
1528 __FILE__,__LINE__,info->device_name,info->tx_count);
d12341f9 1529
1da177e4
LT		 1530 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
1531 return;
1532
1533 if (info->tx_count <= 0 || tty->stopped ||
1534 tty->hw_stopped || !info->tx_buf)
1535 return;
1536
1537 if (debug_level >= DEBUG_LEVEL_INFO)
1538 printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
1539 __FILE__,__LINE__,info->device_name);
1540
1541 spin_lock_irqsave(&info->lock,flags);
1542 if (!info->tx_active)
eeb46134 1543 tx_start(info, tty);
1da177e4
LT		 1544 spin_unlock_irqrestore(&info->lock,flags);
1545}
1546
1547/* Send a block of data
d12341f9 1548 *
1da177e4 1549 * Arguments:
d12341f9 1550 *
1da177e4
LT		 1551 * tty pointer to tty information structure
1552 * buf pointer to buffer containing send data
1553 * count size of send data in bytes
d12341f9 1554 *
1da177e4
LT		 1555 * Returns: number of characters written
1556 */
1557static int mgslpc_write(struct tty_struct * tty,
1558 const unsigned char *buf, int count)
1559{
1560 int c, ret = 0;
1561 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1562 unsigned long flags;
d12341f9 1563
1da177e4
LT		 1564 if (debug_level >= DEBUG_LEVEL_INFO)
1565 printk( "%s(%d):mgslpc_write(%s) count=%d\n",
1566 __FILE__,__LINE__,info->device_name,count);
d12341f9 1567
1da177e4 1568 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
326f28e9 1569 !info->tx_buf)
1da177e4
LT		 1570 goto cleanup;
1571
1572 if (info->params.mode == MGSL_MODE_HDLC) {
1573 if (count > TXBUFSIZE) {
1574 ret = -EIO;
1575 goto cleanup;
1576 }
1577 if (info->tx_active)
1578 goto cleanup;
1579 else if (info->tx_count)
1580 goto start;
1581 }
1582
1583 for (;;) {
1584 c = min(count,
1585 min(TXBUFSIZE - info->tx_count - 1,
1586 TXBUFSIZE - info->tx_put));
1587 if (c <= 0)
1588 break;
d12341f9 1589
1da177e4
LT		 1590 memcpy(info->tx_buf + info->tx_put, buf, c);
1591
1592 spin_lock_irqsave(&info->lock,flags);
1593 info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
1594 info->tx_count += c;
1595 spin_unlock_irqrestore(&info->lock,flags);
1596
1597 buf += c;
1598 count -= c;
1599 ret += c;
1600 }
1601start:
1602 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1603 spin_lock_irqsave(&info->lock,flags);
1604 if (!info->tx_active)
eeb46134 1605 tx_start(info, tty);
1da177e4
LT		 1606 spin_unlock_irqrestore(&info->lock,flags);
1607 }
d12341f9 1608cleanup:
1da177e4
LT		 1609 if (debug_level >= DEBUG_LEVEL_INFO)
1610 printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
1611 __FILE__,__LINE__,info->device_name,ret);
1612 return ret;
1613}
1614
1615/* Return the count of free bytes in transmit buffer
1616 */
1617static int mgslpc_write_room(struct tty_struct *tty)
1618{
1619 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1620 int ret;
d12341f9 1621
1da177e4
LT		 1622 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
1623 return 0;
1624
1625 if (info->params.mode == MGSL_MODE_HDLC) {
1626 /* HDLC (frame oriented) mode */
1627 if (info->tx_active)
1628 return 0;
1629 else
1630 return HDLC_MAX_FRAME_SIZE;
1631 } else {
1632 ret = TXBUFSIZE - info->tx_count - 1;
1633 if (ret < 0)
1634 ret = 0;
1635 }
d12341f9 1636
1da177e4
LT		 1637 if (debug_level >= DEBUG_LEVEL_INFO)
1638 printk("%s(%d):mgslpc_write_room(%s)=%d\n",
1639 __FILE__,__LINE__, info->device_name, ret);
1640 return ret;
1641}
1642
1643/* Return the count of bytes in transmit buffer
1644 */
1645static int mgslpc_chars_in_buffer(struct tty_struct *tty)
1646{
1647 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1648 int rc;
d12341f9 1649
1da177e4
LT		 1650 if (debug_level >= DEBUG_LEVEL_INFO)
1651 printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
1652 __FILE__,__LINE__, info->device_name );
d12341f9 1653
1da177e4
LT		 1654 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
1655 return 0;
d12341f9 1656
1da177e4
LT		 1657 if (info->params.mode == MGSL_MODE_HDLC)
1658 rc = info->tx_active ? info->max_frame_size : 0;
1659 else
1660 rc = info->tx_count;
1661
1662 if (debug_level >= DEBUG_LEVEL_INFO)
1663 printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
1664 __FILE__,__LINE__, info->device_name, rc);
d12341f9 1665
1da177e4
LT		 1666 return rc;
1667}
1668
1669/* Discard all data in the send buffer
1670 */
1671static void mgslpc_flush_buffer(struct tty_struct *tty)
1672{
1673 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1674 unsigned long flags;
d12341f9 1675
1da177e4
LT		 1676 if (debug_level >= DEBUG_LEVEL_INFO)
1677 printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
1678 __FILE__,__LINE__, info->device_name );
d12341f9 1679
1da177e4
LT		 1680 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
1681 return;
d12341f9
JG		 1682
1683 spin_lock_irqsave(&info->lock,flags);
1da177e4 1684 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1685 del_timer(&info->tx_timer);
1da177e4
LT		 1686 spin_unlock_irqrestore(&info->lock,flags);
1687
1688 wake_up_interruptible(&tty->write_wait);
1689 tty_wakeup(tty);
1690}
1691
1692/* Send a high-priority XON/XOFF character
1693 */
1694static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
1695{
1696 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1697 unsigned long flags;
1698
1699 if (debug_level >= DEBUG_LEVEL_INFO)
1700 printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
1701 __FILE__,__LINE__, info->device_name, ch );
d12341f9 1702
1da177e4
LT		 1703 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
1704 return;
1705
1706 info->x_char = ch;
1707 if (ch) {
1708 spin_lock_irqsave(&info->lock,flags);
1709 if (!info->tx_enabled)
eeb46134 1710 tx_start(info, tty);
1da177e4
LT		 1711 spin_unlock_irqrestore(&info->lock,flags);
1712 }
1713}
1714
1715/* Signal remote device to throttle send data (our receive data)
1716 */
1717static void mgslpc_throttle(struct tty_struct * tty)
1718{
1719 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1720 unsigned long flags;
d12341f9 1721
1da177e4
LT		 1722 if (debug_level >= DEBUG_LEVEL_INFO)
1723 printk("%s(%d):mgslpc_throttle(%s) entry\n",
1724 __FILE__,__LINE__, info->device_name );
1725
1726 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
1727 return;
d12341f9 1728
1da177e4
LT		 1729 if (I_IXOFF(tty))
1730 mgslpc_send_xchar(tty, STOP_CHAR(tty));
d12341f9 1731
373f5aed 1732 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 1733 spin_lock_irqsave(&info->lock,flags);
1734 info->serial_signals &= ~SerialSignal_RTS;
1735 set_signals(info);
1736 spin_unlock_irqrestore(&info->lock,flags);
1737 }
1738}
1739
1740/* Signal remote device to stop throttling send data (our receive data)
1741 */
1742static void mgslpc_unthrottle(struct tty_struct * tty)
1743{
1744 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1745 unsigned long flags;
d12341f9 1746
1da177e4
LT		 1747 if (debug_level >= DEBUG_LEVEL_INFO)
1748 printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
1749 __FILE__,__LINE__, info->device_name );
1750
1751 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
1752 return;
d12341f9 1753
1da177e4
LT		 1754 if (I_IXOFF(tty)) {
1755 if (info->x_char)
1756 info->x_char = 0;
1757 else
1758 mgslpc_send_xchar(tty, START_CHAR(tty));
1759 }
d12341f9 1760
373f5aed 1761 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 1762 spin_lock_irqsave(&info->lock,flags);
1763 info->serial_signals |= SerialSignal_RTS;
1764 set_signals(info);
1765 spin_unlock_irqrestore(&info->lock,flags);
1766 }
1767}
1768
1769/* get the current serial statistics
1770 */
1771static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
1772{
1773 int err;
1774 if (debug_level >= DEBUG_LEVEL_INFO)
1775 printk("get_params(%s)\n", info->device_name);
a7482a2e
PF		 1776 if (!user_icount) {
1777 memset(&info->icount, 0, sizeof(info->icount));
1778 } else {
1779 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
1780 if (err)
1781 return -EFAULT;
1782 }
1da177e4
LT		 1783 return 0;
1784}
1785
1786/* get the current serial parameters
1787 */
1788static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
1789{
1790 int err;
1791 if (debug_level >= DEBUG_LEVEL_INFO)
1792 printk("get_params(%s)\n", info->device_name);
1793 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
1794 if (err)
1795 return -EFAULT;
1796 return 0;
1797}
1798
1799/* set the serial parameters
d12341f9 1800 *
1da177e4 1801 * Arguments:
d12341f9 1802 *
1da177e4
LT		 1803 * info pointer to device instance data
1804 * new_params user buffer containing new serial params
1805 *
1806 * Returns: 0 if success, otherwise error code
1807 */
eeb46134 1808static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
1da177e4
LT		 1809{
1810 unsigned long flags;
1811 MGSL_PARAMS tmp_params;
1812 int err;
d12341f9 1813
1da177e4
LT		 1814 if (debug_level >= DEBUG_LEVEL_INFO)
1815 printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
1816 info->device_name );
1817 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
1818 if (err) {
1819 if ( debug_level >= DEBUG_LEVEL_INFO )
1820 printk( "%s(%d):set_params(%s) user buffer copy failed\n",
1821 __FILE__,__LINE__,info->device_name);
1822 return -EFAULT;
1823 }
d12341f9 1824
1da177e4
LT		 1825 spin_lock_irqsave(&info->lock,flags);
1826 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
1827 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 1828
eeb46134 1829 mgslpc_change_params(info, tty);
d12341f9 1830
1da177e4
LT		 1831 return 0;
1832}
1833
1834static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
1835{
1836 int err;
1837 if (debug_level >= DEBUG_LEVEL_INFO)
1838 printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
1839 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
1840 if (err)
1841 return -EFAULT;
1842 return 0;
1843}
1844
1845static int set_txidle(MGSLPC_INFO * info, int idle_mode)
1846{
1847 unsigned long flags;
1848 if (debug_level >= DEBUG_LEVEL_INFO)
1849 printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
1850 spin_lock_irqsave(&info->lock,flags);
1851 info->idle_mode = idle_mode;
1852 tx_set_idle(info);
1853 spin_unlock_irqrestore(&info->lock,flags);
1854 return 0;
1855}
1856
1857static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
1858{
1859 int err;
1860 if (debug_level >= DEBUG_LEVEL_INFO)
1861 printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
1862 COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
1863 if (err)
1864 return -EFAULT;
1865 return 0;
1866}
1867
1868static int set_interface(MGSLPC_INFO * info, int if_mode)
1869{
1870 unsigned long flags;
1871 unsigned char val;
1872 if (debug_level >= DEBUG_LEVEL_INFO)
1873 printk("set_interface(%s,%d)\n", info->device_name, if_mode);
1874 spin_lock_irqsave(&info->lock,flags);
1875 info->if_mode = if_mode;
1876
1877 val = read_reg(info, PVR) & 0x0f;
1878 switch (info->if_mode)
1879 {
1880 case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
1881 case MGSL_INTERFACE_V35: val |= PVR_V35; break;
1882 case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
1883 }
1884 write_reg(info, PVR, val);
1885
1886 spin_unlock_irqrestore(&info->lock,flags);
1887 return 0;
1888}
1889
eeb46134 1890static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
1da177e4
LT		 1891{
1892 unsigned long flags;
d12341f9 1893
1da177e4
LT		 1894 if (debug_level >= DEBUG_LEVEL_INFO)
1895 printk("set_txenable(%s,%d)\n", info->device_name, enable);
d12341f9 1896
1da177e4
LT		 1897 spin_lock_irqsave(&info->lock,flags);
1898 if (enable) {
1899 if (!info->tx_enabled)
eeb46134 1900 tx_start(info, tty);
1da177e4
LT		 1901 } else {
1902 if (info->tx_enabled)
1903 tx_stop(info);
1904 }
1905 spin_unlock_irqrestore(&info->lock,flags);
1906 return 0;
1907}
1908
1909static int tx_abort(MGSLPC_INFO * info)
1910{
1911 unsigned long flags;
d12341f9 1912
1da177e4
LT		 1913 if (debug_level >= DEBUG_LEVEL_INFO)
1914 printk("tx_abort(%s)\n", info->device_name);
d12341f9 1915
1da177e4
LT		 1916 spin_lock_irqsave(&info->lock,flags);
1917 if (info->tx_active && info->tx_count &&
1918 info->params.mode == MGSL_MODE_HDLC) {
1919 /* clear data count so FIFO is not filled on next IRQ.
1920 * This results in underrun and abort transmission.
1921 */
1922 info->tx_count = info->tx_put = info->tx_get = 0;
0fab6de0 1923 info->tx_aborting = true;
1da177e4
LT		 1924 }
1925 spin_unlock_irqrestore(&info->lock,flags);
1926 return 0;
1927}
1928
1929static int set_rxenable(MGSLPC_INFO * info, int enable)
1930{
1931 unsigned long flags;
d12341f9 1932
1da177e4
LT		 1933 if (debug_level >= DEBUG_LEVEL_INFO)
1934 printk("set_rxenable(%s,%d)\n", info->device_name, enable);
d12341f9 1935
1da177e4
LT		 1936 spin_lock_irqsave(&info->lock,flags);
1937 if (enable) {
1938 if (!info->rx_enabled)
1939 rx_start(info);
1940 } else {
1941 if (info->rx_enabled)
1942 rx_stop(info);
1943 }
1944 spin_unlock_irqrestore(&info->lock,flags);
1945 return 0;
1946}
1947
1948/* wait for specified event to occur
d12341f9 1949 *
1da177e4
LT		 1950 * Arguments: info pointer to device instance data
1951 * mask pointer to bitmask of events to wait for
1952 * Return Value: 0 if successful and bit mask updated with
1953 * of events triggerred,
1954 * otherwise error code
1955 */
1956static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
1957{
1958 unsigned long flags;
1959 int s;
1960 int rc=0;
1961 struct mgsl_icount cprev, cnow;
1962 int events;
1963 int mask;
1964 struct _input_signal_events oldsigs, newsigs;
1965 DECLARE_WAITQUEUE(wait, current);
1966
1967 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
1968 if (rc)
1969 return -EFAULT;
d12341f9 1970
1da177e4
LT		 1971 if (debug_level >= DEBUG_LEVEL_INFO)
1972 printk("wait_events(%s,%d)\n", info->device_name, mask);
1973
1974 spin_lock_irqsave(&info->lock,flags);
1975
1976 /* return immediately if state matches requested events */
1977 get_signals(info);
1978 s = info->serial_signals;
1979 events = mask &
1980 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
1981 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
1982 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
1983 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
1984 if (events) {
1985 spin_unlock_irqrestore(&info->lock,flags);
1986 goto exit;
1987 }
1988
1989 /* save current irq counts */
1990 cprev = info->icount;
1991 oldsigs = info->input_signal_events;
d12341f9 1992
1da177e4
LT		 1993 if ((info->params.mode == MGSL_MODE_HDLC) &&
1994 (mask & MgslEvent_ExitHuntMode))
1995 irq_enable(info, CHA, IRQ_EXITHUNT);
d12341f9 1996
1da177e4
LT		 1997 set_current_state(TASK_INTERRUPTIBLE);
1998 add_wait_queue(&info->event_wait_q, &wait);
d12341f9 1999
1da177e4 2000 spin_unlock_irqrestore(&info->lock,flags);
d12341f9
JG		 2001
2002
1da177e4
LT		 2003 for(;;) {
2004 schedule();
2005 if (signal_pending(current)) {
2006 rc = -ERESTARTSYS;
2007 break;
2008 }
d12341f9 2009
1da177e4
LT		 2010 /* get current irq counts */
2011 spin_lock_irqsave(&info->lock,flags);
2012 cnow = info->icount;
2013 newsigs = info->input_signal_events;
2014 set_current_state(TASK_INTERRUPTIBLE);
2015 spin_unlock_irqrestore(&info->lock,flags);
2016
2017 /* if no change, wait aborted for some reason */
2018 if (newsigs.dsr_up == oldsigs.dsr_up &&
2019 newsigs.dsr_down == oldsigs.dsr_down &&
2020 newsigs.dcd_up == oldsigs.dcd_up &&
2021 newsigs.dcd_down == oldsigs.dcd_down &&
2022 newsigs.cts_up == oldsigs.cts_up &&
2023 newsigs.cts_down == oldsigs.cts_down &&
2024 newsigs.ri_up == oldsigs.ri_up &&
2025 newsigs.ri_down == oldsigs.ri_down &&
2026 cnow.exithunt == cprev.exithunt &&
2027 cnow.rxidle == cprev.rxidle) {
2028 rc = -EIO;
2029 break;
2030 }
2031
2032 events = mask &
2033 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2034 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2035 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2036 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2037 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2038 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2039 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2040 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2041 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2042 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2043 if (events)
2044 break;
d12341f9 2045
1da177e4
LT		 2046 cprev = cnow;
2047 oldsigs = newsigs;
2048 }
d12341f9 2049
1da177e4
LT		 2050 remove_wait_queue(&info->event_wait_q, &wait);
2051 set_current_state(TASK_RUNNING);
2052
2053 if (mask & MgslEvent_ExitHuntMode) {
2054 spin_lock_irqsave(&info->lock,flags);
2055 if (!waitqueue_active(&info->event_wait_q))
2056 irq_disable(info, CHA, IRQ_EXITHUNT);
2057 spin_unlock_irqrestore(&info->lock,flags);
2058 }
2059exit:
2060 if (rc == 0)
2061 PUT_USER(rc, events, mask_ptr);
2062 return rc;
2063}
2064
2065static int modem_input_wait(MGSLPC_INFO *info,int arg)
2066{
2067 unsigned long flags;
2068 int rc;
2069 struct mgsl_icount cprev, cnow;
2070 DECLARE_WAITQUEUE(wait, current);
2071
2072 /* save current irq counts */
2073 spin_lock_irqsave(&info->lock,flags);
2074 cprev = info->icount;
2075 add_wait_queue(&info->status_event_wait_q, &wait);
2076 set_current_state(TASK_INTERRUPTIBLE);
2077 spin_unlock_irqrestore(&info->lock,flags);
2078
2079 for(;;) {
2080 schedule();
2081 if (signal_pending(current)) {
2082 rc = -ERESTARTSYS;
2083 break;
2084 }
2085
2086 /* get new irq counts */
2087 spin_lock_irqsave(&info->lock,flags);
2088 cnow = info->icount;
2089 set_current_state(TASK_INTERRUPTIBLE);
2090 spin_unlock_irqrestore(&info->lock,flags);
2091
2092 /* if no change, wait aborted for some reason */
2093 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2094 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2095 rc = -EIO;
2096 break;
2097 }
2098
2099 /* check for change in caller specified modem input */
2100 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2101 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2102 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2103 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2104 rc = 0;
2105 break;
2106 }
2107
2108 cprev = cnow;
2109 }
2110 remove_wait_queue(&info->status_event_wait_q, &wait);
2111 set_current_state(TASK_RUNNING);
2112 return rc;
2113}
2114
2115/* return the state of the serial control and status signals
2116 */
60b33c13 2117static int tiocmget(struct tty_struct *tty)
1da177e4
LT		 2118{
2119 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2120 unsigned int result;
2121 unsigned long flags;
2122
2123 spin_lock_irqsave(&info->lock,flags);
2124 get_signals(info);
2125 spin_unlock_irqrestore(&info->lock,flags);
2126
2127 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2128 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2129 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2130 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2131 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2132 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2133
2134 if (debug_level >= DEBUG_LEVEL_INFO)
2135 printk("%s(%d):%s tiocmget() value=%08X\n",
2136 __FILE__,__LINE__, info->device_name, result );
2137 return result;
2138}
2139
2140/* set modem control signals (DTR/RTS)
2141 */
20b9d177 2142static int tiocmset(struct tty_struct *tty,
1da177e4
LT		 2143 unsigned int set, unsigned int clear)
2144{
2145 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2146 unsigned long flags;
2147
2148 if (debug_level >= DEBUG_LEVEL_INFO)
2149 printk("%s(%d):%s tiocmset(%x,%x)\n",
2150 __FILE__,__LINE__,info->device_name, set, clear);
2151
2152 if (set & TIOCM_RTS)
2153 info->serial_signals |= SerialSignal_RTS;
2154 if (set & TIOCM_DTR)
2155 info->serial_signals |= SerialSignal_DTR;
2156 if (clear & TIOCM_RTS)
2157 info->serial_signals &= ~SerialSignal_RTS;
2158 if (clear & TIOCM_DTR)
2159 info->serial_signals &= ~SerialSignal_DTR;
2160
2161 spin_lock_irqsave(&info->lock,flags);
2162 set_signals(info);
2163 spin_unlock_irqrestore(&info->lock,flags);
2164
2165 return 0;
2166}
2167
2168/* Set or clear transmit break condition
2169 *
2170 * Arguments: tty pointer to tty instance data
2171 * break_state -1=set break condition, 0=clear
2172 */
9e98966c 2173static int mgslpc_break(struct tty_struct *tty, int break_state)
1da177e4
LT		 2174{
2175 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2176 unsigned long flags;
d12341f9 2177
1da177e4
LT		 2178 if (debug_level >= DEBUG_LEVEL_INFO)
2179 printk("%s(%d):mgslpc_break(%s,%d)\n",
2180 __FILE__,__LINE__, info->device_name, break_state);
d12341f9 2181
1da177e4 2182 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
9e98966c 2183 return -EINVAL;
1da177e4
LT		 2184
2185 spin_lock_irqsave(&info->lock,flags);
2186 if (break_state == -1)
2187 set_reg_bits(info, CHA+DAFO, BIT6);
d12341f9 2188 else
1da177e4
LT		 2189 clear_reg_bits(info, CHA+DAFO, BIT6);
2190 spin_unlock_irqrestore(&info->lock,flags);
9e98966c 2191 return 0;
1da177e4
LT		 2192}
2193
0587102c
AC		 2194static int mgslpc_get_icount(struct tty_struct *tty,
2195 struct serial_icounter_struct *icount)
2196{
2197 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2198 struct mgsl_icount cnow; /* kernel counter temps */
2199 unsigned long flags;
2200
2201 spin_lock_irqsave(&info->lock,flags);
2202 cnow = info->icount;
2203 spin_unlock_irqrestore(&info->lock,flags);
2204
2205 icount->cts = cnow.cts;
2206 icount->dsr = cnow.dsr;
2207 icount->rng = cnow.rng;
2208 icount->dcd = cnow.dcd;
2209 icount->rx = cnow.rx;
2210 icount->tx = cnow.tx;
2211 icount->frame = cnow.frame;
2212 icount->overrun = cnow.overrun;
2213 icount->parity = cnow.parity;
2214 icount->brk = cnow.brk;
2215 icount->buf_overrun = cnow.buf_overrun;
2216
2217 return 0;
2218}
2219
1da177e4 2220/* Service an IOCTL request
d12341f9 2221 *
1da177e4 2222 * Arguments:
d12341f9 2223 *
1da177e4 2224 * tty pointer to tty instance data
1da177e4
LT		 2225 * cmd IOCTL command code
2226 * arg command argument/context
d12341f9 2227 *
1da177e4
LT		 2228 * Return Value: 0 if success, otherwise error code
2229 */
751b3840 2230static int mgslpc_ioctl(struct tty_struct *tty,
1da177e4
LT		 2231 unsigned int cmd, unsigned long arg)
2232{
2233 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2234 void __user *argp = (void __user *)arg;
d12341f9 2235
1da177e4
LT		 2236 if (debug_level >= DEBUG_LEVEL_INFO)
2237 printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2238 info->device_name, cmd );
d12341f9 2239
1da177e4
LT		 2240 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
2241 return -ENODEV;
2242
2243 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
0587102c 2244 (cmd != TIOCMIWAIT)) {
1da177e4
LT		 2245 if (tty->flags & (1 << TTY_IO_ERROR))
2246 return -EIO;
2247 }
2248
1da177e4
LT		 2249 switch (cmd) {
2250 case MGSL_IOCGPARAMS:
2251 return get_params(info, argp);
2252 case MGSL_IOCSPARAMS:
eeb46134 2253 return set_params(info, argp, tty);
1da177e4
LT		 2254 case MGSL_IOCGTXIDLE:
2255 return get_txidle(info, argp);
2256 case MGSL_IOCSTXIDLE:
2257 return set_txidle(info, (int)arg);
2258 case MGSL_IOCGIF:
2259 return get_interface(info, argp);
2260 case MGSL_IOCSIF:
2261 return set_interface(info,(int)arg);
2262 case MGSL_IOCTXENABLE:
eeb46134 2263 return set_txenable(info,(int)arg, tty);
1da177e4
LT		 2264 case MGSL_IOCRXENABLE:
2265 return set_rxenable(info,(int)arg);
2266 case MGSL_IOCTXABORT:
2267 return tx_abort(info);
2268 case MGSL_IOCGSTATS:
2269 return get_stats(info, argp);
2270 case MGSL_IOCWAITEVENT:
2271 return wait_events(info, argp);
2272 case TIOCMIWAIT:
2273 return modem_input_wait(info,(int)arg);
1da177e4
LT		 2274 default:
2275 return -ENOIOCTLCMD;
2276 }
2277 return 0;
2278}
2279
2280/* Set new termios settings
d12341f9 2281 *
1da177e4 2282 * Arguments:
d12341f9 2283 *
1da177e4
LT		 2284 * tty pointer to tty structure
2285 * termios pointer to buffer to hold returned old termios
2286 */
606d099c 2287static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 2288{
2289 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2290 unsigned long flags;
d12341f9 2291
1da177e4
LT		 2292 if (debug_level >= DEBUG_LEVEL_INFO)
2293 printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
2294 tty->driver->name );
d12341f9 2295
1da177e4 2296 /* just return if nothing has changed */
373f5aed
AC		 2297 if ((tty->termios.c_cflag == old_termios->c_cflag)
2298 && (RELEVANT_IFLAG(tty->termios.c_iflag)
1da177e4
LT		 2299 == RELEVANT_IFLAG(old_termios->c_iflag)))
2300 return;
2301
eeb46134 2302 mgslpc_change_params(info, tty);
1da177e4
LT		 2303
2304 /* Handle transition to B0 status */
2305 if (old_termios->c_cflag & CBAUD &&
373f5aed 2306 !(tty->termios.c_cflag & CBAUD)) {
1da177e4
LT		 2307 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2308 spin_lock_irqsave(&info->lock,flags);
2309 set_signals(info);
2310 spin_unlock_irqrestore(&info->lock,flags);
2311 }
d12341f9 2312
1da177e4
LT		 2313 /* Handle transition away from B0 status */
2314 if (!(old_termios->c_cflag & CBAUD) &&
373f5aed 2315 tty->termios.c_cflag & CBAUD) {
1da177e4 2316 info->serial_signals |= SerialSignal_DTR;
373f5aed 2317 if (!(tty->termios.c_cflag & CRTSCTS) ||
1da177e4
LT		 2318 !test_bit(TTY_THROTTLED, &tty->flags)) {
2319 info->serial_signals |= SerialSignal_RTS;
2320 }
2321 spin_lock_irqsave(&info->lock,flags);
2322 set_signals(info);
2323 spin_unlock_irqrestore(&info->lock,flags);
2324 }
d12341f9 2325
1da177e4
LT		 2326 /* Handle turning off CRTSCTS */
2327 if (old_termios->c_cflag & CRTSCTS &&
373f5aed 2328 !(tty->termios.c_cflag & CRTSCTS)) {
1da177e4
LT		 2329 tty->hw_stopped = 0;
2330 tx_release(tty);
2331 }
2332}
2333
2334static void mgslpc_close(struct tty_struct *tty, struct file * filp)
2335{
2336 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2337 struct tty_port *port = &info->port;
1da177e4
LT		 2338
2339 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
2340 return;
d12341f9 2341
1da177e4
LT		 2342 if (debug_level >= DEBUG_LEVEL_INFO)
2343 printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
eeb46134 2344 __FILE__,__LINE__, info->device_name, port->count);
1da177e4 2345
eeb46134 2346 WARN_ON(!port->count);
d12341f9 2347
eeb46134 2348 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 2349 goto cleanup;
d12341f9 2350
eeb46134 2351 if (port->flags & ASYNC_INITIALIZED)
1da177e4
LT		 2352 mgslpc_wait_until_sent(tty, info->timeout);
2353
978e595f 2354 mgslpc_flush_buffer(tty);
1da177e4 2355
978e595f 2356 tty_ldisc_flush(tty);
eeb46134
AC		 2357 shutdown(info, tty);
2358
2359 tty_port_close_end(port, tty);
2360 tty_port_tty_set(port, NULL);
d12341f9 2361cleanup:
1da177e4
LT		 2362 if (debug_level >= DEBUG_LEVEL_INFO)
2363 printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
eeb46134 2364 tty->driver->name, port->count);
1da177e4
LT		 2365}
2366
2367/* Wait until the transmitter is empty.
2368 */
2369static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
2370{
2371 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2372 unsigned long orig_jiffies, char_time;
2373
2374 if (!info )
2375 return;
2376
2377 if (debug_level >= DEBUG_LEVEL_INFO)
2378 printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
2379 __FILE__,__LINE__, info->device_name );
d12341f9 2380
1da177e4
LT		 2381 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
2382 return;
2383
eeb46134 2384 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4 2385 goto exit;
d12341f9 2386
1da177e4 2387 orig_jiffies = jiffies;
d12341f9 2388
1da177e4
LT		 2389 /* Set check interval to 1/5 of estimated time to
2390 * send a character, and make it at least 1. The check
2391 * interval should also be less than the timeout.
2392 * Note: use tight timings here to satisfy the NIST-PCTS.
d12341f9
JG		 2393 */
2394
1da177e4
LT		 2395 if ( info->params.data_rate ) {
2396 char_time = info->timeout/(32 * 5);
2397 if (!char_time)
2398 char_time++;
2399 } else
2400 char_time = 1;
d12341f9 2401
1da177e4
LT		 2402 if (timeout)
2403 char_time = min_t(unsigned long, char_time, timeout);
d12341f9 2404
1da177e4
LT		 2405 if (info->params.mode == MGSL_MODE_HDLC) {
2406 while (info->tx_active) {
2407 msleep_interruptible(jiffies_to_msecs(char_time));
2408 if (signal_pending(current))
2409 break;
2410 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2411 break;
2412 }
2413 } else {
2414 while ((info->tx_count || info->tx_active) &&
2415 info->tx_enabled) {
2416 msleep_interruptible(jiffies_to_msecs(char_time));
2417 if (signal_pending(current))
2418 break;
2419 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2420 break;
2421 }
2422 }
d12341f9 2423
1da177e4
LT		 2424exit:
2425 if (debug_level >= DEBUG_LEVEL_INFO)
2426 printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
2427 __FILE__,__LINE__, info->device_name );
2428}
2429
2430/* Called by tty_hangup() when a hangup is signaled.
2431 * This is the same as closing all open files for the port.
2432 */
2433static void mgslpc_hangup(struct tty_struct *tty)
2434{
2435 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
d12341f9 2436
1da177e4
LT		 2437 if (debug_level >= DEBUG_LEVEL_INFO)
2438 printk("%s(%d):mgslpc_hangup(%s)\n",
2439 __FILE__,__LINE__, info->device_name );
d12341f9 2440
1da177e4
LT		 2441 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
2442 return;
2443
2444 mgslpc_flush_buffer(tty);
eeb46134
AC		 2445 shutdown(info, tty);
2446 tty_port_hangup(&info->port);
1da177e4
LT		 2447}
2448
eeb46134 2449static int carrier_raised(struct tty_port *port)
1da177e4 2450{
eeb46134
AC		 2451 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2452 unsigned long flags;
d12341f9 2453
eeb46134
AC		 2454 spin_lock_irqsave(&info->lock,flags);
2455 get_signals(info);
2456 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 2457
eeb46134
AC		 2458 if (info->serial_signals & SerialSignal_DCD)
2459 return 1;
2460 return 0;
2461}
d12341f9 2462
fcc8ac18 2463static void dtr_rts(struct tty_port *port, int onoff)
eeb46134
AC		 2464{
2465 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2466 unsigned long flags;
d12341f9 2467
eeb46134 2468 spin_lock_irqsave(&info->lock,flags);
fcc8ac18
AC		 2469 if (onoff)
2470 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2471 else
2472 info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
eeb46134
AC		 2473 set_signals(info);
2474 spin_unlock_irqrestore(&info->lock,flags);
1da177e4
LT		 2475}
2476
eeb46134 2477
1da177e4
LT		 2478static int mgslpc_open(struct tty_struct *tty, struct file * filp)
2479{
2480 MGSLPC_INFO *info;
eeb46134 2481 struct tty_port *port;
1da177e4
LT		 2482 int retval, line;
2483 unsigned long flags;
2484
d12341f9 2485 /* verify range of specified line number */
1da177e4 2486 line = tty->index;
410235fd 2487 if (line >= mgslpc_device_count) {
1da177e4
LT		 2488 printk("%s(%d):mgslpc_open with invalid line #%d.\n",
2489 __FILE__,__LINE__,line);
2490 return -ENODEV;
2491 }
2492
2493 /* find the info structure for the specified line */
2494 info = mgslpc_device_list;
2495 while(info && info->line != line)
2496 info = info->next_device;
2497 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
2498 return -ENODEV;
d12341f9 2499
eeb46134 2500 port = &info->port;
1da177e4 2501 tty->driver_data = info;
eeb46134 2502 tty_port_tty_set(port, tty);
d12341f9 2503
1da177e4
LT		 2504 if (debug_level >= DEBUG_LEVEL_INFO)
2505 printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
eeb46134 2506 __FILE__,__LINE__,tty->driver->name, port->count);
1da177e4
LT		 2507
2508 /* If port is closing, signal caller to try again */
eeb46134
AC		 2509 if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
2510 if (port->flags & ASYNC_CLOSING)
2511 interruptible_sleep_on(&port->close_wait);
2512 retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 2513 -EAGAIN : -ERESTARTSYS);
2514 goto cleanup;
2515 }
d12341f9 2516
d6c53c0e 2517 port->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 2518
2519 spin_lock_irqsave(&info->netlock, flags);
2520 if (info->netcount) {
2521 retval = -EBUSY;
2522 spin_unlock_irqrestore(&info->netlock, flags);
2523 goto cleanup;
2524 }
eeb46134
AC		 2525 spin_lock(&port->lock);
2526 port->count++;
2527 spin_unlock(&port->lock);
1da177e4
LT		 2528 spin_unlock_irqrestore(&info->netlock, flags);
2529
eeb46134 2530 if (port->count == 1) {
1da177e4 2531 /* 1st open on this device, init hardware */
eeb46134 2532 retval = startup(info, tty);
1da177e4
LT		 2533 if (retval < 0)
2534 goto cleanup;
2535 }
2536
eeb46134 2537 retval = tty_port_block_til_ready(&info->port, tty, filp);
1da177e4
LT		 2538 if (retval) {
2539 if (debug_level >= DEBUG_LEVEL_INFO)
2540 printk("%s(%d):block_til_ready(%s) returned %d\n",
2541 __FILE__,__LINE__, info->device_name, retval);
2542 goto cleanup;
2543 }
2544
2545 if (debug_level >= DEBUG_LEVEL_INFO)
2546 printk("%s(%d):mgslpc_open(%s) success\n",
2547 __FILE__,__LINE__, info->device_name);
2548 retval = 0;
d12341f9
JG		 2549
2550cleanup:
1da177e4
LT		 2551 return retval;
2552}
2553
2554/*
2555 * /proc fs routines....
2556 */
2557
87687144 2558static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
1da177e4
LT		 2559{
2560 char stat_buf[30];
1da177e4
LT		 2561 unsigned long flags;
2562
87687144 2563 seq_printf(m, "%s:io:%04X irq:%d",
1da177e4
LT		 2564 info->device_name, info->io_base, info->irq_level);
2565
2566 /* output current serial signal states */
2567 spin_lock_irqsave(&info->lock,flags);
2568 get_signals(info);
2569 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 2570
1da177e4
LT		 2571 stat_buf[0] = 0;
2572 stat_buf[1] = 0;
2573 if (info->serial_signals & SerialSignal_RTS)
2574 strcat(stat_buf, "|RTS");
2575 if (info->serial_signals & SerialSignal_CTS)
2576 strcat(stat_buf, "|CTS");
2577 if (info->serial_signals & SerialSignal_DTR)
2578 strcat(stat_buf, "|DTR");
2579 if (info->serial_signals & SerialSignal_DSR)
2580 strcat(stat_buf, "|DSR");
2581 if (info->serial_signals & SerialSignal_DCD)
2582 strcat(stat_buf, "|CD");
2583 if (info->serial_signals & SerialSignal_RI)
2584 strcat(stat_buf, "|RI");
2585
2586 if (info->params.mode == MGSL_MODE_HDLC) {
87687144 2587 seq_printf(m, " HDLC txok:%d rxok:%d",
1da177e4
LT		 2588 info->icount.txok, info->icount.rxok);
2589 if (info->icount.txunder)
87687144 2590 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 2591 if (info->icount.txabort)
87687144 2592 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 2593 if (info->icount.rxshort)
87687144 2594 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 2595 if (info->icount.rxlong)
87687144 2596 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 2597 if (info->icount.rxover)
87687144 2598 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 2599 if (info->icount.rxcrc)
87687144 2600 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1da177e4 2601 } else {
87687144 2602 seq_printf(m, " ASYNC tx:%d rx:%d",
1da177e4
LT		 2603 info->icount.tx, info->icount.rx);
2604 if (info->icount.frame)
87687144 2605 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 2606 if (info->icount.parity)
87687144 2607 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 2608 if (info->icount.brk)
87687144 2609 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 2610 if (info->icount.overrun)
87687144 2611 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4 2612 }
d12341f9 2613
1da177e4 2614 /* Append serial signal status to end */
87687144 2615 seq_printf(m, " %s\n", stat_buf+1);
d12341f9 2616
87687144 2617 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 2618 info->tx_active,info->bh_requested,info->bh_running,
2619 info->pending_bh);
1da177e4
LT		 2620}
2621
2622/* Called to print information about devices
2623 */
87687144 2624static int mgslpc_proc_show(struct seq_file *m, void *v)
1da177e4 2625{
1da177e4 2626 MGSLPC_INFO *info;
d12341f9 2627
87687144 2628 seq_printf(m, "synclink driver:%s\n", driver_version);
d12341f9 2629
1da177e4
LT		 2630 info = mgslpc_device_list;
2631 while( info ) {
87687144 2632 line_info(m, info);
1da177e4
LT		 2633 info = info->next_device;
2634 }
87687144
AD		 2635 return 0;
2636}
1da177e4 2637
87687144
AD		 2638static int mgslpc_proc_open(struct inode *inode, struct file *file)
2639{
2640 return single_open(file, mgslpc_proc_show, NULL);
1da177e4
LT		 2641}
2642
87687144
AD		 2643static const struct file_operations mgslpc_proc_fops = {
2644 .owner = THIS_MODULE,
2645 .open = mgslpc_proc_open,
2646 .read = seq_read,
2647 .llseek = seq_lseek,
2648 .release = single_release,
2649};
2650
cdaad343 2651static int rx_alloc_buffers(MGSLPC_INFO *info)
1da177e4
LT		 2652{
2653 /* each buffer has header and data */
2654 info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
2655
2656 /* calculate total allocation size for 8 buffers */
2657 info->rx_buf_total_size = info->rx_buf_size * 8;
2658
2659 /* limit total allocated memory */
2660 if (info->rx_buf_total_size > 0x10000)
2661 info->rx_buf_total_size = 0x10000;
2662
2663 /* calculate number of buffers */
2664 info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
2665
2666 info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
2667 if (info->rx_buf == NULL)
2668 return -ENOMEM;
2669
a6b68a69
PF		 2670 /* unused flag buffer to satisfy receive_buf calling interface */
2671 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
2672 if (!info->flag_buf) {
2673 kfree(info->rx_buf);
2674 info->rx_buf = NULL;
2675 return -ENOMEM;
2676 }
2677
1da177e4
LT		 2678 rx_reset_buffers(info);
2679 return 0;
2680}
2681
cdaad343 2682static void rx_free_buffers(MGSLPC_INFO *info)
1da177e4 2683{
735d5661 2684 kfree(info->rx_buf);
1da177e4 2685 info->rx_buf = NULL;
a6b68a69
PF		 2686 kfree(info->flag_buf);
2687 info->flag_buf = NULL;
1da177e4
LT		 2688}
2689
cdaad343 2690static int claim_resources(MGSLPC_INFO *info)
1da177e4
LT		 2691{
2692 if (rx_alloc_buffers(info) < 0 ) {
25985edc 2693 printk( "Can't allocate rx buffer %s\n", info->device_name);
1da177e4
LT		 2694 release_resources(info);
2695 return -ENODEV;
d12341f9 2696 }
1da177e4
LT		 2697 return 0;
2698}
2699
cdaad343 2700static void release_resources(MGSLPC_INFO *info)
1da177e4
LT		 2701{
2702 if (debug_level >= DEBUG_LEVEL_INFO)
2703 printk("release_resources(%s)\n", info->device_name);
2704 rx_free_buffers(info);
2705}
2706
2707/* Add the specified device instance data structure to the
2708 * global linked list of devices and increment the device count.
d12341f9 2709 *
1da177e4
LT		 2710 * Arguments: info pointer to device instance data
2711 */
cdaad343 2712static void mgslpc_add_device(MGSLPC_INFO *info)
1da177e4
LT		 2713{
2714 info->next_device = NULL;
2715 info->line = mgslpc_device_count;
2716 sprintf(info->device_name,"ttySLP%d",info->line);
d12341f9 2717
1da177e4
LT		 2718 if (info->line < MAX_DEVICE_COUNT) {
2719 if (maxframe[info->line])
2720 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 2721 }
2722
2723 mgslpc_device_count++;
d12341f9 2724
1da177e4
LT		 2725 if (!mgslpc_device_list)
2726 mgslpc_device_list = info;
d12341f9 2727 else {
1da177e4
LT		 2728 MGSLPC_INFO *current_dev = mgslpc_device_list;
2729 while( current_dev->next_device )
2730 current_dev = current_dev->next_device;
2731 current_dev->next_device = info;
2732 }
d12341f9 2733
1da177e4
LT		 2734 if (info->max_frame_size < 4096)
2735 info->max_frame_size = 4096;
2736 else if (info->max_frame_size > 65535)
2737 info->max_frame_size = 65535;
d12341f9 2738
1da177e4
LT		 2739 printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
2740 info->device_name, info->io_base, info->irq_level);
2741
af69c7f9 2742#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2743 hdlcdev_init(info);
2744#endif
16a1065f 2745 tty_port_register_device(&info->port, serial_driver, info->line,
a33ba827 2746 &info->p_dev->dev);
1da177e4
LT		 2747}
2748
cdaad343 2749static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
1da177e4
LT		 2750{
2751 MGSLPC_INFO *info = mgslpc_device_list;
2752 MGSLPC_INFO *last = NULL;
2753
2754 while(info) {
2755 if (info == remove_info) {
2756 if (last)
2757 last->next_device = info->next_device;
2758 else
2759 mgslpc_device_list = info->next_device;
16a1065f 2760 tty_unregister_device(serial_driver, info->line);
af69c7f9 2761#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2762 hdlcdev_exit(info);
2763#endif
2764 release_resources(info);
191c5f10 2765 tty_port_destroy(&info->port);
1da177e4
LT		 2766 kfree(info);
2767 mgslpc_device_count--;
2768 return;
2769 }
2770 last = info;
2771 info = info->next_device;
2772 }
2773}
2774
25f8f54f 2775static const struct pcmcia_device_id mgslpc_ids[] = {
4af48c8c
DB		 2776 PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
2777 PCMCIA_DEVICE_NULL
2778};
2779MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
2780
1da177e4
LT		 2781static struct pcmcia_driver mgslpc_driver = {
2782 .owner = THIS_MODULE,
2e9b981a 2783 .name = "synclink_cs",
15b99ac1 2784 .probe = mgslpc_probe,
cc3b4866 2785 .remove = mgslpc_detach,
4af48c8c 2786 .id_table = mgslpc_ids,
98e4c28b
DB		 2787 .suspend = mgslpc_suspend,
2788 .resume = mgslpc_resume,
1da177e4
LT		 2789};
2790
b68e31d0 2791static const struct tty_operations mgslpc_ops = {
1da177e4
LT		 2792 .open = mgslpc_open,
2793 .close = mgslpc_close,
2794 .write = mgslpc_write,
2795 .put_char = mgslpc_put_char,
2796 .flush_chars = mgslpc_flush_chars,
2797 .write_room = mgslpc_write_room,
2798 .chars_in_buffer = mgslpc_chars_in_buffer,
2799 .flush_buffer = mgslpc_flush_buffer,
2800 .ioctl = mgslpc_ioctl,
2801 .throttle = mgslpc_throttle,
2802 .unthrottle = mgslpc_unthrottle,
2803 .send_xchar = mgslpc_send_xchar,
2804 .break_ctl = mgslpc_break,
2805 .wait_until_sent = mgslpc_wait_until_sent,
1da177e4
LT		 2806 .set_termios = mgslpc_set_termios,
2807 .stop = tx_pause,
2808 .start = tx_release,
2809 .hangup = mgslpc_hangup,
2810 .tiocmget = tiocmget,
2811 .tiocmset = tiocmset,
dc98d965 2812 .get_icount = mgslpc_get_icount,
87687144 2813 .proc_fops = &mgslpc_proc_fops,
1da177e4
LT		 2814};
2815
1da177e4 2816static int __init synclink_cs_init(void)
1da177e4
LT		 2817{
2818 int rc;
2819
cc93441e
JS		 2820 if (break_on_load) {
2821 mgslpc_get_text_ptr();
2822 BREAKPOINT();
1da177e4
LT		 2823 }
2824
cc93441e
JS		 2825 serial_driver = tty_alloc_driver(MAX_DEVICE_COUNT,
2826 TTY_DRIVER_REAL_RAW |
2827 TTY_DRIVER_DYNAMIC_DEV);
c3a6344a
DC		 2828 if (IS_ERR(serial_driver)) {
2829 rc = PTR_ERR(serial_driver);
cc93441e
JS		 2830 goto err;
2831 }
1da177e4 2832
cc93441e
JS		 2833 /* Initialize the tty_driver structure */
2834 serial_driver->driver_name = "synclink_cs";
2835 serial_driver->name = "ttySLP";
2836 serial_driver->major = ttymajor;
2837 serial_driver->minor_start = 64;
2838 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
2839 serial_driver->subtype = SERIAL_TYPE_NORMAL;
2840 serial_driver->init_termios = tty_std_termios;
2841 serial_driver->init_termios.c_cflag =
2842 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2843 tty_set_operations(serial_driver, &mgslpc_ops);
1da177e4 2844
cc93441e
JS		 2845 rc = tty_register_driver(serial_driver);
2846 if (rc < 0) {
2847 printk(KERN_ERR "%s(%d):Couldn't register serial driver\n",
2848 __FILE__, __LINE__);
2849 goto err_put_tty;
2850 }
1da177e4 2851
16a1065f
JS		 2852 rc = pcmcia_register_driver(&mgslpc_driver);
2853 if (rc < 0)
2854 goto err_unreg_tty;
d12341f9 2855
cc93441e
JS		 2856 printk(KERN_INFO "%s %s, tty major#%d\n", driver_name, driver_version,
2857 serial_driver->major);
d12341f9 2858
737586fe 2859 return 0;
16a1065f
JS		 2860err_unreg_tty:
2861 tty_unregister_driver(serial_driver);
737586fe
JS		 2862err_put_tty:
2863 put_tty_driver(serial_driver);
16a1065f 2864err:
737586fe 2865 return rc;
1da177e4
LT		 2866}
2867
d12341f9 2868static void __exit synclink_cs_exit(void)
1da177e4 2869{
16a1065f 2870 pcmcia_unregister_driver(&mgslpc_driver);
737586fe
JS		 2871 tty_unregister_driver(serial_driver);
2872 put_tty_driver(serial_driver);
1da177e4
LT		 2873}
2874
2875module_init(synclink_cs_init);
2876module_exit(synclink_cs_exit);
2877
2878static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
2879{
2880 unsigned int M, N;
2881 unsigned char val;
2882
d12341f9
JG		 2883 /* note:standard BRG mode is broken in V3.2 chip
2884 * so enhanced mode is always used
1da177e4
LT		 2885 */
2886
2887 if (rate) {
2888 N = 3686400 / rate;
2889 if (!N)
2890 N = 1;
2891 N >>= 1;
2892 for (M = 1; N > 64 && M < 16; M++)
2893 N >>= 1;
2894 N--;
2895
2896 /* BGR[5..0] = N
2897 * BGR[9..6] = M
2898 * BGR[7..0] contained in BGR register
2899 * BGR[9..8] contained in CCR2[7..6]
2900 * divisor = (N+1)*2^M
2901 *
2902 * Note: M *must* not be zero (causes asymetric duty cycle)
d12341f9 2903 */
1da177e4
LT		 2904 write_reg(info, (unsigned char) (channel + BGR),
2905 (unsigned char) ((M << 6) + N));
2906 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
2907 val |= ((M << 4) & 0xc0);
2908 write_reg(info, (unsigned char) (channel + CCR2), val);
2909 }
2910}
2911
2912/* Enabled the AUX clock output at the specified frequency.
2913 */
2914static void enable_auxclk(MGSLPC_INFO *info)
2915{
2916 unsigned char val;
d12341f9 2917
1da177e4
LT		 2918 /* MODE
2919 *
2920 * 07..06 MDS[1..0] 10 = transparent HDLC mode
2921 * 05 ADM Address Mode, 0 = no addr recognition
2922 * 04 TMD Timer Mode, 0 = external
2923 * 03 RAC Receiver Active, 0 = inactive
2924 * 02 RTS 0=RTS active during xmit, 1=RTS always active
2925 * 01 TRS Timer Resolution, 1=512
2926 * 00 TLP Test Loop, 0 = no loop
2927 *
2928 * 1000 0010
d12341f9 2929 */
1da177e4 2930 val = 0x82;
d12341f9
JG		 2931
2932 /* channel B RTS is used to enable AUXCLK driver on SP505 */
1da177e4
LT		 2933 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2934 val |= BIT2;
2935 write_reg(info, CHB + MODE, val);
d12341f9 2936
1da177e4
LT		 2937 /* CCR0
2938 *
2939 * 07 PU Power Up, 1=active, 0=power down
2940 * 06 MCE Master Clock Enable, 1=enabled
2941 * 05 Reserved, 0
2942 * 04..02 SC[2..0] Encoding
2943 * 01..00 SM[1..0] Serial Mode, 00=HDLC
2944 *
2945 * 11000000
d12341f9 2946 */
1da177e4 2947 write_reg(info, CHB + CCR0, 0xc0);
d12341f9 2948
1da177e4
LT		 2949 /* CCR1
2950 *
2951 * 07 SFLG Shared Flag, 0 = disable shared flags
2952 * 06 GALP Go Active On Loop, 0 = not used
2953 * 05 GLP Go On Loop, 0 = not used
2954 * 04 ODS Output Driver Select, 1=TxD is push-pull output
2955 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
2956 * 02..00 CM[2..0] Clock Mode
2957 *
2958 * 0001 0111
d12341f9 2959 */
1da177e4 2960 write_reg(info, CHB + CCR1, 0x17);
d12341f9 2961
1da177e4
LT		 2962 /* CCR2 (Channel B)
2963 *
2964 * 07..06 BGR[9..8] Baud rate bits 9..8
2965 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
2966 * 04 SSEL Clock source select, 1=submode b
2967 * 03 TOE 0=TxCLK is input, 1=TxCLK is output
2968 * 02 RWX Read/Write Exchange 0=disabled
2969 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
2970 * 00 DIV, data inversion 0=disabled, 1=enabled
2971 *
2972 * 0011 1000
d12341f9 2973 */
1da177e4
LT		 2974 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2975 write_reg(info, CHB + CCR2, 0x38);
2976 else
2977 write_reg(info, CHB + CCR2, 0x30);
d12341f9 2978
1da177e4
LT		 2979 /* CCR4
2980 *
2981 * 07 MCK4 Master Clock Divide by 4, 1=enabled
2982 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
2983 * 05 TST1 Test Pin, 0=normal operation
2984 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
2985 * 03..02 Reserved, must be 0
2986 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
2987 *
2988 * 0101 0000
d12341f9 2989 */
1da177e4 2990 write_reg(info, CHB + CCR4, 0x50);
d12341f9 2991
1da177e4
LT		 2992 /* if auxclk not enabled, set internal BRG so
2993 * CTS transitions can be detected (requires TxC)
d12341f9 2994 */
1da177e4
LT		 2995 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2996 mgslpc_set_rate(info, CHB, info->params.clock_speed);
2997 else
2998 mgslpc_set_rate(info, CHB, 921600);
2999}
3000
d12341f9 3001static void loopback_enable(MGSLPC_INFO *info)
1da177e4
LT		 3002{
3003 unsigned char val;
d12341f9
JG		 3004
3005 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
1da177e4
LT		 3006 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
3007 write_reg(info, CHA + CCR1, val);
d12341f9
JG		 3008
3009 /* CCR2:04 SSEL Clock source select, 1=submode b */
1da177e4
LT		 3010 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
3011 write_reg(info, CHA + CCR2, val);
d12341f9
JG		 3012
3013 /* set LinkSpeed if available, otherwise default to 2Mbps */
1da177e4
LT		 3014 if (info->params.clock_speed)
3015 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3016 else
3017 mgslpc_set_rate(info, CHA, 1843200);
d12341f9
JG		 3018
3019 /* MODE:00 TLP Test Loop, 1=loopback enabled */
1da177e4
LT		 3020 val = read_reg(info, CHA + MODE) | BIT0;
3021 write_reg(info, CHA + MODE, val);
3022}
3023
cdaad343 3024static void hdlc_mode(MGSLPC_INFO *info)
1da177e4
LT		 3025{
3026 unsigned char val;
3027 unsigned char clkmode, clksubmode;
3028
d12341f9 3029 /* disable all interrupts */
1da177e4
LT		 3030 irq_disable(info, CHA, 0xffff);
3031 irq_disable(info, CHB, 0xffff);
3032 port_irq_disable(info, 0xff);
d12341f9
JG		 3033
3034 /* assume clock mode 0a, rcv=RxC xmt=TxC */
1da177e4
LT		 3035 clkmode = clksubmode = 0;
3036 if (info->params.flags & HDLC_FLAG_RXC_DPLL
3037 && info->params.flags & HDLC_FLAG_TXC_DPLL) {
d12341f9 3038 /* clock mode 7a, rcv = DPLL, xmt = DPLL */
1da177e4
LT		 3039 clkmode = 7;
3040 } else if (info->params.flags & HDLC_FLAG_RXC_BRG
3041 && info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3042 /* clock mode 7b, rcv = BRG, xmt = BRG */
1da177e4
LT		 3043 clkmode = 7;
3044 clksubmode = 1;
3045 } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
3046 if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3047 /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
1da177e4
LT		 3048 clkmode = 6;
3049 clksubmode = 1;
3050 } else {
d12341f9 3051 /* clock mode 6a, rcv = DPLL, xmt = TxC */
1da177e4
LT		 3052 clkmode = 6;
3053 }
3054 } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3055 /* clock mode 0b, rcv = RxC, xmt = BRG */
1da177e4
LT		 3056 clksubmode = 1;
3057 }
d12341f9 3058
1da177e4
LT		 3059 /* MODE
3060 *
3061 * 07..06 MDS[1..0] 10 = transparent HDLC mode
3062 * 05 ADM Address Mode, 0 = no addr recognition
3063 * 04 TMD Timer Mode, 0 = external
3064 * 03 RAC Receiver Active, 0 = inactive
3065 * 02 RTS 0=RTS active during xmit, 1=RTS always active
3066 * 01 TRS Timer Resolution, 1=512
3067 * 00 TLP Test Loop, 0 = no loop
3068 *
3069 * 1000 0010
d12341f9 3070 */
1da177e4
LT		 3071 val = 0x82;
3072 if (info->params.loopback)
3073 val |= BIT0;
d12341f9
JG		 3074
3075 /* preserve RTS state */
1da177e4
LT		 3076 if (info->serial_signals & SerialSignal_RTS)
3077 val |= BIT2;
3078 write_reg(info, CHA + MODE, val);
d12341f9 3079
1da177e4
LT		 3080 /* CCR0
3081 *
3082 * 07 PU Power Up, 1=active, 0=power down
3083 * 06 MCE Master Clock Enable, 1=enabled
3084 * 05 Reserved, 0
3085 * 04..02 SC[2..0] Encoding
3086 * 01..00 SM[1..0] Serial Mode, 00=HDLC
3087 *
3088 * 11000000
d12341f9 3089 */
1da177e4
LT		 3090 val = 0xc0;
3091 switch (info->params.encoding)
3092 {
3093 case HDLC_ENCODING_NRZI:
3094 val |= BIT3;
3095 break;
3096 case HDLC_ENCODING_BIPHASE_SPACE:
3097 val |= BIT4;
3098 break; // FM0
3099 case HDLC_ENCODING_BIPHASE_MARK:
3100 val |= BIT4 + BIT2;
3101 break; // FM1
3102 case HDLC_ENCODING_BIPHASE_LEVEL:
3103 val |= BIT4 + BIT3;
3104 break; // Manchester
3105 }
3106 write_reg(info, CHA + CCR0, val);
d12341f9 3107
1da177e4
LT		 3108 /* CCR1
3109 *
3110 * 07 SFLG Shared Flag, 0 = disable shared flags
3111 * 06 GALP Go Active On Loop, 0 = not used
3112 * 05 GLP Go On Loop, 0 = not used
3113 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3114 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
3115 * 02..00 CM[2..0] Clock Mode
3116 *
3117 * 0001 0000
d12341f9 3118 */
1da177e4
LT		 3119 val = 0x10 + clkmode;
3120 write_reg(info, CHA + CCR1, val);
d12341f9 3121
1da177e4
LT		 3122 /* CCR2
3123 *
3124 * 07..06 BGR[9..8] Baud rate bits 9..8
3125 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3126 * 04 SSEL Clock source select, 1=submode b
3127 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3128 * 02 RWX Read/Write Exchange 0=disabled
3129 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3130 * 00 DIV, data inversion 0=disabled, 1=enabled
3131 *
3132 * 0000 0000
d12341f9 3133 */
1da177e4
LT		 3134 val = 0x00;
3135 if (clkmode == 2 || clkmode == 3 || clkmode == 6
3136 || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
3137 val |= BIT5;
3138 if (clksubmode)
3139 val |= BIT4;
3140 if (info->params.crc_type == HDLC_CRC_32_CCITT)
3141 val |= BIT1;
3142 if (info->params.encoding == HDLC_ENCODING_NRZB)
3143 val |= BIT0;
3144 write_reg(info, CHA + CCR2, val);
d12341f9 3145
1da177e4
LT		 3146 /* CCR3
3147 *
3148 * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
3149 * 05 EPT Enable preamble transmission, 1=enabled
3150 * 04 RADD Receive address pushed to FIFO, 0=disabled
3151 * 03 CRL CRC Reset Level, 0=FFFF
3152 * 02 RCRC Rx CRC 0=On 1=Off
3153 * 01 TCRC Tx CRC 0=On 1=Off
3154 * 00 PSD DPLL Phase Shift Disable
3155 *
3156 * 0000 0000
d12341f9 3157 */
1da177e4
LT		 3158 val = 0x00;
3159 if (info->params.crc_type == HDLC_CRC_NONE)
3160 val |= BIT2 + BIT1;
3161 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3162 val |= BIT5;
3163 switch (info->params.preamble_length)
3164 {
3165 case HDLC_PREAMBLE_LENGTH_16BITS:
3166 val |= BIT6;
3167 break;
3168 case HDLC_PREAMBLE_LENGTH_32BITS:
3169 val |= BIT6;
3170 break;
3171 case HDLC_PREAMBLE_LENGTH_64BITS:
3172 val |= BIT7 + BIT6;
3173 break;
3174 }
3175 write_reg(info, CHA + CCR3, val);
d12341f9
JG		 3176
3177 /* PRE - Preamble pattern */
1da177e4
LT		 3178 val = 0;
3179 switch (info->params.preamble)
3180 {
3181 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3182 case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
3183 case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
3184 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3185 }
3186 write_reg(info, CHA + PRE, val);
d12341f9 3187
1da177e4
LT		 3188 /* CCR4
3189 *
3190 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3191 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3192 * 05 TST1 Test Pin, 0=normal operation
3193 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3194 * 03..02 Reserved, must be 0
3195 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3196 *
3197 * 0101 0000
d12341f9 3198 */
1da177e4
LT		 3199 val = 0x50;
3200 write_reg(info, CHA + CCR4, val);
3201 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3202 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
3203 else
3204 mgslpc_set_rate(info, CHA, info->params.clock_speed);
d12341f9 3205
1da177e4
LT		 3206 /* RLCR Receive length check register
3207 *
3208 * 7 1=enable receive length check
3209 * 6..0 Max frame length = (RL + 1) * 32
d12341f9 3210 */
1da177e4 3211 write_reg(info, CHA + RLCR, 0);
d12341f9 3212
1da177e4
LT		 3213 /* XBCH Transmit Byte Count High
3214 *
3215 * 07 DMA mode, 0 = interrupt driven
3216 * 06 NRM, 0=ABM (ignored)
3217 * 05 CAS Carrier Auto Start
3218 * 04 XC Transmit Continuously (ignored)
3219 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3220 *
3221 * 0000 0000
d12341f9 3222 */
1da177e4
LT		 3223 val = 0x00;
3224 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3225 val |= BIT5;
3226 write_reg(info, CHA + XBCH, val);
3227 enable_auxclk(info);
3228 if (info->params.loopback || info->testing_irq)
3229 loopback_enable(info);
3230 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3231 {
3232 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3233 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3234 set_reg_bits(info, CHA + PVR, BIT3);
3235 } else
3236 clear_reg_bits(info, CHA + PVR, BIT3);
3237
3238 irq_enable(info, CHA,
3239 IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
3240 IRQ_UNDERRUN + IRQ_TXFIFO);
3241 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3242 wait_command_complete(info, CHA);
3243 read_reg16(info, CHA + ISR); /* clear pending IRQs */
d12341f9 3244
1da177e4
LT		 3245 /* Master clock mode enabled above to allow reset commands
3246 * to complete even if no data clocks are present.
3247 *
3248 * Disable master clock mode for normal communications because
3249 * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
3250 * IRQ when in master clock mode.
3251 *
3252 * Leave master clock mode enabled for IRQ test because the
3253 * timer IRQ used by the test can only happen in master clock mode.
d12341f9 3254 */
1da177e4
LT		 3255 if (!info->testing_irq)
3256 clear_reg_bits(info, CHA + CCR0, BIT6);
3257
3258 tx_set_idle(info);
3259
3260 tx_stop(info);
3261 rx_stop(info);
3262}
3263
cdaad343 3264static void rx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3265{
3266 if (debug_level >= DEBUG_LEVEL_ISR)
3267 printk("%s(%d):rx_stop(%s)\n",
3268 __FILE__,__LINE__, info->device_name );
d12341f9
JG		 3269
3270 /* MODE:03 RAC Receiver Active, 0=inactive */
1da177e4
LT		 3271 clear_reg_bits(info, CHA + MODE, BIT3);
3272
0fab6de0
JP		 3273 info->rx_enabled = false;
3274 info->rx_overflow = false;
1da177e4
LT		 3275}
3276
cdaad343 3277static void rx_start(MGSLPC_INFO *info)
1da177e4
LT		 3278{
3279 if (debug_level >= DEBUG_LEVEL_ISR)
3280 printk("%s(%d):rx_start(%s)\n",
3281 __FILE__,__LINE__, info->device_name );
3282
3283 rx_reset_buffers(info);
0fab6de0
JP		 3284 info->rx_enabled = false;
3285 info->rx_overflow = false;
1da177e4 3286
d12341f9 3287 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3288 set_reg_bits(info, CHA + MODE, BIT3);
3289
0fab6de0 3290 info->rx_enabled = true;
1da177e4
LT		 3291}
3292
eeb46134 3293static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3294{
3295 if (debug_level >= DEBUG_LEVEL_ISR)
3296 printk("%s(%d):tx_start(%s)\n",
3297 __FILE__,__LINE__, info->device_name );
d12341f9 3298
1da177e4
LT		 3299 if (info->tx_count) {
3300 /* If auto RTS enabled and RTS is inactive, then assert */
3301 /* RTS and set a flag indicating that the driver should */
3302 /* negate RTS when the transmission completes. */
0fab6de0 3303 info->drop_rts_on_tx_done = false;
1da177e4
LT		 3304
3305 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3306 get_signals(info);
3307 if (!(info->serial_signals & SerialSignal_RTS)) {
3308 info->serial_signals |= SerialSignal_RTS;
3309 set_signals(info);
0fab6de0 3310 info->drop_rts_on_tx_done = true;
1da177e4
LT		 3311 }
3312 }
3313
3314 if (info->params.mode == MGSL_MODE_ASYNC) {
3315 if (!info->tx_active) {
0fab6de0 3316 info->tx_active = true;
eeb46134 3317 tx_ready(info, tty);
1da177e4
LT		 3318 }
3319 } else {
0fab6de0 3320 info->tx_active = true;
eeb46134 3321 tx_ready(info, tty);
40565f19
JS		 3322 mod_timer(&info->tx_timer, jiffies +
3323 msecs_to_jiffies(5000));
1da177e4
LT		 3324 }
3325 }
3326
3327 if (!info->tx_enabled)
0fab6de0 3328 info->tx_enabled = true;
1da177e4
LT		 3329}
3330
cdaad343 3331static void tx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3332{
3333 if (debug_level >= DEBUG_LEVEL_ISR)
3334 printk("%s(%d):tx_stop(%s)\n",
3335 __FILE__,__LINE__, info->device_name );
d12341f9
JG		 3336
3337 del_timer(&info->tx_timer);
1da177e4 3338
0fab6de0
JP		 3339 info->tx_enabled = false;
3340 info->tx_active = false;
1da177e4
LT		 3341}
3342
3343/* Reset the adapter to a known state and prepare it for further use.
3344 */
cdaad343 3345static void reset_device(MGSLPC_INFO *info)
1da177e4 3346{
d12341f9 3347 /* power up both channels (set BIT7) */
1da177e4
LT		 3348 write_reg(info, CHA + CCR0, 0x80);
3349 write_reg(info, CHB + CCR0, 0x80);
3350 write_reg(info, CHA + MODE, 0);
3351 write_reg(info, CHB + MODE, 0);
d12341f9
JG		 3352
3353 /* disable all interrupts */
1da177e4
LT		 3354 irq_disable(info, CHA, 0xffff);
3355 irq_disable(info, CHB, 0xffff);
3356 port_irq_disable(info, 0xff);
d12341f9 3357
1da177e4
LT		 3358 /* PCR Port Configuration Register
3359 *
3360 * 07..04 DEC[3..0] Serial I/F select outputs
3361 * 03 output, 1=AUTO CTS control enabled
3362 * 02 RI Ring Indicator input 0=active
3363 * 01 DSR input 0=active
3364 * 00 DTR output 0=active
3365 *
3366 * 0000 0110
d12341f9 3367 */
1da177e4 3368 write_reg(info, PCR, 0x06);
d12341f9 3369
1da177e4
LT		 3370 /* PVR Port Value Register
3371 *
3372 * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
3373 * 03 AUTO CTS output 1=enabled
3374 * 02 RI Ring Indicator input
3375 * 01 DSR input
3376 * 00 DTR output (1=inactive)
3377 *
3378 * 0000 0001
3379 */
3380// write_reg(info, PVR, PVR_DTR);
d12341f9 3381
1da177e4
LT		 3382 /* IPC Interrupt Port Configuration
3383 *
3384 * 07 VIS 1=Masked interrupts visible
3385 * 06..05 Reserved, 0
3386 * 04..03 SLA Slave address, 00 ignored
3387 * 02 CASM Cascading Mode, 1=daisy chain
3388 * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
3389 *
3390 * 0000 0101
d12341f9 3391 */
1da177e4
LT		 3392 write_reg(info, IPC, 0x05);
3393}
3394
cdaad343 3395static void async_mode(MGSLPC_INFO *info)
1da177e4
LT		 3396{
3397 unsigned char val;
3398
d12341f9 3399 /* disable all interrupts */
1da177e4
LT		 3400 irq_disable(info, CHA, 0xffff);
3401 irq_disable(info, CHB, 0xffff);
3402 port_irq_disable(info, 0xff);
d12341f9 3403
1da177e4
LT		 3404 /* MODE
3405 *
3406 * 07 Reserved, 0
3407 * 06 FRTS RTS State, 0=active
3408 * 05 FCTS Flow Control on CTS
3409 * 04 FLON Flow Control Enable
3410 * 03 RAC Receiver Active, 0 = inactive
3411 * 02 RTS 0=Auto RTS, 1=manual RTS
3412 * 01 TRS Timer Resolution, 1=512
3413 * 00 TLP Test Loop, 0 = no loop
3414 *
3415 * 0000 0110
d12341f9 3416 */
1da177e4
LT		 3417 val = 0x06;
3418 if (info->params.loopback)
3419 val |= BIT0;
d12341f9
JG		 3420
3421 /* preserve RTS state */
1da177e4
LT		 3422 if (!(info->serial_signals & SerialSignal_RTS))
3423 val |= BIT6;
3424 write_reg(info, CHA + MODE, val);
d12341f9 3425
1da177e4
LT		 3426 /* CCR0
3427 *
3428 * 07 PU Power Up, 1=active, 0=power down
3429 * 06 MCE Master Clock Enable, 1=enabled
3430 * 05 Reserved, 0
3431 * 04..02 SC[2..0] Encoding, 000=NRZ
3432 * 01..00 SM[1..0] Serial Mode, 11=Async
3433 *
3434 * 1000 0011
d12341f9 3435 */
1da177e4 3436 write_reg(info, CHA + CCR0, 0x83);
d12341f9 3437
1da177e4
LT		 3438 /* CCR1
3439 *
3440 * 07..05 Reserved, 0
3441 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3442 * 03 BCR Bit Clock Rate, 1=16x
3443 * 02..00 CM[2..0] Clock Mode, 111=BRG
3444 *
3445 * 0001 1111
d12341f9 3446 */
1da177e4 3447 write_reg(info, CHA + CCR1, 0x1f);
d12341f9 3448
1da177e4
LT		 3449 /* CCR2 (channel A)
3450 *
3451 * 07..06 BGR[9..8] Baud rate bits 9..8
3452 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3453 * 04 SSEL Clock source select, 1=submode b
3454 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3455 * 02 RWX Read/Write Exchange 0=disabled
3456 * 01 Reserved, 0
3457 * 00 DIV, data inversion 0=disabled, 1=enabled
3458 *
3459 * 0001 0000
d12341f9 3460 */
1da177e4 3461 write_reg(info, CHA + CCR2, 0x10);
d12341f9 3462
1da177e4
LT		 3463 /* CCR3
3464 *
3465 * 07..01 Reserved, 0
3466 * 00 PSD DPLL Phase Shift Disable
3467 *
3468 * 0000 0000
d12341f9 3469 */
1da177e4 3470 write_reg(info, CHA + CCR3, 0);
d12341f9 3471
1da177e4
LT		 3472 /* CCR4
3473 *
3474 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3475 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3476 * 05 TST1 Test Pin, 0=normal operation
3477 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3478 * 03..00 Reserved, must be 0
3479 *
3480 * 0101 0000
d12341f9 3481 */
1da177e4
LT		 3482 write_reg(info, CHA + CCR4, 0x50);
3483 mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
d12341f9 3484
1da177e4
LT		 3485 /* DAFO Data Format
3486 *
3487 * 07 Reserved, 0
3488 * 06 XBRK transmit break, 0=normal operation
3489 * 05 Stop bits (0=1, 1=2)
3490 * 04..03 PAR[1..0] Parity (01=odd, 10=even)
3491 * 02 PAREN Parity Enable
3492 * 01..00 CHL[1..0] Character Length (00=8, 01=7)
3493 *
d12341f9 3494 */
1da177e4
LT		 3495 val = 0x00;
3496 if (info->params.data_bits != 8)
3497 val |= BIT0; /* 7 bits */
3498 if (info->params.stop_bits != 1)
3499 val |= BIT5;
3500 if (info->params.parity != ASYNC_PARITY_NONE)
3501 {
3502 val |= BIT2; /* Parity enable */
3503 if (info->params.parity == ASYNC_PARITY_ODD)
3504 val |= BIT3;
3505 else
3506 val |= BIT4;
3507 }
3508 write_reg(info, CHA + DAFO, val);
d12341f9 3509
1da177e4
LT		 3510 /* RFC Rx FIFO Control
3511 *
3512 * 07 Reserved, 0
3513 * 06 DPS, 1=parity bit not stored in data byte
3514 * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
3515 * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
3516 * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
3517 * 01 Reserved, 0
3518 * 00 TCDE Terminate Char Detect Enable, 0=disabled
3519 *
3520 * 0101 1100
d12341f9 3521 */
1da177e4 3522 write_reg(info, CHA + RFC, 0x5c);
d12341f9 3523
1da177e4
LT		 3524 /* RLCR Receive length check register
3525 *
3526 * Max frame length = (RL + 1) * 32
d12341f9 3527 */
1da177e4 3528 write_reg(info, CHA + RLCR, 0);
d12341f9 3529
1da177e4
LT		 3530 /* XBCH Transmit Byte Count High
3531 *
3532 * 07 DMA mode, 0 = interrupt driven
3533 * 06 NRM, 0=ABM (ignored)
3534 * 05 CAS Carrier Auto Start
3535 * 04 XC Transmit Continuously (ignored)
3536 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3537 *
3538 * 0000 0000
d12341f9 3539 */
1da177e4
LT		 3540 val = 0x00;
3541 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3542 val |= BIT5;
3543 write_reg(info, CHA + XBCH, val);
3544 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3545 irq_enable(info, CHA, IRQ_CTS);
d12341f9
JG		 3546
3547 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3548 set_reg_bits(info, CHA + MODE, BIT3);
3549 enable_auxclk(info);
3550 if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
3551 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3552 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3553 set_reg_bits(info, CHA + PVR, BIT3);
3554 } else
3555 clear_reg_bits(info, CHA + PVR, BIT3);
3556 irq_enable(info, CHA,
3557 IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
3558 IRQ_ALLSENT + IRQ_TXFIFO);
3559 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3560 wait_command_complete(info, CHA);
3561 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3562}
3563
3564/* Set the HDLC idle mode for the transmitter.
3565 */
cdaad343 3566static void tx_set_idle(MGSLPC_INFO *info)
1da177e4 3567{
d12341f9 3568 /* Note: ESCC2 only supports flags and one idle modes */
1da177e4
LT		 3569 if (info->idle_mode == HDLC_TXIDLE_FLAGS)
3570 set_reg_bits(info, CHA + CCR1, BIT3);
3571 else
3572 clear_reg_bits(info, CHA + CCR1, BIT3);
3573}
3574
3575/* get state of the V24 status (input) signals.
3576 */
cdaad343 3577static void get_signals(MGSLPC_INFO *info)
1da177e4
LT		 3578{
3579 unsigned char status = 0;
d12341f9
JG		 3580
3581 /* preserve DTR and RTS */
1da177e4
LT		 3582 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
3583
3584 if (read_reg(info, CHB + VSTR) & BIT7)
3585 info->serial_signals |= SerialSignal_DCD;
3586 if (read_reg(info, CHB + STAR) & BIT1)
3587 info->serial_signals |= SerialSignal_CTS;
3588
3589 status = read_reg(info, CHA + PVR);
3590 if (!(status & PVR_RI))
3591 info->serial_signals |= SerialSignal_RI;
3592 if (!(status & PVR_DSR))
3593 info->serial_signals |= SerialSignal_DSR;
3594}
3595
3596/* Set the state of DTR and RTS based on contents of
3597 * serial_signals member of device extension.
3598 */
cdaad343 3599static void set_signals(MGSLPC_INFO *info)
1da177e4
LT		 3600{
3601 unsigned char val;
3602
3603 val = read_reg(info, CHA + MODE);
3604 if (info->params.mode == MGSL_MODE_ASYNC) {
3605 if (info->serial_signals & SerialSignal_RTS)
3606 val &= ~BIT6;
3607 else
3608 val |= BIT6;
3609 } else {
3610 if (info->serial_signals & SerialSignal_RTS)
3611 val |= BIT2;
3612 else
3613 val &= ~BIT2;
3614 }
3615 write_reg(info, CHA + MODE, val);
3616
3617 if (info->serial_signals & SerialSignal_DTR)
3618 clear_reg_bits(info, CHA + PVR, PVR_DTR);
3619 else
3620 set_reg_bits(info, CHA + PVR, PVR_DTR);
3621}
3622
cdaad343 3623static void rx_reset_buffers(MGSLPC_INFO *info)
1da177e4
LT		 3624{
3625 RXBUF *buf;
3626 int i;
3627
3628 info->rx_put = 0;
3629 info->rx_get = 0;
3630 info->rx_frame_count = 0;
3631 for (i=0 ; i < info->rx_buf_count ; i++) {
3632 buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
3633 buf->status = buf->count = 0;
3634 }
3635}
3636
3637/* Attempt to return a received HDLC frame
3638 * Only frames received without errors are returned.
3639 *
0fab6de0 3640 * Returns true if frame returned, otherwise false
1da177e4 3641 */
eeb46134 3642static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3643{
3644 unsigned short status;
3645 RXBUF *buf;
3646 unsigned int framesize = 0;
3647 unsigned long flags;
0fab6de0 3648 bool return_frame = false;
d12341f9 3649
1da177e4 3650 if (info->rx_frame_count == 0)
0fab6de0 3651 return false;
1da177e4
LT		 3652
3653 buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
3654
3655 status = buf->status;
3656
3657 /* 07 VFR 1=valid frame
3658 * 06 RDO 1=data overrun
3659 * 05 CRC 1=OK, 0=error
3660 * 04 RAB 1=frame aborted
3661 */
3662 if ((status & 0xf0) != 0xA0) {
3663 if (!(status & BIT7) || (status & BIT4))
3664 info->icount.rxabort++;
3665 else if (status & BIT6)
3666 info->icount.rxover++;
3667 else if (!(status & BIT5)) {
3668 info->icount.rxcrc++;
3669 if (info->params.crc_type & HDLC_CRC_RETURN_EX)
0fab6de0 3670 return_frame = true;
1da177e4
LT		 3671 }
3672 framesize = 0;
af69c7f9 3673#if SYNCLINK_GENERIC_HDLC
1da177e4 3674 {
198191c4
KH		 3675 info->netdev->stats.rx_errors++;
3676 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 3677 }
3678#endif
3679 } else
0fab6de0 3680 return_frame = true;
1da177e4
LT		 3681
3682 if (return_frame)
3683 framesize = buf->count;
3684
3685 if (debug_level >= DEBUG_LEVEL_BH)
3686 printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
3687 __FILE__,__LINE__,info->device_name,status,framesize);
d12341f9 3688
1da177e4 3689 if (debug_level >= DEBUG_LEVEL_DATA)
d12341f9
JG		 3690 trace_block(info, buf->data, framesize, 0);
3691
1da177e4
LT		 3692 if (framesize) {
3693 if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
3694 framesize+1 > info->max_frame_size) ||
3695 framesize > info->max_frame_size)
3696 info->icount.rxlong++;
3697 else {
3698 if (status & BIT5)
3699 info->icount.rxok++;
3700
3701 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
3702 *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
3703 ++framesize;
3704 }
3705
af69c7f9 3706#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3707 if (info->netcount)
3708 hdlcdev_rx(info, buf->data, framesize);
3709 else
3710#endif
3711 ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
3712 }
3713 }
3714
3715 spin_lock_irqsave(&info->lock,flags);
3716 buf->status = buf->count = 0;
3717 info->rx_frame_count--;
3718 info->rx_get++;
3719 if (info->rx_get >= info->rx_buf_count)
3720 info->rx_get = 0;
3721 spin_unlock_irqrestore(&info->lock,flags);
3722
0fab6de0 3723 return true;
1da177e4
LT		 3724}
3725
0fab6de0 3726static bool register_test(MGSLPC_INFO *info)
1da177e4 3727{
d12341f9 3728 static unsigned char patterns[] =
1da177e4 3729 { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
fe971071 3730 static unsigned int count = ARRAY_SIZE(patterns);
1da177e4 3731 unsigned int i;
0fab6de0 3732 bool rc = true;
1da177e4
LT		 3733 unsigned long flags;
3734
3735 spin_lock_irqsave(&info->lock,flags);
3736 reset_device(info);
3737
3738 for (i = 0; i < count; i++) {
3739 write_reg(info, XAD1, patterns[i]);
3740 write_reg(info, XAD2, patterns[(i + 1) % count]);
fe971071 3741 if ((read_reg(info, XAD1) != patterns[i]) ||
1da177e4 3742 (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
0fab6de0 3743 rc = false;
1da177e4
LT		 3744 break;
3745 }
3746 }
3747
3748 spin_unlock_irqrestore(&info->lock,flags);
3749 return rc;
3750}
3751
0fab6de0 3752static bool irq_test(MGSLPC_INFO *info)
1da177e4
LT		 3753{
3754 unsigned long end_time;
3755 unsigned long flags;
3756
3757 spin_lock_irqsave(&info->lock,flags);
3758 reset_device(info);
3759
0fab6de0 3760 info->testing_irq = true;
1da177e4
LT		 3761 hdlc_mode(info);
3762
0fab6de0 3763 info->irq_occurred = false;
1da177e4
LT		 3764
3765 /* init hdlc mode */
3766
3767 irq_enable(info, CHA, IRQ_TIMER);
3768 write_reg(info, CHA + TIMR, 0); /* 512 cycles */
3769 issue_command(info, CHA, CMD_START_TIMER);
3770
3771 spin_unlock_irqrestore(&info->lock,flags);
3772
3773 end_time=100;
3774 while(end_time-- && !info->irq_occurred) {
3775 msleep_interruptible(10);
3776 }
d12341f9 3777
0fab6de0 3778 info->testing_irq = false;
1da177e4
LT		 3779
3780 spin_lock_irqsave(&info->lock,flags);
3781 reset_device(info);
3782 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 3783
0fab6de0 3784 return info->irq_occurred;
1da177e4
LT		 3785}
3786
cdaad343 3787static int adapter_test(MGSLPC_INFO *info)
1da177e4
LT		 3788{
3789 if (!register_test(info)) {
3790 info->init_error = DiagStatus_AddressFailure;
3791 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
3792 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
3793 return -ENODEV;
3794 }
3795
3796 if (!irq_test(info)) {
3797 info->init_error = DiagStatus_IrqFailure;
3798 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
3799 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
3800 return -ENODEV;
3801 }
3802
3803 if (debug_level >= DEBUG_LEVEL_INFO)
3804 printk("%s(%d):device %s passed diagnostics\n",
3805 __FILE__,__LINE__,info->device_name);
3806 return 0;
3807}
3808
cdaad343 3809static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
1da177e4
LT		 3810{
3811 int i;
3812 int linecount;
3813 if (xmit)
3814 printk("%s tx data:\n",info->device_name);
3815 else
3816 printk("%s rx data:\n",info->device_name);
d12341f9 3817
1da177e4
LT		 3818 while(count) {
3819 if (count > 16)
3820 linecount = 16;
3821 else
3822 linecount = count;
d12341f9 3823
1da177e4
LT		 3824 for(i=0;i<linecount;i++)
3825 printk("%02X ",(unsigned char)data[i]);
3826 for(;i<17;i++)
3827 printk(" ");
3828 for(i=0;i<linecount;i++) {
3829 if (data[i]>=040 && data[i]<=0176)
3830 printk("%c",data[i]);
3831 else
3832 printk(".");
3833 }
3834 printk("\n");
d12341f9 3835
1da177e4
LT		 3836 data += linecount;
3837 count -= linecount;
3838 }
3839}
3840
3841/* HDLC frame time out
3842 * update stats and do tx completion processing
3843 */
cdaad343 3844static void tx_timeout(unsigned long context)
1da177e4
LT		 3845{
3846 MGSLPC_INFO *info = (MGSLPC_INFO*)context;
3847 unsigned long flags;
d12341f9 3848
1da177e4
LT		 3849 if ( debug_level >= DEBUG_LEVEL_INFO )
3850 printk( "%s(%d):tx_timeout(%s)\n",
3851 __FILE__,__LINE__,info->device_name);
3852 if(info->tx_active &&
3853 info->params.mode == MGSL_MODE_HDLC) {
3854 info->icount.txtimeout++;
3855 }
3856 spin_lock_irqsave(&info->lock,flags);
0fab6de0 3857 info->tx_active = false;
1da177e4
LT		 3858 info->tx_count = info->tx_put = info->tx_get = 0;
3859
3860 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 3861
af69c7f9 3862#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3863 if (info->netcount)
3864 hdlcdev_tx_done(info);
3865 else
3866#endif
eeb46134
AC		 3867 {
3868 struct tty_struct *tty = tty_port_tty_get(&info->port);
3869 bh_transmit(info, tty);
3870 tty_kref_put(tty);
3871 }
1da177e4
LT		 3872}
3873
af69c7f9 3874#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3875
3876/**
3877 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
3878 * set encoding and frame check sequence (FCS) options
3879 *
3880 * dev pointer to network device structure
3881 * encoding serial encoding setting
3882 * parity FCS setting
3883 *
3884 * returns 0 if success, otherwise error code
3885 */
3886static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
3887 unsigned short parity)
3888{
3889 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3890 struct tty_struct *tty;
1da177e4
LT		 3891 unsigned char new_encoding;
3892 unsigned short new_crctype;
3893
3894 /* return error if TTY interface open */
eeb46134 3895 if (info->port.count)
1da177e4
LT		 3896 return -EBUSY;
3897
3898 switch (encoding)
3899 {
3900 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
3901 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
3902 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
3903 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
3904 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
3905 default: return -EINVAL;
3906 }
3907
3908 switch (parity)
3909 {
3910 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
3911 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
3912 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
3913 default: return -EINVAL;
3914 }
3915
3916 info->params.encoding = new_encoding;
53b3531b 3917 info->params.crc_type = new_crctype;
1da177e4
LT		 3918
3919 /* if network interface up, reprogram hardware */
eeb46134
AC		 3920 if (info->netcount) {
3921 tty = tty_port_tty_get(&info->port);
3922 mgslpc_program_hw(info, tty);
3923 tty_kref_put(tty);
3924 }
1da177e4
LT		 3925
3926 return 0;
3927}
3928
3929/**
3930 * called by generic HDLC layer to send frame
3931 *
3932 * skb socket buffer containing HDLC frame
3933 * dev pointer to network device structure
1da177e4 3934 */
4c5d502d
SH		 3935static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
3936 struct net_device *dev)
1da177e4
LT		 3937{
3938 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 3939 unsigned long flags;
3940
3941 if (debug_level >= DEBUG_LEVEL_INFO)
3942 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
3943
3944 /* stop sending until this frame completes */
3945 netif_stop_queue(dev);
3946
3947 /* copy data to device buffers */
d626f62b 3948 skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
1da177e4
LT		 3949 info->tx_get = 0;
3950 info->tx_put = info->tx_count = skb->len;
3951
3952 /* update network statistics */
198191c4
KH		 3953 dev->stats.tx_packets++;
3954 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 3955
3956 /* done with socket buffer, so free it */
3957 dev_kfree_skb(skb);
3958
3959 /* save start time for transmit timeout detection */
3960 dev->trans_start = jiffies;
3961
3962 /* start hardware transmitter if necessary */
3963 spin_lock_irqsave(&info->lock,flags);
eeb46134
AC		 3964 if (!info->tx_active) {
3965 struct tty_struct *tty = tty_port_tty_get(&info->port);
3966 tx_start(info, tty);
3967 tty_kref_put(tty);
3968 }
1da177e4
LT		 3969 spin_unlock_irqrestore(&info->lock,flags);
3970
4c5d502d 3971 return NETDEV_TX_OK;
1da177e4
LT		 3972}
3973
3974/**
3975 * called by network layer when interface enabled
3976 * claim resources and initialize hardware
3977 *
3978 * dev pointer to network device structure
3979 *
3980 * returns 0 if success, otherwise error code
3981 */
3982static int hdlcdev_open(struct net_device *dev)
3983{
3984 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3985 struct tty_struct *tty;
1da177e4
LT		 3986 int rc;
3987 unsigned long flags;
3988
3989 if (debug_level >= DEBUG_LEVEL_INFO)
3990 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
3991
3992 /* generic HDLC layer open processing */
3993 if ((rc = hdlc_open(dev)))
3994 return rc;
3995
3996 /* arbitrate between network and tty opens */
3997 spin_lock_irqsave(&info->netlock, flags);
eeb46134 3998 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 3999 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
4000 spin_unlock_irqrestore(&info->netlock, flags);
4001 return -EBUSY;
4002 }
4003 info->netcount=1;
4004 spin_unlock_irqrestore(&info->netlock, flags);
4005
eeb46134 4006 tty = tty_port_tty_get(&info->port);
1da177e4 4007 /* claim resources and init adapter */
eeb46134
AC		 4008 if ((rc = startup(info, tty)) != 0) {
4009 tty_kref_put(tty);
1da177e4
LT		 4010 spin_lock_irqsave(&info->netlock, flags);
4011 info->netcount=0;
4012 spin_unlock_irqrestore(&info->netlock, flags);
4013 return rc;
4014 }
1da177e4
LT		 4015 /* assert DTR and RTS, apply hardware settings */
4016 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
eeb46134
AC		 4017 mgslpc_program_hw(info, tty);
4018 tty_kref_put(tty);
1da177e4
LT		 4019
4020 /* enable network layer transmit */
4021 dev->trans_start = jiffies;
4022 netif_start_queue(dev);
4023
4024 /* inform generic HDLC layer of current DCD status */
4025 spin_lock_irqsave(&info->lock, flags);
4026 get_signals(info);
4027 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 4028 if (info->serial_signals & SerialSignal_DCD)
4029 netif_carrier_on(dev);
4030 else
4031 netif_carrier_off(dev);
1da177e4
LT		 4032 return 0;
4033}
4034
4035/**
4036 * called by network layer when interface is disabled
4037 * shutdown hardware and release resources
4038 *
4039 * dev pointer to network device structure
4040 *
4041 * returns 0 if success, otherwise error code
4042 */
4043static int hdlcdev_close(struct net_device *dev)
4044{
4045 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 4046 struct tty_struct *tty = tty_port_tty_get(&info->port);
1da177e4
LT		 4047 unsigned long flags;
4048
4049 if (debug_level >= DEBUG_LEVEL_INFO)
4050 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
4051
4052 netif_stop_queue(dev);
4053
4054 /* shutdown adapter and release resources */
eeb46134
AC		 4055 shutdown(info, tty);
4056 tty_kref_put(tty);
1da177e4
LT		 4057 hdlc_close(dev);
4058
4059 spin_lock_irqsave(&info->netlock, flags);
4060 info->netcount=0;
4061 spin_unlock_irqrestore(&info->netlock, flags);
4062
4063 return 0;
4064}
4065
4066/**
4067 * called by network layer to process IOCTL call to network device
4068 *
4069 * dev pointer to network device structure
4070 * ifr pointer to network interface request structure
4071 * cmd IOCTL command code
4072 *
4073 * returns 0 if success, otherwise error code
4074 */
4075static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4076{
4077 const size_t size = sizeof(sync_serial_settings);
4078 sync_serial_settings new_line;
4079 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
4080 MGSLPC_INFO *info = dev_to_port(dev);
4081 unsigned int flags;
4082
4083 if (debug_level >= DEBUG_LEVEL_INFO)
4084 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
4085
4086 /* return error if TTY interface open */
eeb46134 4087 if (info->port.count)
1da177e4
LT		 4088 return -EBUSY;
4089
4090 if (cmd != SIOCWANDEV)
4091 return hdlc_ioctl(dev, ifr, cmd);
4092
5b917a14
VK		 4093 memset(&new_line, 0, size);
4094
1da177e4
LT		 4095 switch(ifr->ifr_settings.type) {
4096 case IF_GET_IFACE: /* return current sync_serial_settings */
4097
4098 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
4099 if (ifr->ifr_settings.size < size) {
4100 ifr->ifr_settings.size = size; /* data size wanted */
4101 return -ENOBUFS;
4102 }
4103
4104 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4105 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4106 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4107 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4108
4109 switch (flags){
4110 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4111 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4112 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4113 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4114 default: new_line.clock_type = CLOCK_DEFAULT;
4115 }
4116
4117 new_line.clock_rate = info->params.clock_speed;
4118 new_line.loopback = info->params.loopback ? 1:0;
4119
4120 if (copy_to_user(line, &new_line, size))
4121 return -EFAULT;
4122 return 0;
4123
4124 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
4125
4126 if(!capable(CAP_NET_ADMIN))
4127 return -EPERM;
4128 if (copy_from_user(&new_line, line, size))
4129 return -EFAULT;
4130
4131 switch (new_line.clock_type)
4132 {
4133 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
4134 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
4135 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
4136 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
4137 case CLOCK_DEFAULT: flags = info->params.flags &
4138 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4139 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4140 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4141 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
4142 default: return -EINVAL;
4143 }
4144
4145 if (new_line.loopback != 0 && new_line.loopback != 1)
4146 return -EINVAL;
4147
4148 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4149 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4150 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4151 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4152 info->params.flags |= flags;
4153
4154 info->params.loopback = new_line.loopback;
4155
4156 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
4157 info->params.clock_speed = new_line.clock_rate;
4158 else
4159 info->params.clock_speed = 0;
4160
4161 /* if network interface up, reprogram hardware */
eeb46134
AC		 4162 if (info->netcount) {
4163 struct tty_struct *tty = tty_port_tty_get(&info->port);
4164 mgslpc_program_hw(info, tty);
4165 tty_kref_put(tty);
4166 }
1da177e4
LT		 4167 return 0;
4168
4169 default:
4170 return hdlc_ioctl(dev, ifr, cmd);
4171 }
4172}
4173
4174/**
4175 * called by network layer when transmit timeout is detected
4176 *
4177 * dev pointer to network device structure
4178 */
4179static void hdlcdev_tx_timeout(struct net_device *dev)
4180{
4181 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 4182 unsigned long flags;
4183
4184 if (debug_level >= DEBUG_LEVEL_INFO)
4185 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
4186
198191c4
KH		 4187 dev->stats.tx_errors++;
4188 dev->stats.tx_aborted_errors++;
1da177e4
LT		 4189
4190 spin_lock_irqsave(&info->lock,flags);
4191 tx_stop(info);
4192 spin_unlock_irqrestore(&info->lock,flags);
4193
4194 netif_wake_queue(dev);
4195}
4196
4197/**
4198 * called by device driver when transmit completes
4199 * reenable network layer transmit if stopped
4200 *
4201 * info pointer to device instance information
4202 */
4203static void hdlcdev_tx_done(MGSLPC_INFO *info)
4204{
4205 if (netif_queue_stopped(info->netdev))
4206 netif_wake_queue(info->netdev);
4207}
4208
4209/**
4210 * called by device driver when frame received
4211 * pass frame to network layer
4212 *
4213 * info pointer to device instance information
4214 * buf pointer to buffer contianing frame data
4215 * size count of data bytes in buf
4216 */
4217static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
4218{
4219 struct sk_buff *skb = dev_alloc_skb(size);
4220 struct net_device *dev = info->netdev;
1da177e4
LT		 4221
4222 if (debug_level >= DEBUG_LEVEL_INFO)
4223 printk("hdlcdev_rx(%s)\n",dev->name);
4224
4225 if (skb == NULL) {
4226 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
198191c4 4227 dev->stats.rx_dropped++;
1da177e4
LT		 4228 return;
4229 }
4230
198191c4 4231 memcpy(skb_put(skb, size), buf, size);
1da177e4 4232
198191c4 4233 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 4234
198191c4
KH		 4235 dev->stats.rx_packets++;
4236 dev->stats.rx_bytes += size;
1da177e4
LT		 4237
4238 netif_rx(skb);
1da177e4
LT		 4239}
4240
991990a1
KH		 4241static const struct net_device_ops hdlcdev_ops = {
4242 .ndo_open = hdlcdev_open,
4243 .ndo_stop = hdlcdev_close,
4244 .ndo_change_mtu = hdlc_change_mtu,
4245 .ndo_start_xmit = hdlc_start_xmit,
4246 .ndo_do_ioctl = hdlcdev_ioctl,
4247 .ndo_tx_timeout = hdlcdev_tx_timeout,
4248};
4249
1da177e4
LT		 4250/**
4251 * called by device driver when adding device instance
4252 * do generic HDLC initialization
4253 *
4254 * info pointer to device instance information
4255 *
4256 * returns 0 if success, otherwise error code
4257 */
4258static int hdlcdev_init(MGSLPC_INFO *info)
4259{
4260 int rc;
4261 struct net_device *dev;
4262 hdlc_device *hdlc;
4263
4264 /* allocate and initialize network and HDLC layer objects */
4265
4266 if (!(dev = alloc_hdlcdev(info))) {
4267 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
4268 return -ENOMEM;
4269 }
4270
4271 /* for network layer reporting purposes only */
4272 dev->base_addr = info->io_base;
4273 dev->irq = info->irq_level;
4274
4275 /* network layer callbacks and settings */
991990a1
KH		 4276 dev->netdev_ops = &hdlcdev_ops;
4277 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 4278 dev->tx_queue_len = 50;
4279
4280 /* generic HDLC layer callbacks and settings */
4281 hdlc = dev_to_hdlc(dev);
4282 hdlc->attach = hdlcdev_attach;
4283 hdlc->xmit = hdlcdev_xmit;
4284
4285 /* register objects with HDLC layer */
4286 if ((rc = register_hdlc_device(dev))) {
4287 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
4288 free_netdev(dev);
4289 return rc;
4290 }
4291
4292 info->netdev = dev;
4293 return 0;
4294}
4295
4296/**
4297 * called by device driver when removing device instance
4298 * do generic HDLC cleanup
4299 *
4300 * info pointer to device instance information
4301 */
4302static void hdlcdev_exit(MGSLPC_INFO *info)
4303{
4304 unregister_hdlc_device(info->netdev);
4305 free_netdev(info->netdev);
4306 info->netdev = NULL;
4307}
4308
4309#endif /* CONFIG_HDLC */
4310
kernel source for telekom puls (alcatel/mediatek)