[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / pc8736x_gpio.c

/* linux/drivers/char/pc8736x_gpio.c

   National Semiconductor PC8736x GPIO driver.  Allows a user space
   process to play with the GPIO pins.

   Copyright (c) 2005 Jim Cromie <jim.cromie@gmail.com>

   adapted from linux/drivers/char/scx200_gpio.c
   Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>,
*/

#include <linux/config.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/nsc_gpio.h>
#include <linux/platform_device.h>
#include <asm/uaccess.h>
#include <asm/io.h>

#define DEVNAME "pc8736x_gpio"

MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
MODULE_DESCRIPTION("NatSemi PC-8736x GPIO Pin Driver");
MODULE_LICENSE("GPL");

static int major;		/* default to dynamic major */
module_param(major, int, 0);
MODULE_PARM_DESC(major, "Major device number");

static DEFINE_SPINLOCK(pc8736x_gpio_config_lock);
static unsigned pc8736x_gpio_base;
static u8 pc8736x_gpio_shadow[4];

#define SIO_BASE1       0x2E	/* 1st command-reg to check */
#define SIO_BASE2       0x4E	/* alt command-reg to check */
#define SIO_BASE_OFFSET 0x20

#define SIO_SID		0x20	/* SuperI/O ID Register */
#define SIO_SID_VALUE	0xe9	/* Expected value in SuperI/O ID Register */

#define SIO_CF1		0x21	/* chip config, bit0 is chip enable */

#define PC8736X_GPIO_SIZE	16

#define SIO_UNIT_SEL	0x7	/* unit select reg */
#define SIO_UNIT_ACT	0x30	/* unit enable */
#define SIO_GPIO_UNIT	0x7	/* unit number of GPIO */
#define SIO_VLM_UNIT	0x0D
#define SIO_TMS_UNIT	0x0E

/* config-space addrs to read/write each unit's runtime addr */
#define SIO_BASE_HADDR		0x60
#define SIO_BASE_LADDR		0x61

/* GPIO config-space pin-control addresses */
#define SIO_GPIO_PIN_SELECT	0xF0
#define SIO_GPIO_PIN_CONFIG     0xF1
#define SIO_GPIO_PIN_EVENT      0xF2

static unsigned char superio_cmd = 0;
static unsigned char selected_device = 0xFF;	/* bogus start val */

/* GPIO port runtime access, functionality */
static int port_offset[] = { 0, 4, 8, 10 };	/* non-uniform offsets ! */
/* static int event_capable[] = { 1, 1, 0, 0 };   ports 2,3 are hobbled */

#define PORT_OUT	0
#define PORT_IN		1
#define PORT_EVT_EN	2
#define PORT_EVT_STST	3

static struct platform_device *pdev;  /* use in dev_*() */

static inline void superio_outb(int addr, int val)
{
	outb_p(addr, superio_cmd);
	outb_p(val, superio_cmd + 1);
}

static inline int superio_inb(int addr)
{
	outb_p(addr, superio_cmd);
	return inb_p(superio_cmd + 1);
}

static int pc8736x_superio_present(void)
{
	/* try the 2 possible values, read a hardware reg to verify */
	superio_cmd = SIO_BASE1;
	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
		return superio_cmd;

	superio_cmd = SIO_BASE2;
	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
		return superio_cmd;

	return 0;
}

static void device_select(unsigned devldn)
{
	superio_outb(SIO_UNIT_SEL, devldn);
	selected_device = devldn;
}

static void select_pin(unsigned iminor)
{
	/* select GPIO port/pin from device minor number */
	device_select(SIO_GPIO_UNIT);
	superio_outb(SIO_GPIO_PIN_SELECT,
		     ((iminor << 1) & 0xF0) | (iminor & 0x7));
}

static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits,
					    u32 func_slct)
{
	u32 config, new_config;
	unsigned long flags;

	spin_lock_irqsave(&pc8736x_gpio_config_lock, flags);

	device_select(SIO_GPIO_UNIT);
	select_pin(index);

	/* read current config value */
	config = superio_inb(func_slct);

	/* set new config */
	new_config = (config & mask) | bits;
	superio_outb(func_slct, new_config);

	spin_unlock_irqrestore(&pc8736x_gpio_config_lock, flags);

	return config;
}

static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits)
{
	return pc8736x_gpio_configure_fn(index, mask, bits,
					 SIO_GPIO_PIN_CONFIG);
}

static int pc8736x_gpio_get(unsigned minor)
{
	int port, bit, val;

	port = minor >> 3;
	bit = minor & 7;
	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
	val >>= bit;
	val &= 1;

	dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n",
		minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit,
		val);

	return val;
}

static void pc8736x_gpio_set(unsigned minor, int val)
{
	int port, bit, curval;

	minor &= 0x1f;
	port = minor >> 3;
	bit = minor & 7;
	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);

	dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n",
		pc8736x_gpio_base + port_offset[port] + PORT_OUT,
		curval, bit, (curval & ~(1 << bit)), val, (val << bit));

	val = (curval & ~(1 << bit)) | (val << bit);

	dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)"
		" %2x -> %2x\n", minor, port, bit, curval, val);

	outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT);

	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);

	dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val);
	pc8736x_gpio_shadow[port] = val;
}

static void pc8736x_gpio_set_high(unsigned index)
{
	pc8736x_gpio_set(index, 1);
}

static void pc8736x_gpio_set_low(unsigned index)
{
	pc8736x_gpio_set(index, 0);
}

static int pc8736x_gpio_current(unsigned minor)
{
	int port, bit;
	minor &= 0x1f;
	port = minor >> 3;
	bit = minor & 7;
	return ((pc8736x_gpio_shadow[port] >> bit) & 0x01);
}

static void pc8736x_gpio_change(unsigned index)
{
	pc8736x_gpio_set(index, !pc8736x_gpio_current(index));
}

static struct nsc_gpio_ops pc8736x_access = {
	.owner		= THIS_MODULE,
	.gpio_config	= pc8736x_gpio_configure,
	.gpio_dump	= nsc_gpio_dump,
	.gpio_get	= pc8736x_gpio_get,
	.gpio_set	= pc8736x_gpio_set,
	.gpio_set_high	= pc8736x_gpio_set_high,
	.gpio_set_low	= pc8736x_gpio_set_low,
	.gpio_change	= pc8736x_gpio_change,
	.gpio_current	= pc8736x_gpio_current
};

static int pc8736x_gpio_open(struct inode *inode, struct file *file)
{
	unsigned m = iminor(inode);
	file->private_data = &pc8736x_access;

	dev_dbg(&pdev->dev, "open %d\n", m);

	if (m > 63)
		return -EINVAL;
	return nonseekable_open(inode, file);
}

static struct file_operations pc8736x_gpio_fops = {
	.owner	= THIS_MODULE,
	.open	= pc8736x_gpio_open,
	.write	= nsc_gpio_write,
	.read	= nsc_gpio_read,
};

static void __init pc8736x_init_shadow(void)
{
	int port;

	/* read the current values driven on the GPIO signals */
	for (port = 0; port < 4; ++port)
		pc8736x_gpio_shadow[port]
		    = inb_p(pc8736x_gpio_base + port_offset[port]
			    + PORT_OUT);

}

static int __init pc8736x_gpio_init(void)
{
	int rc = 0;

	pdev = platform_device_alloc(DEVNAME, 0);
	if (!pdev)
		return -ENOMEM;

	rc = platform_device_add(pdev);
	if (rc) {
		rc = -ENODEV;
		goto undo_platform_dev_alloc;
	}
	dev_info(&pdev->dev, "NatSemi pc8736x GPIO Driver Initializing\n");

	if (!pc8736x_superio_present()) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "no device found\n");
		goto undo_platform_dev_add;
	}
	pc8736x_access.dev = &pdev->dev;

	/* Verify that chip and it's GPIO unit are both enabled.
	   My BIOS does this, so I take minimum action here
	 */
	rc = superio_inb(SIO_CF1);
	if (!(rc & 0x01)) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "device not enabled\n");
		goto undo_platform_dev_add;
	}
	device_select(SIO_GPIO_UNIT);
	if (!superio_inb(SIO_UNIT_ACT)) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "GPIO unit not enabled\n");
		goto undo_platform_dev_add;
	}

	/* read the GPIO unit base addr that chip responds to */
	pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
			     | superio_inb(SIO_BASE_LADDR));

	if (!request_region(pc8736x_gpio_base, 16, DEVNAME)) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "GPIO ioport %x busy\n",
			pc8736x_gpio_base);
		goto undo_platform_dev_add;
	}
	dev_info(&pdev->dev, "GPIO ioport %x reserved\n", pc8736x_gpio_base);

	rc = register_chrdev(major, DEVNAME, &pc8736x_gpio_fops);
	if (rc < 0) {
		dev_err(&pdev->dev, "register-chrdev failed: %d\n", rc);
		goto undo_platform_dev_add;
	}
	if (!major) {
		major = rc;
		dev_dbg(&pdev->dev, "got dynamic major %d\n", major);
	}

	pc8736x_init_shadow();
	return 0;

undo_platform_dev_add:
	platform_device_put(pdev);
undo_platform_dev_alloc:
	kfree(pdev);
	return rc;
}

static void __exit pc8736x_gpio_cleanup(void)
{
	dev_dbg(&pdev->dev, " cleanup\n");

	release_region(pc8736x_gpio_base, 16);

	unregister_chrdev(major, DEVNAME);
}

EXPORT_SYMBOL(pc8736x_access);

module_init(pc8736x_gpio_init);
module_exit(pc8736x_gpio_cleanup);
Commit	Line	Data
681a3e7d JC	1	/* linux/drivers/char/pc8736x_gpio.c
	2
	3	National Semiconductor PC8736x GPIO driver. Allows a user space
	4	process to play with the GPIO pins.
	5
	6	Copyright (c) 2005 Jim Cromie <jim.cromie@gmail.com>
	7
	8	adapted from linux/drivers/char/scx200_gpio.c
	9	Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>,
	10	*/
	11
	12	#include <linux/config.h>
	13	#include <linux/fs.h>
	14	#include <linux/module.h>
	15	#include <linux/errno.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/ioport.h>
	19	#include <linux/nsc_gpio.h>
58b087cd	20	#include <linux/platform_device.h>
681a3e7d JC	21	#include <asm/uaccess.h>
	22	#include <asm/io.h>
	23
58b087cd	24	#define DEVNAME "pc8736x_gpio"
681a3e7d JC	25
681a3e7d JC	26	MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
58b087cd	27	MODULE_DESCRIPTION("NatSemi PC-8736x GPIO Pin Driver");
681a3e7d JC	28	MODULE_LICENSE("GPL");
	29
	30	static int major; /* default to dynamic major */
	31	module_param(major, int, 0);
	32	MODULE_PARM_DESC(major, "Major device number");
	33
	34	static DEFINE_SPINLOCK(pc8736x_gpio_config_lock);
	35	static unsigned pc8736x_gpio_base;
6cad56fd	36	static u8 pc8736x_gpio_shadow[4];
681a3e7d JC	37
	38	#define SIO_BASE1 0x2E /* 1st command-reg to check */
	39	#define SIO_BASE2 0x4E /* alt command-reg to check */
	40	#define SIO_BASE_OFFSET 0x20
	41
	42	#define SIO_SID 0x20 /* SuperI/O ID Register */
	43	#define SIO_SID_VALUE 0xe9 /* Expected value in SuperI/O ID Register */
	44
	45	#define SIO_CF1 0x21 /* chip config, bit0 is chip enable */
	46
58b087cd JC	47	#define PC8736X_GPIO_SIZE 16
58b087cd JC	48
681a3e7d JC	49	#define SIO_UNIT_SEL 0x7 /* unit select reg */
	50	#define SIO_UNIT_ACT 0x30 /* unit enable */
	51	#define SIO_GPIO_UNIT 0x7 /* unit number of GPIO */
	52	#define SIO_VLM_UNIT 0x0D
	53	#define SIO_TMS_UNIT 0x0E
	54
	55	/* config-space addrs to read/write each unit's runtime addr */
	56	#define SIO_BASE_HADDR 0x60
	57	#define SIO_BASE_LADDR 0x61
	58
	59	/* GPIO config-space pin-control addresses */
	60	#define SIO_GPIO_PIN_SELECT 0xF0
	61	#define SIO_GPIO_PIN_CONFIG 0xF1
	62	#define SIO_GPIO_PIN_EVENT 0xF2
	63
	64	static unsigned char superio_cmd = 0;
	65	static unsigned char selected_device = 0xFF; /* bogus start val */
	66
	67	/* GPIO port runtime access, functionality */
	68	static int port_offset[] = { 0, 4, 8, 10 }; /* non-uniform offsets ! */
	69	/* static int event_capable[] = { 1, 1, 0, 0 }; ports 2,3 are hobbled */
	70
	71	#define PORT_OUT 0
	72	#define PORT_IN 1
	73	#define PORT_EVT_EN 2
	74	#define PORT_EVT_STST 3
	75
58b087cd JC	76	static struct platform_device pdev; / use in dev_() /
58b087cd JC	77
681a3e7d JC	78	static inline void superio_outb(int addr, int val)
	79	{
	80	outb_p(addr, superio_cmd);
	81	outb_p(val, superio_cmd + 1);
	82	}
	83
	84	static inline int superio_inb(int addr)
	85	{
	86	outb_p(addr, superio_cmd);
	87	return inb_p(superio_cmd + 1);
	88	}
	89
	90	static int pc8736x_superio_present(void)
	91	{
	92	/* try the 2 possible values, read a hardware reg to verify */
	93	superio_cmd = SIO_BASE1;
	94	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
	95	return superio_cmd;
	96
	97	superio_cmd = SIO_BASE2;
	98	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
	99	return superio_cmd;
	100
	101	return 0;
	102	}
	103
	104	static void device_select(unsigned devldn)
	105	{
	106	superio_outb(SIO_UNIT_SEL, devldn);
	107	selected_device = devldn;
	108	}
	109
	110	static void select_pin(unsigned iminor)
	111	{
	112	/* select GPIO port/pin from device minor number */
	113	device_select(SIO_GPIO_UNIT);
	114	superio_outb(SIO_GPIO_PIN_SELECT,
	115	((iminor << 1) & 0xF0) \| (iminor & 0x7));
	116	}
	117
	118	static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits,
	119	u32 func_slct)
	120	{
	121	u32 config, new_config;
	122	unsigned long flags;
	123
	124	spin_lock_irqsave(&pc8736x_gpio_config_lock, flags);
	125
	126	device_select(SIO_GPIO_UNIT);
	127	select_pin(index);
	128
	129	/* read current config value */
	130	config = superio_inb(func_slct);
	131
	132	/* set new config */
	133	new_config = (config & mask) \| bits;
	134	superio_outb(func_slct, new_config);
	135
	136	spin_unlock_irqrestore(&pc8736x_gpio_config_lock, flags);
	137
	138	return config;
	139	}
	140
	141	static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits)
142	{
143	return pc8736x_gpio_configure_fn(index, mask, bits,
144	SIO_GPIO_PIN_CONFIG);
145	}
146
147	static int pc8736x_gpio_get(unsigned minor)
148	{
149	int port, bit, val;
150
151	port = minor >> 3;
152	bit = minor & 7;
153	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
154	val >>= bit;
155	val &= 1;
156
58b087cd JC	157	dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n",
	158	minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit,
	159	val);
681a3e7d JC	160
	161	return val;
	162	}
	163
	164	static void pc8736x_gpio_set(unsigned minor, int val)
	165	{
	166	int port, bit, curval;
	167
	168	minor &= 0x1f;
	169	port = minor >> 3;
	170	bit = minor & 7;
	171	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	172
58b087cd JC	173	dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n",
	174	pc8736x_gpio_base + port_offset[port] + PORT_OUT,
	175	curval, bit, (curval & ~(1 << bit)), val, (val << bit));
681a3e7d JC	176
	177	val = (curval & ~(1 << bit)) \| (val << bit);
	178
58b087cd JC	179	dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)"
58b087cd JC	180	" %2x -> %2x\n", minor, port, bit, curval, val);
681a3e7d JC	181
	182	outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	183
	184	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	185	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
	186
58b087cd	187	dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val);
6cad56fd	188	pc8736x_gpio_shadow[port] = val;
681a3e7d JC	189	}
	190
	191	static void pc8736x_gpio_set_high(unsigned index)
	192	{
	193	pc8736x_gpio_set(index, 1);
	194	}
	195
	196	static void pc8736x_gpio_set_low(unsigned index)
	197	{
	198	pc8736x_gpio_set(index, 0);
	199	}
	200
6cad56fd	201	static int pc8736x_gpio_current(unsigned minor)
681a3e7d	202	{
6cad56fd JC	203	int port, bit;
	204	minor &= 0x1f;
	205	port = minor >> 3;
	206	bit = minor & 7;
	207	return ((pc8736x_gpio_shadow[port] >> bit) & 0x01);
681a3e7d JC	208	}
	209
	210	static void pc8736x_gpio_change(unsigned index)
	211	{
6cad56fd	212	pc8736x_gpio_set(index, !pc8736x_gpio_current(index));
681a3e7d JC	213	}
681a3e7d JC	214
681a3e7d JC	215	static struct nsc_gpio_ops pc8736x_access = {
	216	.owner = THIS_MODULE,
	217	.gpio_config = pc8736x_gpio_configure,
	218	.gpio_dump = nsc_gpio_dump,
	219	.gpio_get = pc8736x_gpio_get,
	220	.gpio_set = pc8736x_gpio_set,
	221	.gpio_set_high = pc8736x_gpio_set_high,
	222	.gpio_set_low = pc8736x_gpio_set_low,
	223	.gpio_change = pc8736x_gpio_change,
	224	.gpio_current = pc8736x_gpio_current
	225	};
	226
	227	static int pc8736x_gpio_open(struct inode inode, struct file file)
	228	{
	229	unsigned m = iminor(inode);
	230	file->private_data = &pc8736x_access;
	231
58b087cd	232	dev_dbg(&pdev->dev, "open %d\n", m);
681a3e7d JC	233
	234	if (m > 63)
	235	return -EINVAL;
	236	return nonseekable_open(inode, file);
	237	}
	238
	239	static struct file_operations pc8736x_gpio_fops = {
58b087cd JC	240	.owner = THIS_MODULE,
	241	.open = pc8736x_gpio_open,
	242	.write = nsc_gpio_write,
	243	.read = nsc_gpio_read,
681a3e7d JC	244	};
681a3e7d JC	245
6cad56fd JC	246	static void __init pc8736x_init_shadow(void)
	247	{
	248	int port;
	249
	250	/* read the current values driven on the GPIO signals */
	251	for (port = 0; port < 4; ++port)
	252	pc8736x_gpio_shadow[port]
	253	= inb_p(pc8736x_gpio_base + port_offset[port]
	254	+ PORT_OUT);
	255
	256	}
	257
681a3e7d JC	258	static int __init pc8736x_gpio_init(void)
681a3e7d JC	259	{
58b087cd JC	260	int rc = 0;
	261
	262	pdev = platform_device_alloc(DEVNAME, 0);
	263	if (!pdev)
	264	return -ENOMEM;
681a3e7d	265
58b087cd JC	266	rc = platform_device_add(pdev);
	267	if (rc) {
	268	rc = -ENODEV;
	269	goto undo_platform_dev_alloc;
	270	}
	271	dev_info(&pdev->dev, "NatSemi pc8736x GPIO Driver Initializing\n");
681a3e7d JC	272
681a3e7d JC	273	if (!pc8736x_superio_present()) {
58b087cd JC	274	rc = -ENODEV;
	275	dev_err(&pdev->dev, "no device found\n");
	276	goto undo_platform_dev_add;
681a3e7d	277	}
f31000e5	278	pc8736x_access.dev = &pdev->dev;
681a3e7d JC	279
	280	/* Verify that chip and it's GPIO unit are both enabled.
	281	My BIOS does this, so I take minimum action here
	282	*/
	283	rc = superio_inb(SIO_CF1);
	284	if (!(rc & 0x01)) {
58b087cd JC	285	rc = -ENODEV;
	286	dev_err(&pdev->dev, "device not enabled\n");
	287	goto undo_platform_dev_add;
681a3e7d JC	288	}
	289	device_select(SIO_GPIO_UNIT);
	290	if (!superio_inb(SIO_UNIT_ACT)) {
58b087cd JC	291	rc = -ENODEV;
	292	dev_err(&pdev->dev, "GPIO unit not enabled\n");
	293	goto undo_platform_dev_add;
681a3e7d JC	294	}
681a3e7d JC	295
58b087cd	296	/* read the GPIO unit base addr that chip responds to */
681a3e7d JC	297	pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
	298	\| superio_inb(SIO_BASE_LADDR));
	299
58b087cd JC	300	if (!request_region(pc8736x_gpio_base, 16, DEVNAME)) {
	301	rc = -ENODEV;
	302	dev_err(&pdev->dev, "GPIO ioport %x busy\n",
	303	pc8736x_gpio_base);
	304	goto undo_platform_dev_add;
	305	}
	306	dev_info(&pdev->dev, "GPIO ioport %x reserved\n", pc8736x_gpio_base);
681a3e7d	307
58b087cd JC	308	rc = register_chrdev(major, DEVNAME, &pc8736x_gpio_fops);
	309	if (rc < 0) {
	310	dev_err(&pdev->dev, "register-chrdev failed: %d\n", rc);
	311	goto undo_platform_dev_add;
681a3e7d JC	312	}
681a3e7d JC	313	if (!major) {
58b087cd JC	314	major = rc;
58b087cd JC	315	dev_dbg(&pdev->dev, "got dynamic major %d\n", major);
681a3e7d JC	316	}
	317
	318	pc8736x_init_shadow();
	319	return 0;
58b087cd JC	320
	321	undo_platform_dev_add:
	322	platform_device_put(pdev);
	323	undo_platform_dev_alloc:
	324	kfree(pdev);
	325	return rc;
681a3e7d JC	326	}
	327
	328	static void __exit pc8736x_gpio_cleanup(void)
	329	{
58b087cd	330	dev_dbg(&pdev->dev, " cleanup\n");
681a3e7d JC	331
	332	release_region(pc8736x_gpio_base, 16);
	333
58b087cd	334	unregister_chrdev(major, DEVNAME);
681a3e7d JC	335	}
681a3e7d JC	336
6cad56fd JC	337	EXPORT_SYMBOL(pc8736x_access);
6cad56fd JC	338
681a3e7d JC	339	module_init(pc8736x_gpio_init);
681a3e7d JC	340	module_exit(pc8736x_gpio_cleanup);