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char: select fw_loader by moxa
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / mxser.c
CommitLineData
1da177e4
LT		 1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 *
80ff8a80
JS		 4 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
5 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
1da177e4 6 *
1c45607a
JS		 7 * This code is loosely based on the 1.8 moxa driver which is based on
8 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
9 * others.
1da177e4
LT		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
8ea2c2ec 14 * (at your option) any later version.
1da177e4 15 *
1da177e4
LT		 16 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
17 * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com.
18 * - Fixed x86_64 cleanness
19 * - Fixed sleep with spinlock held in mxser_send_break
20 */
21
1da177e4 22#include <linux/module.h>
1da177e4
LT		 23#include <linux/errno.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/timer.h>
27#include <linux/interrupt.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/serial.h>
31#include <linux/serial_reg.h>
32#include <linux/major.h>
33#include <linux/string.h>
34#include <linux/fcntl.h>
35#include <linux/ptrace.h>
36#include <linux/gfp.h>
37#include <linux/ioport.h>
38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/delay.h>
40#include <linux/pci.h>
1977f032 41#include <linux/bitops.h>
1da177e4
LT		 42
43#include <asm/system.h>
44#include <asm/io.h>
45#include <asm/irq.h>
1da177e4
LT		 46#include <asm/uaccess.h>
47
48#include "mxser.h"
49
80ff8a80 50#define MXSER_VERSION "2.0.3" /* 1.11 */
1da177e4
LT		 51#define MXSERMAJOR 174
52#define MXSERCUMAJOR 175
53
1da177e4 54#define MXSER_BOARDS 4 /* Max. boards */
1da177e4 55#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
1c45607a
JS		 56#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
57#define MXSER_ISR_PASS_LIMIT 100
1da177e4
LT		 58
59#define MXSER_ERR_IOADDR -1
60#define MXSER_ERR_IRQ -2
61#define MXSER_ERR_IRQ_CONFLIT -3
62#define MXSER_ERR_VECTOR -4
63
1c45607a
JS		 64/*CheckIsMoxaMust return value*/
65#define MOXA_OTHER_UART 0x00
66#define MOXA_MUST_MU150_HWID 0x01
67#define MOXA_MUST_MU860_HWID 0x02
68
1da177e4
LT		 69#define WAKEUP_CHARS 256
70
71#define UART_MCR_AFE 0x20
72#define UART_LSR_SPECIAL 0x1E
73
1c45607a
JS		 74#define PCI_DEVICE_ID_CB108 0x1080
75#define PCI_DEVICE_ID_CB114 0x1142
80ff8a80 76#define PCI_DEVICE_ID_CP114UL 0x1143
1c45607a
JS		 77#define PCI_DEVICE_ID_CB134I 0x1341
78#define PCI_DEVICE_ID_CP138U 0x1380
79#define PCI_DEVICE_ID_POS104UL 0x1044
1da177e4 80
1da177e4
LT		 81
82#define C168_ASIC_ID 1
83#define C104_ASIC_ID 2
84#define C102_ASIC_ID 0xB
85#define CI132_ASIC_ID 4
86#define CI134_ASIC_ID 3
87#define CI104J_ASIC_ID 5
88
1c45607a
JS		 89#define MXSER_HIGHBAUD 1
90#define MXSER_HAS2 2
1da177e4 91
8ea2c2ec 92/* This is only for PCI */
1c45607a 93static const struct {
1da177e4
LT		 94 int type;
95 int tx_fifo;
96 int rx_fifo;
97 int xmit_fifo_size;
98 int rx_high_water;
99 int rx_trigger;
100 int rx_low_water;
101 long max_baud;
1c45607a 102} Gpci_uart_info[] = {
1da177e4
LT		 103 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
104 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
105 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
106};
1c45607a 107#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
1da177e4 108
1c45607a
JS		 109struct mxser_cardinfo {
110 char *name;
111 unsigned int nports;
112 unsigned int flags;
113};
1da177e4 114
1c45607a
JS		 115static const struct mxser_cardinfo mxser_cards[] = {
116/* 0*/ { "C168 series", 8, },
117 { "C104 series", 4, },
118 { "CI-104J series", 4, },
119 { "C168H/PCI series", 8, },
120 { "C104H/PCI series", 4, },
121/* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */
122 { "CI-132 series", 4, MXSER_HAS2 },
123 { "CI-134 series", 4, },
124 { "CP-132 series", 2, },
125 { "CP-114 series", 4, },
126/*10*/ { "CT-114 series", 4, },
127 { "CP-102 series", 2, MXSER_HIGHBAUD },
128 { "CP-104U series", 4, },
129 { "CP-168U series", 8, },
130 { "CP-132U series", 2, },
131/*15*/ { "CP-134U series", 4, },
132 { "CP-104JU series", 4, },
133 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
134 { "CP-118U series", 8, },
135 { "CP-102UL series", 2, },
136/*20*/ { "CP-102U series", 2, },
137 { "CP-118EL series", 8, },
138 { "CP-168EL series", 8, },
139 { "CP-104EL series", 4, },
140 { "CB-108 series", 8, },
141/*25*/ { "CB-114 series", 4, },
142 { "CB-134I series", 4, },
143 { "CP-138U series", 8, },
80ff8a80
JS		 144 { "POS-104UL series", 4, },
145 { "CP-114UL series", 4, }
1c45607a 146};
1da177e4 147
1c45607a
JS		 148/* driver_data correspond to the lines in the structure above
149 see also ISA probe function before you change something */
1da177e4 150static struct pci_device_id mxser_pcibrds[] = {
1c45607a
JS		 151 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 },
152 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
153 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 },
154 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 },
155 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 },
156 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 },
157 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 },
158 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 },
159 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 },
160 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 },
161 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
162 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 },
163 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 },
164 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
165 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 },
166 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
167 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
168 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
169 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 },
170 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 },
171 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 },
172 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 },
173 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 },
80ff8a80 174 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 29 },
1c45607a 175 { }
1da177e4 176};
1da177e4
LT		 177MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
178
1da177e4
LT		 179static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 };
180static int ttymajor = MXSERMAJOR;
1da177e4
LT		 181
182/* Variables for insmod */
183
184MODULE_AUTHOR("Casper Yang");
185MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
8d3b33f6
RR		 186module_param_array(ioaddr, int, NULL, 0);
187module_param(ttymajor, int, 0);
1da177e4
LT		 188MODULE_LICENSE("GPL");
189
190struct mxser_log {
191 int tick;
192 unsigned long rxcnt[MXSER_PORTS];
193 unsigned long txcnt[MXSER_PORTS];
194};
195
196
197struct mxser_mon {
198 unsigned long rxcnt;
199 unsigned long txcnt;
200 unsigned long up_rxcnt;
201 unsigned long up_txcnt;
202 int modem_status;
203 unsigned char hold_reason;
204};
205
206struct mxser_mon_ext {
207 unsigned long rx_cnt[32];
208 unsigned long tx_cnt[32];
209 unsigned long up_rxcnt[32];
210 unsigned long up_txcnt[32];
211 int modem_status[32];
212
213 long baudrate[32];
214 int databits[32];
215 int stopbits[32];
216 int parity[32];
217 int flowctrl[32];
218 int fifo[32];
219 int iftype[32];
220};
8ea2c2ec 221
1c45607a
JS		 222struct mxser_board;
223
224struct mxser_port {
225 struct mxser_board *board;
226 struct tty_struct *tty;
227
228 unsigned long ioaddr;
229 unsigned long opmode_ioaddr;
230 int max_baud;
1da177e4 231
1da177e4
LT		 232 int rx_high_water;
233 int rx_trigger; /* Rx fifo trigger level */
234 int rx_low_water;
235 int baud_base; /* max. speed */
1da177e4 236 int type; /* UART type */
1c45607a
JS		 237 int flags; /* defined in tty.h */
238
1da177e4 239 int x_char; /* xon/xoff character */
1da177e4
LT		 240 int IER; /* Interrupt Enable Register */
241 int MCR; /* Modem control register */
1c45607a
JS		 242
243 unsigned char stop_rx;
244 unsigned char ldisc_stop_rx;
245
246 int custom_divisor;
247 int close_delay;
248 unsigned short closing_wait;
249 unsigned char err_shadow;
1da177e4 250 unsigned long event;
1c45607a 251
1da177e4
LT		 252 int count; /* # of fd on device */
253 int blocked_open; /* # of blocked opens */
1c45607a
JS		 254 struct async_icount icount; /* kernel counters for 4 input interrupts */
255 int timeout;
256
257 int read_status_mask;
258 int ignore_status_mask;
259 int xmit_fifo_size;
1da177e4
LT		 260 unsigned char *xmit_buf;
261 int xmit_head;
262 int xmit_tail;
263 int xmit_cnt;
1c45607a 264
606d099c 265 struct ktermios normal_termios;
1c45607a 266
1da177e4 267 struct mxser_mon mon_data;
1c45607a 268
1da177e4 269 spinlock_t slock;
1c45607a
JS		 270 wait_queue_head_t open_wait;
271 wait_queue_head_t delta_msr_wait;
272};
273
274struct mxser_board {
275 unsigned int idx;
276 int irq;
277 const struct mxser_cardinfo *info;
278 unsigned long vector;
279 unsigned long vector_mask;
280
281 int chip_flag;
282 int uart_type;
283
284 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
1da177e4
LT		 285};
286
1da177e4
LT		 287struct mxser_mstatus {
288 tcflag_t cflag;
289 int cts;
290 int dsr;
291 int ri;
292 int dcd;
293};
294
295static struct mxser_mstatus GMStatus[MXSER_PORTS];
296
297static int mxserBoardCAP[MXSER_BOARDS] = {
298 0, 0, 0, 0
8ea2c2ec 299 /* 0x180, 0x280, 0x200, 0x320 */
1da177e4
LT		 300};
301
1c45607a 302static struct mxser_board mxser_boards[MXSER_BOARDS];
1da177e4 303static struct tty_driver *mxvar_sdriver;
1da177e4
LT		 304static struct mxser_log mxvar_log;
305static int mxvar_diagflag;
306static unsigned char mxser_msr[MXSER_PORTS + 1];
307static struct mxser_mon_ext mon_data_ext;
308static int mxser_set_baud_method[MXSER_PORTS + 1];
1da177e4 309
148ff86b
CH		 310static void mxser_enable_must_enchance_mode(unsigned long baseio)
311{
312 u8 oldlcr;
313 u8 efr;
314
315 oldlcr = inb(baseio + UART_LCR);
316 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
317
318 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
319 efr |= MOXA_MUST_EFR_EFRB_ENABLE;
320
321 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
322 outb(oldlcr, baseio + UART_LCR);
323}
324
325static void mxser_disable_must_enchance_mode(unsigned long baseio)
326{
327 u8 oldlcr;
328 u8 efr;
329
330 oldlcr = inb(baseio + UART_LCR);
331 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
332
333 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
334 efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
335
336 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
337 outb(oldlcr, baseio + UART_LCR);
338}
339
340static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
341{
342 u8 oldlcr;
343 u8 efr;
344
345 oldlcr = inb(baseio + UART_LCR);
346 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
347
348 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
349 efr &= ~MOXA_MUST_EFR_BANK_MASK;
350 efr |= MOXA_MUST_EFR_BANK0;
351
352 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
353 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
354 outb(oldlcr, baseio + UART_LCR);
355}
356
357static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
358{
359 u8 oldlcr;
360 u8 efr;
361
362 oldlcr = inb(baseio + UART_LCR);
363 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
364
365 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
366 efr &= ~MOXA_MUST_EFR_BANK_MASK;
367 efr |= MOXA_MUST_EFR_BANK0;
368
369 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
370 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
371 outb(oldlcr, baseio + UART_LCR);
372}
373
374static void mxser_set_must_fifo_value(struct mxser_port *info)
375{
376 u8 oldlcr;
377 u8 efr;
378
379 oldlcr = inb(info->ioaddr + UART_LCR);
380 outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
381
382 efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
383 efr &= ~MOXA_MUST_EFR_BANK_MASK;
384 efr |= MOXA_MUST_EFR_BANK1;
385
386 outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
387 outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
388 outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
389 outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
390 outb(oldlcr, info->ioaddr + UART_LCR);
391}
392
393static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
394{
395 u8 oldlcr;
396 u8 efr;
397
398 oldlcr = inb(baseio + UART_LCR);
399 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
400
401 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
402 efr &= ~MOXA_MUST_EFR_BANK_MASK;
403 efr |= MOXA_MUST_EFR_BANK2;
404
405 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
406 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
407 outb(oldlcr, baseio + UART_LCR);
408}
409
410static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
411{
412 u8 oldlcr;
413 u8 efr;
414
415 oldlcr = inb(baseio + UART_LCR);
416 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
417
418 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
419 efr &= ~MOXA_MUST_EFR_BANK_MASK;
420 efr |= MOXA_MUST_EFR_BANK2;
421
422 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
423 *pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
424 outb(oldlcr, baseio + UART_LCR);
425}
426
427static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
428{
429 u8 oldlcr;
430 u8 efr;
431
432 oldlcr = inb(baseio + UART_LCR);
433 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
434
435 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
436 efr &= ~MOXA_MUST_EFR_SF_MASK;
437
438 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
439 outb(oldlcr, baseio + UART_LCR);
440}
441
442static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
443{
444 u8 oldlcr;
445 u8 efr;
446
447 oldlcr = inb(baseio + UART_LCR);
448 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
449
450 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
451 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
452 efr |= MOXA_MUST_EFR_SF_TX1;
453
454 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
455 outb(oldlcr, baseio + UART_LCR);
456}
457
458static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
459{
460 u8 oldlcr;
461 u8 efr;
462
463 oldlcr = inb(baseio + UART_LCR);
464 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
465
466 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
467 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
468
469 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
470 outb(oldlcr, baseio + UART_LCR);
471}
472
473static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
474{
475 u8 oldlcr;
476 u8 efr;
477
478 oldlcr = inb(baseio + UART_LCR);
479 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
480
481 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
482 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
483 efr |= MOXA_MUST_EFR_SF_RX1;
484
485 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
486 outb(oldlcr, baseio + UART_LCR);
487}
488
489static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
490{
491 u8 oldlcr;
492 u8 efr;
493
494 oldlcr = inb(baseio + UART_LCR);
495 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
496
497 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
498 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
499
500 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
501 outb(oldlcr, baseio + UART_LCR);
502}
503
b8cc5549 504#ifdef CONFIG_PCI
1c45607a 505static int __devinit CheckIsMoxaMust(unsigned long io)
1da177e4
LT		 506{
507 u8 oldmcr, hwid;
508 int i;
509
510 outb(0, io + UART_LCR);
148ff86b 511 mxser_disable_must_enchance_mode(io);
1da177e4
LT		 512 oldmcr = inb(io + UART_MCR);
513 outb(0, io + UART_MCR);
148ff86b 514 mxser_set_must_xon1_value(io, 0x11);
1da177e4
LT		 515 if ((hwid = inb(io + UART_MCR)) != 0) {
516 outb(oldmcr, io + UART_MCR);
8ea2c2ec 517 return MOXA_OTHER_UART;
1da177e4
LT		 518 }
519
148ff86b 520 mxser_get_must_hardware_id(io, &hwid);
1c45607a
JS		 521 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
522 if (hwid == Gpci_uart_info[i].type)
8ea2c2ec 523 return (int)hwid;
1da177e4
LT		 524 }
525 return MOXA_OTHER_UART;
526}
b8cc5549 527#endif
1da177e4 528
1c45607a 529static void process_txrx_fifo(struct mxser_port *info)
1da177e4
LT		 530{
531 int i;
532
533 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
534 info->rx_trigger = 1;
535 info->rx_high_water = 1;
536 info->rx_low_water = 1;
537 info->xmit_fifo_size = 1;
1c45607a
JS		 538 } else
539 for (i = 0; i < UART_INFO_NUM; i++)
540 if (info->board->chip_flag == Gpci_uart_info[i].type) {
1da177e4
LT		 541 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
542 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
543 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
544 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
545 break;
546 }
1da177e4
LT		 547}
548
1c45607a 549static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
1da177e4 550{
1c45607a 551 unsigned char status = 0;
1da177e4 552
1c45607a 553 status = inb(baseaddr + UART_MSR);
1da177e4 554
1c45607a
JS		 555 mxser_msr[port] &= 0x0F;
556 mxser_msr[port] |= status;
557 status = mxser_msr[port];
558 if (mode)
559 mxser_msr[port] = 0;
1da177e4 560
1c45607a
JS		 561 return status;
562}
1da177e4 563
1c45607a
JS		 564static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp,
565 struct mxser_port *port)
566{
567 DECLARE_WAITQUEUE(wait, current);
568 int retval;
569 int do_clocal = 0;
570 unsigned long flags;
1da177e4 571
1c45607a
JS		 572 /*
573 * If non-blocking mode is set, or the port is not enabled,
574 * then make the check up front and then exit.
575 */
576 if ((filp->f_flags & O_NONBLOCK) ||
577 test_bit(TTY_IO_ERROR, &tty->flags)) {
578 port->flags |= ASYNC_NORMAL_ACTIVE;
579 return 0;
580 }
1da177e4 581
1c45607a
JS		 582 if (tty->termios->c_cflag & CLOCAL)
583 do_clocal = 1;
1da177e4 584
1da177e4 585 /*
1c45607a
JS		 586 * Block waiting for the carrier detect and the line to become
587 * free (i.e., not in use by the callout). While we are in
588 * this loop, port->count is dropped by one, so that
589 * mxser_close() knows when to free things. We restore it upon
590 * exit, either normal or abnormal.
1da177e4 591 */
1c45607a
JS		 592 retval = 0;
593 add_wait_queue(&port->open_wait, &wait);
1da177e4 594
1c45607a
JS		 595 spin_lock_irqsave(&port->slock, flags);
596 if (!tty_hung_up_p(filp))
597 port->count--;
598 spin_unlock_irqrestore(&port->slock, flags);
599 port->blocked_open++;
600 while (1) {
601 spin_lock_irqsave(&port->slock, flags);
602 outb(inb(port->ioaddr + UART_MCR) |
603 UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR);
604 spin_unlock_irqrestore(&port->slock, flags);
605 set_current_state(TASK_INTERRUPTIBLE);
606 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)) {
607 if (port->flags & ASYNC_HUP_NOTIFY)
608 retval = -EAGAIN;
609 else
610 retval = -ERESTARTSYS;
611 break;
612 }
613 if (!(port->flags & ASYNC_CLOSING) &&
614 (do_clocal ||
615 (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD)))
616 break;
617 if (signal_pending(current)) {
618 retval = -ERESTARTSYS;
619 break;
620 }
621 schedule();
1da177e4 622 }
1c45607a
JS		 623 set_current_state(TASK_RUNNING);
624 remove_wait_queue(&port->open_wait, &wait);
625 if (!tty_hung_up_p(filp))
626 port->count++;
627 port->blocked_open--;
628 if (retval)
1da177e4 629 return retval;
1c45607a 630 port->flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 631 return 0;
632}
633
1c45607a 634static int mxser_set_baud(struct mxser_port *info, long newspd)
1da177e4 635{
1c45607a
JS		 636 int quot = 0, baud;
637 unsigned char cval;
1da177e4 638
1c45607a
JS		 639 if (!info->tty || !info->tty->termios)
640 return -1;
1da177e4 641
1c45607a
JS		 642 if (!(info->ioaddr))
643 return -1;
1da177e4 644
1c45607a
JS		 645 if (newspd > info->max_baud)
646 return -1;
1da177e4 647
1c45607a
JS		 648 if (newspd == 134) {
649 quot = 2 * info->baud_base / 269;
650 tty_encode_baud_rate(info->tty, 134, 134);
651 } else if (newspd) {
652 quot = info->baud_base / newspd;
653 if (quot == 0)
654 quot = 1;
655 baud = info->baud_base/quot;
656 tty_encode_baud_rate(info->tty, baud, baud);
657 } else {
658 quot = 0;
659 }
1da177e4 660
1c45607a
JS		 661 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
662 info->timeout += HZ / 50; /* Add .02 seconds of slop */
1da177e4 663
1c45607a
JS		 664 if (quot) {
665 info->MCR |= UART_MCR_DTR;
666 outb(info->MCR, info->ioaddr + UART_MCR);
667 } else {
668 info->MCR &= ~UART_MCR_DTR;
669 outb(info->MCR, info->ioaddr + UART_MCR);
670 return 0;
671 }
1da177e4 672
1c45607a 673 cval = inb(info->ioaddr + UART_LCR);
1da177e4 674
1c45607a 675 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
1da177e4 676
1c45607a
JS		 677 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
678 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
679 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
1da177e4 680
1c45607a
JS		 681#ifdef BOTHER
682 if (C_BAUD(info->tty) == BOTHER) {
683 quot = info->baud_base % newspd;
684 quot *= 8;
685 if (quot % newspd > newspd / 2) {
686 quot /= newspd;
687 quot++;
688 } else
689 quot /= newspd;
690
148ff86b 691 mxser_set_must_enum_value(info->ioaddr, quot);
1c45607a
JS		 692 } else
693#endif
148ff86b 694 mxser_set_must_enum_value(info->ioaddr, 0);
1da177e4 695
8ea2c2ec 696 return 0;
1da177e4 697}
1da177e4 698
1c45607a
JS		 699/*
700 * This routine is called to set the UART divisor registers to match
701 * the specified baud rate for a serial port.
702 */
703static int mxser_change_speed(struct mxser_port *info,
704 struct ktermios *old_termios)
1da177e4 705{
1c45607a
JS		 706 unsigned cflag, cval, fcr;
707 int ret = 0;
708 unsigned char status;
1da177e4 709
1c45607a
JS		 710 if (!info->tty || !info->tty->termios)
711 return ret;
712 cflag = info->tty->termios->c_cflag;
713 if (!(info->ioaddr))
714 return ret;
1da177e4 715
1c45607a
JS		 716 if (mxser_set_baud_method[info->tty->index] == 0)
717 mxser_set_baud(info, tty_get_baud_rate(info->tty));
1da177e4 718
1c45607a
JS		 719 /* byte size and parity */
720 switch (cflag & CSIZE) {
721 case CS5:
722 cval = 0x00;
723 break;
724 case CS6:
725 cval = 0x01;
726 break;
727 case CS7:
728 cval = 0x02;
729 break;
730 case CS8:
731 cval = 0x03;
732 break;
733 default:
734 cval = 0x00;
735 break; /* too keep GCC shut... */
736 }
737 if (cflag & CSTOPB)
738 cval |= 0x04;
739 if (cflag & PARENB)
740 cval |= UART_LCR_PARITY;
741 if (!(cflag & PARODD))
742 cval |= UART_LCR_EPAR;
743 if (cflag & CMSPAR)
744 cval |= UART_LCR_SPAR;
1da177e4 745
1c45607a
JS		 746 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
747 if (info->board->chip_flag) {
748 fcr = UART_FCR_ENABLE_FIFO;
749 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 750 mxser_set_must_fifo_value(info);
1c45607a
JS		 751 } else
752 fcr = 0;
753 } else {
754 fcr = UART_FCR_ENABLE_FIFO;
755 if (info->board->chip_flag) {
756 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 757 mxser_set_must_fifo_value(info);
1c45607a
JS		 758 } else {
759 switch (info->rx_trigger) {
760 case 1:
761 fcr |= UART_FCR_TRIGGER_1;
762 break;
763 case 4:
764 fcr |= UART_FCR_TRIGGER_4;
765 break;
766 case 8:
767 fcr |= UART_FCR_TRIGGER_8;
768 break;
769 default:
770 fcr |= UART_FCR_TRIGGER_14;
771 break;
772 }
1da177e4 773 }
1da177e4
LT		 774 }
775
1c45607a
JS		 776 /* CTS flow control flag and modem status interrupts */
777 info->IER &= ~UART_IER_MSI;
778 info->MCR &= ~UART_MCR_AFE;
779 if (cflag & CRTSCTS) {
780 info->flags |= ASYNC_CTS_FLOW;
781 info->IER |= UART_IER_MSI;
782 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
783 info->MCR |= UART_MCR_AFE;
784 } else {
785 status = inb(info->ioaddr + UART_MSR);
786 if (info->tty->hw_stopped) {
787 if (status & UART_MSR_CTS) {
788 info->tty->hw_stopped = 0;
789 if (info->type != PORT_16550A &&
790 !info->board->chip_flag) {
791 outb(info->IER & ~UART_IER_THRI,
792 info->ioaddr +
793 UART_IER);
794 info->IER |= UART_IER_THRI;
795 outb(info->IER, info->ioaddr +
796 UART_IER);
797 }
798 tty_wakeup(info->tty);
799 }
800 } else {
801 if (!(status & UART_MSR_CTS)) {
802 info->tty->hw_stopped = 1;
803 if ((info->type != PORT_16550A) &&
804 (!info->board->chip_flag)) {
805 info->IER &= ~UART_IER_THRI;
806 outb(info->IER, info->ioaddr +
807 UART_IER);
808 }
809 }
810 }
1da177e4 811 }
1c45607a
JS		 812 } else {
813 info->flags &= ~ASYNC_CTS_FLOW;
814 }
815 outb(info->MCR, info->ioaddr + UART_MCR);
816 if (cflag & CLOCAL) {
817 info->flags &= ~ASYNC_CHECK_CD;
818 } else {
819 info->flags |= ASYNC_CHECK_CD;
820 info->IER |= UART_IER_MSI;
821 }
822 outb(info->IER, info->ioaddr + UART_IER);
823
824 /*
825 * Set up parity check flag
826 */
827 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
828 if (I_INPCK(info->tty))
829 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
830 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
831 info->read_status_mask |= UART_LSR_BI;
1da177e4 832
1c45607a 833 info->ignore_status_mask = 0;
1da177e4 834
1c45607a
JS		 835 if (I_IGNBRK(info->tty)) {
836 info->ignore_status_mask |= UART_LSR_BI;
837 info->read_status_mask |= UART_LSR_BI;
8ea2c2ec 838 /*
1c45607a
JS		 839 * If we're ignore parity and break indicators, ignore
840 * overruns too. (For real raw support).
8ea2c2ec 841 */
1c45607a
JS		 842 if (I_IGNPAR(info->tty)) {
843 info->ignore_status_mask |=
844 UART_LSR_OE |
845 UART_LSR_PE |
846 UART_LSR_FE;
847 info->read_status_mask |=
848 UART_LSR_OE |
849 UART_LSR_PE |
850 UART_LSR_FE;
851 }
1da177e4 852 }
1c45607a 853 if (info->board->chip_flag) {
148ff86b
CH		 854 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(info->tty));
855 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(info->tty));
1c45607a 856 if (I_IXON(info->tty)) {
148ff86b
CH		 857 mxser_enable_must_rx_software_flow_control(
858 info->ioaddr);
1c45607a 859 } else {
148ff86b
CH		 860 mxser_disable_must_rx_software_flow_control(
861 info->ioaddr);
1da177e4 862 }
1c45607a 863 if (I_IXOFF(info->tty)) {
148ff86b
CH		 864 mxser_enable_must_tx_software_flow_control(
865 info->ioaddr);
1c45607a 866 } else {
148ff86b
CH		 867 mxser_disable_must_tx_software_flow_control(
868 info->ioaddr);
1da177e4
LT		 869 }
870 }
1da177e4 871
1da177e4 872
1c45607a
JS		 873 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
874 outb(cval, info->ioaddr + UART_LCR);
1da177e4 875
1c45607a 876 return ret;
1da177e4
LT		 877}
878
1c45607a 879static void mxser_check_modem_status(struct mxser_port *port, int status)
1da177e4 880{
1c45607a
JS		 881 /* update input line counters */
882 if (status & UART_MSR_TERI)
883 port->icount.rng++;
884 if (status & UART_MSR_DDSR)
885 port->icount.dsr++;
886 if (status & UART_MSR_DDCD)
887 port->icount.dcd++;
888 if (status & UART_MSR_DCTS)
889 port->icount.cts++;
890 port->mon_data.modem_status = status;
891 wake_up_interruptible(&port->delta_msr_wait);
1da177e4 892
1c45607a
JS		 893 if ((port->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
894 if (status & UART_MSR_DCD)
895 wake_up_interruptible(&port->open_wait);
896 }
1da177e4 897
1c45607a
JS		 898 if (port->flags & ASYNC_CTS_FLOW) {
899 if (port->tty->hw_stopped) {
900 if (status & UART_MSR_CTS) {
901 port->tty->hw_stopped = 0;
902
903 if ((port->type != PORT_16550A) &&
904 (!port->board->chip_flag)) {
905 outb(port->IER & ~UART_IER_THRI,
906 port->ioaddr + UART_IER);
907 port->IER |= UART_IER_THRI;
908 outb(port->IER, port->ioaddr +
909 UART_IER);
910 }
911 tty_wakeup(port->tty);
912 }
913 } else {
914 if (!(status & UART_MSR_CTS)) {
915 port->tty->hw_stopped = 1;
916 if (port->type != PORT_16550A &&
917 !port->board->chip_flag) {
918 port->IER &= ~UART_IER_THRI;
919 outb(port->IER, port->ioaddr +
920 UART_IER);
921 }
922 }
923 }
1da177e4
LT		 924 }
925}
926
1c45607a 927static int mxser_startup(struct mxser_port *info)
1da177e4 928{
1c45607a
JS		 929 unsigned long page;
930 unsigned long flags;
1da177e4 931
1c45607a
JS		 932 page = __get_free_page(GFP_KERNEL);
933 if (!page)
934 return -ENOMEM;
1da177e4 935
1c45607a 936 spin_lock_irqsave(&info->slock, flags);
1da177e4 937
1c45607a
JS		 938 if (info->flags & ASYNC_INITIALIZED) {
939 free_page(page);
940 spin_unlock_irqrestore(&info->slock, flags);
941 return 0;
942 }
6f08b72c 943
1c45607a
JS		 944 if (!info->ioaddr || !info->type) {
945 if (info->tty)
946 set_bit(TTY_IO_ERROR, &info->tty->flags);
947 free_page(page);
948 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 949 return 0;
1c45607a
JS		 950 }
951 if (info->xmit_buf)
952 free_page(page);
953 else
954 info->xmit_buf = (unsigned char *) page;
1da177e4 955
1da177e4 956 /*
1c45607a
JS		 957 * Clear the FIFO buffers and disable them
958 * (they will be reenabled in mxser_change_speed())
1da177e4 959 */
1c45607a
JS		 960 if (info->board->chip_flag)
961 outb((UART_FCR_CLEAR_RCVR |
962 UART_FCR_CLEAR_XMIT |
963 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
964 else
965 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
966 info->ioaddr + UART_FCR);
1da177e4 967
1c45607a
JS		 968 /*
969 * At this point there's no way the LSR could still be 0xFF;
970 * if it is, then bail out, because there's likely no UART
971 * here.
972 */
973 if (inb(info->ioaddr + UART_LSR) == 0xff) {
974 spin_unlock_irqrestore(&info->slock, flags);
975 if (capable(CAP_SYS_ADMIN)) {
976 if (info->tty)
977 set_bit(TTY_IO_ERROR, &info->tty->flags);
978 return 0;
979 } else
980 return -ENODEV;
981 }
1da177e4 982
1c45607a
JS		 983 /*
984 * Clear the interrupt registers.
985 */
986 (void) inb(info->ioaddr + UART_LSR);
987 (void) inb(info->ioaddr + UART_RX);
988 (void) inb(info->ioaddr + UART_IIR);
989 (void) inb(info->ioaddr + UART_MSR);
990
991 /*
992 * Now, initialize the UART
993 */
994 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
995 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
996 outb(info->MCR, info->ioaddr + UART_MCR);
997
998 /*
999 * Finally, enable interrupts
1000 */
1001 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
1002
1003 if (info->board->chip_flag)
1004 info->IER |= MOXA_MUST_IER_EGDAI;
1005 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
1006
1007 /*
1008 * And clear the interrupt registers again for luck.
1009 */
1010 (void) inb(info->ioaddr + UART_LSR);
1011 (void) inb(info->ioaddr + UART_RX);
1012 (void) inb(info->ioaddr + UART_IIR);
1013 (void) inb(info->ioaddr + UART_MSR);
1014
1015 if (info->tty)
1016 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1017 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1018
1019 /*
1020 * and set the speed of the serial port
1021 */
1022 mxser_change_speed(info, NULL);
1023 info->flags |= ASYNC_INITIALIZED;
1024 spin_unlock_irqrestore(&info->slock, flags);
1025
1026 return 0;
1027}
1028
1029/*
1030 * This routine will shutdown a serial port; interrupts maybe disabled, and
1031 * DTR is dropped if the hangup on close termio flag is on.
1032 */
1033static void mxser_shutdown(struct mxser_port *info)
1034{
1035 unsigned long flags;
1036
1037 if (!(info->flags & ASYNC_INITIALIZED))
1038 return;
1039
1040 spin_lock_irqsave(&info->slock, flags);
1041
1042 /*
1043 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
1044 * here so the queue might never be waken up
1045 */
1046 wake_up_interruptible(&info->delta_msr_wait);
1047
1048 /*
1049 * Free the IRQ, if necessary
1050 */
1051 if (info->xmit_buf) {
1052 free_page((unsigned long) info->xmit_buf);
1053 info->xmit_buf = NULL;
1da177e4
LT		 1054 }
1055
1c45607a
JS		 1056 info->IER = 0;
1057 outb(0x00, info->ioaddr + UART_IER);
1058
1059 if (!info->tty || (info->tty->termios->c_cflag & HUPCL))
1060 info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS);
1061 outb(info->MCR, info->ioaddr + UART_MCR);
1062
1063 /* clear Rx/Tx FIFO's */
1064 if (info->board->chip_flag)
1065 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
1066 MOXA_MUST_FCR_GDA_MODE_ENABLE,
1067 info->ioaddr + UART_FCR);
1068 else
1069 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1070 info->ioaddr + UART_FCR);
1071
1072 /* read data port to reset things */
1073 (void) inb(info->ioaddr + UART_RX);
1074
1075 if (info->tty)
1076 set_bit(TTY_IO_ERROR, &info->tty->flags);
1077
1078 info->flags &= ~ASYNC_INITIALIZED;
1079
1080 if (info->board->chip_flag)
1081 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
1082
1083 spin_unlock_irqrestore(&info->slock, flags);
1084}
1085
1086/*
1087 * This routine is called whenever a serial port is opened. It
1088 * enables interrupts for a serial port, linking in its async structure into
1089 * the IRQ chain. It also performs the serial-specific
1090 * initialization for the tty structure.
1091 */
1092static int mxser_open(struct tty_struct *tty, struct file *filp)
1093{
1094 struct mxser_port *info;
1095 unsigned long flags;
1096 int retval, line;
1097
1098 line = tty->index;
1099 if (line == MXSER_PORTS)
1100 return 0;
1101 if (line < 0 || line > MXSER_PORTS)
1102 return -ENODEV;
1103 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
1104 if (!info->ioaddr)
1105 return -ENODEV;
1106
1107 tty->driver_data = info;
1108 info->tty = tty;
8ea2c2ec 1109 /*
1c45607a
JS		 1110 * Start up serial port
1111 */
1112 spin_lock_irqsave(&info->slock, flags);
1113 info->count++;
1114 spin_unlock_irqrestore(&info->slock, flags);
1115 retval = mxser_startup(info);
1116 if (retval)
1117 return retval;
1118
1119 retval = mxser_block_til_ready(tty, filp, info);
1120 if (retval)
1121 return retval;
1da177e4 1122
8cddd707 1123 /* unmark here for very high baud rate (ex. 921600 bps) used */
1da177e4
LT		 1124 tty->low_latency = 1;
1125 return 0;
1126}
1127
978e595f
AC		 1128static void mxser_flush_buffer(struct tty_struct *tty)
1129{
1130 struct mxser_port *info = tty->driver_data;
1131 char fcr;
1132 unsigned long flags;
1133
1134
1135 spin_lock_irqsave(&info->slock, flags);
1136 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1137
1138 fcr = inb(info->ioaddr + UART_FCR);
1139 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1140 info->ioaddr + UART_FCR);
1141 outb(fcr, info->ioaddr + UART_FCR);
1142
1143 spin_unlock_irqrestore(&info->slock, flags);
1144
1145 tty_wakeup(tty);
1146}
1147
1148
1da177e4
LT		 1149/*
1150 * This routine is called when the serial port gets closed. First, we
1151 * wait for the last remaining data to be sent. Then, we unlink its
1152 * async structure from the interrupt chain if necessary, and we free
1153 * that IRQ if nothing is left in the chain.
1154 */
1155static void mxser_close(struct tty_struct *tty, struct file *filp)
1156{
1c45607a 1157 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1158
1159 unsigned long timeout;
1160 unsigned long flags;
1da177e4
LT		 1161
1162 if (tty->index == MXSER_PORTS)
1163 return;
1164 if (!info)
6f08b72c 1165 return;
1da177e4
LT		 1166
1167 spin_lock_irqsave(&info->slock, flags);
1168
1169 if (tty_hung_up_p(filp)) {
1170 spin_unlock_irqrestore(&info->slock, flags);
1171 return;
1172 }
1173 if ((tty->count == 1) && (info->count != 1)) {
1174 /*
1175 * Uh, oh. tty->count is 1, which means that the tty
1176 * structure will be freed. Info->count should always
1177 * be one in these conditions. If it's greater than
1178 * one, we've got real problems, since it means the
1179 * serial port won't be shutdown.
1180 */
8ea2c2ec
JJ		 1181 printk(KERN_ERR "mxser_close: bad serial port count; "
1182 "tty->count is 1, info->count is %d\n", info->count);
1da177e4
LT		 1183 info->count = 1;
1184 }
1185 if (--info->count < 0) {
8ea2c2ec 1186 printk(KERN_ERR "mxser_close: bad serial port count for "
1c45607a 1187 "ttys%d: %d\n", tty->index, info->count);
1da177e4
LT		 1188 info->count = 0;
1189 }
1190 if (info->count) {
1191 spin_unlock_irqrestore(&info->slock, flags);
1192 return;
1193 }
1194 info->flags |= ASYNC_CLOSING;
1195 spin_unlock_irqrestore(&info->slock, flags);
1196 /*
1197 * Save the termios structure, since this port may have
1198 * separate termios for callout and dialin.
1199 */
1200 if (info->flags & ASYNC_NORMAL_ACTIVE)
1201 info->normal_termios = *tty->termios;
1202 /*
1203 * Now we wait for the transmit buffer to clear; and we notify
1204 * the line discipline to only process XON/XOFF characters.
1205 */
1206 tty->closing = 1;
1207 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
1208 tty_wait_until_sent(tty, info->closing_wait);
1209 /*
1210 * At this point we stop accepting input. To do this, we
1211 * disable the receive line status interrupts, and tell the
1212 * interrupt driver to stop checking the data ready bit in the
1213 * line status register.
1214 */
1215 info->IER &= ~UART_IER_RLSI;
1c45607a 1216 if (info->board->chip_flag)
1da177e4 1217 info->IER &= ~MOXA_MUST_RECV_ISR;
1c45607a 1218
1da177e4 1219 if (info->flags & ASYNC_INITIALIZED) {
1c45607a 1220 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1221 /*
1222 * Before we drop DTR, make sure the UART transmitter
1223 * has completely drained; this is especially
1224 * important if there is a transmit FIFO!
1225 */
1226 timeout = jiffies + HZ;
1c45607a 1227 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
da4cd8df 1228 schedule_timeout_interruptible(5);
1da177e4
LT		 1229 if (time_after(jiffies, timeout))
1230 break;
1231 }
1232 }
1233 mxser_shutdown(info);
1234
978e595f 1235 mxser_flush_buffer(tty);
1c45607a
JS		 1236 tty_ldisc_flush(tty);
1237
1da177e4
LT		 1238 tty->closing = 0;
1239 info->event = 0;
1240 info->tty = NULL;
1241 if (info->blocked_open) {
da4cd8df
NA		 1242 if (info->close_delay)
1243 schedule_timeout_interruptible(info->close_delay);
1da177e4
LT		 1244 wake_up_interruptible(&info->open_wait);
1245 }
1246
1247 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING);
1da177e4
LT		 1248}
1249
1250static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1251{
1252 int c, total = 0;
1c45607a 1253 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1254 unsigned long flags;
1255
8a7f7c93 1256 if (!info->xmit_buf)
8ea2c2ec 1257 return 0;
1da177e4
LT		 1258
1259 while (1) {
8ea2c2ec
JJ		 1260 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1261 SERIAL_XMIT_SIZE - info->xmit_head));
1da177e4
LT		 1262 if (c <= 0)
1263 break;
1264
1265 memcpy(info->xmit_buf + info->xmit_head, buf, c);
1266 spin_lock_irqsave(&info->slock, flags);
8ea2c2ec
JJ		 1267 info->xmit_head = (info->xmit_head + c) &
1268 (SERIAL_XMIT_SIZE - 1);
1da177e4
LT		 1269 info->xmit_cnt += c;
1270 spin_unlock_irqrestore(&info->slock, flags);
1271
1272 buf += c;
1273 count -= c;
1274 total += c;
1da177e4
LT		 1275 }
1276
1c45607a 1277 if (info->xmit_cnt && !tty->stopped) {
8ea2c2ec
JJ		 1278 if (!tty->hw_stopped ||
1279 (info->type == PORT_16550A) ||
1c45607a 1280 (info->board->chip_flag)) {
1da177e4 1281 spin_lock_irqsave(&info->slock, flags);
1c45607a
JS		 1282 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1283 UART_IER);
1da177e4 1284 info->IER |= UART_IER_THRI;
1c45607a 1285 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1286 spin_unlock_irqrestore(&info->slock, flags);
1287 }
1288 }
1289 return total;
1290}
1291
0be2eade 1292static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1293{
1c45607a 1294 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1295 unsigned long flags;
1296
8a7f7c93 1297 if (!info->xmit_buf)
0be2eade 1298 return 0;
1da177e4
LT		 1299
1300 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
0be2eade 1301 return 0;
1da177e4
LT		 1302
1303 spin_lock_irqsave(&info->slock, flags);
1304 info->xmit_buf[info->xmit_head++] = ch;
1305 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1306 info->xmit_cnt++;
1307 spin_unlock_irqrestore(&info->slock, flags);
1c45607a 1308 if (!tty->stopped) {
8ea2c2ec
JJ		 1309 if (!tty->hw_stopped ||
1310 (info->type == PORT_16550A) ||
1c45607a 1311 info->board->chip_flag) {
1da177e4 1312 spin_lock_irqsave(&info->slock, flags);
1c45607a 1313 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1314 info->IER |= UART_IER_THRI;
1c45607a 1315 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1316 spin_unlock_irqrestore(&info->slock, flags);
1317 }
1318 }
0be2eade 1319 return 1;
1da177e4
LT		 1320}
1321
1322
1323static void mxser_flush_chars(struct tty_struct *tty)
1324{
1c45607a 1325 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1326 unsigned long flags;
1327
8ea2c2ec
JJ		 1328 if (info->xmit_cnt <= 0 ||
1329 tty->stopped ||
1330 !info->xmit_buf ||
1331 (tty->hw_stopped &&
1332 (info->type != PORT_16550A) &&
1c45607a 1333 (!info->board->chip_flag)
8ea2c2ec 1334 ))
1da177e4
LT		 1335 return;
1336
1337 spin_lock_irqsave(&info->slock, flags);
1338
1c45607a 1339 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1340 info->IER |= UART_IER_THRI;
1c45607a 1341 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1342
1343 spin_unlock_irqrestore(&info->slock, flags);
1344}
1345
1346static int mxser_write_room(struct tty_struct *tty)
1347{
1c45607a 1348 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1349 int ret;
1350
1351 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
1352 if (ret < 0)
1353 ret = 0;
8ea2c2ec 1354 return ret;
1da177e4
LT		 1355}
1356
1357static int mxser_chars_in_buffer(struct tty_struct *tty)
1358{
1c45607a 1359 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1360 return info->xmit_cnt;
1361}
1362
1c45607a
JS		 1363/*
1364 * ------------------------------------------------------------
1365 * friends of mxser_ioctl()
1366 * ------------------------------------------------------------
1367 */
1368static int mxser_get_serial_info(struct mxser_port *info,
1369 struct serial_struct __user *retinfo)
1370{
1371 struct serial_struct tmp = {
1372 .type = info->type,
1373 .line = info->tty->index,
1374 .port = info->ioaddr,
1375 .irq = info->board->irq,
1376 .flags = info->flags,
1377 .baud_base = info->baud_base,
1378 .close_delay = info->close_delay,
1379 .closing_wait = info->closing_wait,
1380 .custom_divisor = info->custom_divisor,
1381 .hub6 = 0
1382 };
1383 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
1384 return -EFAULT;
1385 return 0;
1386}
1387
1388static int mxser_set_serial_info(struct mxser_port *info,
1389 struct serial_struct __user *new_info)
1da177e4 1390{
1c45607a 1391 struct serial_struct new_serial;
80ff8a80 1392 speed_t baud;
1c45607a
JS		 1393 unsigned long sl_flags;
1394 unsigned int flags;
1395 int retval = 0;
1da177e4 1396
1c45607a 1397 if (!new_info || !info->ioaddr)
80ff8a80 1398 return -ENODEV;
1c45607a
JS		 1399 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
1400 return -EFAULT;
1da177e4 1401
80ff8a80
JS		 1402 if (new_serial.irq != info->board->irq ||
1403 new_serial.port != info->ioaddr)
1404 return -EINVAL;
1da177e4 1405
1c45607a 1406 flags = info->flags & ASYNC_SPD_MASK;
1da177e4 1407
1c45607a
JS		 1408 if (!capable(CAP_SYS_ADMIN)) {
1409 if ((new_serial.baud_base != info->baud_base) ||
1410 (new_serial.close_delay != info->close_delay) ||
1411 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK)))
1412 return -EPERM;
1413 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
1414 (new_serial.flags & ASYNC_USR_MASK));
1415 } else {
1da177e4 1416 /*
1c45607a
JS		 1417 * OK, past this point, all the error checking has been done.
1418 * At this point, we start making changes.....
1da177e4 1419 */
1c45607a
JS		 1420 info->flags = ((info->flags & ~ASYNC_FLAGS) |
1421 (new_serial.flags & ASYNC_FLAGS));
1422 info->close_delay = new_serial.close_delay * HZ / 100;
1423 info->closing_wait = new_serial.closing_wait * HZ / 100;
1424 info->tty->low_latency =
1425 (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1426 info->tty->low_latency = 0;
80ff8a80
JS		 1427 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
1428 (new_serial.baud_base != info->baud_base ||
1429 new_serial.custom_divisor !=
1430 info->custom_divisor)) {
1431 baud = new_serial.baud_base / new_serial.custom_divisor;
1432 tty_encode_baud_rate(info->tty, baud, baud);
1433 }
1c45607a 1434 }
fc83815c 1435
1c45607a 1436 info->type = new_serial.type;
1da177e4 1437
1c45607a
JS		 1438 process_txrx_fifo(info);
1439
1440 if (info->flags & ASYNC_INITIALIZED) {
1441 if (flags != (info->flags & ASYNC_SPD_MASK)) {
1442 spin_lock_irqsave(&info->slock, sl_flags);
1443 mxser_change_speed(info, NULL);
1444 spin_unlock_irqrestore(&info->slock, sl_flags);
1da177e4 1445 }
1c45607a
JS		 1446 } else
1447 retval = mxser_startup(info);
1da177e4 1448
1c45607a
JS		 1449 return retval;
1450}
1da177e4 1451
1c45607a
JS		 1452/*
1453 * mxser_get_lsr_info - get line status register info
1454 *
1455 * Purpose: Let user call ioctl() to get info when the UART physically
1456 * is emptied. On bus types like RS485, the transmitter must
1457 * release the bus after transmitting. This must be done when
1458 * the transmit shift register is empty, not be done when the
1459 * transmit holding register is empty. This functionality
1460 * allows an RS485 driver to be written in user space.
1461 */
1462static int mxser_get_lsr_info(struct mxser_port *info,
1463 unsigned int __user *value)
1464{
1465 unsigned char status;
1466 unsigned int result;
1467 unsigned long flags;
1da177e4 1468
1c45607a
JS		 1469 spin_lock_irqsave(&info->slock, flags);
1470 status = inb(info->ioaddr + UART_LSR);
1471 spin_unlock_irqrestore(&info->slock, flags);
1472 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1473 return put_user(result, value);
1474}
1da177e4 1475
1c45607a
JS		 1476/*
1477 * This routine sends a break character out the serial port.
1478 */
1479static void mxser_send_break(struct mxser_port *info, int duration)
1480{
1481 unsigned long flags;
1da177e4 1482
1c45607a
JS		 1483 if (!info->ioaddr)
1484 return;
1485 set_current_state(TASK_INTERRUPTIBLE);
1486 spin_lock_irqsave(&info->slock, flags);
1487 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
1488 info->ioaddr + UART_LCR);
1489 spin_unlock_irqrestore(&info->slock, flags);
1490 schedule_timeout(duration);
1491 spin_lock_irqsave(&info->slock, flags);
1492 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
1493 info->ioaddr + UART_LCR);
1494 spin_unlock_irqrestore(&info->slock, flags);
1495}
1da177e4 1496
1c45607a
JS		 1497static int mxser_tiocmget(struct tty_struct *tty, struct file *file)
1498{
1499 struct mxser_port *info = tty->driver_data;
1500 unsigned char control, status;
1501 unsigned long flags;
1da177e4 1502
8ea2c2ec 1503
1c45607a
JS		 1504 if (tty->index == MXSER_PORTS)
1505 return -ENOIOCTLCMD;
1506 if (test_bit(TTY_IO_ERROR, &tty->flags))
1507 return -EIO;
1da177e4 1508
1c45607a 1509 control = info->MCR;
1da177e4 1510
1c45607a
JS		 1511 spin_lock_irqsave(&info->slock, flags);
1512 status = inb(info->ioaddr + UART_MSR);
1513 if (status & UART_MSR_ANY_DELTA)
1514 mxser_check_modem_status(info, status);
1515 spin_unlock_irqrestore(&info->slock, flags);
1516 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1517 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1518 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1519 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1520 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1521 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1522}
1da177e4 1523
1c45607a
JS		 1524static int mxser_tiocmset(struct tty_struct *tty, struct file *file,
1525 unsigned int set, unsigned int clear)
1526{
1527 struct mxser_port *info = tty->driver_data;
1528 unsigned long flags;
1da177e4 1529
1da177e4 1530
1c45607a
JS		 1531 if (tty->index == MXSER_PORTS)
1532 return -ENOIOCTLCMD;
1533 if (test_bit(TTY_IO_ERROR, &tty->flags))
1534 return -EIO;
1da177e4 1535
1c45607a 1536 spin_lock_irqsave(&info->slock, flags);
1da177e4 1537
1c45607a
JS		 1538 if (set & TIOCM_RTS)
1539 info->MCR |= UART_MCR_RTS;
1540 if (set & TIOCM_DTR)
1541 info->MCR |= UART_MCR_DTR;
1da177e4 1542
1c45607a
JS		 1543 if (clear & TIOCM_RTS)
1544 info->MCR &= ~UART_MCR_RTS;
1545 if (clear & TIOCM_DTR)
1546 info->MCR &= ~UART_MCR_DTR;
8ea2c2ec 1547
1c45607a
JS		 1548 outb(info->MCR, info->ioaddr + UART_MCR);
1549 spin_unlock_irqrestore(&info->slock, flags);
1550 return 0;
1551}
1da177e4 1552
1c45607a
JS		 1553static int __init mxser_program_mode(int port)
1554{
1555 int id, i, j, n;
1556
1557 outb(0, port);
1558 outb(0, port);
1559 outb(0, port);
1560 (void)inb(port);
1561 (void)inb(port);
1562 outb(0, port);
1563 (void)inb(port);
1564
1565 id = inb(port + 1) & 0x1F;
1566 if ((id != C168_ASIC_ID) &&
1567 (id != C104_ASIC_ID) &&
1568 (id != C102_ASIC_ID) &&
1569 (id != CI132_ASIC_ID) &&
1570 (id != CI134_ASIC_ID) &&
1571 (id != CI104J_ASIC_ID))
1572 return -1;
1573 for (i = 0, j = 0; i < 4; i++) {
1574 n = inb(port + 2);
1575 if (n == 'M') {
1576 j = 1;
1577 } else if ((j == 1) && (n == 1)) {
1578 j = 2;
1579 break;
1580 } else
1581 j = 0;
1da177e4 1582 }
1c45607a
JS		 1583 if (j != 2)
1584 id = -2;
1585 return id;
1da177e4
LT		 1586}
1587
1c45607a
JS		 1588static void __init mxser_normal_mode(int port)
1589{
1590 int i, n;
1591
1592 outb(0xA5, port + 1);
1593 outb(0x80, port + 3);
1594 outb(12, port + 0); /* 9600 bps */
1595 outb(0, port + 1);
1596 outb(0x03, port + 3); /* 8 data bits */
1597 outb(0x13, port + 4); /* loop back mode */
1598 for (i = 0; i < 16; i++) {
1599 n = inb(port + 5);
1600 if ((n & 0x61) == 0x60)
1601 break;
1602 if ((n & 1) == 1)
1603 (void)inb(port);
1604 }
1605 outb(0x00, port + 4);
1606}
1607
1608#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1609#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1610#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1611#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1612#define EN_CCMD 0x000 /* Chip's command register */
1613#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1614#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1615#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1616#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1617#define EN0_DCFG 0x00E /* Data configuration reg WR */
1618#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1619#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1620#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
1621static int __init mxser_read_register(int port, unsigned short *regs)
1622{
1623 int i, k, value, id;
1624 unsigned int j;
1625
1626 id = mxser_program_mode(port);
1627 if (id < 0)
1628 return id;
1629 for (i = 0; i < 14; i++) {
1630 k = (i & 0x3F) | 0x180;
1631 for (j = 0x100; j > 0; j >>= 1) {
1632 outb(CHIP_CS, port);
1633 if (k & j) {
1634 outb(CHIP_CS | CHIP_DO, port);
1635 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1636 } else {
1637 outb(CHIP_CS, port);
1638 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1639 }
1640 }
1641 (void)inb(port);
1642 value = 0;
1643 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1644 outb(CHIP_CS, port);
1645 outb(CHIP_CS | CHIP_SK, port);
1646 if (inb(port) & CHIP_DI)
1647 value |= j;
1648 }
1649 regs[i] = value;
1650 outb(0, port);
1651 }
1652 mxser_normal_mode(port);
1653 return id;
1654}
1da177e4
LT		 1655
1656static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1657{
1c45607a
JS		 1658 struct mxser_port *port;
1659 int result, status;
1660 unsigned int i, j;
9d6d162d 1661 int ret = 0;
1da177e4
LT		 1662
1663 switch (cmd) {
1da177e4 1664 case MOXA_GET_MAJOR:
1c45607a 1665 return put_user(ttymajor, (int __user *)argp);
1da177e4
LT		 1666
1667 case MOXA_CHKPORTENABLE:
1668 result = 0;
9d6d162d 1669 lock_kernel();
1c45607a
JS		 1670 for (i = 0; i < MXSER_BOARDS; i++)
1671 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1672 if (mxser_boards[i].ports[j].ioaddr)
1673 result |= (1 << i);
9d6d162d 1674 unlock_kernel();
8ea2c2ec 1675 return put_user(result, (unsigned long __user *)argp);
1da177e4 1676 case MOXA_GETDATACOUNT:
9d6d162d 1677 lock_kernel();
1da177e4 1678 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
9d6d162d
AC		 1679 ret = -EFAULT;
1680 unlock_kernel();
1681 return ret;
1da177e4 1682 case MOXA_GETMSTATUS:
9d6d162d 1683 lock_kernel();
1c45607a
JS		 1684 for (i = 0; i < MXSER_BOARDS; i++)
1685 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1686 port = &mxser_boards[i].ports[j];
1687
1688 GMStatus[i].ri = 0;
1689 if (!port->ioaddr) {
1690 GMStatus[i].dcd = 0;
1691 GMStatus[i].dsr = 0;
1692 GMStatus[i].cts = 0;
1693 continue;
1694 }
1da177e4 1695
1c45607a
JS		 1696 if (!port->tty || !port->tty->termios)
1697 GMStatus[i].cflag =
1698 port->normal_termios.c_cflag;
1699 else
1700 GMStatus[i].cflag =
1701 port->tty->termios->c_cflag;
1da177e4 1702
1c45607a
JS		 1703 status = inb(port->ioaddr + UART_MSR);
1704 if (status & 0x80 /*UART_MSR_DCD */ )
1705 GMStatus[i].dcd = 1;
1706 else
1707 GMStatus[i].dcd = 0;
1da177e4 1708
1c45607a
JS		 1709 if (status & 0x20 /*UART_MSR_DSR */ )
1710 GMStatus[i].dsr = 1;
1711 else
1712 GMStatus[i].dsr = 0;
1da177e4
LT		 1713
1714
1c45607a
JS		 1715 if (status & 0x10 /*UART_MSR_CTS */ )
1716 GMStatus[i].cts = 1;
1717 else
1718 GMStatus[i].cts = 0;
1719 }
9d6d162d 1720 unlock_kernel();
8ea2c2ec
JJ		 1721 if (copy_to_user(argp, GMStatus,
1722 sizeof(struct mxser_mstatus) * MXSER_PORTS))
1da177e4
LT		 1723 return -EFAULT;
1724 return 0;
8ea2c2ec 1725 case MOXA_ASPP_MON_EXT: {
1c45607a
JS		 1726 int p, shiftbit;
1727 unsigned long opmode;
1728 unsigned cflag, iflag;
1729
9d6d162d
AC		 1730 lock_kernel();
1731 for (i = 0; i < MXSER_BOARDS; i++) {
1c45607a
JS		 1732 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1733 port = &mxser_boards[i].ports[j];
1734 if (!port->ioaddr)
1da177e4
LT		 1735 continue;
1736
1c45607a
JS		 1737 status = mxser_get_msr(port->ioaddr, 0, i);
1738
1da177e4 1739 if (status & UART_MSR_TERI)
1c45607a 1740 port->icount.rng++;
1da177e4 1741 if (status & UART_MSR_DDSR)
1c45607a 1742 port->icount.dsr++;
1da177e4 1743 if (status & UART_MSR_DDCD)
1c45607a 1744 port->icount.dcd++;
1da177e4 1745 if (status & UART_MSR_DCTS)
1c45607a
JS		 1746 port->icount.cts++;
1747
1748 port->mon_data.modem_status = status;
1749 mon_data_ext.rx_cnt[i] = port->mon_data.rxcnt;
1750 mon_data_ext.tx_cnt[i] = port->mon_data.txcnt;
1751 mon_data_ext.up_rxcnt[i] =
1752 port->mon_data.up_rxcnt;
1753 mon_data_ext.up_txcnt[i] =
1754 port->mon_data.up_txcnt;
1755 mon_data_ext.modem_status[i] =
1756 port->mon_data.modem_status;
1757 mon_data_ext.baudrate[i] =
1758 tty_get_baud_rate(port->tty);
1759
1760 if (!port->tty || !port->tty->termios) {
1761 cflag = port->normal_termios.c_cflag;
1762 iflag = port->normal_termios.c_iflag;
1da177e4 1763 } else {
1c45607a
JS		 1764 cflag = port->tty->termios->c_cflag;
1765 iflag = port->tty->termios->c_iflag;
1da177e4
LT		 1766 }
1767
1768 mon_data_ext.databits[i] = cflag & CSIZE;
1769
1770 mon_data_ext.stopbits[i] = cflag & CSTOPB;
1771
1c45607a
JS		 1772 mon_data_ext.parity[i] =
1773 cflag & (PARENB | PARODD | CMSPAR);
1da177e4
LT		 1774
1775 mon_data_ext.flowctrl[i] = 0x00;
1776
1777 if (cflag & CRTSCTS)
1778 mon_data_ext.flowctrl[i] |= 0x03;
1779
1780 if (iflag & (IXON | IXOFF))
1781 mon_data_ext.flowctrl[i] |= 0x0C;
1782
1c45607a 1783 if (port->type == PORT_16550A)
1da177e4
LT		 1784 mon_data_ext.fifo[i] = 1;
1785 else
1786 mon_data_ext.fifo[i] = 0;
1787
1788 p = i % 4;
1789 shiftbit = p * 2;
1c45607a 1790 opmode = inb(port->opmode_ioaddr) >> shiftbit;
1da177e4
LT		 1791 opmode &= OP_MODE_MASK;
1792
1793 mon_data_ext.iftype[i] = opmode;
1794
1795 }
9d6d162d
AC		 1796 }
1797 unlock_kernel();
1798 if (copy_to_user(argp, &mon_data_ext,
1799 sizeof(mon_data_ext)))
1800 return -EFAULT;
1801 return 0;
1802 }
1803 default:
1da177e4
LT		 1804 return -ENOIOCTLCMD;
1805 }
1806 return 0;
1807}
1808
1c45607a
JS		 1809static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1810 struct async_icount *cprev)
1da177e4 1811{
1c45607a
JS		 1812 struct async_icount cnow;
1813 unsigned long flags;
1814 int ret;
1da177e4 1815
1c45607a
JS		 1816 spin_lock_irqsave(&info->slock, flags);
1817 cnow = info->icount; /* atomic copy */
1818 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 1819
1c45607a
JS		 1820 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1821 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1822 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1823 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1da177e4 1824
1c45607a
JS		 1825 *cprev = cnow;
1826
1827 return ret;
1828}
1829
1830static int mxser_ioctl(struct tty_struct *tty, struct file *file,
1831 unsigned int cmd, unsigned long arg)
1da177e4 1832{
1c45607a
JS		 1833 struct mxser_port *info = tty->driver_data;
1834 struct async_icount cnow;
1835 struct serial_icounter_struct __user *p_cuser;
1836 unsigned long flags;
1837 void __user *argp = (void __user *)arg;
1838 int retval;
1da177e4 1839
1c45607a
JS		 1840 if (tty->index == MXSER_PORTS)
1841 return mxser_ioctl_special(cmd, argp);
1da177e4 1842
1c45607a
JS		 1843 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1844 int p;
1845 unsigned long opmode;
1846 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1847 int shiftbit;
1848 unsigned char val, mask;
1da177e4 1849
1c45607a
JS		 1850 p = tty->index % 4;
1851 if (cmd == MOXA_SET_OP_MODE) {
1852 if (get_user(opmode, (int __user *) argp))
1853 return -EFAULT;
1854 if (opmode != RS232_MODE &&
1855 opmode != RS485_2WIRE_MODE &&
1856 opmode != RS422_MODE &&
1857 opmode != RS485_4WIRE_MODE)
1858 return -EFAULT;
9d6d162d 1859 lock_kernel();
1c45607a
JS		 1860 mask = ModeMask[p];
1861 shiftbit = p * 2;
1862 val = inb(info->opmode_ioaddr);
1863 val &= mask;
1864 val |= (opmode << shiftbit);
1865 outb(val, info->opmode_ioaddr);
9d6d162d 1866 unlock_kernel();
1c45607a 1867 } else {
9d6d162d 1868 lock_kernel();
1c45607a
JS		 1869 shiftbit = p * 2;
1870 opmode = inb(info->opmode_ioaddr) >> shiftbit;
1871 opmode &= OP_MODE_MASK;
9d6d162d 1872 unlock_kernel();
1c45607a
JS		 1873 if (put_user(opmode, (int __user *)argp))
1874 return -EFAULT;
1875 }
1876 return 0;
1877 }
1878
1879 if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT &&
1880 test_bit(TTY_IO_ERROR, &tty->flags))
1881 return -EIO;
1882
1883 switch (cmd) {
1884 case TCSBRK: /* SVID version: non-zero arg --> no break */
1885 retval = tty_check_change(tty);
1886 if (retval)
1887 return retval;
1888 tty_wait_until_sent(tty, 0);
1889 if (!arg)
1890 mxser_send_break(info, HZ / 4); /* 1/4 second */
1891 return 0;
1892 case TCSBRKP: /* support for POSIX tcsendbreak() */
1893 retval = tty_check_change(tty);
1894 if (retval)
1895 return retval;
1896 tty_wait_until_sent(tty, 0);
1897 mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4);
1898 return 0;
1c45607a 1899 case TIOCGSERIAL:
9d6d162d
AC		 1900 lock_kernel();
1901 retval = mxser_get_serial_info(info, argp);
1902 unlock_kernel();
1903 return retval;
1c45607a 1904 case TIOCSSERIAL:
9d6d162d
AC		 1905 lock_kernel();
1906 retval = mxser_set_serial_info(info, argp);
1907 unlock_kernel();
1908 return retval;
1c45607a 1909 case TIOCSERGETLSR: /* Get line status register */
9d6d162d 1910 return mxser_get_lsr_info(info, argp);
1c45607a
JS		 1911 /*
1912 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1913 * - mask passed in arg for lines of interest
1914 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1915 * Caller should use TIOCGICOUNT to see which one it was
1916 */
1917 case TIOCMIWAIT:
1918 spin_lock_irqsave(&info->slock, flags);
1919 cnow = info->icount; /* note the counters on entry */
1920 spin_unlock_irqrestore(&info->slock, flags);
1921
1922 return wait_event_interruptible(info->delta_msr_wait,
1923 mxser_cflags_changed(info, arg, &cnow));
1924 /*
1925 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1926 * Return: write counters to the user passed counter struct
1927 * NB: both 1->0 and 0->1 transitions are counted except for
1928 * RI where only 0->1 is counted.
1929 */
1930 case TIOCGICOUNT:
1931 spin_lock_irqsave(&info->slock, flags);
1932 cnow = info->icount;
1933 spin_unlock_irqrestore(&info->slock, flags);
1934 p_cuser = argp;
1935 if (put_user(cnow.frame, &p_cuser->frame))
1936 return -EFAULT;
1937 if (put_user(cnow.brk, &p_cuser->brk))
1938 return -EFAULT;
1939 if (put_user(cnow.overrun, &p_cuser->overrun))
1940 return -EFAULT;
1941 if (put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1942 return -EFAULT;
1943 if (put_user(cnow.parity, &p_cuser->parity))
1944 return -EFAULT;
1945 if (put_user(cnow.rx, &p_cuser->rx))
1946 return -EFAULT;
1947 if (put_user(cnow.tx, &p_cuser->tx))
1948 return -EFAULT;
1949 put_user(cnow.cts, &p_cuser->cts);
1950 put_user(cnow.dsr, &p_cuser->dsr);
1951 put_user(cnow.rng, &p_cuser->rng);
1952 put_user(cnow.dcd, &p_cuser->dcd);
1953 return 0;
1954 case MOXA_HighSpeedOn:
1955 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1956 case MOXA_SDS_RSTICOUNTER:
9d6d162d 1957 lock_kernel();
1c45607a
JS		 1958 info->mon_data.rxcnt = 0;
1959 info->mon_data.txcnt = 0;
9d6d162d 1960 unlock_kernel();
1c45607a
JS		 1961 return 0;
1962
1963 case MOXA_ASPP_OQUEUE:{
1964 int len, lsr;
1965
9d6d162d 1966 lock_kernel();
1c45607a 1967 len = mxser_chars_in_buffer(tty);
1c45607a 1968 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT;
1c45607a 1969 len += (lsr ? 0 : 1);
9d6d162d 1970 unlock_kernel();
1c45607a
JS		 1971
1972 return put_user(len, (int __user *)argp);
1973 }
1974 case MOXA_ASPP_MON: {
1975 int mcr, status;
1976
9d6d162d 1977 lock_kernel();
1c45607a
JS		 1978 status = mxser_get_msr(info->ioaddr, 1, tty->index);
1979 mxser_check_modem_status(info, status);
1980
1981 mcr = inb(info->ioaddr + UART_MCR);
1982 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1983 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1984 else
1985 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1986
1987 if (mcr & MOXA_MUST_MCR_TX_XON)
1988 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1989 else
1990 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1991
1992 if (info->tty->hw_stopped)
1993 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1994 else
1995 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
9d6d162d 1996 unlock_kernel();
1c45607a
JS		 1997 if (copy_to_user(argp, &info->mon_data,
1998 sizeof(struct mxser_mon)))
1999 return -EFAULT;
2000
2001 return 0;
2002 }
2003 case MOXA_ASPP_LSTATUS: {
2004 if (put_user(info->err_shadow, (unsigned char __user *)argp))
2005 return -EFAULT;
2006
2007 info->err_shadow = 0;
2008 return 0;
2009 }
2010 case MOXA_SET_BAUD_METHOD: {
2011 int method;
2012
2013 if (get_user(method, (int __user *)argp))
2014 return -EFAULT;
2015 mxser_set_baud_method[tty->index] = method;
2016 return put_user(method, (int __user *)argp);
2017 }
2018 default:
2019 return -ENOIOCTLCMD;
2020 }
2021 return 0;
2022}
2023
2024static void mxser_stoprx(struct tty_struct *tty)
2025{
2026 struct mxser_port *info = tty->driver_data;
2027
2028 info->ldisc_stop_rx = 1;
2029 if (I_IXOFF(tty)) {
2030 if (info->board->chip_flag) {
2031 info->IER &= ~MOXA_MUST_RECV_ISR;
2032 outb(info->IER, info->ioaddr + UART_IER);
2033 } else {
2034 info->x_char = STOP_CHAR(tty);
2035 outb(0, info->ioaddr + UART_IER);
2036 info->IER |= UART_IER_THRI;
2037 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 2038 }
2039 }
2040
2041 if (info->tty->termios->c_cflag & CRTSCTS) {
1c45607a
JS		 2042 info->MCR &= ~UART_MCR_RTS;
2043 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 2044 }
2045}
2046
2047/*
2048 * This routine is called by the upper-layer tty layer to signal that
2049 * incoming characters should be throttled.
2050 */
2051static void mxser_throttle(struct tty_struct *tty)
2052{
1da177e4 2053 mxser_stoprx(tty);
1da177e4
LT		 2054}
2055
2056static void mxser_unthrottle(struct tty_struct *tty)
2057{
1c45607a 2058 struct mxser_port *info = tty->driver_data;
1da177e4 2059
1c45607a
JS		 2060 /* startrx */
2061 info->ldisc_stop_rx = 0;
2062 if (I_IXOFF(tty)) {
2063 if (info->x_char)
2064 info->x_char = 0;
2065 else {
2066 if (info->board->chip_flag) {
2067 info->IER |= MOXA_MUST_RECV_ISR;
2068 outb(info->IER, info->ioaddr + UART_IER);
2069 } else {
2070 info->x_char = START_CHAR(tty);
2071 outb(0, info->ioaddr + UART_IER);
2072 info->IER |= UART_IER_THRI;
2073 outb(info->IER, info->ioaddr + UART_IER);
2074 }
1da177e4 2075 }
1c45607a 2076 }
1da177e4 2077
1c45607a
JS		 2078 if (info->tty->termios->c_cflag & CRTSCTS) {
2079 info->MCR |= UART_MCR_RTS;
2080 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 2081 }
2082}
2083
2084/*
2085 * mxser_stop() and mxser_start()
2086 *
2087 * This routines are called before setting or resetting tty->stopped.
2088 * They enable or disable transmitter interrupts, as necessary.
2089 */
2090static void mxser_stop(struct tty_struct *tty)
2091{
1c45607a 2092 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2093 unsigned long flags;
2094
2095 spin_lock_irqsave(&info->slock, flags);
2096 if (info->IER & UART_IER_THRI) {
2097 info->IER &= ~UART_IER_THRI;
1c45607a 2098 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 2099 }
2100 spin_unlock_irqrestore(&info->slock, flags);
2101}
2102
2103static void mxser_start(struct tty_struct *tty)
2104{
1c45607a 2105 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2106 unsigned long flags;
2107
2108 spin_lock_irqsave(&info->slock, flags);
1c45607a
JS		 2109 if (info->xmit_cnt && info->xmit_buf) {
2110 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 2111 info->IER |= UART_IER_THRI;
1c45607a 2112 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 2113 }
2114 spin_unlock_irqrestore(&info->slock, flags);
2115}
2116
1c45607a
JS		 2117static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
2118{
2119 struct mxser_port *info = tty->driver_data;
2120 unsigned long flags;
2121
2122 spin_lock_irqsave(&info->slock, flags);
2123 mxser_change_speed(info, old_termios);
2124 spin_unlock_irqrestore(&info->slock, flags);
2125
2126 if ((old_termios->c_cflag & CRTSCTS) &&
2127 !(tty->termios->c_cflag & CRTSCTS)) {
2128 tty->hw_stopped = 0;
2129 mxser_start(tty);
2130 }
2131
2132 /* Handle sw stopped */
2133 if ((old_termios->c_iflag & IXON) &&
2134 !(tty->termios->c_iflag & IXON)) {
2135 tty->stopped = 0;
2136
2137 if (info->board->chip_flag) {
2138 spin_lock_irqsave(&info->slock, flags);
148ff86b
CH		 2139 mxser_disable_must_rx_software_flow_control(
2140 info->ioaddr);
1c45607a
JS		 2141 spin_unlock_irqrestore(&info->slock, flags);
2142 }
2143
2144 mxser_start(tty);
2145 }
2146}
2147
1da177e4
LT		 2148/*
2149 * mxser_wait_until_sent() --- wait until the transmitter is empty
2150 */
2151static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
2152{
1c45607a 2153 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2154 unsigned long orig_jiffies, char_time;
2155 int lsr;
2156
2157 if (info->type == PORT_UNKNOWN)
2158 return;
2159
2160 if (info->xmit_fifo_size == 0)
2161 return; /* Just in case.... */
2162
2163 orig_jiffies = jiffies;
2164 /*
2165 * Set the check interval to be 1/5 of the estimated time to
2166 * send a single character, and make it at least 1. The check
2167 * interval should also be less than the timeout.
2168 *
2169 * Note: we have to use pretty tight timings here to satisfy
2170 * the NIST-PCTS.
2171 */
2172 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
2173 char_time = char_time / 5;
2174 if (char_time == 0)
2175 char_time = 1;
2176 if (timeout && timeout < char_time)
2177 char_time = timeout;
2178 /*
2179 * If the transmitter hasn't cleared in twice the approximate
2180 * amount of time to send the entire FIFO, it probably won't
2181 * ever clear. This assumes the UART isn't doing flow
2182 * control, which is currently the case. Hence, if it ever
2183 * takes longer than info->timeout, this is probably due to a
2184 * UART bug of some kind. So, we clamp the timeout parameter at
2185 * 2*info->timeout.
2186 */
2187 if (!timeout || timeout > 2 * info->timeout)
2188 timeout = 2 * info->timeout;
2189#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8ea2c2ec
JJ		 2190 printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...",
2191 timeout, char_time);
1da177e4
LT		 2192 printk("jiff=%lu...", jiffies);
2193#endif
978e595f 2194 lock_kernel();
1c45607a 2195 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
1da177e4
LT		 2196#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2197 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
2198#endif
da4cd8df 2199 schedule_timeout_interruptible(char_time);
1da177e4 2200 if (signal_pending(current))
1c45607a
JS		 2201 break;
2202 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2203 break;
1da177e4 2204 }
1c45607a 2205 set_current_state(TASK_RUNNING);
978e595f 2206 unlock_kernel();
1da177e4 2207
1c45607a
JS		 2208#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2209 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
2210#endif
2211}
1da177e4 2212
1c45607a
JS		 2213/*
2214 * This routine is called by tty_hangup() when a hangup is signaled.
2215 */
2216static void mxser_hangup(struct tty_struct *tty)
2217{
2218 struct mxser_port *info = tty->driver_data;
1da177e4 2219
1c45607a
JS		 2220 mxser_flush_buffer(tty);
2221 mxser_shutdown(info);
2222 info->event = 0;
2223 info->count = 0;
2224 info->flags &= ~ASYNC_NORMAL_ACTIVE;
2225 info->tty = NULL;
2226 wake_up_interruptible(&info->open_wait);
1da177e4
LT		 2227}
2228
1c45607a
JS		 2229/*
2230 * mxser_rs_break() --- routine which turns the break handling on or off
2231 */
2232static void mxser_rs_break(struct tty_struct *tty, int break_state)
1da177e4 2233{
1c45607a 2234 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2235 unsigned long flags;
2236
1c45607a
JS		 2237 spin_lock_irqsave(&info->slock, flags);
2238 if (break_state == -1)
2239 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2240 info->ioaddr + UART_LCR);
2241 else
2242 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2243 info->ioaddr + UART_LCR);
2244 spin_unlock_irqrestore(&info->slock, flags);
2245}
1da177e4 2246
1c45607a
JS		 2247static void mxser_receive_chars(struct mxser_port *port, int *status)
2248{
2249 struct tty_struct *tty = port->tty;
2250 unsigned char ch, gdl;
2251 int ignored = 0;
2252 int cnt = 0;
2253 int recv_room;
2254 int max = 256;
1da177e4 2255
1c45607a
JS		 2256 recv_room = tty->receive_room;
2257 if ((recv_room == 0) && (!port->ldisc_stop_rx))
2258 mxser_stoprx(tty);
1da177e4 2259
1c45607a 2260 if (port->board->chip_flag != MOXA_OTHER_UART) {
1da177e4 2261
1c45607a
JS		 2262 if (*status & UART_LSR_SPECIAL)
2263 goto intr_old;
2264 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2265 (*status & MOXA_MUST_LSR_RERR))
2266 goto intr_old;
2267 if (*status & MOXA_MUST_LSR_RERR)
2268 goto intr_old;
1da177e4 2269
1c45607a
JS		 2270 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2271
2272 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2273 gdl &= MOXA_MUST_GDL_MASK;
2274 if (gdl >= recv_room) {
2275 if (!port->ldisc_stop_rx)
2276 mxser_stoprx(tty);
2277 }
2278 while (gdl--) {
2279 ch = inb(port->ioaddr + UART_RX);
2280 tty_insert_flip_char(tty, ch, 0);
2281 cnt++;
2282 }
2283 goto end_intr;
1da177e4 2284 }
1c45607a
JS		 2285intr_old:
2286
2287 do {
2288 if (max-- < 0)
2289 break;
1da177e4 2290
1c45607a
JS		 2291 ch = inb(port->ioaddr + UART_RX);
2292 if (port->board->chip_flag && (*status & UART_LSR_OE))
2293 outb(0x23, port->ioaddr + UART_FCR);
2294 *status &= port->read_status_mask;
2295 if (*status & port->ignore_status_mask) {
2296 if (++ignored > 100)
2297 break;
2298 } else {
2299 char flag = 0;
2300 if (*status & UART_LSR_SPECIAL) {
2301 if (*status & UART_LSR_BI) {
2302 flag = TTY_BREAK;
2303 port->icount.brk++;
1da177e4 2304
1c45607a
JS		 2305 if (port->flags & ASYNC_SAK)
2306 do_SAK(tty);
2307 } else if (*status & UART_LSR_PE) {
2308 flag = TTY_PARITY;
2309 port->icount.parity++;
2310 } else if (*status & UART_LSR_FE) {
2311 flag = TTY_FRAME;
2312 port->icount.frame++;
2313 } else if (*status & UART_LSR_OE) {
2314 flag = TTY_OVERRUN;
2315 port->icount.overrun++;
2316 } else
2317 flag = TTY_BREAK;
2318 }
2319 tty_insert_flip_char(tty, ch, flag);
2320 cnt++;
2321 if (cnt >= recv_room) {
2322 if (!port->ldisc_stop_rx)
2323 mxser_stoprx(tty);
2324 break;
2325 }
1da177e4 2326
1c45607a 2327 }
1da177e4 2328
1c45607a
JS		 2329 if (port->board->chip_flag)
2330 break;
1da177e4 2331
1c45607a
JS		 2332 *status = inb(port->ioaddr + UART_LSR);
2333 } while (*status & UART_LSR_DR);
1da177e4 2334
1c45607a
JS		 2335end_intr:
2336 mxvar_log.rxcnt[port->tty->index] += cnt;
2337 port->mon_data.rxcnt += cnt;
2338 port->mon_data.up_rxcnt += cnt;
1da177e4 2339
1c45607a
JS		 2340 /*
2341 * We are called from an interrupt context with &port->slock
2342 * being held. Drop it temporarily in order to prevent
2343 * recursive locking.
2344 */
2345 spin_unlock(&port->slock);
2346 tty_flip_buffer_push(tty);
2347 spin_lock(&port->slock);
1da177e4
LT		 2348}
2349
1c45607a 2350static void mxser_transmit_chars(struct mxser_port *port)
1da177e4 2351{
1c45607a 2352 int count, cnt;
1da177e4 2353
1c45607a
JS		 2354 if (port->x_char) {
2355 outb(port->x_char, port->ioaddr + UART_TX);
2356 port->x_char = 0;
2357 mxvar_log.txcnt[port->tty->index]++;
2358 port->mon_data.txcnt++;
2359 port->mon_data.up_txcnt++;
2360 port->icount.tx++;
2361 return;
2362 }
1da177e4 2363
1c45607a
JS		 2364 if (port->xmit_buf == NULL)
2365 return;
1da177e4 2366
1c45607a
JS		 2367 if ((port->xmit_cnt <= 0) || port->tty->stopped ||
2368 (port->tty->hw_stopped &&
2369 (port->type != PORT_16550A) &&
2370 (!port->board->chip_flag))) {
2371 port->IER &= ~UART_IER_THRI;
2372 outb(port->IER, port->ioaddr + UART_IER);
2373 return;
1da177e4
LT		 2374 }
2375
1c45607a
JS		 2376 cnt = port->xmit_cnt;
2377 count = port->xmit_fifo_size;
2378 do {
2379 outb(port->xmit_buf[port->xmit_tail++],
2380 port->ioaddr + UART_TX);
2381 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2382 if (--port->xmit_cnt <= 0)
2383 break;
2384 } while (--count > 0);
2385 mxvar_log.txcnt[port->tty->index] += (cnt - port->xmit_cnt);
1da177e4 2386
1c45607a
JS		 2387 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2388 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2389 port->icount.tx += (cnt - port->xmit_cnt);
1da177e4 2390
1c45607a
JS		 2391 if (port->xmit_cnt < WAKEUP_CHARS)
2392 tty_wakeup(port->tty);
2393
2394 if (port->xmit_cnt <= 0) {
2395 port->IER &= ~UART_IER_THRI;
2396 outb(port->IER, port->ioaddr + UART_IER);
1da177e4 2397 }
1da177e4
LT		 2398}
2399
2400/*
1c45607a 2401 * This is the serial driver's generic interrupt routine
1da177e4 2402 */
1c45607a 2403static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1da177e4 2404{
1c45607a
JS		 2405 int status, iir, i;
2406 struct mxser_board *brd = NULL;
2407 struct mxser_port *port;
2408 int max, irqbits, bits, msr;
2409 unsigned int int_cnt, pass_counter = 0;
2410 int handled = IRQ_NONE;
1da177e4 2411
1c45607a
JS		 2412 for (i = 0; i < MXSER_BOARDS; i++)
2413 if (dev_id == &mxser_boards[i]) {
2414 brd = dev_id;
2415 break;
2416 }
1da177e4 2417
1c45607a
JS		 2418 if (i == MXSER_BOARDS)
2419 goto irq_stop;
2420 if (brd == NULL)
2421 goto irq_stop;
2422 max = brd->info->nports;
2423 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
2424 irqbits = inb(brd->vector) & brd->vector_mask;
2425 if (irqbits == brd->vector_mask)
2426 break;
1da177e4 2427
1c45607a
JS		 2428 handled = IRQ_HANDLED;
2429 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2430 if (irqbits == brd->vector_mask)
2431 break;
2432 if (bits & irqbits)
2433 continue;
2434 port = &brd->ports[i];
2435
2436 int_cnt = 0;
2437 spin_lock(&port->slock);
2438 do {
2439 iir = inb(port->ioaddr + UART_IIR);
2440 if (iir & UART_IIR_NO_INT)
2441 break;
2442 iir &= MOXA_MUST_IIR_MASK;
2443 if (!port->tty ||
2444 (port->flags & ASYNC_CLOSING) ||
2445 !(port->flags &
2446 ASYNC_INITIALIZED)) {
2447 status = inb(port->ioaddr + UART_LSR);
2448 outb(0x27, port->ioaddr + UART_FCR);
2449 inb(port->ioaddr + UART_MSR);
2450 break;
2451 }
1da177e4 2452
1c45607a
JS		 2453 status = inb(port->ioaddr + UART_LSR);
2454
2455 if (status & UART_LSR_PE)
2456 port->err_shadow |= NPPI_NOTIFY_PARITY;
2457 if (status & UART_LSR_FE)
2458 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2459 if (status & UART_LSR_OE)
2460 port->err_shadow |=
2461 NPPI_NOTIFY_HW_OVERRUN;
2462 if (status & UART_LSR_BI)
2463 port->err_shadow |= NPPI_NOTIFY_BREAK;
2464
2465 if (port->board->chip_flag) {
2466 if (iir == MOXA_MUST_IIR_GDA ||
2467 iir == MOXA_MUST_IIR_RDA ||
2468 iir == MOXA_MUST_IIR_RTO ||
2469 iir == MOXA_MUST_IIR_LSR)
2470 mxser_receive_chars(port,
2471 &status);
2472
2473 } else {
2474 status &= port->read_status_mask;
2475 if (status & UART_LSR_DR)
2476 mxser_receive_chars(port,
2477 &status);
2478 }
2479 msr = inb(port->ioaddr + UART_MSR);
2480 if (msr & UART_MSR_ANY_DELTA)
2481 mxser_check_modem_status(port, msr);
2482
2483 if (port->board->chip_flag) {
2484 if (iir == 0x02 && (status &
2485 UART_LSR_THRE))
2486 mxser_transmit_chars(port);
2487 } else {
2488 if (status & UART_LSR_THRE)
2489 mxser_transmit_chars(port);
2490 }
2491 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2492 spin_unlock(&port->slock);
2493 }
2494 }
1da177e4 2495
1c45607a
JS		 2496irq_stop:
2497 return handled;
2498}
1da177e4 2499
1c45607a
JS		 2500static const struct tty_operations mxser_ops = {
2501 .open = mxser_open,
2502 .close = mxser_close,
2503 .write = mxser_write,
2504 .put_char = mxser_put_char,
2505 .flush_chars = mxser_flush_chars,
2506 .write_room = mxser_write_room,
2507 .chars_in_buffer = mxser_chars_in_buffer,
2508 .flush_buffer = mxser_flush_buffer,
2509 .ioctl = mxser_ioctl,
2510 .throttle = mxser_throttle,
2511 .unthrottle = mxser_unthrottle,
2512 .set_termios = mxser_set_termios,
2513 .stop = mxser_stop,
2514 .start = mxser_start,
2515 .hangup = mxser_hangup,
2516 .break_ctl = mxser_rs_break,
2517 .wait_until_sent = mxser_wait_until_sent,
2518 .tiocmget = mxser_tiocmget,
2519 .tiocmset = mxser_tiocmset,
2520};
1da177e4 2521
1c45607a
JS		 2522/*
2523 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2524 */
1da177e4 2525
1c45607a
JS		 2526static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev,
2527 unsigned int irq)
2528{
2529 if (irq)
2530 free_irq(brd->irq, brd);
2531 if (pdev != NULL) { /* PCI */
2532#ifdef CONFIG_PCI
2533 pci_release_region(pdev, 2);
2534 pci_release_region(pdev, 3);
2535#endif
2536 } else {
2537 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2538 release_region(brd->vector, 1);
2539 }
1da177e4
LT		 2540}
2541
1c45607a
JS		 2542static int __devinit mxser_initbrd(struct mxser_board *brd,
2543 struct pci_dev *pdev)
1da177e4 2544{
1c45607a
JS		 2545 struct mxser_port *info;
2546 unsigned int i;
2547 int retval;
1da177e4 2548
1c45607a 2549 printk(KERN_INFO "max. baud rate = %d bps.\n", brd->ports[0].max_baud);
1da177e4 2550
1c45607a
JS		 2551 for (i = 0; i < brd->info->nports; i++) {
2552 info = &brd->ports[i];
2553 info->board = brd;
2554 info->stop_rx = 0;
2555 info->ldisc_stop_rx = 0;
1da177e4 2556
1c45607a
JS		 2557 /* Enhance mode enabled here */
2558 if (brd->chip_flag != MOXA_OTHER_UART)
148ff86b 2559 mxser_enable_must_enchance_mode(info->ioaddr);
1da177e4 2560
1c45607a
JS		 2561 info->flags = ASYNC_SHARE_IRQ;
2562 info->type = brd->uart_type;
1da177e4 2563
1c45607a 2564 process_txrx_fifo(info);
1da177e4 2565
1c45607a
JS		 2566 info->custom_divisor = info->baud_base * 16;
2567 info->close_delay = 5 * HZ / 10;
2568 info->closing_wait = 30 * HZ;
2569 info->normal_termios = mxvar_sdriver->init_termios;
2570 init_waitqueue_head(&info->open_wait);
2571 init_waitqueue_head(&info->delta_msr_wait);
2572 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2573 info->err_shadow = 0;
2574 spin_lock_init(&info->slock);
1da177e4 2575
1c45607a
JS		 2576 /* before set INT ISR, disable all int */
2577 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2578 info->ioaddr + UART_IER);
2579 }
1da177e4 2580
1c45607a
JS		 2581 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2582 brd);
2583 if (retval) {
2584 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2585 "conflict with another device.\n",
2586 brd->info->name, brd->irq);
2587 /* We hold resources, we need to release them. */
2588 mxser_release_res(brd, pdev, 0);
2589 }
2590 return retval;
2591}
1da177e4 2592
1c45607a 2593static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
1da177e4
LT		 2594{
2595 int id, i, bits;
2596 unsigned short regs[16], irq;
2597 unsigned char scratch, scratch2;
2598
1c45607a 2599 brd->chip_flag = MOXA_OTHER_UART;
1da177e4
LT		 2600
2601 id = mxser_read_register(cap, regs);
1c45607a
JS		 2602 switch (id) {
2603 case C168_ASIC_ID:
2604 brd->info = &mxser_cards[0];
2605 break;
2606 case C104_ASIC_ID:
2607 brd->info = &mxser_cards[1];
2608 break;
2609 case CI104J_ASIC_ID:
2610 brd->info = &mxser_cards[2];
2611 break;
2612 case C102_ASIC_ID:
2613 brd->info = &mxser_cards[5];
2614 break;
2615 case CI132_ASIC_ID:
2616 brd->info = &mxser_cards[6];
2617 break;
2618 case CI134_ASIC_ID:
2619 brd->info = &mxser_cards[7];
2620 break;
2621 default:
8ea2c2ec 2622 return 0;
1c45607a 2623 }
1da177e4
LT		 2624
2625 irq = 0;
1c45607a
JS		 2626 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2627 Flag-hack checks if configuration should be read as 2-port here. */
2628 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
1da177e4
LT		 2629 irq = regs[9] & 0xF000;
2630 irq = irq | (irq >> 4);
2631 if (irq != (regs[9] & 0xFF00))
8ea2c2ec 2632 return MXSER_ERR_IRQ_CONFLIT;
1c45607a 2633 } else if (brd->info->nports == 4) {
1da177e4
LT		 2634 irq = regs[9] & 0xF000;
2635 irq = irq | (irq >> 4);
2636 irq = irq | (irq >> 8);
2637 if (irq != regs[9])
8ea2c2ec 2638 return MXSER_ERR_IRQ_CONFLIT;
1c45607a 2639 } else if (brd->info->nports == 8) {
1da177e4
LT		 2640 irq = regs[9] & 0xF000;
2641 irq = irq | (irq >> 4);
2642 irq = irq | (irq >> 8);
2643 if ((irq != regs[9]) || (irq != regs[10]))
8ea2c2ec 2644 return MXSER_ERR_IRQ_CONFLIT;
1da177e4
LT		 2645 }
2646
8ea2c2ec
JJ		 2647 if (!irq)
2648 return MXSER_ERR_IRQ;
1c45607a 2649 brd->irq = ((int)(irq & 0xF000) >> 12);
1da177e4 2650 for (i = 0; i < 8; i++)
1c45607a 2651 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
8ea2c2ec
JJ		 2652 if ((regs[12] & 0x80) == 0)
2653 return MXSER_ERR_VECTOR;
1c45607a 2654 brd->vector = (int)regs[11]; /* interrupt vector */
1da177e4 2655 if (id == 1)
1c45607a 2656 brd->vector_mask = 0x00FF;
1da177e4 2657 else
1c45607a 2658 brd->vector_mask = 0x000F;
1da177e4
LT		 2659 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2660 if (regs[12] & bits) {
1c45607a
JS		 2661 brd->ports[i].baud_base = 921600;
2662 brd->ports[i].max_baud = 921600;
1da177e4 2663 } else {
1c45607a
JS		 2664 brd->ports[i].baud_base = 115200;
2665 brd->ports[i].max_baud = 115200;
1da177e4
LT		 2666 }
2667 }
2668 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2669 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2670 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2671 outb(scratch2, cap + UART_LCR);
2672 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2673 scratch = inb(cap + UART_IIR);
2674
2675 if (scratch & 0xC0)
1c45607a 2676 brd->uart_type = PORT_16550A;
1da177e4 2677 else
1c45607a
JS		 2678 brd->uart_type = PORT_16450;
2679 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
2680 "mxser(IO)"))
2681 return MXSER_ERR_IOADDR;
2682 if (!request_region(brd->vector, 1, "mxser(vector)")) {
2683 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2684 return MXSER_ERR_VECTOR;
2685 }
2686 return brd->info->nports;
1da177e4
LT		 2687}
2688
1c45607a
JS		 2689static int __devinit mxser_probe(struct pci_dev *pdev,
2690 const struct pci_device_id *ent)
1da177e4 2691{
1c45607a
JS		 2692#ifdef CONFIG_PCI
2693 struct mxser_board *brd;
2694 unsigned int i, j;
2695 unsigned long ioaddress;
2696 int retval = -EINVAL;
1da177e4 2697
1c45607a
JS		 2698 for (i = 0; i < MXSER_BOARDS; i++)
2699 if (mxser_boards[i].info == NULL)
2700 break;
2701
2702 if (i >= MXSER_BOARDS) {
2703 printk(KERN_ERR "Too many Smartio/Industio family boards found "
2704 "(maximum %d), board not configured\n", MXSER_BOARDS);
2705 goto err;
2706 }
2707
2708 brd = &mxser_boards[i];
2709 brd->idx = i * MXSER_PORTS_PER_BOARD;
2710 printk(KERN_INFO "Found MOXA %s board (BusNo=%d, DevNo=%d)\n",
2711 mxser_cards[ent->driver_data].name,
2712 pdev->bus->number, PCI_SLOT(pdev->devfn));
2713
2714 retval = pci_enable_device(pdev);
2715 if (retval) {
2716 printk(KERN_ERR "Moxa SmartI/O PCI enable fail !\n");
2717 goto err;
2718 }
2719
2720 /* io address */
2721 ioaddress = pci_resource_start(pdev, 2);
2722 retval = pci_request_region(pdev, 2, "mxser(IO)");
2723 if (retval)
2724 goto err;
2725
2726 brd->info = &mxser_cards[ent->driver_data];
2727 for (i = 0; i < brd->info->nports; i++)
2728 brd->ports[i].ioaddr = ioaddress + 8 * i;
2729
2730 /* vector */
2731 ioaddress = pci_resource_start(pdev, 3);
2732 retval = pci_request_region(pdev, 3, "mxser(vector)");
2733 if (retval)
2734 goto err_relio;
2735 brd->vector = ioaddress;
2736
2737 /* irq */
2738 brd->irq = pdev->irq;
2739
2740 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2741 brd->uart_type = PORT_16550A;
2742 brd->vector_mask = 0;
2743
2744 for (i = 0; i < brd->info->nports; i++) {
2745 for (j = 0; j < UART_INFO_NUM; j++) {
2746 if (Gpci_uart_info[j].type == brd->chip_flag) {
2747 brd->ports[i].max_baud =
2748 Gpci_uart_info[j].max_baud;
2749
2750 /* exception....CP-102 */
2751 if (brd->info->flags & MXSER_HIGHBAUD)
2752 brd->ports[i].max_baud = 921600;
2753 break;
1da177e4
LT		 2754 }
2755 }
1c45607a
JS		 2756 }
2757
2758 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
2759 for (i = 0; i < brd->info->nports; i++) {
2760 if (i < 4)
2761 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2762 else
2763 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
1da177e4 2764 }
1c45607a
JS		 2765 outb(0, ioaddress + 4); /* default set to RS232 mode */
2766 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
1da177e4 2767 }
1c45607a
JS		 2768
2769 for (i = 0; i < brd->info->nports; i++) {
2770 brd->vector_mask |= (1 << i);
2771 brd->ports[i].baud_base = 921600;
2772 }
2773
2774 /* mxser_initbrd will hook ISR. */
2775 retval = mxser_initbrd(brd, pdev);
2776 if (retval)
2777 goto err_null;
2778
2779 for (i = 0; i < brd->info->nports; i++)
2780 tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev);
2781
2782 pci_set_drvdata(pdev, brd);
2783
2784 return 0;
2785err_relio:
2786 pci_release_region(pdev, 2);
2787err_null:
2788 brd->info = NULL;
2789err:
2790 return retval;
2791#else
2792 return -ENODEV;
2793#endif
1da177e4
LT		 2794}
2795
1c45607a 2796static void __devexit mxser_remove(struct pci_dev *pdev)
1da177e4 2797{
1c45607a
JS		 2798 struct mxser_board *brd = pci_get_drvdata(pdev);
2799 unsigned int i;
1da177e4 2800
1c45607a
JS		 2801 for (i = 0; i < brd->info->nports; i++)
2802 tty_unregister_device(mxvar_sdriver, brd->idx + i);
1da177e4 2803
1c45607a
JS		 2804 mxser_release_res(brd, pdev, 1);
2805 brd->info = NULL;
1da177e4
LT		 2806}
2807
1c45607a
JS		 2808static struct pci_driver mxser_driver = {
2809 .name = "mxser",
2810 .id_table = mxser_pcibrds,
2811 .probe = mxser_probe,
2812 .remove = __devexit_p(mxser_remove)
2813};
2814
2815static int __init mxser_module_init(void)
1da177e4 2816{
1c45607a
JS		 2817 struct mxser_board *brd;
2818 unsigned long cap;
2819 unsigned int i, m, isaloop;
2820 int retval, b;
1da177e4 2821
1c45607a
JS		 2822 pr_debug("Loading module mxser ...\n");
2823
2824 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2825 if (!mxvar_sdriver)
2826 return -ENOMEM;
2827
2828 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2829 MXSER_VERSION);
2830
2831 /* Initialize the tty_driver structure */
2832 mxvar_sdriver->owner = THIS_MODULE;
2833 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
2834 mxvar_sdriver->name = "ttyMI";
2835 mxvar_sdriver->major = ttymajor;
2836 mxvar_sdriver->minor_start = 0;
2837 mxvar_sdriver->num = MXSER_PORTS + 1;
2838 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2839 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2840 mxvar_sdriver->init_termios = tty_std_termios;
2841 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2842 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2843 tty_set_operations(mxvar_sdriver, &mxser_ops);
2844
2845 retval = tty_register_driver(mxvar_sdriver);
2846 if (retval) {
2847 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2848 "tty driver !\n");
2849 goto err_put;
1da177e4 2850 }
1c45607a
JS		 2851
2852 mxvar_diagflag = 0;
2853
2854 m = 0;
2855 /* Start finding ISA boards here */
2856 for (isaloop = 0; isaloop < 2; isaloop++)
2857 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) {
2858 if (!isaloop)
2859 cap = mxserBoardCAP[b]; /* predefined */
2860 else
2861 cap = ioaddr[b]; /* module param */
2862
2863 if (!cap)
2864 continue;
2865
2866 brd = &mxser_boards[m];
2867 retval = mxser_get_ISA_conf(cap, brd);
2868
2869 if (retval != 0)
2870 printk(KERN_INFO "Found MOXA %s board "
2871 "(CAP=0x%x)\n",
2872 brd->info->name, ioaddr[b]);
2873
2874 if (retval <= 0) {
2875 if (retval == MXSER_ERR_IRQ)
2876 printk(KERN_ERR "Invalid interrupt "
2877 "number, board not "
2878 "configured\n");
2879 else if (retval == MXSER_ERR_IRQ_CONFLIT)
2880 printk(KERN_ERR "Invalid interrupt "
2881 "number, board not "
2882 "configured\n");
2883 else if (retval == MXSER_ERR_VECTOR)
2884 printk(KERN_ERR "Invalid interrupt "
2885 "vector, board not "
2886 "configured\n");
2887 else if (retval == MXSER_ERR_IOADDR)
2888 printk(KERN_ERR "Invalid I/O address, "
2889 "board not configured\n");
2890
2891 brd->info = NULL;
2892 continue;
2893 }
2894
2895 /* mxser_initbrd will hook ISR. */
2896 if (mxser_initbrd(brd, NULL) < 0) {
2897 brd->info = NULL;
2898 continue;
2899 }
2900
2901 brd->idx = m * MXSER_PORTS_PER_BOARD;
2902 for (i = 0; i < brd->info->nports; i++)
2903 tty_register_device(mxvar_sdriver, brd->idx + i,
2904 NULL);
2905
2906 m++;
2907 }
2908
2909 retval = pci_register_driver(&mxser_driver);
2910 if (retval) {
2911 printk(KERN_ERR "Can't register pci driver\n");
2912 if (!m) {
2913 retval = -ENODEV;
2914 goto err_unr;
2915 } /* else: we have some ISA cards under control */
2916 }
2917
2918 pr_debug("Done.\n");
2919
2920 return 0;
2921err_unr:
2922 tty_unregister_driver(mxvar_sdriver);
2923err_put:
2924 put_tty_driver(mxvar_sdriver);
2925 return retval;
2926}
2927
2928static void __exit mxser_module_exit(void)
2929{
2930 unsigned int i, j;
2931
2932 pr_debug("Unloading module mxser ...\n");
2933
2934 pci_unregister_driver(&mxser_driver);
2935
2936 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2937 if (mxser_boards[i].info != NULL)
2938 for (j = 0; j < mxser_boards[i].info->nports; j++)
2939 tty_unregister_device(mxvar_sdriver,
2940 mxser_boards[i].idx + j);
2941 tty_unregister_driver(mxvar_sdriver);
2942 put_tty_driver(mxvar_sdriver);
2943
2944 for (i = 0; i < MXSER_BOARDS; i++)
2945 if (mxser_boards[i].info != NULL)
2946 mxser_release_res(&mxser_boards[i], NULL, 1);
2947
2948 pr_debug("Done.\n");
1da177e4
LT		 2949}
2950
2951module_init(mxser_module_init);
2952module_exit(mxser_module_exit);
kernel source for telekom puls (alcatel/mediatek)