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drm: Fixes sparse warnings in via_dmablit.c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / drm / savage_bci.c
CommitLineData
282a1674
DA		 1/* savage_bci.c -- BCI support for Savage
2 *
3 * Copyright 2004 Felix Kuehling
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25#include "drmP.h"
26#include "savage_drm.h"
27#include "savage_drv.h"
28
29/* Need a long timeout for shadow status updates can take a while
30 * and so can waiting for events when the queue is full. */
b5e89ed5
DA		 31#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
32#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
282a1674
DA		 33#define SAVAGE_FREELIST_DEBUG 0
34
35static int
b5e89ed5 36savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n)
282a1674
DA		 37{
38 uint32_t mask = dev_priv->status_used_mask;
39 uint32_t threshold = dev_priv->bci_threshold_hi;
40 uint32_t status;
41 int i;
42
43#if SAVAGE_BCI_DEBUG
44 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold)
45 DRM_ERROR("Trying to emit %d words "
46 "(more than guaranteed space in COB)\n", n);
47#endif
48
49 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
50 DRM_MEMORYBARRIER();
51 status = dev_priv->status_ptr[0];
52 if ((status & mask) < threshold)
53 return 0;
54 DRM_UDELAY(1);
55 }
56
57#if SAVAGE_BCI_DEBUG
58 DRM_ERROR("failed!\n");
59 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold);
60#endif
61 return DRM_ERR(EBUSY);
62}
63
64static int
b5e89ed5 65savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n)
282a1674
DA		 66{
67 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
68 uint32_t status;
69 int i;
70
71 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
72 status = SAVAGE_READ(SAVAGE_STATUS_WORD0);
73 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed)
74 return 0;
75 DRM_UDELAY(1);
76 }
77
78#if SAVAGE_BCI_DEBUG
79 DRM_ERROR("failed!\n");
80 DRM_INFO(" status=0x%08x\n", status);
81#endif
82 return DRM_ERR(EBUSY);
83}
84
85static int
b5e89ed5 86savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n)
282a1674
DA		 87{
88 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
89 uint32_t status;
90 int i;
91
92 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
93 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0);
94 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed)
95 return 0;
96 DRM_UDELAY(1);
97 }
98
99#if SAVAGE_BCI_DEBUG
100 DRM_ERROR("failed!\n");
101 DRM_INFO(" status=0x%08x\n", status);
102#endif
103 return DRM_ERR(EBUSY);
104}
105
106/*
107 * Waiting for events.
108 *
109 * The BIOSresets the event tag to 0 on mode changes. Therefore we
110 * never emit 0 to the event tag. If we find a 0 event tag we know the
111 * BIOS stomped on it and return success assuming that the BIOS waited
112 * for engine idle.
113 *
114 * Note: if the Xserver uses the event tag it has to follow the same
115 * rule. Otherwise there may be glitches every 2^16 events.
116 */
117static int
b5e89ed5 118savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e)
282a1674
DA		 119{
120 uint32_t status;
121 int i;
122
123 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
124 DRM_MEMORYBARRIER();
125 status = dev_priv->status_ptr[1];
126 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
127 (status & 0xffff) == 0)
128 return 0;
129 DRM_UDELAY(1);
130 }
131
132#if SAVAGE_BCI_DEBUG
133 DRM_ERROR("failed!\n");
134 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
135#endif
136
137 return DRM_ERR(EBUSY);
138}
139
140static int
b5e89ed5 141savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e)
282a1674
DA		 142{
143 uint32_t status;
144 int i;
145
146 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
147 status = SAVAGE_READ(SAVAGE_STATUS_WORD1);
148 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
149 (status & 0xffff) == 0)
150 return 0;
151 DRM_UDELAY(1);
152 }
153
154#if SAVAGE_BCI_DEBUG
155 DRM_ERROR("failed!\n");
156 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
157#endif
158
159 return DRM_ERR(EBUSY);
160}
161
b5e89ed5 162uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
282a1674
DA		 163 unsigned int flags)
164{
165 uint16_t count;
166 BCI_LOCALS;
167
168 if (dev_priv->status_ptr) {
169 /* coordinate with Xserver */
170 count = dev_priv->status_ptr[1023];
171 if (count < dev_priv->event_counter)
172 dev_priv->event_wrap++;
173 } else {
174 count = dev_priv->event_counter;
175 }
176 count = (count + 1) & 0xffff;
177 if (count == 0) {
b5e89ed5 178 count++; /* See the comment above savage_wait_event_*. */
282a1674
DA		 179 dev_priv->event_wrap++;
180 }
181 dev_priv->event_counter = count;
182 if (dev_priv->status_ptr)
b5e89ed5 183 dev_priv->status_ptr[1023] = (uint32_t) count;
282a1674
DA		 184
185 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
186 unsigned int wait_cmd = BCI_CMD_WAIT;
187 if ((flags & SAVAGE_WAIT_2D))
188 wait_cmd |= BCI_CMD_WAIT_2D;
189 if ((flags & SAVAGE_WAIT_3D))
190 wait_cmd |= BCI_CMD_WAIT_3D;
191 BEGIN_BCI(2);
192 BCI_WRITE(wait_cmd);
193 } else {
194 BEGIN_BCI(1);
195 }
b5e89ed5 196 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count);
282a1674
DA		 197
198 return count;
199}
200
201/*
202 * Freelist management
203 */
b5e89ed5 204static int savage_freelist_init(drm_device_t * dev)
282a1674
DA		 205{
206 drm_savage_private_t *dev_priv = dev->dev_private;
207 drm_device_dma_t *dma = dev->dma;
208 drm_buf_t *buf;
209 drm_savage_buf_priv_t *entry;
210 int i;
211 DRM_DEBUG("count=%d\n", dma->buf_count);
212
213 dev_priv->head.next = &dev_priv->tail;
214 dev_priv->head.prev = NULL;
215 dev_priv->head.buf = NULL;
216
217 dev_priv->tail.next = NULL;
218 dev_priv->tail.prev = &dev_priv->head;
219 dev_priv->tail.buf = NULL;
220
221 for (i = 0; i < dma->buf_count; i++) {
222 buf = dma->buflist[i];
223 entry = buf->dev_private;
224
225 SET_AGE(&entry->age, 0, 0);
226 entry->buf = buf;
227
228 entry->next = dev_priv->head.next;
229 entry->prev = &dev_priv->head;
230 dev_priv->head.next->prev = entry;
231 dev_priv->head.next = entry;
232 }
233
234 return 0;
235}
236
b5e89ed5 237static drm_buf_t *savage_freelist_get(drm_device_t * dev)
282a1674
DA		 238{
239 drm_savage_private_t *dev_priv = dev->dev_private;
240 drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
241 uint16_t event;
242 unsigned int wrap;
243 DRM_DEBUG("\n");
244
245 UPDATE_EVENT_COUNTER();
246 if (dev_priv->status_ptr)
247 event = dev_priv->status_ptr[1] & 0xffff;
248 else
249 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
250 wrap = dev_priv->event_wrap;
251 if (event > dev_priv->event_counter)
b5e89ed5 252 wrap--; /* hardware hasn't passed the last wrap yet */
282a1674
DA		 253
254 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
255 DRM_DEBUG(" head=0x%04x %d\n", event, wrap);
256
257 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) {
258 drm_savage_buf_priv_t *next = tail->next;
259 drm_savage_buf_priv_t *prev = tail->prev;
260 prev->next = next;
261 next->prev = prev;
262 tail->next = tail->prev = NULL;
263 return tail->buf;
264 }
265
266 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf);
267 return NULL;
268}
269
b5e89ed5 270void savage_freelist_put(drm_device_t * dev, drm_buf_t * buf)
282a1674
DA		 271{
272 drm_savage_private_t *dev_priv = dev->dev_private;
273 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
274
275 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap);
276
277 if (entry->next != NULL || entry->prev != NULL) {
278 DRM_ERROR("entry already on freelist.\n");
279 return;
280 }
281
282 prev = &dev_priv->head;
283 next = prev->next;
284 prev->next = entry;
285 next->prev = entry;
286 entry->prev = prev;
287 entry->next = next;
288}
289
290/*
291 * Command DMA
292 */
b5e89ed5 293static int savage_dma_init(drm_savage_private_t * dev_priv)
282a1674
DA		 294{
295 unsigned int i;
296
297 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
b5e89ed5 298 (SAVAGE_DMA_PAGE_SIZE * 4);
282a1674 299 dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) *
b5e89ed5 300 dev_priv->nr_dma_pages, DRM_MEM_DRIVER);
282a1674
DA		 301 if (dev_priv->dma_pages == NULL)
302 return DRM_ERR(ENOMEM);
303
304 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
305 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0);
306 dev_priv->dma_pages[i].used = 0;
307 dev_priv->dma_pages[i].flushed = 0;
308 }
309 SET_AGE(&dev_priv->last_dma_age, 0, 0);
310
311 dev_priv->first_dma_page = 0;
312 dev_priv->current_dma_page = 0;
313
314 return 0;
315}
316
b5e89ed5 317void savage_dma_reset(drm_savage_private_t * dev_priv)
282a1674
DA		 318{
319 uint16_t event;
320 unsigned int wrap, i;
321 event = savage_bci_emit_event(dev_priv, 0);
322 wrap = dev_priv->event_wrap;
323 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
324 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
325 dev_priv->dma_pages[i].used = 0;
326 dev_priv->dma_pages[i].flushed = 0;
327 }
328 SET_AGE(&dev_priv->last_dma_age, event, wrap);
329 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
330}
331
b5e89ed5 332void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page)
282a1674
DA		 333{
334 uint16_t event;
335 unsigned int wrap;
336
337 /* Faked DMA buffer pages don't age. */
338 if (dev_priv->cmd_dma == &dev_priv->fake_dma)
339 return;
340
341 UPDATE_EVENT_COUNTER();
342 if (dev_priv->status_ptr)
343 event = dev_priv->status_ptr[1] & 0xffff;
344 else
345 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
346 wrap = dev_priv->event_wrap;
347 if (event > dev_priv->event_counter)
b5e89ed5 348 wrap--; /* hardware hasn't passed the last wrap yet */
282a1674
DA		 349
350 if (dev_priv->dma_pages[page].age.wrap > wrap ||
351 (dev_priv->dma_pages[page].age.wrap == wrap &&
352 dev_priv->dma_pages[page].age.event > event)) {
353 if (dev_priv->wait_evnt(dev_priv,
354 dev_priv->dma_pages[page].age.event)
355 < 0)
356 DRM_ERROR("wait_evnt failed!\n");
357 }
358}
359
b5e89ed5 360uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n)
282a1674
DA		 361{
362 unsigned int cur = dev_priv->current_dma_page;
363 unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
b5e89ed5
DA		 364 dev_priv->dma_pages[cur].used;
365 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) /
366 SAVAGE_DMA_PAGE_SIZE;
282a1674
DA		 367 uint32_t *dma_ptr;
368 unsigned int i;
369
370 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
371 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
372
373 if (cur + nr_pages < dev_priv->nr_dma_pages) {
b5e89ed5
DA		 374 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
375 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
282a1674
DA		 376 if (n < rest)
377 rest = n;
378 dev_priv->dma_pages[cur].used += rest;
379 n -= rest;
380 cur++;
381 } else {
382 dev_priv->dma_flush(dev_priv);
b5e89ed5
DA		 383 nr_pages =
384 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE;
282a1674
DA		 385 for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
386 dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
387 dev_priv->dma_pages[i].used = 0;
388 dev_priv->dma_pages[i].flushed = 0;
389 }
b5e89ed5 390 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle;
282a1674
DA		 391 dev_priv->first_dma_page = cur = 0;
392 }
393 for (i = cur; nr_pages > 0; ++i, --nr_pages) {
394#if SAVAGE_DMA_DEBUG
395 if (dev_priv->dma_pages[i].used) {
396 DRM_ERROR("unflushed page %u: used=%u\n",
397 i, dev_priv->dma_pages[i].used);
398 }
399#endif
400 if (n > SAVAGE_DMA_PAGE_SIZE)
401 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE;
402 else
403 dev_priv->dma_pages[i].used = n;
404 n -= SAVAGE_DMA_PAGE_SIZE;
405 }
406 dev_priv->current_dma_page = --i;
407
408 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
409 i, dev_priv->dma_pages[i].used, n);
410
411 savage_dma_wait(dev_priv, dev_priv->current_dma_page);
412
413 return dma_ptr;
414}
415
b5e89ed5 416static void savage_dma_flush(drm_savage_private_t * dev_priv)
282a1674
DA		 417{
418 unsigned int first = dev_priv->first_dma_page;
419 unsigned int cur = dev_priv->current_dma_page;
420 uint16_t event;
421 unsigned int wrap, pad, align, len, i;
422 unsigned long phys_addr;
423 BCI_LOCALS;
424
425 if (first == cur &&
426 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed)
427 return;
428
429 /* pad length to multiples of 2 entries
430 * align start of next DMA block to multiles of 8 entries */
431 pad = -dev_priv->dma_pages[cur].used & 1;
432 align = -(dev_priv->dma_pages[cur].used + pad) & 7;
433
434 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
435 "pad=%u, align=%u\n",
436 first, cur, dev_priv->dma_pages[first].flushed,
437 dev_priv->dma_pages[cur].used, pad, align);
438
439 /* pad with noops */
440 if (pad) {
b5e89ed5
DA		 441 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
442 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
282a1674 443 dev_priv->dma_pages[cur].used += pad;
b5e89ed5 444 while (pad != 0) {
282a1674
DA		 445 *dma_ptr++ = BCI_CMD_WAIT;
446 pad--;
447 }
448 }
449
450 DRM_MEMORYBARRIER();
451
452 /* do flush ... */
453 phys_addr = dev_priv->cmd_dma->offset +
b5e89ed5
DA		 454 (first * SAVAGE_DMA_PAGE_SIZE +
455 dev_priv->dma_pages[first].flushed) * 4;
282a1674 456 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
b5e89ed5 457 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed;
282a1674
DA		 458
459 DRM_DEBUG("phys_addr=%lx, len=%u\n",
460 phys_addr | dev_priv->dma_type, len);
461
462 BEGIN_BCI(3);
463 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1);
464 BCI_WRITE(phys_addr | dev_priv->dma_type);
465 BCI_DMA(len);
466
467 /* fix alignment of the start of the next block */
468 dev_priv->dma_pages[cur].used += align;
469
470 /* age DMA pages */
471 event = savage_bci_emit_event(dev_priv, 0);
472 wrap = dev_priv->event_wrap;
473 for (i = first; i < cur; ++i) {
474 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
475 dev_priv->dma_pages[i].used = 0;
476 dev_priv->dma_pages[i].flushed = 0;
477 }
478 /* age the current page only when it's full */
479 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) {
480 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap);
481 dev_priv->dma_pages[cur].used = 0;
482 dev_priv->dma_pages[cur].flushed = 0;
483 /* advance to next page */
484 cur++;
485 if (cur == dev_priv->nr_dma_pages)
486 cur = 0;
487 dev_priv->first_dma_page = dev_priv->current_dma_page = cur;
488 } else {
489 dev_priv->first_dma_page = cur;
490 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used;
491 }
492 SET_AGE(&dev_priv->last_dma_age, event, wrap);
493
494 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur,
495 dev_priv->dma_pages[cur].used,
496 dev_priv->dma_pages[cur].flushed);
497}
498
b5e89ed5 499static void savage_fake_dma_flush(drm_savage_private_t * dev_priv)
282a1674
DA		 500{
501 unsigned int i, j;
502 BCI_LOCALS;
503
504 if (dev_priv->first_dma_page == dev_priv->current_dma_page &&
505 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0)
506 return;
507
508 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
509 dev_priv->first_dma_page, dev_priv->current_dma_page,
510 dev_priv->dma_pages[dev_priv->current_dma_page].used);
511
512 for (i = dev_priv->first_dma_page;
513 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
514 ++i) {
b5e89ed5
DA		 515 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
516 i * SAVAGE_DMA_PAGE_SIZE;
282a1674
DA		 517#if SAVAGE_DMA_DEBUG
518 /* Sanity check: all pages except the last one must be full. */
519 if (i < dev_priv->current_dma_page &&
520 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) {
521 DRM_ERROR("partial DMA page %u: used=%u",
522 i, dev_priv->dma_pages[i].used);
523 }
524#endif
525 BEGIN_BCI(dev_priv->dma_pages[i].used);
526 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) {
527 BCI_WRITE(dma_ptr[j]);
528 }
529 dev_priv->dma_pages[i].used = 0;
530 }
531
532 /* reset to first page */
533 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
534}
535
22eae947
DA		 536int savage_driver_load(drm_device_t *dev, unsigned long chipset)
537{
538 drm_savage_private_t *dev_priv;
539
540 dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
541 if (dev_priv == NULL)
542 return DRM_ERR(ENOMEM);
543
544 memset(dev_priv, 0, sizeof(drm_savage_private_t));
545 dev->dev_private = (void *)dev_priv;
546
547 dev_priv->chipset = (enum savage_family)chipset;
548
549 return 0;
550}
551
552
282a1674
DA		 553/*
554 * Initalize mappings. On Savage4 and SavageIX the alignment
555 * and size of the aperture is not suitable for automatic MTRR setup
22eae947
DA		 556 * in drm_addmap. Therefore we add them manually before the maps are
557 * initialized, and tear them down on last close.
282a1674 558 */
22eae947 559int savage_driver_firstopen(drm_device_t *dev)
282a1674 560{
22eae947 561 drm_savage_private_t *dev_priv = dev->dev_private;
282a1674
DA		 562 unsigned long mmio_base, fb_base, fb_size, aperture_base;
563 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist
564 * in case we decide we need information on the BAR for BSD in the
565 * future.
566 */
567 unsigned int fb_rsrc, aper_rsrc;
568 int ret = 0;
569
282a1674
DA		 570 dev_priv->mtrr[0].handle = -1;
571 dev_priv->mtrr[1].handle = -1;
572 dev_priv->mtrr[2].handle = -1;
573 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
574 fb_rsrc = 0;
575 fb_base = drm_get_resource_start(dev, 0);
576 fb_size = SAVAGE_FB_SIZE_S3;
577 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
578 aper_rsrc = 0;
579 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
580 /* this should always be true */
581 if (drm_get_resource_len(dev, 0) == 0x08000000) {
582 /* Don't make MMIO write-cobining! We need 3
583 * MTRRs. */
584 dev_priv->mtrr[0].base = fb_base;
585 dev_priv->mtrr[0].size = 0x01000000;
b5e89ed5 586 dev_priv->mtrr[0].handle =
269dc512
DA		 587 drm_mtrr_add(dev_priv->mtrr[0].base,
588 dev_priv->mtrr[0].size, DRM_MTRR_WC);
b5e89ed5 589 dev_priv->mtrr[1].base = fb_base + 0x02000000;
282a1674 590 dev_priv->mtrr[1].size = 0x02000000;
b5e89ed5 591 dev_priv->mtrr[1].handle =
269dc512
DA		 592 drm_mtrr_add(dev_priv->mtrr[1].base,
593 dev_priv->mtrr[1].size, DRM_MTRR_WC);
b5e89ed5 594 dev_priv->mtrr[2].base = fb_base + 0x04000000;
282a1674 595 dev_priv->mtrr[2].size = 0x04000000;
b5e89ed5 596 dev_priv->mtrr[2].handle =
269dc512
DA		 597 drm_mtrr_add(dev_priv->mtrr[2].base,
598 dev_priv->mtrr[2].size, DRM_MTRR_WC);
282a1674
DA		 599 } else {
600 DRM_ERROR("strange pci_resource_len %08lx\n",
601 drm_get_resource_len(dev, 0));
602 }
22eae947
DA		 603 } else if (dev_priv->chipset != S3_SUPERSAVAGE &&
604 dev_priv->chipset != S3_SAVAGE2000) {
282a1674
DA		 605 mmio_base = drm_get_resource_start(dev, 0);
606 fb_rsrc = 1;
607 fb_base = drm_get_resource_start(dev, 1);
608 fb_size = SAVAGE_FB_SIZE_S4;
609 aper_rsrc = 1;
610 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
611 /* this should always be true */
612 if (drm_get_resource_len(dev, 1) == 0x08000000) {
613 /* Can use one MTRR to cover both fb and
614 * aperture. */
615 dev_priv->mtrr[0].base = fb_base;
616 dev_priv->mtrr[0].size = 0x08000000;
b5e89ed5 617 dev_priv->mtrr[0].handle =
269dc512
DA		 618 drm_mtrr_add(dev_priv->mtrr[0].base,
619 dev_priv->mtrr[0].size, DRM_MTRR_WC);
282a1674
DA		 620 } else {
621 DRM_ERROR("strange pci_resource_len %08lx\n",
622 drm_get_resource_len(dev, 1));
623 }
624 } else {
625 mmio_base = drm_get_resource_start(dev, 0);
626 fb_rsrc = 1;
627 fb_base = drm_get_resource_start(dev, 1);
628 fb_size = drm_get_resource_len(dev, 1);
629 aper_rsrc = 2;
630 aperture_base = drm_get_resource_start(dev, 2);
631 /* Automatic MTRR setup will do the right thing. */
632 }
633
634 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
635 _DRM_READ_ONLY, &dev_priv->mmio);
636 if (ret)
637 return ret;
638
639 ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
640 _DRM_WRITE_COMBINING, &dev_priv->fb);
641 if (ret)
642 return ret;
643
644 ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
645 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
646 &dev_priv->aperture);
647 if (ret)
648 return ret;
649
650 return ret;
651}
652
653/*
654 * Delete MTRRs and free device-private data.
655 */
22eae947 656void savage_driver_lastclose(drm_device_t *dev)
282a1674
DA		 657{
658 drm_savage_private_t *dev_priv = dev->dev_private;
659 int i;
660
661 for (i = 0; i < 3; ++i)
662 if (dev_priv->mtrr[i].handle >= 0)
269dc512 663 drm_mtrr_del(dev_priv->mtrr[i].handle,
282a1674 664 dev_priv->mtrr[i].base,
269dc512 665 dev_priv->mtrr[i].size, DRM_MTRR_WC);
22eae947
DA		 666}
667
668int savage_driver_unload(drm_device_t *dev)
669{
670 drm_savage_private_t *dev_priv = dev->dev_private;
282a1674
DA		 671
672 drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
673
674 return 0;
675}
676
b5e89ed5 677static int savage_do_init_bci(drm_device_t * dev, drm_savage_init_t * init)
282a1674
DA		 678{
679 drm_savage_private_t *dev_priv = dev->dev_private;
680
681 if (init->fb_bpp != 16 && init->fb_bpp != 32) {
682 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp);
683 return DRM_ERR(EINVAL);
684 }
685 if (init->depth_bpp != 16 && init->depth_bpp != 32) {
686 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp);
687 return DRM_ERR(EINVAL);
688 }
689 if (init->dma_type != SAVAGE_DMA_AGP &&
690 init->dma_type != SAVAGE_DMA_PCI) {
691 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type);
692 return DRM_ERR(EINVAL);
693 }
694
695 dev_priv->cob_size = init->cob_size;
696 dev_priv->bci_threshold_lo = init->bci_threshold_lo;
697 dev_priv->bci_threshold_hi = init->bci_threshold_hi;
698 dev_priv->dma_type = init->dma_type;
699
700 dev_priv->fb_bpp = init->fb_bpp;
701 dev_priv->front_offset = init->front_offset;
702 dev_priv->front_pitch = init->front_pitch;
703 dev_priv->back_offset = init->back_offset;
704 dev_priv->back_pitch = init->back_pitch;
705 dev_priv->depth_bpp = init->depth_bpp;
706 dev_priv->depth_offset = init->depth_offset;
707 dev_priv->depth_pitch = init->depth_pitch;
708
709 dev_priv->texture_offset = init->texture_offset;
710 dev_priv->texture_size = init->texture_size;
711
712 DRM_GETSAREA();
713 if (!dev_priv->sarea) {
714 DRM_ERROR("could not find sarea!\n");
715 savage_do_cleanup_bci(dev);
716 return DRM_ERR(EINVAL);
717 }
718 if (init->status_offset != 0) {
719 dev_priv->status = drm_core_findmap(dev, init->status_offset);
720 if (!dev_priv->status) {
721 DRM_ERROR("could not find shadow status region!\n");
722 savage_do_cleanup_bci(dev);
723 return DRM_ERR(EINVAL);
724 }
725 } else {
726 dev_priv->status = NULL;
727 }
728 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) {
729 dev->agp_buffer_map = drm_core_findmap(dev,
730 init->buffers_offset);
731 if (!dev->agp_buffer_map) {
732 DRM_ERROR("could not find DMA buffer region!\n");
733 savage_do_cleanup_bci(dev);
734 return DRM_ERR(EINVAL);
735 }
736 drm_core_ioremap(dev->agp_buffer_map, dev);
737 if (!dev->agp_buffer_map) {
738 DRM_ERROR("failed to ioremap DMA buffer region!\n");
739 savage_do_cleanup_bci(dev);
740 return DRM_ERR(ENOMEM);
741 }
742 }
743 if (init->agp_textures_offset) {
744 dev_priv->agp_textures =
b5e89ed5 745 drm_core_findmap(dev, init->agp_textures_offset);
282a1674
DA		 746 if (!dev_priv->agp_textures) {
747 DRM_ERROR("could not find agp texture region!\n");
748 savage_do_cleanup_bci(dev);
749 return DRM_ERR(EINVAL);
750 }
751 } else {
752 dev_priv->agp_textures = NULL;
753 }
754
755 if (init->cmd_dma_offset) {
756 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
757 DRM_ERROR("command DMA not supported on "
758 "Savage3D/MX/IX.\n");
759 savage_do_cleanup_bci(dev);
760 return DRM_ERR(EINVAL);
761 }
762 if (dev->dma && dev->dma->buflist) {
763 DRM_ERROR("command and vertex DMA not supported "
764 "at the same time.\n");
765 savage_do_cleanup_bci(dev);
766 return DRM_ERR(EINVAL);
767 }
768 dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset);
769 if (!dev_priv->cmd_dma) {
770 DRM_ERROR("could not find command DMA region!\n");
771 savage_do_cleanup_bci(dev);
772 return DRM_ERR(EINVAL);
773 }
774 if (dev_priv->dma_type == SAVAGE_DMA_AGP) {
775 if (dev_priv->cmd_dma->type != _DRM_AGP) {
776 DRM_ERROR("AGP command DMA region is not a "
777 "_DRM_AGP map!\n");
778 savage_do_cleanup_bci(dev);
779 return DRM_ERR(EINVAL);
780 }
781 drm_core_ioremap(dev_priv->cmd_dma, dev);
782 if (!dev_priv->cmd_dma->handle) {
783 DRM_ERROR("failed to ioremap command "
784 "DMA region!\n");
785 savage_do_cleanup_bci(dev);
786 return DRM_ERR(ENOMEM);
787 }
788 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) {
789 DRM_ERROR("PCI command DMA region is not a "
790 "_DRM_CONSISTENT map!\n");
791 savage_do_cleanup_bci(dev);
792 return DRM_ERR(EINVAL);
793 }
794 } else {
795 dev_priv->cmd_dma = NULL;
796 }
797
798 dev_priv->dma_flush = savage_dma_flush;
799 if (!dev_priv->cmd_dma) {
800 DRM_DEBUG("falling back to faked command DMA.\n");
801 dev_priv->fake_dma.offset = 0;
802 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE;
803 dev_priv->fake_dma.type = _DRM_SHM;
804 dev_priv->fake_dma.handle = drm_alloc(SAVAGE_FAKE_DMA_SIZE,
805 DRM_MEM_DRIVER);
806 if (!dev_priv->fake_dma.handle) {
807 DRM_ERROR("could not allocate faked DMA buffer!\n");
808 savage_do_cleanup_bci(dev);
809 return DRM_ERR(ENOMEM);
810 }
811 dev_priv->cmd_dma = &dev_priv->fake_dma;
812 dev_priv->dma_flush = savage_fake_dma_flush;
813 }
814
815 dev_priv->sarea_priv =
b5e89ed5
DA		 816 (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle +
817 init->sarea_priv_offset);
282a1674
DA		 818
819 /* setup bitmap descriptors */
820 {
821 unsigned int color_tile_format;
822 unsigned int depth_tile_format;
823 unsigned int front_stride, back_stride, depth_stride;
824 if (dev_priv->chipset <= S3_SAVAGE4) {
825 color_tile_format = dev_priv->fb_bpp == 16 ?
b5e89ed5 826 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
282a1674 827 depth_tile_format = dev_priv->depth_bpp == 16 ?
b5e89ed5 828 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
282a1674
DA		 829 } else {
830 color_tile_format = SAVAGE_BD_TILE_DEST;
831 depth_tile_format = SAVAGE_BD_TILE_DEST;
832 }
b5e89ed5
DA		 833 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
834 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
835 depth_stride =
836 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
282a1674
DA		 837
838 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
b5e89ed5
DA		 839 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
840 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
282a1674 841
b5e89ed5
DA		 842 dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE |
843 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
844 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
282a1674
DA		 845
846 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
b5e89ed5
DA		 847 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
848 (depth_tile_format << SAVAGE_BD_TILE_SHIFT);
282a1674
DA		 849 }
850
851 /* setup status and bci ptr */
852 dev_priv->event_counter = 0;
853 dev_priv->event_wrap = 0;
854 dev_priv->bci_ptr = (volatile uint32_t *)
b5e89ed5 855 ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
282a1674
DA		 856 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
857 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
858 } else {
859 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4;
860 }
861 if (dev_priv->status != NULL) {
862 dev_priv->status_ptr =
b5e89ed5 863 (volatile uint32_t *)dev_priv->status->handle;
282a1674
DA		 864 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
865 dev_priv->wait_evnt = savage_bci_wait_event_shadow;
866 dev_priv->status_ptr[1023] = dev_priv->event_counter;
867 } else {
868 dev_priv->status_ptr = NULL;
869 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
870 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d;
871 } else {
872 dev_priv->wait_fifo = savage_bci_wait_fifo_s4;
873 }
874 dev_priv->wait_evnt = savage_bci_wait_event_reg;
875 }
876
877 /* cliprect functions */
878 if (S3_SAVAGE3D_SERIES(dev_priv->chipset))
879 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d;
880 else
881 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4;
882
883 if (savage_freelist_init(dev) < 0) {
884 DRM_ERROR("could not initialize freelist\n");
885 savage_do_cleanup_bci(dev);
886 return DRM_ERR(ENOMEM);
887 }
888
b5e89ed5 889 if (savage_dma_init(dev_priv) < 0) {
282a1674
DA		 890 DRM_ERROR("could not initialize command DMA\n");
891 savage_do_cleanup_bci(dev);
892 return DRM_ERR(ENOMEM);
893 }
894
895 return 0;
896}
897
b5e89ed5 898int savage_do_cleanup_bci(drm_device_t * dev)
282a1674
DA		 899{
900 drm_savage_private_t *dev_priv = dev->dev_private;
901
902 if (dev_priv->cmd_dma == &dev_priv->fake_dma) {
903 if (dev_priv->fake_dma.handle)
904 drm_free(dev_priv->fake_dma.handle,
905 SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER);
906 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle &&
907 dev_priv->cmd_dma->type == _DRM_AGP &&
908 dev_priv->dma_type == SAVAGE_DMA_AGP)
909 drm_core_ioremapfree(dev_priv->cmd_dma, dev);
910
911 if (dev_priv->dma_type == SAVAGE_DMA_AGP &&
912 dev->agp_buffer_map && dev->agp_buffer_map->handle) {
913 drm_core_ioremapfree(dev->agp_buffer_map, dev);
914 /* make sure the next instance (which may be running
915 * in PCI mode) doesn't try to use an old
916 * agp_buffer_map. */
917 dev->agp_buffer_map = NULL;
918 }
919
920 if (dev_priv->dma_pages)
921 drm_free(dev_priv->dma_pages,
b5e89ed5 922 sizeof(drm_savage_dma_page_t) * dev_priv->nr_dma_pages,
282a1674
DA		 923 DRM_MEM_DRIVER);
924
925 return 0;
926}
927
928static int savage_bci_init(DRM_IOCTL_ARGS)
929{
930 DRM_DEVICE;
931 drm_savage_init_t init;
932
933 LOCK_TEST_WITH_RETURN(dev, filp);
934
b5e89ed5 935 DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *) data,
282a1674
DA		 936 sizeof(init));
937
938 switch (init.func) {
939 case SAVAGE_INIT_BCI:
940 return savage_do_init_bci(dev, &init);
941 case SAVAGE_CLEANUP_BCI:
942 return savage_do_cleanup_bci(dev);
943 }
944
945 return DRM_ERR(EINVAL);
946}
947
948static int savage_bci_event_emit(DRM_IOCTL_ARGS)
949{
950 DRM_DEVICE;
951 drm_savage_private_t *dev_priv = dev->dev_private;
952 drm_savage_event_emit_t event;
953
954 DRM_DEBUG("\n");
955
956 LOCK_TEST_WITH_RETURN(dev, filp);
957
b5e89ed5 958 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *) data,
282a1674
DA		 959 sizeof(event));
960
961 event.count = savage_bci_emit_event(dev_priv, event.flags);
962 event.count |= dev_priv->event_wrap << 16;
b5e89ed5
DA		 963 DRM_COPY_TO_USER_IOCTL(&((drm_savage_event_emit_t __user *) data)->
964 count, event.count, sizeof(event.count));
282a1674
DA		 965 return 0;
966}
967
968static int savage_bci_event_wait(DRM_IOCTL_ARGS)
969{
970 DRM_DEVICE;
971 drm_savage_private_t *dev_priv = dev->dev_private;
972 drm_savage_event_wait_t event;
973 unsigned int event_e, hw_e;
974 unsigned int event_w, hw_w;
975
976 DRM_DEBUG("\n");
977
b5e89ed5 978 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *) data,
282a1674
DA		 979 sizeof(event));
980
981 UPDATE_EVENT_COUNTER();
982 if (dev_priv->status_ptr)
983 hw_e = dev_priv->status_ptr[1] & 0xffff;
984 else
985 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
986 hw_w = dev_priv->event_wrap;
987 if (hw_e > dev_priv->event_counter)
b5e89ed5 988 hw_w--; /* hardware hasn't passed the last wrap yet */
282a1674
DA		 989
990 event_e = event.count & 0xffff;
991 event_w = event.count >> 16;
992
993 /* Don't need to wait if
994 * - event counter wrapped since the event was emitted or
995 * - the hardware has advanced up to or over the event to wait for.
996 */
b5e89ed5 997 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e))
282a1674
DA		 998 return 0;
999 else
1000 return dev_priv->wait_evnt(dev_priv, event_e);
1001}
1002
1003/*
1004 * DMA buffer management
1005 */
1006
269dc512 1007static int savage_bci_get_buffers(DRMFILE filp, drm_device_t *dev, drm_dma_t *d)
282a1674
DA		 1008{
1009 drm_buf_t *buf;
1010 int i;
1011
1012 for (i = d->granted_count; i < d->request_count; i++) {
1013 buf = savage_freelist_get(dev);
1014 if (!buf)
1015 return DRM_ERR(EAGAIN);
1016
1017 buf->filp = filp;
1018
1019 if (DRM_COPY_TO_USER(&d->request_indices[i],
1020 &buf->idx, sizeof(buf->idx)))
1021 return DRM_ERR(EFAULT);
1022 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1023 &buf->total, sizeof(buf->total)))
1024 return DRM_ERR(EFAULT);
1025
1026 d->granted_count++;
1027 }
1028 return 0;
1029}
1030
1031int savage_bci_buffers(DRM_IOCTL_ARGS)
1032{
1033 DRM_DEVICE;
1034 drm_device_dma_t *dma = dev->dma;
1035 drm_dma_t d;
1036 int ret = 0;
1037
1038 LOCK_TEST_WITH_RETURN(dev, filp);
1039
b5e89ed5 1040 DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *) data, sizeof(d));
282a1674
DA		 1041
1042 /* Please don't send us buffers.
1043 */
1044 if (d.send_count != 0) {
1045 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1046 DRM_CURRENTPID, d.send_count);
1047 return DRM_ERR(EINVAL);
1048 }
1049
1050 /* We'll send you buffers.
1051 */
1052 if (d.request_count < 0 || d.request_count > dma->buf_count) {
1053 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1054 DRM_CURRENTPID, d.request_count, dma->buf_count);
1055 return DRM_ERR(EINVAL);
1056 }
1057
1058 d.granted_count = 0;
1059
1060 if (d.request_count) {
1061 ret = savage_bci_get_buffers(filp, dev, &d);
1062 }
1063
b5e89ed5 1064 DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *) data, d, sizeof(d));
282a1674
DA		 1065
1066 return ret;
1067}
1068
269dc512 1069void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp)
b5e89ed5 1070{
282a1674
DA		 1071 drm_device_dma_t *dma = dev->dma;
1072 drm_savage_private_t *dev_priv = dev->dev_private;
1073 int i;
1074
1075 if (!dma)
1076 return;
1077 if (!dev_priv)
1078 return;
1079 if (!dma->buflist)
1080 return;
1081
b5e89ed5 1082 /*i830_flush_queue(dev); */
282a1674
DA		 1083
1084 for (i = 0; i < dma->buf_count; i++) {
1085 drm_buf_t *buf = dma->buflist[i];
1086 drm_savage_buf_priv_t *buf_priv = buf->dev_private;
1087
1088 if (buf->filp == filp && buf_priv &&
1089 buf_priv->next == NULL && buf_priv->prev == NULL) {
1090 uint16_t event;
1091 DRM_DEBUG("reclaimed from client\n");
1092 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
1093 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
1094 savage_freelist_put(dev, buf);
1095 }
1096 }
1097
1098 drm_core_reclaim_buffers(dev, filp);
1099}
1100
282a1674 1101drm_ioctl_desc_t savage_ioctls[] = {
a7a2cc31
DA		 1102 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1103 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, DRM_AUTH},
1104 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, DRM_AUTH},
1105 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, DRM_AUTH},
282a1674
DA		 1106};
1107
1108int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
kernel source for telekom puls (alcatel/mediatek)