[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / agp / parisc-agp.c

/*
 * HP Quicksilver AGP GART routines
 *
 * Copyright (c) 2006, Kyle McMartin <kyle@parisc-linux.org>
 *
 * Based on drivers/char/agpgart/hp-agp.c which is
 * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
 *	Bjorn Helgaas <bjorn.helgaas@hp.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/klist.h>
#include <linux/agp_backend.h>
#include <linux/log2.h>

#include <asm/parisc-device.h>
#include <asm/ropes.h>

#include "agp.h"

#define DRVNAME	"quicksilver"
#define DRVPFX	DRVNAME ": "

#define AGP8X_MODE_BIT		3
#define AGP8X_MODE		(1 << AGP8X_MODE_BIT)

static unsigned long
parisc_agp_mask_memory(struct agp_bridge_data *bridge, unsigned long addr,
		       int type);

static struct _parisc_agp_info {
	void __iomem *ioc_regs;
	void __iomem *lba_regs;

	int lba_cap_offset;

	u64 *gatt;
	u64 gatt_entries;

	u64 gart_base;
	u64 gart_size;

	int io_page_size;
	int io_pages_per_kpage;
} parisc_agp_info;

static struct gatt_mask parisc_agp_masks[] =
{
        {
		.mask = SBA_PDIR_VALID_BIT,
		.type = 0
	}
};

static struct aper_size_info_fixed parisc_agp_sizes[] =
{
        {0, 0, 0},              /* filled in by parisc_agp_fetch_size() */
};

static int
parisc_agp_fetch_size(void)
{
	int size;

	size = parisc_agp_info.gart_size / MB(1);
	parisc_agp_sizes[0].size = size;
	agp_bridge->current_size = (void *) &parisc_agp_sizes[0];

	return size;
}

static int
parisc_agp_configure(void)
{
	struct _parisc_agp_info *info = &parisc_agp_info;

	agp_bridge->gart_bus_addr = info->gart_base;
	agp_bridge->capndx = info->lba_cap_offset;
	agp_bridge->mode = readl(info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS);

	return 0;
}

static void
parisc_agp_tlbflush(struct agp_memory *mem)
{
	struct _parisc_agp_info *info = &parisc_agp_info;

	writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM);
	readq(info->ioc_regs+IOC_PCOM);	/* flush */
}

static int
parisc_agp_create_gatt_table(struct agp_bridge_data *bridge)
{
	struct _parisc_agp_info *info = &parisc_agp_info;
	int i;

	for (i = 0; i < info->gatt_entries; i++) {
		info->gatt[i] = (unsigned long)agp_bridge->scratch_page;
	}

	return 0;
}

static int
parisc_agp_free_gatt_table(struct agp_bridge_data *bridge)
{
	struct _parisc_agp_info *info = &parisc_agp_info;

	info->gatt[0] = SBA_AGPGART_COOKIE;

	return 0;
}

static int
parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
{
	struct _parisc_agp_info *info = &parisc_agp_info;
	int i, k;
	off_t j, io_pg_start;
	int io_pg_count;

	if (type != 0 || mem->type != 0) {
		return -EINVAL;
	}

	io_pg_start = info->io_pages_per_kpage * pg_start;
	io_pg_count = info->io_pages_per_kpage * mem->page_count;
	if ((io_pg_start + io_pg_count) > info->gatt_entries) {
		return -EINVAL;
	}

	j = io_pg_start;
	while (j < (io_pg_start + io_pg_count)) {
		if (info->gatt[j])
			return -EBUSY;
		j++;
	}

	if (!mem->is_flushed) {
		global_cache_flush();
		mem->is_flushed = true;
	}

	for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
		unsigned long paddr;

		paddr = page_to_phys(mem->pages[i]);
		for (k = 0;
		     k < info->io_pages_per_kpage;
		     k++, j++, paddr += info->io_page_size) {
			info->gatt[j] =
				parisc_agp_mask_memory(agp_bridge,
					paddr, type);
		}
	}

	agp_bridge->driver->tlb_flush(mem);

	return 0;
}

static int
parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
{
	struct _parisc_agp_info *info = &parisc_agp_info;
	int i, io_pg_start, io_pg_count;

	if (type != 0 || mem->type != 0) {
		return -EINVAL;
	}

	io_pg_start = info->io_pages_per_kpage * pg_start;
	io_pg_count = info->io_pages_per_kpage * mem->page_count;
	for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
		info->gatt[i] = agp_bridge->scratch_page;
	}

	agp_bridge->driver->tlb_flush(mem);
	return 0;
}

static unsigned long
parisc_agp_mask_memory(struct agp_bridge_data *bridge, unsigned long addr,
		       int type)
{
	return SBA_PDIR_VALID_BIT | addr;
}

static unsigned long
parisc_agp_page_mask_memory(struct agp_bridge_data *bridge, struct page *page,
			    int type)
{
	unsigned long addr = phys_to_gart(page_to_phys(page));
	return SBA_PDIR_VALID_BIT | addr;
}

static void
parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode)
{
	struct _parisc_agp_info *info = &parisc_agp_info;
	u32 command;

	command = readl(info->lba_regs + info->lba_cap_offset + PCI_AGP_STATUS);

	command = agp_collect_device_status(bridge, mode, command);
	command |= 0x00000100;

	writel(command, info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND);

	agp_device_command(command, (mode & AGP8X_MODE) != 0);
}

static const struct agp_bridge_driver parisc_agp_driver = {
	.owner			= THIS_MODULE,
	.size_type		= FIXED_APER_SIZE,
	.configure		= parisc_agp_configure,
	.fetch_size		= parisc_agp_fetch_size,
	.tlb_flush		= parisc_agp_tlbflush,
	.mask_memory		= parisc_agp_mask_memory,
	.masks			= parisc_agp_masks,
	.agp_enable		= parisc_agp_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= parisc_agp_create_gatt_table,
	.free_gatt_table	= parisc_agp_free_gatt_table,
	.insert_memory		= parisc_agp_insert_memory,
	.remove_memory		= parisc_agp_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_alloc_pages	= agp_generic_alloc_pages,
	.agp_destroy_page	= agp_generic_destroy_page,
	.agp_destroy_pages	= agp_generic_destroy_pages,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
	.cant_use_aperture	= true,
};

static int __init
agp_ioc_init(void __iomem *ioc_regs)
{
	struct _parisc_agp_info *info = &parisc_agp_info;
        u64 iova_base, *io_pdir, io_tlb_ps;
        int io_tlb_shift;

        printk(KERN_INFO DRVPFX "IO PDIR shared with sba_iommu\n");

        info->ioc_regs = ioc_regs;

        io_tlb_ps = readq(info->ioc_regs+IOC_TCNFG);
        switch (io_tlb_ps) {
        case 0: io_tlb_shift = 12; break;
        case 1: io_tlb_shift = 13; break;
        case 2: io_tlb_shift = 14; break;
        case 3: io_tlb_shift = 16; break;
        default:
                printk(KERN_ERR DRVPFX "Invalid IOTLB page size "
                       "configuration 0x%llx\n", io_tlb_ps);
                info->gatt = NULL;
                info->gatt_entries = 0;
                return -ENODEV;
        }
        info->io_page_size = 1 << io_tlb_shift;
        info->io_pages_per_kpage = PAGE_SIZE / info->io_page_size;

        iova_base = readq(info->ioc_regs+IOC_IBASE) & ~0x1;
        info->gart_base = iova_base + PLUTO_IOVA_SIZE - PLUTO_GART_SIZE;

        info->gart_size = PLUTO_GART_SIZE;
        info->gatt_entries = info->gart_size / info->io_page_size;

        io_pdir = phys_to_virt(readq(info->ioc_regs+IOC_PDIR_BASE));
        info->gatt = &io_pdir[(PLUTO_IOVA_SIZE/2) >> PAGE_SHIFT];

        if (info->gatt[0] != SBA_AGPGART_COOKIE) {
                info->gatt = NULL;
                info->gatt_entries = 0;
                printk(KERN_ERR DRVPFX "No reserved IO PDIR entry found; "
                       "GART disabled\n");
                return -ENODEV;
        }

        return 0;
}

static int
lba_find_capability(int cap)
{
	struct _parisc_agp_info *info = &parisc_agp_info;
        u16 status;
        u8 pos, id;
        int ttl = 48;

        status = readw(info->lba_regs + PCI_STATUS);
        if (!(status & PCI_STATUS_CAP_LIST))
                return 0;
        pos = readb(info->lba_regs + PCI_CAPABILITY_LIST);
        while (ttl-- && pos >= 0x40) {
                pos &= ~3;
                id = readb(info->lba_regs + pos + PCI_CAP_LIST_ID);
                if (id == 0xff)
                        break;
                if (id == cap)
                        return pos;
                pos = readb(info->lba_regs + pos + PCI_CAP_LIST_NEXT);
        }
        return 0;
}

static int __init
agp_lba_init(void __iomem *lba_hpa)
{
	struct _parisc_agp_info *info = &parisc_agp_info;
        int cap;

	info->lba_regs = lba_hpa;
        info->lba_cap_offset = lba_find_capability(PCI_CAP_ID_AGP);

        cap = readl(lba_hpa + info->lba_cap_offset) & 0xff;
        if (cap != PCI_CAP_ID_AGP) {
                printk(KERN_ERR DRVPFX "Invalid capability ID 0x%02x at 0x%x\n",
                       cap, info->lba_cap_offset);
                return -ENODEV;
        }

        return 0;
}

static int __init
parisc_agp_setup(void __iomem *ioc_hpa, void __iomem *lba_hpa)
{
	struct pci_dev *fake_bridge_dev = NULL;
	struct agp_bridge_data *bridge;
	int error = 0;

	fake_bridge_dev = alloc_pci_dev();
	if (!fake_bridge_dev) {
		error = -ENOMEM;
		goto fail;
	}

	error = agp_ioc_init(ioc_hpa);
	if (error)
		goto fail;

	error = agp_lba_init(lba_hpa);
	if (error)
		goto fail;

	bridge = agp_alloc_bridge();
	if (!bridge) {
		error = -ENOMEM;
		goto fail;
	}
	bridge->driver = &parisc_agp_driver;

	fake_bridge_dev->vendor = PCI_VENDOR_ID_HP;
	fake_bridge_dev->device = PCI_DEVICE_ID_HP_PCIX_LBA;
	bridge->dev = fake_bridge_dev;

	error = agp_add_bridge(bridge);

fail:
	return error;
}

static int
find_quicksilver(struct device *dev, void *data)
{
	struct parisc_device **lba = data;
	struct parisc_device *padev = to_parisc_device(dev);

	if (IS_QUICKSILVER(padev))
		*lba = padev;

	return 0;
}

static int
parisc_agp_init(void)
{
	extern struct sba_device *sba_list;

	int err = -1;
	struct parisc_device *sba = NULL, *lba = NULL;
	struct lba_device *lbadev = NULL;

	if (!sba_list)
		goto out;

	/* Find our parent Pluto */
	sba = sba_list->dev;
	if (!IS_PLUTO(sba)) {
		printk(KERN_INFO DRVPFX "No Pluto found, so no AGPGART for you.\n");
		goto out;
	}

	/* Now search our Pluto for our precious AGP device... */
	device_for_each_child(&sba->dev, &lba, find_quicksilver);

	if (!lba) {
		printk(KERN_INFO DRVPFX "No AGP devices found.\n");
		goto out;
	}

	lbadev = parisc_get_drvdata(lba);

	/* w00t, let's go find our cookies... */
	parisc_agp_setup(sba_list->ioc[0].ioc_hpa, lbadev->hba.base_addr);

	return 0;

out:
	return err;
}

module_init(parisc_agp_init);

MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
08a64368 KM	1	/*
	2	* HP Quicksilver AGP GART routines
	3	*
	4	* Copyright (c) 2006, Kyle McMartin <kyle@parisc-linux.org>
	5	*
	6	* Based on drivers/char/agpgart/hp-agp.c which is
	7	* (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
	8	* Bjorn Helgaas <bjorn.helgaas@hp.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/klist.h>
	20	#include <linux/agp_backend.h>
e57aa839	21	#include <linux/log2.h>
08a64368	22
98f172b2 KM	23	#include <asm/parisc-device.h>
98f172b2 KM	24	#include <asm/ropes.h>
08a64368 KM	25
	26	#include "agp.h"
	27
	28	#define DRVNAME "quicksilver"
	29	#define DRVPFX DRVNAME ": "
	30
08a64368 KM	31	#define AGP8X_MODE_BIT 3
	32	#define AGP8X_MODE (1 << AGP8X_MODE_BIT)
	33
07613ba2 DA	34	static unsigned long
	35	parisc_agp_mask_memory(struct agp_bridge_data *bridge, unsigned long addr,
	36	int type);
	37
08a64368 KM	38	static struct _parisc_agp_info {
	39	void __iomem *ioc_regs;
	40	void __iomem *lba_regs;
	41
	42	int lba_cap_offset;
	43
	44	u64 *gatt;
	45	u64 gatt_entries;
	46
	47	u64 gart_base;
	48	u64 gart_size;
	49
	50	int io_page_size;
	51	int io_pages_per_kpage;
	52	} parisc_agp_info;
	53
	54	static struct gatt_mask parisc_agp_masks[] =
	55	{
	56	{
	57	.mask = SBA_PDIR_VALID_BIT,
	58	.type = 0
	59	}
	60	};
	61
	62	static struct aper_size_info_fixed parisc_agp_sizes[] =
	63	{
	64	{0, 0, 0}, /* filled in by parisc_agp_fetch_size() */
	65	};
	66
	67	static int
	68	parisc_agp_fetch_size(void)
	69	{
	70	int size;
	71
	72	size = parisc_agp_info.gart_size / MB(1);
	73	parisc_agp_sizes[0].size = size;
	74	agp_bridge->current_size = (void *) &parisc_agp_sizes[0];
	75
	76	return size;
	77	}
	78
	79	static int
	80	parisc_agp_configure(void)
	81	{
	82	struct _parisc_agp_info *info = &parisc_agp_info;
	83
	84	agp_bridge->gart_bus_addr = info->gart_base;
	85	agp_bridge->capndx = info->lba_cap_offset;
	86	agp_bridge->mode = readl(info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS);
	87
	88	return 0;
	89	}
	90
	91	static void
	92	parisc_agp_tlbflush(struct agp_memory *mem)
	93	{
	94	struct _parisc_agp_info *info = &parisc_agp_info;
	95
e57aa839	96	writeq(info->gart_base \| ilog2(info->gart_size), info->ioc_regs+IOC_PCOM);
08a64368 KM	97	readq(info->ioc_regs+IOC_PCOM); /* flush */
	98	}
	99
	100	static int
	101	parisc_agp_create_gatt_table(struct agp_bridge_data *bridge)
	102	{
	103	struct _parisc_agp_info *info = &parisc_agp_info;
	104	int i;
	105
	106	for (i = 0; i < info->gatt_entries; i++) {
	107	info->gatt[i] = (unsigned long)agp_bridge->scratch_page;
	108	}
	109
	110	return 0;
	111	}
	112
	113	static int
	114	parisc_agp_free_gatt_table(struct agp_bridge_data *bridge)
	115	{
	116	struct _parisc_agp_info *info = &parisc_agp_info;
	117
	118	info->gatt[0] = SBA_AGPGART_COOKIE;
	119
	120	return 0;
	121	}
	122
	123	static int
	124	parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
	125	{
	126	struct _parisc_agp_info *info = &parisc_agp_info;
	127	int i, k;
	128	off_t j, io_pg_start;
	129	int io_pg_count;
	130
	131	if (type != 0 \|\| mem->type != 0) {
	132	return -EINVAL;
	133	}
	134
	135	io_pg_start = info->io_pages_per_kpage * pg_start;
	136	io_pg_count = info->io_pages_per_kpage * mem->page_count;
	137	if ((io_pg_start + io_pg_count) > info->gatt_entries) {
	138	return -EINVAL;
	139	}
	140
	141	j = io_pg_start;
	142	while (j < (io_pg_start + io_pg_count)) {
	143	if (info->gatt[j])
	144	return -EBUSY;
	145	j++;
	146	}
	147
c7258012	148	if (!mem->is_flushed) {
08a64368	149	global_cache_flush();
c7258012	150	mem->is_flushed = true;
08a64368 KM	151	}
	152
	153	for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
	154	unsigned long paddr;
	155
07613ba2	156	paddr = page_to_phys(mem->pages[i]);
08a64368 KM	157	for (k = 0;
	158	k < info->io_pages_per_kpage;
	159	k++, j++, paddr += info->io_page_size) {
	160	info->gatt[j] =
07613ba2	161	parisc_agp_mask_memory(agp_bridge,
08a64368 KM	162	paddr, type);
	163	}
	164	}
	165
	166	agp_bridge->driver->tlb_flush(mem);
	167
	168	return 0;
	169	}
	170
	171	static int
	172	parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
	173	{
	174	struct _parisc_agp_info *info = &parisc_agp_info;
	175	int i, io_pg_start, io_pg_count;
	176
	177	if (type != 0 \|\| mem->type != 0) {
	178	return -EINVAL;
	179	}
	180
	181	io_pg_start = info->io_pages_per_kpage * pg_start;
	182	io_pg_count = info->io_pages_per_kpage * mem->page_count;
	183	for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
	184	info->gatt[i] = agp_bridge->scratch_page;
	185	}
	186
	187	agp_bridge->driver->tlb_flush(mem);
	188	return 0;
	189	}
	190
	191	static unsigned long
07613ba2 DA	192	parisc_agp_mask_memory(struct agp_bridge_data *bridge, unsigned long addr,
	193	int type)
	194	{
	195	return SBA_PDIR_VALID_BIT \| addr;
	196	}
	197
	198	static unsigned long
	199	parisc_agp_page_mask_memory(struct agp_bridge_data bridge, struct page page,
	200	int type)
08a64368	201	{
07613ba2	202	unsigned long addr = phys_to_gart(page_to_phys(page));
08a64368 KM	203	return SBA_PDIR_VALID_BIT \| addr;
	204	}
	205
	206	static void
	207	parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode)
	208	{
	209	struct _parisc_agp_info *info = &parisc_agp_info;
	210	u32 command;
	211
	212	command = readl(info->lba_regs + info->lba_cap_offset + PCI_AGP_STATUS);
	213
	214	command = agp_collect_device_status(bridge, mode, command);
	215	command \|= 0x00000100;
	216
	217	writel(command, info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND);
	218
	219	agp_device_command(command, (mode & AGP8X_MODE) != 0);
	220	}
	221
fb55a0de	222	static const struct agp_bridge_driver parisc_agp_driver = {
08a64368 KM	223	.owner = THIS_MODULE,
	224	.size_type = FIXED_APER_SIZE,
	225	.configure = parisc_agp_configure,
	226	.fetch_size = parisc_agp_fetch_size,
	227	.tlb_flush = parisc_agp_tlbflush,
	228	.mask_memory = parisc_agp_mask_memory,
	229	.masks = parisc_agp_masks,
	230	.agp_enable = parisc_agp_enable,
	231	.cache_flush = global_cache_flush,
	232	.create_gatt_table = parisc_agp_create_gatt_table,
	233	.free_gatt_table = parisc_agp_free_gatt_table,
	234	.insert_memory = parisc_agp_insert_memory,
	235	.remove_memory = parisc_agp_remove_memory,
	236	.alloc_by_type = agp_generic_alloc_by_type,
	237	.free_by_type = agp_generic_free_by_type,
	238	.agp_alloc_page = agp_generic_alloc_page,
5f310b63	239	.agp_alloc_pages = agp_generic_alloc_pages,
08a64368	240	.agp_destroy_page = agp_generic_destroy_page,
5f310b63	241	.agp_destroy_pages = agp_generic_destroy_pages,
bf1e5989	242	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
c7258012	243	.cant_use_aperture = true,
08a64368 KM	244	};
	245
	246	static int __init
	247	agp_ioc_init(void __iomem *ioc_regs)
	248	{
	249	struct _parisc_agp_info *info = &parisc_agp_info;
423c8ece	250	u64 iova_base, *io_pdir, io_tlb_ps;
08a64368 KM	251	int io_tlb_shift;
	252
	253	printk(KERN_INFO DRVPFX "IO PDIR shared with sba_iommu\n");
	254
	255	info->ioc_regs = ioc_regs;
	256
	257	io_tlb_ps = readq(info->ioc_regs+IOC_TCNFG);
	258	switch (io_tlb_ps) {
	259	case 0: io_tlb_shift = 12; break;
	260	case 1: io_tlb_shift = 13; break;
	261	case 2: io_tlb_shift = 14; break;
	262	case 3: io_tlb_shift = 16; break;
	263	default:
	264	printk(KERN_ERR DRVPFX "Invalid IOTLB page size "
	265	"configuration 0x%llx\n", io_tlb_ps);
	266	info->gatt = NULL;
	267	info->gatt_entries = 0;
	268	return -ENODEV;
	269	}
	270	info->io_page_size = 1 << io_tlb_shift;
	271	info->io_pages_per_kpage = PAGE_SIZE / info->io_page_size;
	272
	273	iova_base = readq(info->ioc_regs+IOC_IBASE) & ~0x1;
	274	info->gart_base = iova_base + PLUTO_IOVA_SIZE - PLUTO_GART_SIZE;
	275
	276	info->gart_size = PLUTO_GART_SIZE;
	277	info->gatt_entries = info->gart_size / info->io_page_size;
	278
	279	io_pdir = phys_to_virt(readq(info->ioc_regs+IOC_PDIR_BASE));
	280	info->gatt = &io_pdir[(PLUTO_IOVA_SIZE/2) >> PAGE_SHIFT];
	281
	282	if (info->gatt[0] != SBA_AGPGART_COOKIE) {
	283	info->gatt = NULL;
	284	info->gatt_entries = 0;
	285	printk(KERN_ERR DRVPFX "No reserved IO PDIR entry found; "
	286	"GART disabled\n");
	287	return -ENODEV;
	288	}
	289
	290	return 0;
	291	}
	292
	293	static int
	294	lba_find_capability(int cap)
	295	{
	296	struct _parisc_agp_info *info = &parisc_agp_info;
	297	u16 status;
	298	u8 pos, id;
	299	int ttl = 48;
	300
	301	status = readw(info->lba_regs + PCI_STATUS);
	302	if (!(status & PCI_STATUS_CAP_LIST))
	303	return 0;
	304	pos = readb(info->lba_regs + PCI_CAPABILITY_LIST);
	305	while (ttl-- && pos >= 0x40) {
	306	pos &= ~3;
	307	id = readb(info->lba_regs + pos + PCI_CAP_LIST_ID);
	308	if (id == 0xff)
	309	break;
	310	if (id == cap)
	311	return pos;
	312	pos = readb(info->lba_regs + pos + PCI_CAP_LIST_NEXT);
	313	}
	314	return 0;
315	}
316
317	static int __init
318	agp_lba_init(void __iomem *lba_hpa)
319	{
320	struct _parisc_agp_info *info = &parisc_agp_info;
321	int cap;
322
323	info->lba_regs = lba_hpa;
324	info->lba_cap_offset = lba_find_capability(PCI_CAP_ID_AGP);
325
326	cap = readl(lba_hpa + info->lba_cap_offset) & 0xff;
327	if (cap != PCI_CAP_ID_AGP) {
328	printk(KERN_ERR DRVPFX "Invalid capability ID 0x%02x at 0x%x\n",
329	cap, info->lba_cap_offset);
330	return -ENODEV;
331	}
332
333	return 0;
334	}
335
336	static int __init
337	parisc_agp_setup(void __iomem ioc_hpa, void __iomem lba_hpa)
338	{
339	struct pci_dev *fake_bridge_dev = NULL;
340	struct agp_bridge_data *bridge;
341	int error = 0;
342
bab41e9b	343	fake_bridge_dev = alloc_pci_dev();
08a64368 KM	344	if (!fake_bridge_dev) {
	345	error = -ENOMEM;
	346	goto fail;
	347	}
	348
	349	error = agp_ioc_init(ioc_hpa);
	350	if (error)
	351	goto fail;
	352
	353	error = agp_lba_init(lba_hpa);
	354	if (error)
	355	goto fail;
	356
	357	bridge = agp_alloc_bridge();
	358	if (!bridge) {
	359	error = -ENOMEM;
	360	goto fail;
	361	}
	362	bridge->driver = &parisc_agp_driver;
	363
	364	fake_bridge_dev->vendor = PCI_VENDOR_ID_HP;
	365	fake_bridge_dev->device = PCI_DEVICE_ID_HP_PCIX_LBA;
	366	bridge->dev = fake_bridge_dev;
	367
	368	error = agp_add_bridge(bridge);
	369
	370	fail:
	371	return error;
	372	}
	373
bfe4f4f8 JB	374	static int
	375	find_quicksilver(struct device dev, void data)
	376	{
	377	struct parisc_device **lba = data;
	378	struct parisc_device *padev = to_parisc_device(dev);
	379
	380	if (IS_QUICKSILVER(padev))
	381	*lba = padev;
	382
	383	return 0;
08a64368 KM	384	}
	385
	386	static int
	387	parisc_agp_init(void)
	388	{
	389	extern struct sba_device *sba_list;
	390
	391	int err = -1;
	392	struct parisc_device sba = NULL, lba = NULL;
	393	struct lba_device *lbadev = NULL;
08a64368 KM	394
	395	if (!sba_list)
	396	goto out;
	397
	398	/* Find our parent Pluto */
	399	sba = sba_list->dev;
	400	if (!IS_PLUTO(sba)) {
	401	printk(KERN_INFO DRVPFX "No Pluto found, so no AGPGART for you.\n");
	402	goto out;
	403	}
	404
	405	/* Now search our Pluto for our precious AGP device... */
bfe4f4f8	406	device_for_each_child(&sba->dev, &lba, find_quicksilver);
08a64368 KM	407
	408	if (!lba) {
	409	printk(KERN_INFO DRVPFX "No AGP devices found.\n");
	410	goto out;
	411	}
	412
	413	lbadev = parisc_get_drvdata(lba);
	414
	415	/* w00t, let's go find our cookies... */
	416	parisc_agp_setup(sba_list->ioc[0].ioc_hpa, lbadev->hba.base_addr);
	417
	418	return 0;
	419
	420	out:
	421	return err;
	422	}
	423
	424	module_init(parisc_agp_init);
	425
	426	MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>");
	427	MODULE_LICENSE("GPL");