[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / agp / agp.h

/*
 * AGPGART
 * Copyright (C) 2004 Silicon Graphics, Inc.
 * Copyright (C) 2002-2004 Dave Jones
 * Copyright (C) 1999 Jeff Hartmann
 * Copyright (C) 1999 Precision Insight, Inc.
 * Copyright (C) 1999 Xi Graphics, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef _AGP_BACKEND_PRIV_H
#define _AGP_BACKEND_PRIV_H 1

#include <asm/agp.h>	/* for flush_agp_cache() */

#define PFX "agpgart: "

//#define AGP_DEBUG 1
#ifdef AGP_DEBUG
#define DBG(x,y...) printk (KERN_DEBUG PFX "%s: " x "\n", __func__ , ## y)
#else
#define DBG(x,y...) do { } while (0)
#endif

extern struct agp_bridge_data *agp_bridge;

enum aper_size_type {
	U8_APER_SIZE,
	U16_APER_SIZE,
	U32_APER_SIZE,
	LVL2_APER_SIZE,
	FIXED_APER_SIZE
};

struct gatt_mask {
	unsigned long mask;
	u32 type;
	/* totally device specific, for integrated chipsets that
	 * might have different types of memory masks.  For other
	 * devices this will probably be ignored */
};

#define AGP_PAGE_DESTROY_UNMAP 1
#define AGP_PAGE_DESTROY_FREE 2

struct aper_size_info_8 {
	int size;
	int num_entries;
	int page_order;
	u8 size_value;
};

struct aper_size_info_16 {
	int size;
	int num_entries;
	int page_order;
	u16 size_value;
};

struct aper_size_info_32 {
	int size;
	int num_entries;
	int page_order;
	u32 size_value;
};

struct aper_size_info_lvl2 {
	int size;
	int num_entries;
	u32 size_value;
};

struct aper_size_info_fixed {
	int size;
	int num_entries;
	int page_order;
};

struct agp_bridge_driver {
	struct module *owner;
	const void *aperture_sizes;
	int num_aperture_sizes;
	enum aper_size_type size_type;
	bool cant_use_aperture;
	bool needs_scratch_page;
	const struct gatt_mask *masks;
	int (*fetch_size)(void);
	int (*configure)(void);
	void (*agp_enable)(struct agp_bridge_data *, u32);
	void (*cleanup)(void);
	void (*tlb_flush)(struct agp_memory *);
	unsigned long (*mask_memory)(struct agp_bridge_data *, unsigned long, int);
	void (*cache_flush)(void);
	int (*create_gatt_table)(struct agp_bridge_data *);
	int (*free_gatt_table)(struct agp_bridge_data *);
	int (*insert_memory)(struct agp_memory *, off_t, int);
	int (*remove_memory)(struct agp_memory *, off_t, int);
	struct agp_memory *(*alloc_by_type) (size_t, int);
	void (*free_by_type)(struct agp_memory *);
	void *(*agp_alloc_page)(struct agp_bridge_data *);
	int (*agp_alloc_pages)(struct agp_bridge_data *, struct agp_memory *, size_t);
	void (*agp_destroy_page)(void *, int flags);
	void (*agp_destroy_pages)(struct agp_memory *);
	int (*agp_type_to_mask_type) (struct agp_bridge_data *, int);
	void (*chipset_flush)(struct agp_bridge_data *);
};

struct agp_bridge_data {
	const struct agp_version *version;
	const struct agp_bridge_driver *driver;
	struct vm_operations_struct *vm_ops;
	void *previous_size;
	void *current_size;
	void *dev_private_data;
	struct pci_dev *dev;
	u32 __iomem *gatt_table;
	u32 *gatt_table_real;
	unsigned long scratch_page;
	unsigned long scratch_page_real;
	unsigned long gart_bus_addr;
	unsigned long gatt_bus_addr;
	u32 mode;
	enum chipset_type type;
	unsigned long *key_list;
	atomic_t current_memory_agp;
	atomic_t agp_in_use;
	int max_memory_agp;	/* in number of pages */
	int aperture_size_idx;
	int capndx;
	int flags;
	char major_version;
	char minor_version;
	struct list_head list;
	u32 apbase_config;
	/* list of agp_memory mapped to the aperture */
	struct list_head mapped_list;
	spinlock_t mapped_lock;
};

#define KB(x)	((x) * 1024)
#define MB(x)	(KB (KB (x)))
#define GB(x)	(MB (KB (x)))

#define A_SIZE_8(x)	((struct aper_size_info_8 *) x)
#define A_SIZE_16(x)	((struct aper_size_info_16 *) x)
#define A_SIZE_32(x)	((struct aper_size_info_32 *) x)
#define A_SIZE_LVL2(x)	((struct aper_size_info_lvl2 *) x)
#define A_SIZE_FIX(x)	((struct aper_size_info_fixed *) x)
#define A_IDX8(bridge)	(A_SIZE_8((bridge)->driver->aperture_sizes) + i)
#define A_IDX16(bridge)	(A_SIZE_16((bridge)->driver->aperture_sizes) + i)
#define A_IDX32(bridge)	(A_SIZE_32((bridge)->driver->aperture_sizes) + i)
#define MAXKEY		(4096 * 32)

#define PGE_EMPTY(b, p)	(!(p) || (p) == (unsigned long) (b)->scratch_page)


/* Intel registers */
#define INTEL_APSIZE	0xb4
#define INTEL_ATTBASE	0xb8
#define INTEL_AGPCTRL	0xb0
#define INTEL_NBXCFG	0x50
#define INTEL_ERRSTS	0x91

/* Intel i830 registers */
#define I830_GMCH_CTRL			0x52
#define I830_GMCH_ENABLED		0x4
#define I830_GMCH_MEM_MASK		0x1
#define I830_GMCH_MEM_64M		0x1
#define I830_GMCH_MEM_128M		0
#define I830_GMCH_GMS_MASK		0x70
#define I830_GMCH_GMS_DISABLED		0x00
#define I830_GMCH_GMS_LOCAL		0x10
#define I830_GMCH_GMS_STOLEN_512	0x20
#define I830_GMCH_GMS_STOLEN_1024	0x30
#define I830_GMCH_GMS_STOLEN_8192	0x40
#define I830_RDRAM_CHANNEL_TYPE		0x03010
#define I830_RDRAM_ND(x)		(((x) & 0x20) >> 5)
#define I830_RDRAM_DDT(x)		(((x) & 0x18) >> 3)

/* This one is for I830MP w. an external graphic card */
#define INTEL_I830_ERRSTS	0x92

/* Intel 855GM/852GM registers */
#define I855_GMCH_GMS_MASK		0xF0
#define I855_GMCH_GMS_STOLEN_0M		0x0
#define I855_GMCH_GMS_STOLEN_1M		(0x1 << 4)
#define I855_GMCH_GMS_STOLEN_4M		(0x2 << 4)
#define I855_GMCH_GMS_STOLEN_8M		(0x3 << 4)
#define I855_GMCH_GMS_STOLEN_16M	(0x4 << 4)
#define I855_GMCH_GMS_STOLEN_32M	(0x5 << 4)
#define I85X_CAPID			0x44
#define I85X_VARIANT_MASK		0x7
#define I85X_VARIANT_SHIFT		5
#define I855_GME			0x0
#define I855_GM				0x4
#define I852_GME			0x2
#define I852_GM				0x5

/* Intel i845 registers */
#define INTEL_I845_AGPM		0x51
#define INTEL_I845_ERRSTS	0xc8

/* Intel i860 registers */
#define INTEL_I860_MCHCFG	0x50
#define INTEL_I860_ERRSTS	0xc8

/* Intel i810 registers */
#define I810_GMADDR		0x10
#define I810_MMADDR		0x14
#define I810_PTE_BASE		0x10000
#define I810_PTE_MAIN_UNCACHED	0x00000000
#define I810_PTE_LOCAL		0x00000002
#define I810_PTE_VALID		0x00000001
#define I830_PTE_SYSTEM_CACHED  0x00000006
#define I810_SMRAM_MISCC	0x70
#define I810_GFX_MEM_WIN_SIZE	0x00010000
#define I810_GFX_MEM_WIN_32M	0x00010000
#define I810_GMS		0x000000c0
#define I810_GMS_DISABLE	0x00000000
#define I810_PGETBL_CTL		0x2020
#define I810_PGETBL_ENABLED	0x00000001
#define I965_PGETBL_SIZE_MASK	0x0000000e
#define I965_PGETBL_SIZE_512KB	(0 << 1)
#define I965_PGETBL_SIZE_256KB	(1 << 1)
#define I965_PGETBL_SIZE_128KB	(2 << 1)
#define I965_PGETBL_SIZE_1MB	(3 << 1)
#define I965_PGETBL_SIZE_2MB	(4 << 1)
#define I965_PGETBL_SIZE_1_5MB	(5 << 1)
#define G33_PGETBL_SIZE_MASK    (3 << 8)
#define G33_PGETBL_SIZE_1M      (1 << 8)
#define G33_PGETBL_SIZE_2M      (2 << 8)

#define I810_DRAM_CTL		0x3000
#define I810_DRAM_ROW_0		0x00000001
#define I810_DRAM_ROW_0_SDRAM	0x00000001

struct agp_device_ids {
	unsigned short device_id; /* first, to make table easier to read */
	enum chipset_type chipset;
	const char *chipset_name;
	int (*chipset_setup) (struct pci_dev *pdev);	/* used to override generic */
};

/* Driver registration */
struct agp_bridge_data *agp_alloc_bridge(void);
void agp_put_bridge(struct agp_bridge_data *bridge);
int agp_add_bridge(struct agp_bridge_data *bridge);
void agp_remove_bridge(struct agp_bridge_data *bridge);

/* Frontend routines. */
int agp_frontend_initialize(void);
void agp_frontend_cleanup(void);

/* Generic routines. */
void agp_generic_enable(struct agp_bridge_data *bridge, u32 mode);
int agp_generic_create_gatt_table(struct agp_bridge_data *bridge);
int agp_generic_free_gatt_table(struct agp_bridge_data *bridge);
struct agp_memory *agp_create_memory(int scratch_pages);
int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type);
int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type);
struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type);
void agp_generic_free_by_type(struct agp_memory *curr);
void *agp_generic_alloc_page(struct agp_bridge_data *bridge);
int agp_generic_alloc_pages(struct agp_bridge_data *agp_bridge,
			    struct agp_memory *memory, size_t page_count);
void agp_generic_destroy_page(void *addr, int flags);
void agp_generic_destroy_pages(struct agp_memory *memory);
void agp_free_key(int key);
int agp_num_entries(void);
u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command);
void agp_device_command(u32 command, bool agp_v3);
int agp_3_5_enable(struct agp_bridge_data *bridge);
void global_cache_flush(void);
void get_agp_version(struct agp_bridge_data *bridge);
unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
	unsigned long addr, int type);
int agp_generic_type_to_mask_type(struct agp_bridge_data *bridge,
				  int type);
struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev);

/* generic functions for user-populated AGP memory types */
struct agp_memory *agp_generic_alloc_user(size_t page_count, int type);
void agp_alloc_page_array(size_t size, struct agp_memory *mem);
void agp_free_page_array(struct agp_memory *mem);


/* generic routines for agp>=3 */
int agp3_generic_fetch_size(void);
void agp3_generic_tlbflush(struct agp_memory *mem);
int agp3_generic_configure(void);
void agp3_generic_cleanup(void);

/* aperture sizes have been standardised since v3 */
#define AGP_GENERIC_SIZES_ENTRIES 11
extern const struct aper_size_info_16 agp3_generic_sizes[];

#define virt_to_gart(x) (phys_to_gart(virt_to_phys(x)))
#define gart_to_virt(x) (phys_to_virt(gart_to_phys(x)))

extern int agp_off;
extern int agp_try_unsupported_boot;

long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg);

/* Chipset independant registers (from AGP Spec) */
#define AGP_APBASE	0x10

#define AGPSTAT		0x4
#define AGPCMD		0x8
#define AGPNISTAT	0xc
#define AGPCTRL		0x10
#define AGPAPSIZE	0x14
#define AGPNEPG		0x16
#define AGPGARTLO	0x18
#define AGPGARTHI	0x1c
#define AGPNICMD	0x20

#define AGP_MAJOR_VERSION_SHIFT	(20)
#define AGP_MINOR_VERSION_SHIFT	(16)

#define AGPSTAT_RQ_DEPTH	(0xff000000)
#define AGPSTAT_RQ_DEPTH_SHIFT	24

#define AGPSTAT_CAL_MASK	(1<<12|1<<11|1<<10)
#define AGPSTAT_ARQSZ		(1<<15|1<<14|1<<13)
#define AGPSTAT_ARQSZ_SHIFT	13

#define AGPSTAT_SBA		(1<<9)
#define AGPSTAT_AGP_ENABLE	(1<<8)
#define AGPSTAT_FW		(1<<4)
#define AGPSTAT_MODE_3_0	(1<<3)

#define AGPSTAT2_1X		(1<<0)
#define AGPSTAT2_2X		(1<<1)
#define AGPSTAT2_4X		(1<<2)

#define AGPSTAT3_RSVD		(1<<2)
#define AGPSTAT3_8X		(1<<1)
#define AGPSTAT3_4X		(1)

#define AGPCTRL_APERENB		(1<<8)
#define AGPCTRL_GTLBEN		(1<<7)

#define AGP2_RESERVED_MASK 0x00fffcc8
#define AGP3_RESERVED_MASK 0x00ff00c4

#define AGP_ERRATA_FASTWRITES 1<<0
#define AGP_ERRATA_SBA	 1<<1
#define AGP_ERRATA_1X 1<<2

#endif	/* _AGP_BACKEND_PRIV_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* AGPGART
	3	* Copyright (C) 2004 Silicon Graphics, Inc.
	4	* Copyright (C) 2002-2004 Dave Jones
	5	* Copyright (C) 1999 Jeff Hartmann
	6	* Copyright (C) 1999 Precision Insight, Inc.
	7	* Copyright (C) 1999 Xi Graphics, Inc.
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a
	10	* copy of this software and associated documentation files (the "Software"),
	11	* to deal in the Software without restriction, including without limitation
	12	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	13	* and/or sell copies of the Software, and to permit persons to whom the
	14	* Software is furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included
	17	* in all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	20	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
6a92a4e0 DJ	22	* JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
	23	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	24	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
1da177e4 LT	25	* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	26	*
	27	*/
	28
	29	#ifndef _AGP_BACKEND_PRIV_H
	30	#define _AGP_BACKEND_PRIV_H 1
	31
	32	#include <asm/agp.h> /* for flush_agp_cache() */
	33
	34	#define PFX "agpgart: "
	35
	36	//#define AGP_DEBUG 1
	37	#ifdef AGP_DEBUG
bf9d8929	38	#define DBG(x,y...) printk (KERN_DEBUG PFX "%s: " x "\n", __func__ , ## y)
1da177e4 LT	39	#else
	40	#define DBG(x,y...) do { } while (0)
	41	#endif
	42
	43	extern struct agp_bridge_data *agp_bridge;
	44
	45	enum aper_size_type {
	46	U8_APER_SIZE,
	47	U16_APER_SIZE,
	48	U32_APER_SIZE,
	49	LVL2_APER_SIZE,
	50	FIXED_APER_SIZE
	51	};
	52
	53	struct gatt_mask {
	54	unsigned long mask;
	55	u32 type;
6a92a4e0	56	/* totally device specific, for integrated chipsets that
1da177e4 LT	57	* might have different types of memory masks. For other
	58	* devices this will probably be ignored */
	59	};
	60
a2721e99 DA	61	#define AGP_PAGE_DESTROY_UNMAP 1
	62	#define AGP_PAGE_DESTROY_FREE 2
	63
1da177e4 LT	64	struct aper_size_info_8 {
	65	int size;
	66	int num_entries;
	67	int page_order;
	68	u8 size_value;
	69	};
	70
	71	struct aper_size_info_16 {
	72	int size;
	73	int num_entries;
	74	int page_order;
	75	u16 size_value;
	76	};
	77
	78	struct aper_size_info_32 {
	79	int size;
	80	int num_entries;
	81	int page_order;
	82	u32 size_value;
	83	};
	84
	85	struct aper_size_info_lvl2 {
	86	int size;
	87	int num_entries;
	88	u32 size_value;
	89	};
	90
	91	struct aper_size_info_fixed {
	92	int size;
	93	int num_entries;
	94	int page_order;
	95	};
	96
	97	struct agp_bridge_driver {
	98	struct module *owner;
e5524f35	99	const void *aperture_sizes;
1da177e4 LT	100	int num_aperture_sizes;
1da177e4 LT	101	enum aper_size_type size_type;
c7258012 JP	102	bool cant_use_aperture;
c7258012 JP	103	bool needs_scratch_page;
e5524f35	104	const struct gatt_mask *masks;
1da177e4 LT	105	int (*fetch_size)(void);
	106	int (*configure)(void);
	107	void (agp_enable)(struct agp_bridge_data , u32);
	108	void (*cleanup)(void);
	109	void (tlb_flush)(struct agp_memory );
6a92a4e0	110	unsigned long (mask_memory)(struct agp_bridge_data , unsigned long, int);
1da177e4 LT	111	void (*cache_flush)(void);
	112	int (create_gatt_table)(struct agp_bridge_data );
	113	int (free_gatt_table)(struct agp_bridge_data );
	114	int (insert_memory)(struct agp_memory , off_t, int);
	115	int (remove_memory)(struct agp_memory , off_t, int);
	116	struct agp_memory (alloc_by_type) (size_t, int);
	117	void (free_by_type)(struct agp_memory );
	118	void (agp_alloc_page)(struct agp_bridge_data *);
37acee10	119	int (agp_alloc_pages)(struct agp_bridge_data , struct agp_memory *, size_t);
a2721e99	120	void (agp_destroy_page)(void , int flags);
bd07928c	121	void (agp_destroy_pages)(struct agp_memory );
a13af4b4 DA	122	int (agp_type_to_mask_type) (struct agp_bridge_data , int);
a13af4b4 DA	123	void (chipset_flush)(struct agp_bridge_data );
1da177e4 LT	124	};
	125
	126	struct agp_bridge_data {
8eb7925f	127	const struct agp_version *version;
e5524f35	128	const struct agp_bridge_driver *driver;
1da177e4 LT	129	struct vm_operations_struct *vm_ops;
	130	void *previous_size;
	131	void *current_size;
	132	void *dev_private_data;
	133	struct pci_dev *dev;
	134	u32 __iomem *gatt_table;
	135	u32 *gatt_table_real;
	136	unsigned long scratch_page;
	137	unsigned long scratch_page_real;
	138	unsigned long gart_bus_addr;
	139	unsigned long gatt_bus_addr;
	140	u32 mode;
	141	enum chipset_type type;
	142	unsigned long *key_list;
	143	atomic_t current_memory_agp;
	144	atomic_t agp_in_use;
	145	int max_memory_agp; /* in number of pages */
	146	int aperture_size_idx;
	147	int capndx;
	148	int flags;
	149	char major_version;
	150	char minor_version;
	151	struct list_head list;
b0825488	152	u32 apbase_config;
a8c84df9 KP	153	/* list of agp_memory mapped to the aperture */
	154	struct list_head mapped_list;
	155	spinlock_t mapped_lock;
1da177e4 LT	156	};
	157
	158	#define KB(x) ((x) * 1024)
	159	#define MB(x) (KB (KB (x)))
	160	#define GB(x) (MB (KB (x)))
	161
	162	#define A_SIZE_8(x) ((struct aper_size_info_8 *) x)
	163	#define A_SIZE_16(x) ((struct aper_size_info_16 *) x)
	164	#define A_SIZE_32(x) ((struct aper_size_info_32 *) x)
	165	#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x)
	166	#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x)
	167	#define A_IDX8(bridge) (A_SIZE_8((bridge)->driver->aperture_sizes) + i)
	168	#define A_IDX16(bridge) (A_SIZE_16((bridge)->driver->aperture_sizes) + i)
	169	#define A_IDX32(bridge) (A_SIZE_32((bridge)->driver->aperture_sizes) + i)
	170	#define MAXKEY (4096 * 32)
	171
	172	#define PGE_EMPTY(b, p) (!(p) \|\| (p) == (unsigned long) (b)->scratch_page)
	173
	174
	175	/* Intel registers */
	176	#define INTEL_APSIZE 0xb4
	177	#define INTEL_ATTBASE 0xb8
	178	#define INTEL_AGPCTRL 0xb0
	179	#define INTEL_NBXCFG 0x50
	180	#define INTEL_ERRSTS 0x91
	181
	182	/* Intel i830 registers */
	183	#define I830_GMCH_CTRL 0x52
	184	#define I830_GMCH_ENABLED 0x4
	185	#define I830_GMCH_MEM_MASK 0x1
	186	#define I830_GMCH_MEM_64M 0x1
	187	#define I830_GMCH_MEM_128M 0
e67aa27a	188	#define I830_GMCH_GMS_MASK 0x70
1da177e4 LT	189	#define I830_GMCH_GMS_DISABLED 0x00
	190	#define I830_GMCH_GMS_LOCAL 0x10
	191	#define I830_GMCH_GMS_STOLEN_512 0x20
	192	#define I830_GMCH_GMS_STOLEN_1024 0x30
	193	#define I830_GMCH_GMS_STOLEN_8192 0x40
	194	#define I830_RDRAM_CHANNEL_TYPE 0x03010
	195	#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
	196	#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
	197
	198	/* This one is for I830MP w. an external graphic card */
	199	#define INTEL_I830_ERRSTS 0x92
	200
	201	/* Intel 855GM/852GM registers */
e67aa27a	202	#define I855_GMCH_GMS_MASK 0xF0
1da177e4 LT	203	#define I855_GMCH_GMS_STOLEN_0M 0x0
	204	#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
	205	#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
	206	#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
	207	#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
	208	#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
	209	#define I85X_CAPID 0x44
	210	#define I85X_VARIANT_MASK 0x7
	211	#define I85X_VARIANT_SHIFT 5
	212	#define I855_GME 0x0
	213	#define I855_GM 0x4
	214	#define I852_GME 0x2
	215	#define I852_GM 0x5
	216
	217	/* Intel i845 registers */
	218	#define INTEL_I845_AGPM 0x51
	219	#define INTEL_I845_ERRSTS 0xc8
	220
	221	/* Intel i860 registers */
	222	#define INTEL_I860_MCHCFG 0x50
	223	#define INTEL_I860_ERRSTS 0xc8
	224
	225	/* Intel i810 registers */
	226	#define I810_GMADDR 0x10
	227	#define I810_MMADDR 0x14
	228	#define I810_PTE_BASE 0x10000
	229	#define I810_PTE_MAIN_UNCACHED 0x00000000
	230	#define I810_PTE_LOCAL 0x00000002
	231	#define I810_PTE_VALID 0x00000001
a030ce44	232	#define I830_PTE_SYSTEM_CACHED 0x00000006
1da177e4 LT	233	#define I810_SMRAM_MISCC 0x70
	234	#define I810_GFX_MEM_WIN_SIZE 0x00010000
	235	#define I810_GFX_MEM_WIN_32M 0x00010000
	236	#define I810_GMS 0x000000c0
	237	#define I810_GMS_DISABLE 0x00000000
	238	#define I810_PGETBL_CTL 0x2020
	239	#define I810_PGETBL_ENABLED 0x00000001
c41e0deb EA	240	#define I965_PGETBL_SIZE_MASK 0x0000000e
	241	#define I965_PGETBL_SIZE_512KB (0 << 1)
	242	#define I965_PGETBL_SIZE_256KB (1 << 1)
	243	#define I965_PGETBL_SIZE_128KB (2 << 1)
4e8b6e25 ZW	244	#define I965_PGETBL_SIZE_1MB (3 << 1)
	245	#define I965_PGETBL_SIZE_2MB (4 << 1)
	246	#define I965_PGETBL_SIZE_1_5MB (5 << 1)
874808c6 WZ	247	#define G33_PGETBL_SIZE_MASK (3 << 8)
	248	#define G33_PGETBL_SIZE_1M (1 << 8)
	249	#define G33_PGETBL_SIZE_2M (2 << 8)
	250
1da177e4 LT	251	#define I810_DRAM_CTL 0x3000
	252	#define I810_DRAM_ROW_0 0x00000001
	253	#define I810_DRAM_ROW_0_SDRAM 0x00000001
	254
	255	struct agp_device_ids {
	256	unsigned short device_id; /* first, to make table easier to read */
	257	enum chipset_type chipset;
	258	const char *chipset_name;
	259	int (chipset_setup) (struct pci_dev pdev); /* used to override generic */
	260	};
	261
	262	/* Driver registration */
	263	struct agp_bridge_data *agp_alloc_bridge(void);
	264	void agp_put_bridge(struct agp_bridge_data *bridge);
	265	int agp_add_bridge(struct agp_bridge_data *bridge);
	266	void agp_remove_bridge(struct agp_bridge_data *bridge);
	267
	268	/* Frontend routines. */
	269	int agp_frontend_initialize(void);
	270	void agp_frontend_cleanup(void);
	271
	272	/* Generic routines. */
	273	void agp_generic_enable(struct agp_bridge_data *bridge, u32 mode);
	274	int agp_generic_create_gatt_table(struct agp_bridge_data *bridge);
	275	int agp_generic_free_gatt_table(struct agp_bridge_data *bridge);
	276	struct agp_memory *agp_create_memory(int scratch_pages);
	277	int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type);
	278	int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type);
	279	struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type);
	280	void agp_generic_free_by_type(struct agp_memory *curr);
	281	void agp_generic_alloc_page(struct agp_bridge_data bridge);
37acee10 SL	282	int agp_generic_alloc_pages(struct agp_bridge_data *agp_bridge,
37acee10 SL	283	struct agp_memory *memory, size_t page_count);
a2721e99	284	void agp_generic_destroy_page(void *addr, int flags);
bd07928c	285	void agp_generic_destroy_pages(struct agp_memory *memory);
1da177e4 LT	286	void agp_free_key(int key);
	287	int agp_num_entries(void);
	288	u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command);
c7258012	289	void agp_device_command(u32 command, bool agp_v3);
1da177e4 LT	290	int agp_3_5_enable(struct agp_bridge_data *bridge);
	291	void global_cache_flush(void);
	292	void get_agp_version(struct agp_bridge_data *bridge);
	293	unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
	294	unsigned long addr, int type);
a030ce44 TH	295	int agp_generic_type_to_mask_type(struct agp_bridge_data *bridge,
a030ce44 TH	296	int type);
1da177e4 LT	297	struct agp_bridge_data agp_generic_find_bridge(struct pci_dev pdev);
1da177e4 LT	298
a030ce44 TH	299	/* generic functions for user-populated AGP memory types */
	300	struct agp_memory *agp_generic_alloc_user(size_t page_count, int type);
	301	void agp_alloc_page_array(size_t size, struct agp_memory *mem);
	302	void agp_free_page_array(struct agp_memory *mem);
	303
	304
1da177e4 LT	305	/* generic routines for agp>=3 */
	306	int agp3_generic_fetch_size(void);
	307	void agp3_generic_tlbflush(struct agp_memory *mem);
	308	int agp3_generic_configure(void);
	309	void agp3_generic_cleanup(void);
	310
	311	/* aperture sizes have been standardised since v3 */
	312	#define AGP_GENERIC_SIZES_ENTRIES 11
e5524f35	313	extern const struct aper_size_info_16 agp3_generic_sizes[];
1da177e4	314
07eee78e KF	315	#define virt_to_gart(x) (phys_to_gart(virt_to_phys(x)))
07eee78e KF	316	#define gart_to_virt(x) (phys_to_virt(gart_to_phys(x)))
1da177e4 LT	317
	318	extern int agp_off;
	319	extern int agp_try_unsupported_boot;
	320
0316fe83 ZM	321	long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
0316fe83 ZM	322
1da177e4 LT	323	/* Chipset independant registers (from AGP Spec) */
	324	#define AGP_APBASE 0x10
	325
	326	#define AGPSTAT 0x4
	327	#define AGPCMD 0x8
	328	#define AGPNISTAT 0xc
	329	#define AGPCTRL 0x10
	330	#define AGPAPSIZE 0x14
	331	#define AGPNEPG 0x16
	332	#define AGPGARTLO 0x18
	333	#define AGPGARTHI 0x1c
	334	#define AGPNICMD 0x20
	335
	336	#define AGP_MAJOR_VERSION_SHIFT (20)
	337	#define AGP_MINOR_VERSION_SHIFT (16)
	338
	339	#define AGPSTAT_RQ_DEPTH (0xff000000)
	340	#define AGPSTAT_RQ_DEPTH_SHIFT 24
	341
	342	#define AGPSTAT_CAL_MASK (1<<12\|1<<11\|1<<10)
	343	#define AGPSTAT_ARQSZ (1<<15\|1<<14\|1<<13)
	344	#define AGPSTAT_ARQSZ_SHIFT 13
	345
	346	#define AGPSTAT_SBA (1<<9)
	347	#define AGPSTAT_AGP_ENABLE (1<<8)
	348	#define AGPSTAT_FW (1<<4)
	349	#define AGPSTAT_MODE_3_0 (1<<3)
	350
	351	#define AGPSTAT2_1X (1<<0)
	352	#define AGPSTAT2_2X (1<<1)
	353	#define AGPSTAT2_4X (1<<2)
	354
	355	#define AGPSTAT3_RSVD (1<<2)
	356	#define AGPSTAT3_8X (1<<1)
	357	#define AGPSTAT3_4X (1)
	358
	359	#define AGPCTRL_APERENB (1<<8)
	360	#define AGPCTRL_GTLBEN (1<<7)
	361
	362	#define AGP2_RESERVED_MASK 0x00fffcc8
	363	#define AGP3_RESERVED_MASK 0x00ff00c4
	364
	365	#define AGP_ERRATA_FASTWRITES 1<<0
	366	#define AGP_ERRATA_SBA 1<<1
	367	#define AGP_ERRATA_1X 1<<2
	368
	369	#endif /* _AGP_BACKEND_PRIV_H */