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ps3vram: Replace mutex by spinlock + bio_list
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / block / ps3vram.c
CommitLineData
f507cd22
GU		 1/*
2 * ps3vram - Use extra PS3 video ram as MTD block device.
3 *
4 * Copyright 2009 Sony Corporation
5 *
6 * Based on the MTD ps3vram driver, which is
7 * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
8 * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
9 */
10
11#include <linux/blkdev.h>
12#include <linux/delay.h>
13#include <linux/proc_fs.h>
14#include <linux/seq_file.h>
15
16#include <asm/firmware.h>
56ac72db 17#include <asm/iommu.h>
f507cd22
GU		 18#include <asm/lv1call.h>
19#include <asm/ps3.h>
d3352c9f 20#include <asm/ps3gpu.h>
f507cd22
GU		 21
22
23#define DEVICE_NAME "ps3vram"
24
25
26#define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
27#define XDR_IOIF 0x0c000000
28
29#define FIFO_BASE XDR_IOIF
30#define FIFO_SIZE (64 * 1024)
31
32#define DMA_PAGE_SIZE (4 * 1024)
33
34#define CACHE_PAGE_SIZE (256 * 1024)
35#define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
36
37#define CACHE_OFFSET CACHE_PAGE_SIZE
38#define FIFO_OFFSET 0
39
40#define CTRL_PUT 0x10
41#define CTRL_GET 0x11
42#define CTRL_TOP 0x15
43
44#define UPLOAD_SUBCH 1
45#define DOWNLOAD_SUBCH 2
46
47#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
48#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
49
f507cd22
GU		 50#define CACHE_PAGE_PRESENT 1
51#define CACHE_PAGE_DIRTY 2
52
53struct ps3vram_tag {
54 unsigned int address;
55 unsigned int flags;
56};
57
58struct ps3vram_cache {
59 unsigned int page_count;
60 unsigned int page_size;
61 struct ps3vram_tag *tags;
62 unsigned int hit;
63 unsigned int miss;
64};
65
66struct ps3vram_priv {
67 struct request_queue *queue;
68 struct gendisk *gendisk;
69
70 u64 size;
71
72 u64 memory_handle;
73 u64 context_handle;
74 u32 *ctrl;
75 u32 *reports;
76 u8 __iomem *ddr_base;
77 u8 *xdr_buf;
78
79 u32 *fifo_base;
80 u32 *fifo_ptr;
81
82 struct ps3vram_cache cache;
83
fb89e89d
GU		 84 spinlock_t lock; /* protecting list of bios */
85 struct bio_list list;
f507cd22
GU		 86};
87
88
89static int ps3vram_major;
90
91
92static struct block_device_operations ps3vram_fops = {
93 .owner = THIS_MODULE,
94};
95
96
97#define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
98#define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
99#define DMA_NOTIFIER_SIZE 0x40
100#define NOTIFIER 7 /* notifier used for completion report */
101
102static char *size = "256M";
103module_param(size, charp, 0);
104MODULE_PARM_DESC(size, "memory size");
105
106static u32 *ps3vram_get_notifier(u32 *reports, int notifier)
107{
108 return (void *)reports + DMA_NOTIFIER_OFFSET_BASE +
109 DMA_NOTIFIER_SIZE * notifier;
110}
111
112static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
113{
114 struct ps3vram_priv *priv = dev->core.driver_data;
115 u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
116 int i;
117
118 for (i = 0; i < 4; i++)
119 notify[i] = 0xffffffff;
120}
121
122static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
123 unsigned int timeout_ms)
124{
125 struct ps3vram_priv *priv = dev->core.driver_data;
126 u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
127 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
128
129 do {
130 if (!notify[3])
131 return 0;
132 msleep(1);
133 } while (time_before(jiffies, timeout));
134
135 return -ETIMEDOUT;
136}
137
138static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
139{
140 struct ps3vram_priv *priv = dev->core.driver_data;
141
142 priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
143 priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
144}
145
146static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
147 unsigned int timeout_ms)
148{
149 struct ps3vram_priv *priv = dev->core.driver_data;
150 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
151
152 do {
153 if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
154 return 0;
155 msleep(1);
156 } while (time_before(jiffies, timeout));
157
158 dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
159 priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET],
160 priv->ctrl[CTRL_TOP]);
161
162 return -ETIMEDOUT;
163}
164
165static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
166{
167 *(priv->fifo_ptr)++ = data;
168}
169
170static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
171 u32 size)
172{
173 ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
174}
175
176static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
177{
178 struct ps3vram_priv *priv = dev->core.driver_data;
179 int status;
180
181 ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
182
183 priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
184
185 /* asking the HV for a blit will kick the FIFO */
d3352c9f 186 status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
f507cd22 187 if (status)
d3352c9f
GU		 188 dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
189 __func__, status);
f507cd22
GU		 190
191 priv->fifo_ptr = priv->fifo_base;
192}
193
194static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
195{
196 struct ps3vram_priv *priv = dev->core.driver_data;
197 int status;
198
199 mutex_lock(&ps3_gpu_mutex);
200
201 priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
202 (priv->fifo_ptr - priv->fifo_base) * sizeof(u32);
203
204 /* asking the HV for a blit will kick the FIFO */
d3352c9f 205 status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
f507cd22 206 if (status)
d3352c9f
GU		 207 dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
208 __func__, status);
f507cd22
GU		 209
210 if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
211 FIFO_SIZE - 1024) {
212 dev_dbg(&dev->core, "FIFO full, rewinding\n");
213 ps3vram_wait_ring(dev, 200);
214 ps3vram_rewind_ring(dev);
215 }
216
217 mutex_unlock(&ps3_gpu_mutex);
218}
219
220static void ps3vram_bind(struct ps3_system_bus_device *dev)
221{
222 struct ps3vram_priv *priv = dev->core.driver_data;
223
224 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
225 ps3vram_out_ring(priv, 0x31337303);
226 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
227 ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
228 ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
229 ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
230
231 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
232 ps3vram_out_ring(priv, 0x3137c0de);
233 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
234 ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
235 ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
236 ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
237
238 ps3vram_fire_ring(dev);
239}
240
241static int ps3vram_upload(struct ps3_system_bus_device *dev,
242 unsigned int src_offset, unsigned int dst_offset,
243 int len, int count)
244{
245 struct ps3vram_priv *priv = dev->core.driver_data;
246
247 ps3vram_begin_ring(priv, UPLOAD_SUBCH,
248 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
249 ps3vram_out_ring(priv, XDR_IOIF + src_offset);
250 ps3vram_out_ring(priv, dst_offset);
251 ps3vram_out_ring(priv, len);
252 ps3vram_out_ring(priv, len);
253 ps3vram_out_ring(priv, len);
254 ps3vram_out_ring(priv, count);
255 ps3vram_out_ring(priv, (1 << 8) | 1);
256 ps3vram_out_ring(priv, 0);
257
258 ps3vram_notifier_reset(dev);
259 ps3vram_begin_ring(priv, UPLOAD_SUBCH,
260 NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
261 ps3vram_out_ring(priv, 0);
262 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
263 ps3vram_out_ring(priv, 0);
264 ps3vram_fire_ring(dev);
265 if (ps3vram_notifier_wait(dev, 200) < 0) {
266 dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
267 return -1;
268 }
269
270 return 0;
271}
272
273static int ps3vram_download(struct ps3_system_bus_device *dev,
274 unsigned int src_offset, unsigned int dst_offset,
275 int len, int count)
276{
277 struct ps3vram_priv *priv = dev->core.driver_data;
278
279 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
280 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
281 ps3vram_out_ring(priv, src_offset);
282 ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
283 ps3vram_out_ring(priv, len);
284 ps3vram_out_ring(priv, len);
285 ps3vram_out_ring(priv, len);
286 ps3vram_out_ring(priv, count);
287 ps3vram_out_ring(priv, (1 << 8) | 1);
288 ps3vram_out_ring(priv, 0);
289
290 ps3vram_notifier_reset(dev);
291 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
292 NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
293 ps3vram_out_ring(priv, 0);
294 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
295 ps3vram_out_ring(priv, 0);
296 ps3vram_fire_ring(dev);
297 if (ps3vram_notifier_wait(dev, 200) < 0) {
298 dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
299 return -1;
300 }
301
302 return 0;
303}
304
305static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
306{
307 struct ps3vram_priv *priv = dev->core.driver_data;
308 struct ps3vram_cache *cache = &priv->cache;
309
310 if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
311 return;
312
313 dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
314 cache->tags[entry].address);
315 if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
316 cache->tags[entry].address, DMA_PAGE_SIZE,
317 cache->page_size / DMA_PAGE_SIZE) < 0) {
318 dev_err(&dev->core,
319 "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
320 entry * cache->page_size, cache->tags[entry].address,
321 cache->page_size);
322 }
323 cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
324}
325
326static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
327 unsigned int address)
328{
329 struct ps3vram_priv *priv = dev->core.driver_data;
330 struct ps3vram_cache *cache = &priv->cache;
331
332 dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
333 if (ps3vram_download(dev, address,
334 CACHE_OFFSET + entry * cache->page_size,
335 DMA_PAGE_SIZE,
336 cache->page_size / DMA_PAGE_SIZE) < 0) {
337 dev_err(&dev->core,
338 "Failed to download from 0x%x to 0x%x size 0x%x\n",
339 address, entry * cache->page_size, cache->page_size);
340 }
341
342 cache->tags[entry].address = address;
343 cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
344}
345
346
347static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
348{
349 struct ps3vram_priv *priv = dev->core.driver_data;
350 struct ps3vram_cache *cache = &priv->cache;
351 int i;
352
353 dev_dbg(&dev->core, "FLUSH\n");
354 for (i = 0; i < cache->page_count; i++) {
355 ps3vram_cache_evict(dev, i);
356 cache->tags[i].flags = 0;
357 }
358}
359
360static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
361 loff_t address)
362{
363 struct ps3vram_priv *priv = dev->core.driver_data;
364 struct ps3vram_cache *cache = &priv->cache;
365 unsigned int base;
366 unsigned int offset;
367 int i;
368 static int counter;
369
370 offset = (unsigned int) (address & (cache->page_size - 1));
371 base = (unsigned int) (address - offset);
372
373 /* fully associative check */
374 for (i = 0; i < cache->page_count; i++) {
375 if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
376 cache->tags[i].address == base) {
377 cache->hit++;
378 dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
379 cache->tags[i].address);
380 return i;
381 }
382 }
383
384 /* choose a random entry */
385 i = (jiffies + (counter++)) % cache->page_count;
386 dev_dbg(&dev->core, "Using entry %d\n", i);
387
388 ps3vram_cache_evict(dev, i);
389 ps3vram_cache_load(dev, i, base);
390
391 cache->miss++;
392 return i;
393}
394
395static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
396{
397 struct ps3vram_priv *priv = dev->core.driver_data;
398
399 priv->cache.page_count = CACHE_PAGE_COUNT;
400 priv->cache.page_size = CACHE_PAGE_SIZE;
401 priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
402 CACHE_PAGE_COUNT, GFP_KERNEL);
403 if (priv->cache.tags == NULL) {
404 dev_err(&dev->core, "Could not allocate cache tags\n");
405 return -ENOMEM;
406 }
407
408 dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
409 CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
410
411 return 0;
412}
413
414static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
415{
416 struct ps3vram_priv *priv = dev->core.driver_data;
417
418 ps3vram_cache_flush(dev);
419 kfree(priv->cache.tags);
420}
421
422static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
423 size_t len, size_t *retlen, u_char *buf)
424{
425 struct ps3vram_priv *priv = dev->core.driver_data;
426 unsigned int cached, count;
427
428 dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
429 (unsigned int)from, len);
430
431 if (from >= priv->size)
432 return -EIO;
433
434 if (len > priv->size - from)
435 len = priv->size - from;
436
437 /* Copy from vram to buf */
438 count = len;
439 while (count) {
440 unsigned int offset, avail;
441 unsigned int entry;
442
443 offset = (unsigned int) (from & (priv->cache.page_size - 1));
444 avail = priv->cache.page_size - offset;
445
f507cd22
GU		 446 entry = ps3vram_cache_match(dev, from);
447 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
448
449 dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
450 "avail=%08x count=%08x\n", __func__,
451 (unsigned int)from, cached, offset, avail, count);
452
453 if (avail > count)
454 avail = count;
455 memcpy(buf, priv->xdr_buf + cached, avail);
456
f507cd22
GU		 457 buf += avail;
458 count -= avail;
459 from += avail;
460 }
461
462 *retlen = len;
463 return 0;
464}
465
466static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
467 size_t len, size_t *retlen, const u_char *buf)
468{
469 struct ps3vram_priv *priv = dev->core.driver_data;
470 unsigned int cached, count;
471
472 if (to >= priv->size)
473 return -EIO;
474
475 if (len > priv->size - to)
476 len = priv->size - to;
477
478 /* Copy from buf to vram */
479 count = len;
480 while (count) {
481 unsigned int offset, avail;
482 unsigned int entry;
483
484 offset = (unsigned int) (to & (priv->cache.page_size - 1));
485 avail = priv->cache.page_size - offset;
486
f507cd22
GU		 487 entry = ps3vram_cache_match(dev, to);
488 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
489
490 dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
491 "avail=%08x count=%08x\n", __func__, (unsigned int)to,
492 cached, offset, avail, count);
493
494 if (avail > count)
495 avail = count;
496 memcpy(priv->xdr_buf + cached, buf, avail);
497
498 priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
499
f507cd22
GU		 500 buf += avail;
501 count -= avail;
502 to += avail;
503 }
504
505 *retlen = len;
506 return 0;
507}
508
509static int ps3vram_proc_show(struct seq_file *m, void *v)
510{
511 struct ps3vram_priv *priv = m->private;
512
513 seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
514 return 0;
515}
516
517static int ps3vram_proc_open(struct inode *inode, struct file *file)
518{
519 return single_open(file, ps3vram_proc_show, PDE(inode)->data);
520}
521
522static const struct file_operations ps3vram_proc_fops = {
523 .owner = THIS_MODULE,
524 .open = ps3vram_proc_open,
525 .read = seq_read,
526 .llseek = seq_lseek,
527 .release = single_release,
528};
529
530static void __devinit ps3vram_proc_init(struct ps3_system_bus_device *dev)
531{
532 struct ps3vram_priv *priv = dev->core.driver_data;
533 struct proc_dir_entry *pde;
534
3c20e2f2
GU		 535 pde = proc_create_data(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops,
536 priv);
537 if (!pde)
f507cd22 538 dev_warn(&dev->core, "failed to create /proc entry\n");
f507cd22
GU		 539}
540
fb89e89d
GU		 541static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev,
542 struct bio *bio)
f507cd22 543{
fb89e89d 544 struct ps3vram_priv *priv = dev->core.driver_data;
f507cd22
GU		 545 int write = bio_data_dir(bio) == WRITE;
546 const char *op = write ? "write" : "read";
547 loff_t offset = bio->bi_sector << 9;
548 int error = 0;
549 struct bio_vec *bvec;
550 unsigned int i;
fb89e89d 551 struct bio *next;
f507cd22
GU		 552
553 bio_for_each_segment(bvec, bio, i) {
554 /* PS3 is ppc64, so we don't handle highmem */
555 char *ptr = page_address(bvec->bv_page) + bvec->bv_offset;
556 size_t len = bvec->bv_len, retlen;
557
558 dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
559 len, offset);
560 if (write)
561 error = ps3vram_write(dev, offset, len, &retlen, ptr);
562 else
563 error = ps3vram_read(dev, offset, len, &retlen, ptr);
564
565 if (error) {
566 dev_err(&dev->core, "%s failed\n", op);
567 goto out;
568 }
569
570 if (retlen != len) {
571 dev_err(&dev->core, "Short %s\n", op);
734957c8 572 error = -EIO;
f507cd22
GU		 573 goto out;
574 }
575
576 offset += len;
577 }
578
579 dev_dbg(&dev->core, "%s completed\n", op);
580
581out:
fb89e89d
GU		 582 spin_lock_irq(&priv->lock);
583 bio_list_pop(&priv->list);
584 next = bio_list_peek(&priv->list);
585 spin_unlock_irq(&priv->lock);
586
f507cd22 587 bio_endio(bio, error);
fb89e89d
GU		 588 return next;
589}
590
591static int ps3vram_make_request(struct request_queue *q, struct bio *bio)
592{
593 struct ps3_system_bus_device *dev = q->queuedata;
594 struct ps3vram_priv *priv = dev->core.driver_data;
595 int busy;
596
597 dev_dbg(&dev->core, "%s\n", __func__);
598
599 spin_lock_irq(&priv->lock);
600 busy = !bio_list_empty(&priv->list);
601 bio_list_add(&priv->list, bio);
602 spin_unlock_irq(&priv->lock);
603
604 if (busy)
605 return 0;
606
607 do {
608 bio = ps3vram_do_bio(dev, bio);
609 } while (bio);
610
f507cd22
GU		 611 return 0;
612}
613
614static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
615{
616 struct ps3vram_priv *priv;
617 int error, status;
618 struct request_queue *queue;
619 struct gendisk *gendisk;
56ac72db
GU		 620 u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar,
621 reports_size, xdr_lpar;
f507cd22
GU		 622 char *rest;
623
624 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
625 if (!priv) {
626 error = -ENOMEM;
627 goto fail;
628 }
629
fb89e89d
GU		 630 spin_lock_init(&priv->lock);
631 bio_list_init(&priv->list);
f507cd22
GU		 632 dev->core.driver_data = priv;
633
634 priv = dev->core.driver_data;
635
636 /* Allocate XDR buffer (1MiB aligned) */
637 priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
638 get_order(XDR_BUF_SIZE));
639 if (priv->xdr_buf == NULL) {
640 dev_err(&dev->core, "Could not allocate XDR buffer\n");
641 error = -ENOMEM;
642 goto fail_free_priv;
643 }
644
645 /* Put FIFO at begginning of XDR buffer */
646 priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
647 priv->fifo_ptr = priv->fifo_base;
648
649 /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
650 if (ps3_open_hv_device(dev)) {
651 dev_err(&dev->core, "ps3_open_hv_device failed\n");
652 error = -EAGAIN;
3273d877 653 goto out_free_xdr_buf;
f507cd22
GU		 654 }
655
656 /* Request memory */
657 status = -1;
658 ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
659 if (!ddr_size) {
660 dev_err(&dev->core, "Specified size is too small\n");
661 error = -EINVAL;
662 goto out_close_gpu;
663 }
664
665 while (ddr_size > 0) {
666 status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
667 &priv->memory_handle,
668 &ddr_lpar);
669 if (!status)
670 break;
671 ddr_size -= 1024*1024;
672 }
673 if (status) {
674 dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
675 status);
676 error = -ENOMEM;
3273d877 677 goto out_close_gpu;
f507cd22
GU		 678 }
679
680 /* Request context */
681 status = lv1_gpu_context_allocate(priv->memory_handle, 0,
682 &priv->context_handle, &ctrl_lpar,
683 &info_lpar, &reports_lpar,
684 &reports_size);
685 if (status) {
686 dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
687 status);
688 error = -ENOMEM;
689 goto out_free_memory;
690 }
691
692 /* Map XDR buffer to RSX */
56ac72db 693 xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf));
f507cd22 694 status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
56ac72db
GU		 695 xdr_lpar, XDR_BUF_SIZE,
696 CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
697 CBE_IOPTE_M);
f507cd22
GU		 698 if (status) {
699 dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
700 status);
701 error = -ENOMEM;
702 goto out_free_context;
703 }
704
705 priv->ddr_base = ioremap_flags(ddr_lpar, ddr_size, _PAGE_NO_CACHE);
706
707 if (!priv->ddr_base) {
708 dev_err(&dev->core, "ioremap DDR failed\n");
709 error = -ENOMEM;
56ac72db 710 goto out_unmap_context;
f507cd22
GU		 711 }
712
713 priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
714 if (!priv->ctrl) {
715 dev_err(&dev->core, "ioremap CTRL failed\n");
716 error = -ENOMEM;
717 goto out_unmap_vram;
718 }
719
720 priv->reports = ioremap(reports_lpar, reports_size);
721 if (!priv->reports) {
722 dev_err(&dev->core, "ioremap REPORTS failed\n");
723 error = -ENOMEM;
724 goto out_unmap_ctrl;
725 }
726
727 mutex_lock(&ps3_gpu_mutex);
728 ps3vram_init_ring(dev);
729 mutex_unlock(&ps3_gpu_mutex);
730
731 priv->size = ddr_size;
732
733 ps3vram_bind(dev);
734
735 mutex_lock(&ps3_gpu_mutex);
736 error = ps3vram_wait_ring(dev, 100);
737 mutex_unlock(&ps3_gpu_mutex);
738 if (error < 0) {
739 dev_err(&dev->core, "Failed to initialize channels\n");
740 error = -ETIMEDOUT;
741 goto out_unmap_reports;
742 }
743
744 ps3vram_cache_init(dev);
745 ps3vram_proc_init(dev);
746
747 queue = blk_alloc_queue(GFP_KERNEL);
748 if (!queue) {
749 dev_err(&dev->core, "blk_alloc_queue failed\n");
750 error = -ENOMEM;
751 goto out_cache_cleanup;
752 }
753
754 priv->queue = queue;
755 queue->queuedata = dev;
756 blk_queue_make_request(queue, ps3vram_make_request);
757 blk_queue_max_phys_segments(queue, MAX_PHYS_SEGMENTS);
758 blk_queue_max_hw_segments(queue, MAX_HW_SEGMENTS);
759 blk_queue_max_segment_size(queue, MAX_SEGMENT_SIZE);
760 blk_queue_max_sectors(queue, SAFE_MAX_SECTORS);
761
762 gendisk = alloc_disk(1);
763 if (!gendisk) {
764 dev_err(&dev->core, "alloc_disk failed\n");
765 error = -ENOMEM;
766 goto fail_cleanup_queue;
767 }
768
769 priv->gendisk = gendisk;
770 gendisk->major = ps3vram_major;
771 gendisk->first_minor = 0;
772 gendisk->fops = &ps3vram_fops;
773 gendisk->queue = queue;
774 gendisk->private_data = dev;
775 gendisk->driverfs_dev = &dev->core;
776 strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
777 set_capacity(gendisk, priv->size >> 9);
778
779 dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n",
780 gendisk->disk_name, get_capacity(gendisk) >> 11);
781
782 add_disk(gendisk);
783 return 0;
784
785fail_cleanup_queue:
786 blk_cleanup_queue(queue);
787out_cache_cleanup:
788 remove_proc_entry(DEVICE_NAME, NULL);
789 ps3vram_cache_cleanup(dev);
790out_unmap_reports:
791 iounmap(priv->reports);
792out_unmap_ctrl:
793 iounmap(priv->ctrl);
794out_unmap_vram:
795 iounmap(priv->ddr_base);
56ac72db
GU		 796out_unmap_context:
797 lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar,
798 XDR_BUF_SIZE, CBE_IOPTE_M);
f507cd22
GU		 799out_free_context:
800 lv1_gpu_context_free(priv->context_handle);
801out_free_memory:
802 lv1_gpu_memory_free(priv->memory_handle);
803out_close_gpu:
804 ps3_close_hv_device(dev);
805out_free_xdr_buf:
806 free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
807fail_free_priv:
808 kfree(priv);
809 dev->core.driver_data = NULL;
810fail:
811 return error;
812}
813
814static int ps3vram_remove(struct ps3_system_bus_device *dev)
815{
816 struct ps3vram_priv *priv = dev->core.driver_data;
817
818 del_gendisk(priv->gendisk);
819 put_disk(priv->gendisk);
820 blk_cleanup_queue(priv->queue);
821 remove_proc_entry(DEVICE_NAME, NULL);
822 ps3vram_cache_cleanup(dev);
823 iounmap(priv->reports);
824 iounmap(priv->ctrl);
825 iounmap(priv->ddr_base);
56ac72db
GU		 826 lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
827 ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
828 XDR_BUF_SIZE, CBE_IOPTE_M);
f507cd22
GU		 829 lv1_gpu_context_free(priv->context_handle);
830 lv1_gpu_memory_free(priv->memory_handle);
831 ps3_close_hv_device(dev);
832 free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
833 kfree(priv);
834 dev->core.driver_data = NULL;
835 return 0;
836}
837
838static struct ps3_system_bus_driver ps3vram = {
839 .match_id = PS3_MATCH_ID_GPU,
840 .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
841 .core.name = DEVICE_NAME,
842 .core.owner = THIS_MODULE,
843 .probe = ps3vram_probe,
844 .remove = ps3vram_remove,
845 .shutdown = ps3vram_remove,
846};
847
848
849static int __init ps3vram_init(void)
850{
851 int error;
852
853 if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
854 return -ENODEV;
855
856 error = register_blkdev(0, DEVICE_NAME);
857 if (error <= 0) {
858 pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
859 return error;
860 }
861 ps3vram_major = error;
862
863 pr_info("%s: registered block device major %d\n", DEVICE_NAME,
864 ps3vram_major);
865
866 error = ps3_system_bus_driver_register(&ps3vram);
867 if (error)
868 unregister_blkdev(ps3vram_major, DEVICE_NAME);
869
870 return error;
871}
872
873static void __exit ps3vram_exit(void)
874{
875 ps3_system_bus_driver_unregister(&ps3vram);
876 unregister_blkdev(ps3vram_major, DEVICE_NAME);
877}
878
879module_init(ps3vram_init);
880module_exit(ps3vram_exit);
881
882MODULE_LICENSE("GPL");
883MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
884MODULE_AUTHOR("Sony Corporation");
885MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);
kernel source for telekom puls (alcatel/mediatek)