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iwlwifi: don't include iwl-dev.h from iwl-devtrace.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / atm / lanai.c
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1da177e4
LT		 1/* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com>
2 *
3 * This program is free software; you can redistribute it and/or
4 * modify it under the terms of the GNU General Public License
5 * as published by the Free Software Foundation; either version
6 * 2 of the License, or (at your option) any later version.
7 *
8 * This driver supports ATM cards based on the Efficient "Lanai"
9 * chipset such as the Speedstream 3010 and the ENI-25p. The
10 * Speedstream 3060 is currently not supported since we don't
11 * have the code to drive the on-board Alcatel DSL chipset (yet).
12 *
13 * Thanks to Efficient for supporting this project with hardware,
14 * documentation, and by answering my questions.
15 *
16 * Things not working yet:
17 *
18 * o We don't support the Speedstream 3060 yet - this card has
19 * an on-board DSL modem chip by Alcatel and the driver will
20 * need some extra code added to handle it
21 *
22 * o Note that due to limitations of the Lanai only one VCC can be
23 * in CBR at once
24 *
25 * o We don't currently parse the EEPROM at all. The code is all
26 * there as per the spec, but it doesn't actually work. I think
27 * there may be some issues with the docs. Anyway, do NOT
28 * enable it yet - bugs in that code may actually damage your
29 * hardware! Because of this you should hardware an ESI before
30 * trying to use this in a LANE or MPOA environment.
31 *
32 * o AAL0 is stubbed in but the actual rx/tx path isn't written yet:
33 * vcc_tx_aal0() needs to send or queue a SKB
34 * vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs
35 * vcc_rx_aal0() needs to handle AAL0 interrupts
36 * This isn't too much work - I just wanted to get other things
37 * done first.
38 *
39 * o lanai_change_qos() isn't written yet
40 *
41 * o There aren't any ioctl's yet -- I'd like to eventually support
49693280 42 * setting loopback and LED modes that way.
1da177e4
LT		 43 *
44 * o If the segmentation engine or DMA gets shut down we should restart
45 * card as per section 17.0i. (see lanai_reset)
46 *
47 * o setsockopt(SO_CIRANGE) isn't done (although despite what the
48 * API says it isn't exactly commonly implemented)
49 */
50
51/* Version history:
52 * v.1.00 -- 26-JUL-2003 -- PCI/DMA updates
53 * v.0.02 -- 11-JAN-2000 -- Endian fixes
54 * v.0.01 -- 30-NOV-1999 -- Initial release
55 */
56
57#include <linux/module.h>
58#include <linux/mm.h>
59#include <linux/atmdev.h>
60#include <asm/io.h>
61#include <asm/byteorder.h>
62#include <linux/spinlock.h>
63#include <linux/pci.h>
64#include <linux/dma-mapping.h>
65#include <linux/init.h>
66#include <linux/delay.h>
67#include <linux/interrupt.h>
1da177e4
LT		 68
69/* -------------------- TUNABLE PARAMATERS: */
70
71/*
72 * Maximum number of VCIs per card. Setting it lower could theoretically
73 * save some memory, but since we allocate our vcc list with get_free_pages,
74 * it's not really likely for most architectures
75 */
76#define NUM_VCI (1024)
77
78/*
79 * Enable extra debugging
80 */
81#define DEBUG
82/*
83 * Debug _all_ register operations with card, except the memory test.
84 * Also disables the timed poll to prevent extra chattiness. This
85 * isn't for normal use
86 */
87#undef DEBUG_RW
88
89/*
90 * The programming guide specifies a full test of the on-board SRAM
91 * at initialization time. Undefine to remove this
92 */
93#define FULL_MEMORY_TEST
94
95/*
96 * This is the number of (4 byte) service entries that we will
97 * try to allocate at startup. Note that we will end up with
98 * one PAGE_SIZE's worth regardless of what this is set to
99 */
100#define SERVICE_ENTRIES (1024)
101/* TODO: make above a module load-time option */
102
103/*
104 * We normally read the onboard EEPROM in order to discover our MAC
105 * address. Undefine to _not_ do this
106 */
107/* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */
108/* TODO: make above a module load-time option (also) */
109
110/*
111 * Depth of TX fifo (in 128 byte units; range 2-31)
112 * Smaller numbers are better for network latency
113 * Larger numbers are better for PCI latency
114 * I'm really sure where the best tradeoff is, but the BSD driver uses
115 * 7 and it seems to work ok.
116 */
117#define TX_FIFO_DEPTH (7)
118/* TODO: make above a module load-time option */
119
120/*
121 * How often (in jiffies) we will try to unstick stuck connections -
122 * shouldn't need to happen much
123 */
124#define LANAI_POLL_PERIOD (10*HZ)
125/* TODO: make above a module load-time option */
126
127/*
128 * When allocating an AAL5 receiving buffer, try to make it at least
129 * large enough to hold this many max_sdu sized PDUs
130 */
131#define AAL5_RX_MULTIPLIER (3)
132/* TODO: make above a module load-time option */
133
134/*
135 * Same for transmitting buffer
136 */
137#define AAL5_TX_MULTIPLIER (3)
138/* TODO: make above a module load-time option */
139
140/*
141 * When allocating an AAL0 transmiting buffer, how many cells should fit.
142 * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't
143 * really critical
144 */
145#define AAL0_TX_MULTIPLIER (40)
146/* TODO: make above a module load-time option */
147
148/*
149 * How large should we make the AAL0 receiving buffer. Remember that this
150 * is shared between all AAL0 VC's
151 */
152#define AAL0_RX_BUFFER_SIZE (PAGE_SIZE)
153/* TODO: make above a module load-time option */
154
155/*
156 * Should we use Lanai's "powerdown" feature when no vcc's are bound?
157 */
158/* #define USE_POWERDOWN */
159/* TODO: make above a module load-time option (also) */
160
161/* -------------------- DEBUGGING AIDS: */
162
163#define DEV_LABEL "lanai"
164
165#ifdef DEBUG
166
167#define DPRINTK(format, args...) \
168 printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
169#define APRINTK(truth, format, args...) \
170 do { \
171 if (unlikely(!(truth))) \
172 printk(KERN_ERR DEV_LABEL ": " format, ##args); \
173 } while (0)
174
175#else /* !DEBUG */
176
177#define DPRINTK(format, args...)
178#define APRINTK(truth, format, args...)
179
180#endif /* DEBUG */
181
182#ifdef DEBUG_RW
183#define RWDEBUG(format, args...) \
184 printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
185#else /* !DEBUG_RW */
186#define RWDEBUG(format, args...)
187#endif
188
189/* -------------------- DATA DEFINITIONS: */
190
191#define LANAI_MAPPING_SIZE (0x40000)
192#define LANAI_EEPROM_SIZE (128)
193
194typedef int vci_t;
195typedef void __iomem *bus_addr_t;
196
197/* DMA buffer in host memory for TX, RX, or service list. */
198struct lanai_buffer {
199 u32 *start; /* From get_free_pages */
200 u32 *end; /* One past last byte */
201 u32 *ptr; /* Pointer to current host location */
202 dma_addr_t dmaaddr;
203};
204
205struct lanai_vcc_stats {
206 unsigned rx_nomem;
207 union {
208 struct {
209 unsigned rx_badlen;
210 unsigned service_trash;
211 unsigned service_stream;
212 unsigned service_rxcrc;
213 } aal5;
214 struct {
215 } aal0;
216 } x;
217};
218
219struct lanai_dev; /* Forward declaration */
220
221/*
222 * This is the card-specific per-vcc data. Note that unlike some other
223 * drivers there is NOT a 1-to-1 correspondance between these and
224 * atm_vcc's - each one of these represents an actual 2-way vcc, but
225 * an atm_vcc can be 1-way and share with a 1-way vcc in the other
226 * direction. To make it weirder, there can even be 0-way vccs
227 * bound to us, waiting to do a change_qos
228 */
229struct lanai_vcc {
230 bus_addr_t vbase; /* Base of VCC's registers */
231 struct lanai_vcc_stats stats;
232 int nref; /* # of atm_vcc's who reference us */
233 vci_t vci;
234 struct {
235 struct lanai_buffer buf;
236 struct atm_vcc *atmvcc; /* atm_vcc who is receiver */
237 } rx;
238 struct {
239 struct lanai_buffer buf;
240 struct atm_vcc *atmvcc; /* atm_vcc who is transmitter */
241 int endptr; /* last endptr from service entry */
242 struct sk_buff_head backlog;
243 void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int);
244 } tx;
245};
246
247enum lanai_type {
1d0ed384
JS		 248 lanai2 = PCI_DEVICE_ID_EF_ATM_LANAI2,
249 lanaihb = PCI_DEVICE_ID_EF_ATM_LANAIHB
1da177e4
LT		 250};
251
252struct lanai_dev_stats {
253 unsigned ovfl_trash; /* # of cells dropped - buffer overflow */
254 unsigned vci_trash; /* # of cells dropped - closed vci */
255 unsigned hec_err; /* # of cells dropped - bad HEC */
256 unsigned atm_ovfl; /* # of cells dropped - rx fifo overflow */
257 unsigned pcierr_parity_detect;
258 unsigned pcierr_serr_set;
259 unsigned pcierr_master_abort;
260 unsigned pcierr_m_target_abort;
261 unsigned pcierr_s_target_abort;
262 unsigned pcierr_master_parity;
263 unsigned service_notx;
264 unsigned service_norx;
265 unsigned service_rxnotaal5;
266 unsigned dma_reenable;
267 unsigned card_reset;
268};
269
270struct lanai_dev {
271 bus_addr_t base;
272 struct lanai_dev_stats stats;
273 struct lanai_buffer service;
274 struct lanai_vcc **vccs;
275#ifdef USE_POWERDOWN
276 int nbound; /* number of bound vccs */
277#endif
278 enum lanai_type type;
279 vci_t num_vci; /* Currently just NUM_VCI */
280 u8 eeprom[LANAI_EEPROM_SIZE];
281 u32 serialno, magicno;
282 struct pci_dev *pci;
283 DECLARE_BITMAP(backlog_vccs, NUM_VCI); /* VCCs with tx backlog */
284 DECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */
285 struct timer_list timer;
286 int naal0;
287 struct lanai_buffer aal0buf; /* AAL0 RX buffers */
288 u32 conf1, conf2; /* CONFIG[12] registers */
289 u32 status; /* STATUS register */
290 spinlock_t endtxlock;
291 spinlock_t servicelock;
292 struct atm_vcc *cbrvcc;
293 int number;
294 int board_rev;
1da177e4
LT		 295/* TODO - look at race conditions with maintence of conf1/conf2 */
296/* TODO - transmit locking: should we use _irq not _irqsave? */
297/* TODO - organize above in some rational fashion (see <asm/cache.h>) */
298};
299
300/*
301 * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready)
302 * This function iterates one of these, calling a given function for each
303 * vci with their bit set
304 */
305static void vci_bitfield_iterate(struct lanai_dev *lanai,
c22c28f6 306 const unsigned long *lp,
1da177e4
LT		 307 void (*func)(struct lanai_dev *,vci_t vci))
308{
d287d66e
AM		 309 vci_t vci;
310
311 for_each_set_bit(vci, lp, NUM_VCI)
1da177e4 312 func(lanai, vci);
1da177e4
LT		 313}
314
315/* -------------------- BUFFER UTILITIES: */
316
317/*
318 * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes -
319 * usually any page allocation will do. Just to be safe in case
320 * PAGE_SIZE is insanely tiny, though...
321 */
322#define LANAI_PAGE_SIZE ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024)
323
324/*
325 * Allocate a buffer in host RAM for service list, RX, or TX
326 * Returns buf->start==NULL if no memory
327 * Note that the size will be rounded up 2^n bytes, and
328 * if we can't allocate that we'll settle for something smaller
329 * until minbytes
330 */
331static void lanai_buf_allocate(struct lanai_buffer *buf,
332 size_t bytes, size_t minbytes, struct pci_dev *pci)
333{
334 int size;
335
336 if (bytes > (128 * 1024)) /* max lanai buffer size */
337 bytes = 128 * 1024;
338 for (size = LANAI_PAGE_SIZE; size < bytes; size *= 2)
339 ;
340 if (minbytes < LANAI_PAGE_SIZE)
341 minbytes = LANAI_PAGE_SIZE;
342 do {
343 /*
344 * Technically we could use non-consistent mappings for
345 * everything, but the way the lanai uses DMA memory would
346 * make that a terrific pain. This is much simpler.
347 */
348 buf->start = pci_alloc_consistent(pci, size, &buf->dmaaddr);
349 if (buf->start != NULL) { /* Success */
350 /* Lanai requires 256-byte alignment of DMA bufs */
351 APRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0,
352 "bad dmaaddr: 0x%lx\n",
353 (unsigned long) buf->dmaaddr);
354 buf->ptr = buf->start;
355 buf->end = (u32 *)
356 (&((unsigned char *) buf->start)[size]);
357 memset(buf->start, 0, size);
358 break;
359 }
360 size /= 2;
361 } while (size >= minbytes);
362}
363
364/* size of buffer in bytes */
365static inline size_t lanai_buf_size(const struct lanai_buffer *buf)
366{
367 return ((unsigned long) buf->end) - ((unsigned long) buf->start);
368}
369
370static void lanai_buf_deallocate(struct lanai_buffer *buf,
371 struct pci_dev *pci)
372{
373 if (buf->start != NULL) {
374 pci_free_consistent(pci, lanai_buf_size(buf),
375 buf->start, buf->dmaaddr);
376 buf->start = buf->end = buf->ptr = NULL;
377 }
378}
379
380/* size of buffer as "card order" (0=1k .. 7=128k) */
381static int lanai_buf_size_cardorder(const struct lanai_buffer *buf)
382{
383 int order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10);
384
385 /* This can only happen if PAGE_SIZE is gigantic, but just in case */
386 if (order > 7)
387 order = 7;
388 return order;
389}
390
391/* -------------------- PORT I/O UTILITIES: */
392
393/* Registers (and their bit-fields) */
394enum lanai_register {
395 Reset_Reg = 0x00, /* Reset; read for chip type; bits: */
396#define RESET_GET_BOARD_REV(x) (((x)>> 0)&0x03) /* Board revision */
397#define RESET_GET_BOARD_ID(x) (((x)>> 2)&0x03) /* Board ID */
398#define BOARD_ID_LANAI256 (0) /* 25.6M adapter card */
399 Endian_Reg = 0x04, /* Endian setting */
400 IntStatus_Reg = 0x08, /* Interrupt status */
401 IntStatusMasked_Reg = 0x0C, /* Interrupt status (masked) */
402 IntAck_Reg = 0x10, /* Interrupt acknowledge */
403 IntAckMasked_Reg = 0x14, /* Interrupt acknowledge (masked) */
404 IntStatusSet_Reg = 0x18, /* Get status + enable/disable */
405 IntStatusSetMasked_Reg = 0x1C, /* Get status + en/di (masked) */
406 IntControlEna_Reg = 0x20, /* Interrupt control enable */
407 IntControlDis_Reg = 0x24, /* Interrupt control disable */
408 Status_Reg = 0x28, /* Status */
409#define STATUS_PROMDATA (0x00000001) /* PROM_DATA pin */
410#define STATUS_WAITING (0x00000002) /* Interrupt being delayed */
411#define STATUS_SOOL (0x00000004) /* SOOL alarm */
412#define STATUS_LOCD (0x00000008) /* LOCD alarm */
413#define STATUS_LED (0x00000010) /* LED (HAPPI) output */
414#define STATUS_GPIN (0x00000020) /* GPIN pin */
415#define STATUS_BUTTBUSY (0x00000040) /* Butt register is pending */
416 Config1_Reg = 0x2C, /* Config word 1; bits: */
417#define CONFIG1_PROMDATA (0x00000001) /* PROM_DATA pin */
418#define CONFIG1_PROMCLK (0x00000002) /* PROM_CLK pin */
419#define CONFIG1_SET_READMODE(x) ((x)*0x004) /* PCI BM reads; values: */
420#define READMODE_PLAIN (0) /* Plain memory read */
421#define READMODE_LINE (2) /* Memory read line */
422#define READMODE_MULTIPLE (3) /* Memory read multiple */
423#define CONFIG1_DMA_ENABLE (0x00000010) /* Turn on DMA */
424#define CONFIG1_POWERDOWN (0x00000020) /* Turn off clocks */
425#define CONFIG1_SET_LOOPMODE(x) ((x)*0x080) /* Clock&loop mode; values: */
426#define LOOPMODE_NORMAL (0) /* Normal - no loop */
427#define LOOPMODE_TIME (1)
428#define LOOPMODE_DIAG (2)
429#define LOOPMODE_LINE (3)
430#define CONFIG1_MASK_LOOPMODE (0x00000180)
431#define CONFIG1_SET_LEDMODE(x) ((x)*0x0200) /* Mode of LED; values: */
432#define LEDMODE_NOT_SOOL (0) /* !SOOL */
433#define LEDMODE_OFF (1) /* 0 */
434#define LEDMODE_ON (2) /* 1 */
435#define LEDMODE_NOT_LOCD (3) /* !LOCD */
436#define LEDMORE_GPIN (4) /* GPIN */
437#define LEDMODE_NOT_GPIN (7) /* !GPIN */
438#define CONFIG1_MASK_LEDMODE (0x00000E00)
439#define CONFIG1_GPOUT1 (0x00001000) /* Toggle for reset */
440#define CONFIG1_GPOUT2 (0x00002000) /* Loopback PHY */
441#define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */
442 Config2_Reg = 0x30, /* Config word 2; bits: */
443#define CONFIG2_HOWMANY (0x00000001) /* >512 VCIs? */
444#define CONFIG2_PTI7_MODE (0x00000002) /* Make PTI=7 RM, not OAM */
445#define CONFIG2_VPI_CHK_DIS (0x00000004) /* Ignore RX VPI value */
446#define CONFIG2_HEC_DROP (0x00000008) /* Drop cells w/ HEC errors */
447#define CONFIG2_VCI0_NORMAL (0x00000010) /* Treat VCI=0 normally */
448#define CONFIG2_CBR_ENABLE (0x00000020) /* Deal with CBR traffic */
449#define CONFIG2_TRASH_ALL (0x00000040) /* Trashing incoming cells */
450#define CONFIG2_TX_DISABLE (0x00000080) /* Trashing outgoing cells */
451#define CONFIG2_SET_TRASH (0x00000100) /* Turn trashing on */
452 Statistics_Reg = 0x34, /* Statistics; bits: */
453#define STATS_GET_FIFO_OVFL(x) (((x)>> 0)&0xFF) /* FIFO overflowed */
454#define STATS_GET_HEC_ERR(x) (((x)>> 8)&0xFF) /* HEC was bad */
455#define STATS_GET_BAD_VCI(x) (((x)>>16)&0xFF) /* VCI not open */
456#define STATS_GET_BUF_OVFL(x) (((x)>>24)&0xFF) /* VCC buffer full */
457 ServiceStuff_Reg = 0x38, /* Service stuff; bits: */
458#define SSTUFF_SET_SIZE(x) ((x)*0x20000000) /* size of service buffer */
459#define SSTUFF_SET_ADDR(x) ((x)>>8) /* set address of buffer */
460 ServWrite_Reg = 0x3C, /* ServWrite Pointer */
461 ServRead_Reg = 0x40, /* ServRead Pointer */
462 TxDepth_Reg = 0x44, /* FIFO Transmit Depth */
463 Butt_Reg = 0x48, /* Butt register */
464 CBR_ICG_Reg = 0x50,
465 CBR_PTR_Reg = 0x54,
466 PingCount_Reg = 0x58, /* Ping count */
467 DMA_Addr_Reg = 0x5C /* DMA address */
468};
469
470static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
471 enum lanai_register reg)
472{
473 return lanai->base + reg;
474}
475
476static inline u32 reg_read(const struct lanai_dev *lanai,
477 enum lanai_register reg)
478{
479 u32 t;
480 t = readl(reg_addr(lanai, reg));
481 RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
482 (int) reg, t);
483 return t;
484}
485
486static inline void reg_write(const struct lanai_dev *lanai, u32 val,
487 enum lanai_register reg)
488{
489 RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
490 (int) reg, val);
491 writel(val, reg_addr(lanai, reg));
492}
493
494static inline void conf1_write(const struct lanai_dev *lanai)
495{
496 reg_write(lanai, lanai->conf1, Config1_Reg);
497}
498
499static inline void conf2_write(const struct lanai_dev *lanai)
500{
501 reg_write(lanai, lanai->conf2, Config2_Reg);
502}
503
504/* Same as conf2_write(), but defers I/O if we're powered down */
505static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)
506{
507#ifdef USE_POWERDOWN
508 if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))
509 return;
510#endif /* USE_POWERDOWN */
511 conf2_write(lanai);
512}
513
514static inline void reset_board(const struct lanai_dev *lanai)
515{
516 DPRINTK("about to reset board\n");
517 reg_write(lanai, 0, Reset_Reg);
518 /*
519 * If we don't delay a little while here then we can end up
520 * leaving the card in a VERY weird state and lock up the
521 * PCI bus. This isn't documented anywhere but I've convinced
522 * myself after a lot of painful experimentation
523 */
524 udelay(5);
525}
526
527/* -------------------- CARD SRAM UTILITIES: */
528
529/* The SRAM is mapped into normal PCI memory space - the only catch is
530 * that it is only 16-bits wide but must be accessed as 32-bit. The
531 * 16 high bits will be zero. We don't hide this, since they get
532 * programmed mostly like discrete registers anyway
533 */
534#define SRAM_START (0x20000)
535#define SRAM_BYTES (0x20000) /* Again, half don't really exist */
536
537static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
538{
539 return lanai->base + SRAM_START + offset;
540}
541
542static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
543{
544 return readl(sram_addr(lanai, offset));
545}
546
547static inline void sram_write(const struct lanai_dev *lanai,
548 u32 val, int offset)
549{
550 writel(val, sram_addr(lanai, offset));
551}
552
de24a193
AB		 553static int __devinit sram_test_word(const struct lanai_dev *lanai,
554 int offset, u32 pattern)
1da177e4
LT		 555{
556 u32 readback;
557 sram_write(lanai, pattern, offset);
558 readback = sram_read(lanai, offset);
559 if (likely(readback == pattern))
560 return 0;
561 printk(KERN_ERR DEV_LABEL
562 "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n",
563 lanai->number, offset,
564 (unsigned int) pattern, (unsigned int) readback);
565 return -EIO;
566}
567
568static int __devinit sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
569{
570 int offset, result = 0;
571 for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4)
572 result = sram_test_word(lanai, offset, pattern);
573 return result;
574}
575
576static int __devinit sram_test_and_clear(const struct lanai_dev *lanai)
577{
578#ifdef FULL_MEMORY_TEST
579 int result;
580 DPRINTK("testing SRAM\n");
581 if ((result = sram_test_pass(lanai, 0x5555)) != 0)
582 return result;
583 if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
584 return result;
585#endif
586 DPRINTK("clearing SRAM\n");
587 return sram_test_pass(lanai, 0x0000);
588}
589
590/* -------------------- CARD-BASED VCC TABLE UTILITIES: */
591
592/* vcc table */
593enum lanai_vcc_offset {
594 vcc_rxaddr1 = 0x00, /* Location1, plus bits: */
595#define RXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of RX buffer */
596#define RXADDR1_SET_RMMODE(x) ((x)*0x00800) /* RM cell action; values: */
597#define RMMODE_TRASH (0) /* discard */
598#define RMMODE_PRESERVE (1) /* input as AAL0 */
599#define RMMODE_PIPE (2) /* pipe to coscheduler */
600#define RMMODE_PIPEALL (3) /* pipe non-RM too */
601#define RXADDR1_OAM_PRESERVE (0x00002000) /* Input OAM cells as AAL0 */
602#define RXADDR1_SET_MODE(x) ((x)*0x0004000) /* Reassembly mode */
603#define RXMODE_TRASH (0) /* discard */
604#define RXMODE_AAL0 (1) /* non-AAL5 mode */
605#define RXMODE_AAL5 (2) /* AAL5, intr. each PDU */
606#define RXMODE_AAL5_STREAM (3) /* AAL5 w/o per-PDU intr */
607 vcc_rxaddr2 = 0x04, /* Location2 */
608 vcc_rxcrc1 = 0x08, /* RX CRC claculation space */
609 vcc_rxcrc2 = 0x0C,
610 vcc_rxwriteptr = 0x10, /* RX writeptr, plus bits: */
611#define RXWRITEPTR_LASTEFCI (0x00002000) /* Last PDU had EFCI bit */
612#define RXWRITEPTR_DROPPING (0x00004000) /* Had error, dropping */
613#define RXWRITEPTR_TRASHING (0x00008000) /* Trashing */
614 vcc_rxbufstart = 0x14, /* RX bufstart, plus bits: */
615#define RXBUFSTART_CLP (0x00004000)
616#define RXBUFSTART_CI (0x00008000)
617 vcc_rxreadptr = 0x18, /* RX readptr */
618 vcc_txicg = 0x1C, /* TX ICG */
619 vcc_txaddr1 = 0x20, /* Location1, plus bits: */
620#define TXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of TX buffer */
621#define TXADDR1_ABR (0x00008000) /* use ABR (doesn't work) */
622 vcc_txaddr2 = 0x24, /* Location2 */
623 vcc_txcrc1 = 0x28, /* TX CRC claculation space */
624 vcc_txcrc2 = 0x2C,
625 vcc_txreadptr = 0x30, /* TX Readptr, plus bits: */
626#define TXREADPTR_GET_PTR(x) ((x)&0x01FFF)
627#define TXREADPTR_MASK_DELTA (0x0000E000) /* ? */
628 vcc_txendptr = 0x34, /* TX Endptr, plus bits: */
629#define TXENDPTR_CLP (0x00002000)
630#define TXENDPTR_MASK_PDUMODE (0x0000C000) /* PDU mode; values: */
631#define PDUMODE_AAL0 (0*0x04000)
632#define PDUMODE_AAL5 (2*0x04000)
633#define PDUMODE_AAL5STREAM (3*0x04000)
634 vcc_txwriteptr = 0x38, /* TX Writeptr */
635#define TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF)
636 vcc_txcbr_next = 0x3C /* # of next CBR VCI in ring */
637#define TXCBR_NEXT_BOZO (0x00008000) /* "bozo bit" */
638};
639
640#define CARDVCC_SIZE (0x40)
641
642static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
643 vci_t vci)
644{
645 return sram_addr(lanai, vci * CARDVCC_SIZE);
646}
647
648static inline u32 cardvcc_read(const struct lanai_vcc *lvcc,
649 enum lanai_vcc_offset offset)
650{
651 u32 val;
652 APRINTK(lvcc->vbase != NULL, "cardvcc_read: unbound vcc!\n");
653 val= readl(lvcc->vbase + offset);
654 RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n",
655 lvcc->vci, (int) offset, val);
656 return val;
657}
658
659static inline void cardvcc_write(const struct lanai_vcc *lvcc,
660 u32 val, enum lanai_vcc_offset offset)
661{
662 APRINTK(lvcc->vbase != NULL, "cardvcc_write: unbound vcc!\n");
663 APRINTK((val & ~0xFFFF) == 0,
664 "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n",
665 (unsigned int) val, lvcc->vci, (unsigned int) offset);
666 RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n",
667 lvcc->vci, (unsigned int) offset, (unsigned int) val);
668 writel(val, lvcc->vbase + offset);
669}
670
671/* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */
672
673/* How many bytes will an AAL5 PDU take to transmit - remember that:
674 * o we need to add 8 bytes for length, CPI, UU, and CRC
675 * o we need to round up to 48 bytes for cells
676 */
677static inline int aal5_size(int size)
678{
679 int cells = (size + 8 + 47) / 48;
680 return cells * 48;
681}
682
683/* How many bytes can we send if we have "space" space, assuming we have
684 * to send full cells
685 */
686static inline int aal5_spacefor(int space)
687{
688 int cells = space / 48;
689 return cells * 48;
690}
691
692/* -------------------- FREE AN ATM SKB: */
693
694static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb)
695{
696 if (atmvcc->pop != NULL)
697 atmvcc->pop(atmvcc, skb);
698 else
699 dev_kfree_skb_any(skb);
700}
701
702/* -------------------- TURN VCCS ON AND OFF: */
703
704static void host_vcc_start_rx(const struct lanai_vcc *lvcc)
705{
706 u32 addr1;
707 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) {
708 dma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr;
709 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1);
710 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2);
711 cardvcc_write(lvcc, 0, vcc_rxwriteptr);
712 cardvcc_write(lvcc, 0, vcc_rxbufstart);
713 cardvcc_write(lvcc, 0, vcc_rxreadptr);
714 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2);
715 addr1 = ((dmaaddr >> 8) & 0xFF) |
716 RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))|
717 RXADDR1_SET_RMMODE(RMMODE_TRASH) | /* ??? */
718 /* RXADDR1_OAM_PRESERVE | --- no OAM support yet */
719 RXADDR1_SET_MODE(RXMODE_AAL5);
720 } else
721 addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */
722 RXADDR1_OAM_PRESERVE | /* ??? */
723 RXADDR1_SET_MODE(RXMODE_AAL0);
724 /* This one must be last! */
725 cardvcc_write(lvcc, addr1, vcc_rxaddr1);
726}
727
728static void host_vcc_start_tx(const struct lanai_vcc *lvcc)
729{
730 dma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr;
731 cardvcc_write(lvcc, 0, vcc_txicg);
732 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1);
733 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2);
734 cardvcc_write(lvcc, 0, vcc_txreadptr);
735 cardvcc_write(lvcc, 0, vcc_txendptr);
736 cardvcc_write(lvcc, 0, vcc_txwriteptr);
737 cardvcc_write(lvcc,
738 (lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ?
739 TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next);
740 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2);
741 cardvcc_write(lvcc,
742 ((dmaaddr >> 8) & 0xFF) |
743 TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)),
744 vcc_txaddr1);
745}
746
747/* Shutdown receiving on card */
748static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc)
749{
750 if (lvcc->vbase == NULL) /* We were never bound to a VCI */
751 return;
752 /* 15.1.1 - set to trashing, wait one cell time (15us) */
753 cardvcc_write(lvcc,
754 RXADDR1_SET_RMMODE(RMMODE_TRASH) |
755 RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1);
756 udelay(15);
757 /* 15.1.2 - clear rest of entries */
758 cardvcc_write(lvcc, 0, vcc_rxaddr2);
759 cardvcc_write(lvcc, 0, vcc_rxcrc1);
760 cardvcc_write(lvcc, 0, vcc_rxcrc2);
761 cardvcc_write(lvcc, 0, vcc_rxwriteptr);
762 cardvcc_write(lvcc, 0, vcc_rxbufstart);
763 cardvcc_write(lvcc, 0, vcc_rxreadptr);
764}
765
766/* Shutdown transmitting on card.
767 * Unfortunately the lanai needs us to wait until all the data
768 * drains out of the buffer before we can dealloc it, so this
769 * can take awhile -- up to 370ms for a full 128KB buffer
770 * assuming everone else is quiet. In theory the time is
771 * boundless if there's a CBR VCC holding things up.
772 */
773static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
774 struct lanai_vcc *lvcc)
775{
776 struct sk_buff *skb;
777 unsigned long flags, timeout;
778 int read, write, lastread = -1;
779 APRINTK(!in_interrupt(),
780 "lanai_shutdown_tx_vci called w/o process context!\n");
781 if (lvcc->vbase == NULL) /* We were never bound to a VCI */
782 return;
783 /* 15.2.1 - wait for queue to drain */
784 while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL)
785 lanai_free_skb(lvcc->tx.atmvcc, skb);
786 read_lock_irqsave(&vcc_sklist_lock, flags);
787 __clear_bit(lvcc->vci, lanai->backlog_vccs);
788 read_unlock_irqrestore(&vcc_sklist_lock, flags);
789 /*
790 * We need to wait for the VCC to drain but don't wait forever. We
791 * give each 1K of buffer size 1/128th of a second to clear out.
792 * TODO: maybe disable CBR if we're about to timeout?
793 */
794 timeout = jiffies +
795 (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7);
796 write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr));
797 for (;;) {
798 read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
799 if (read == write && /* Is TX buffer empty? */
800 (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR ||
801 (cardvcc_read(lvcc, vcc_txcbr_next) &
802 TXCBR_NEXT_BOZO) == 0))
803 break;
804 if (read != lastread) { /* Has there been any progress? */
805 lastread = read;
806 timeout += HZ / 10;
807 }
808 if (unlikely(time_after(jiffies, timeout))) {
809 printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on "
810 "backlog closing vci %d\n",
811 lvcc->tx.atmvcc->dev->number, lvcc->vci);
812 DPRINTK("read, write = %d, %d\n", read, write);
813 break;
814 }
815 msleep(40);
816 }
817 /* 15.2.2 - clear out all tx registers */
818 cardvcc_write(lvcc, 0, vcc_txreadptr);
819 cardvcc_write(lvcc, 0, vcc_txwriteptr);
820 cardvcc_write(lvcc, 0, vcc_txendptr);
821 cardvcc_write(lvcc, 0, vcc_txcrc1);
822 cardvcc_write(lvcc, 0, vcc_txcrc2);
823 cardvcc_write(lvcc, 0, vcc_txaddr2);
824 cardvcc_write(lvcc, 0, vcc_txaddr1);
825}
826
827/* -------------------- MANAGING AAL0 RX BUFFER: */
828
829static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
830{
831 DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n");
832 lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,
833 lanai->pci);
834 return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;
835}
836
837static inline void aal0_buffer_free(struct lanai_dev *lanai)
838{
839 DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n");
840 lanai_buf_deallocate(&lanai->aal0buf, lanai->pci);
841}
842
843/* -------------------- EEPROM UTILITIES: */
844
845/* Offsets of data in the EEPROM */
846#define EEPROM_COPYRIGHT (0)
847#define EEPROM_COPYRIGHT_LEN (44)
848#define EEPROM_CHECKSUM (62)
849#define EEPROM_CHECKSUM_REV (63)
850#define EEPROM_MAC (64)
851#define EEPROM_MAC_REV (70)
852#define EEPROM_SERIAL (112)
853#define EEPROM_SERIAL_REV (116)
854#define EEPROM_MAGIC (120)
855#define EEPROM_MAGIC_REV (124)
856
857#define EEPROM_MAGIC_VALUE (0x5AB478D2)
858
859#ifndef READ_EEPROM
860
861/* Stub functions to use if EEPROM reading is disabled */
862static int __devinit eeprom_read(struct lanai_dev *lanai)
863{
864 printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n",
865 lanai->number);
866 memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
867 return 0;
868}
869
870static int __devinit eeprom_validate(struct lanai_dev *lanai)
871{
872 lanai->serialno = 0;
873 lanai->magicno = EEPROM_MAGIC_VALUE;
874 return 0;
875}
876
877#else /* READ_EEPROM */
878
879static int __devinit eeprom_read(struct lanai_dev *lanai)
880{
881 int i, address;
882 u8 data;
883 u32 tmp;
884#define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \
885 } while (0)
886#define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK)
887#define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
888#define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA)
889#define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
890#define pre_read() do { data_h(); clock_h(); udelay(5); } while (0)
891#define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
892#define send_stop() do { data_l(); udelay(5); clock_h(); udelay(5); \
893 data_h(); udelay(5); } while (0)
894 /* start with both clock and data high */
895 data_h(); clock_h(); udelay(5);
896 for (address = 0; address < LANAI_EEPROM_SIZE; address++) {
897 data = (address << 1) | 1; /* Command=read + address */
898 /* send start bit */
899 data_l(); udelay(5);
900 clock_l(); udelay(5);
901 for (i = 128; i != 0; i >>= 1) { /* write command out */
902 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
858671f8 903 ((data & i) ? CONFIG1_PROMDATA : 0);
1da177e4
LT		 904 if (lanai->conf1 != tmp) {
905 set_config1(tmp);
906 udelay(5); /* Let new data settle */
907 }
908 clock_h(); udelay(5); clock_l(); udelay(5);
909 }
910 /* look for ack */
911 data_h(); clock_h(); udelay(5);
912 if (read_pin() != 0)
913 goto error; /* No ack seen */
914 clock_l(); udelay(5);
915 /* read back result */
916 for (data = 0, i = 7; i >= 0; i--) {
917 data_h(); clock_h(); udelay(5);
918 data = (data << 1) | !!read_pin();
919 clock_l(); udelay(5);
920 }
921 /* look again for ack */
922 data_h(); clock_h(); udelay(5);
923 if (read_pin() == 0)
924 goto error; /* Spurious ack */
925 clock_l(); udelay(5);
926 send_stop();
927 lanai->eeprom[address] = data;
928 DPRINTK("EEPROM 0x%04X %02X\n",
929 (unsigned int) address, (unsigned int) data);
930 }
931 return 0;
932 error:
933 clock_l(); udelay(5); /* finish read */
934 send_stop();
935 printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n",
936 lanai->number, address);
937 return -EIO;
938#undef set_config1
939#undef clock_h
940#undef clock_l
941#undef data_h
942#undef data_l
943#undef pre_read
944#undef read_pin
945#undef send_stop
946}
947
948/* read a big-endian 4-byte value out of eeprom */
949static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
950{
c22c28f6 951 return be32_to_cpup((const u32 *) &lanai->eeprom[address]);
1da177e4
LT		 952}
953
954/* Checksum/validate EEPROM contents */
955static int __devinit eeprom_validate(struct lanai_dev *lanai)
956{
957 int i, s;
958 u32 v;
959 const u8 *e = lanai->eeprom;
960#ifdef DEBUG
961 /* First, see if we can get an ASCIIZ string out of the copyright */
962 for (i = EEPROM_COPYRIGHT;
963 i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++)
964 if (e[i] < 0x20 || e[i] > 0x7E)
965 break;
966 if ( i != EEPROM_COPYRIGHT &&
967 i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0')
968 DPRINTK("eeprom: copyright = \"%s\"\n",
969 (char *) &e[EEPROM_COPYRIGHT]);
970 else
971 DPRINTK("eeprom: copyright not found\n");
972#endif
973 /* Validate checksum */
974 for (i = s = 0; i < EEPROM_CHECKSUM; i++)
975 s += e[i];
976 s &= 0xFF;
977 if (s != e[EEPROM_CHECKSUM]) {
978 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad "
979 "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
980 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]);
981 return -EIO;
982 }
983 s ^= 0xFF;
984 if (s != e[EEPROM_CHECKSUM_REV]) {
985 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum "
986 "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
987 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]);
988 return -EIO;
989 }
990 /* Verify MAC address */
991 for (i = 0; i < 6; i++)
992 if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) {
993 printk(KERN_ERR DEV_LABEL
994 "(itf %d) : EEPROM MAC addresses don't match "
995 "(0x%02X, inverse 0x%02X)\n", lanai->number,
996 (unsigned int) e[EEPROM_MAC + i],
997 (unsigned int) e[EEPROM_MAC_REV + i]);
998 return -EIO;
999 }
8d9ded23 1000 DPRINTK("eeprom: MAC address = %pM\n", &e[EEPROM_MAC]);
1da177e4
LT		 1001 /* Verify serial number */
1002 lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
1003 v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
1004 if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
1005 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers "
1006 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1007 (unsigned int) lanai->serialno, (unsigned int) v);
1008 return -EIO;
1009 }
1010 DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno);
1011 /* Verify magic number */
1012 lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
1013 v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
1014 if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
1015 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers "
1016 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1017 lanai->magicno, v);
1018 return -EIO;
1019 }
1020 DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
1021 if (lanai->magicno != EEPROM_MAGIC_VALUE)
1022 printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM "
1023 "magic not what expected (got 0x%08X, not 0x%08X)\n",
1024 lanai->number, (unsigned int) lanai->magicno,
1025 (unsigned int) EEPROM_MAGIC_VALUE);
1026 return 0;
1027}
1028
1029#endif /* READ_EEPROM */
1030
1031static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
1032{
1033 return &lanai->eeprom[EEPROM_MAC];
1034}
1035
1036/* -------------------- INTERRUPT HANDLING UTILITIES: */
1037
1038/* Interrupt types */
1039#define INT_STATS (0x00000002) /* Statistics counter overflow */
1040#define INT_SOOL (0x00000004) /* SOOL changed state */
1041#define INT_LOCD (0x00000008) /* LOCD changed state */
1042#define INT_LED (0x00000010) /* LED (HAPPI) changed state */
1043#define INT_GPIN (0x00000020) /* GPIN changed state */
1044#define INT_PING (0x00000040) /* PING_COUNT fulfilled */
1045#define INT_WAKE (0x00000080) /* Lanai wants bus */
1046#define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */
1047#define INT_LOCK (0x00000200) /* Service list overflow */
1048#define INT_MISMATCH (0x00000400) /* TX magic list mismatch */
1049#define INT_AAL0_STR (0x00000800) /* Non-AAL5 buffer half filled */
1050#define INT_AAL0 (0x00001000) /* Non-AAL5 data available */
1051#define INT_SERVICE (0x00002000) /* Service list entries available */
1052#define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */
1053#define INT_TABORTBM (0x00008000) /* Abort rcv'd as bus master */
1054#define INT_TIMEOUTBM (0x00010000) /* No response to bus master */
1055#define INT_PCIPARITY (0x00020000) /* Parity error on PCI */
1056
1057/* Sets of the above */
1058#define INT_ALL (0x0003FFFE) /* All interrupts */
1059#define INT_STATUS (0x0000003C) /* Some status pin changed */
1060#define INT_DMASHUT (0x00038000) /* DMA engine got shut down */
1061#define INT_SEGSHUT (0x00000700) /* Segmentation got shut down */
1062
1063static inline u32 intr_pending(const struct lanai_dev *lanai)
1064{
1065 return reg_read(lanai, IntStatusMasked_Reg);
1066}
1067
1068static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
1069{
1070 reg_write(lanai, i, IntControlEna_Reg);
1071}
1072
1073static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
1074{
1075 reg_write(lanai, i, IntControlDis_Reg);
1076}
1077
1078/* -------------------- CARD/PCI STATUS: */
1079
1080static void status_message(int itf, const char *name, int status)
1081{
1082 static const char *onoff[2] = { "off to on", "on to off" };
1083 printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n",
1084 itf, name, onoff[!status]);
1085}
1086
1087static void lanai_check_status(struct lanai_dev *lanai)
1088{
1089 u32 new = reg_read(lanai, Status_Reg);
1090 u32 changes = new ^ lanai->status;
1091 lanai->status = new;
1092#define e(flag, name) \
1093 if (changes & flag) \
1094 status_message(lanai->number, name, new & flag)
1095 e(STATUS_SOOL, "SOOL");
1096 e(STATUS_LOCD, "LOCD");
1097 e(STATUS_LED, "LED");
1098 e(STATUS_GPIN, "GPIN");
1099#undef e
1100}
1101
1102static void pcistatus_got(int itf, const char *name)
1103{
1104 printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name);
1105}
1106
1107static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
1108{
1109 u16 s;
1110 int result;
1111 result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
1112 if (result != PCIBIOS_SUCCESSFUL) {
1113 printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: "
1114 "%d\n", lanai->number, result);
1115 return;
1116 }
1117 s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR |
1118 PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT |
1119 PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY;
1120 if (s == 0)
1121 return;
1122 result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
1123 if (result != PCIBIOS_SUCCESSFUL)
1124 printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: "
1125 "%d\n", lanai->number, result);
1126 if (clearonly)
1127 return;
1128#define e(flag, name, stat) \
1129 if (s & flag) { \
1130 pcistatus_got(lanai->number, name); \
1131 ++lanai->stats.pcierr_##stat; \
1132 }
1133 e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect);
1134 e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set);
1135 e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort);
1136 e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort);
1137 e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort);
1138 e(PCI_STATUS_PARITY, "master parity", master_parity);
1139#undef e
1140}
1141
1142/* -------------------- VCC TX BUFFER UTILITIES: */
1143
1144/* space left in tx buffer in bytes */
1145static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr)
1146{
1147 int r;
1148 r = endptr * 16;
1149 r -= ((unsigned long) lvcc->tx.buf.ptr) -
1150 ((unsigned long) lvcc->tx.buf.start);
1151 r -= 16; /* Leave "bubble" - if start==end it looks empty */
1152 if (r < 0)
1153 r += lanai_buf_size(&lvcc->tx.buf);
1154 return r;
1155}
1156
1157/* test if VCC is currently backlogged */
c22c28f6 1158static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc)
1da177e4
LT		 1159{
1160 return !skb_queue_empty(&lvcc->tx.backlog);
1161}
1162
1163/* Bit fields in the segmentation buffer descriptor */
1164#define DESCRIPTOR_MAGIC (0xD0000000)
1165#define DESCRIPTOR_AAL5 (0x00008000)
1166#define DESCRIPTOR_AAL5_STREAM (0x00004000)
1167#define DESCRIPTOR_CLP (0x00002000)
1168
1169/* Add 32-bit descriptor with its padding */
1170static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc,
1171 u32 flags, int len)
1172{
1173 int pos;
1174 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0,
1175 "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr);
1176 lvcc->tx.buf.ptr += 4; /* Hope the values REALLY don't matter */
1177 pos = ((unsigned char *) lvcc->tx.buf.ptr) -
1178 (unsigned char *) lvcc->tx.buf.start;
1179 APRINTK((pos & ~0x0001FFF0) == 0,
1180 "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, "
1181 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1182 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1183 pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1);
1184 APRINTK((pos & ~0x0001FFF0) == 0,
1185 "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, "
1186 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1187 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1188 lvcc->tx.buf.ptr[-1] =
1189 cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 |
1190 ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ?
1191 DESCRIPTOR_CLP : 0) | flags | pos >> 4);
1192 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1193 lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1194}
1195
1196/* Add 32-bit AAL5 trailer and leave room for its CRC */
1197static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc,
1198 int len, int cpi, int uu)
1199{
1200 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8,
1201 "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr);
1202 lvcc->tx.buf.ptr += 2;
1203 lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len);
1204 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1205 lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1206}
1207
1208static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc,
1209 const unsigned char *src, int n)
1210{
1211 unsigned char *e;
1212 int m;
1213 e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1214 m = e - (unsigned char *) lvcc->tx.buf.end;
1215 if (m < 0)
1216 m = 0;
1217 memcpy(lvcc->tx.buf.ptr, src, n - m);
1218 if (m != 0) {
1219 memcpy(lvcc->tx.buf.start, src + n - m, m);
1220 e = ((unsigned char *) lvcc->tx.buf.start) + m;
1221 }
1222 lvcc->tx.buf.ptr = (u32 *) e;
1223}
1224
1225static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n)
1226{
1227 unsigned char *e;
1228 int m;
1229 if (n == 0)
1230 return;
1231 e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1232 m = e - (unsigned char *) lvcc->tx.buf.end;
1233 if (m < 0)
1234 m = 0;
1235 memset(lvcc->tx.buf.ptr, 0, n - m);
1236 if (m != 0) {
1237 memset(lvcc->tx.buf.start, 0, m);
1238 e = ((unsigned char *) lvcc->tx.buf.start) + m;
1239 }
1240 lvcc->tx.buf.ptr = (u32 *) e;
1241}
1242
1243/* Update "butt" register to specify new WritePtr */
1244static inline void lanai_endtx(struct lanai_dev *lanai,
1245 const struct lanai_vcc *lvcc)
1246{
1247 int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) -
1248 (unsigned char *) lvcc->tx.buf.start;
1249 APRINTK((ptr & ~0x0001FFF0) == 0,
1250 "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n",
1251 ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr,
1252 lvcc->tx.buf.end);
1253
1254 /*
1255 * Since the "butt register" is a shared resounce on the card we
1256 * serialize all accesses to it through this spinlock. This is
1257 * mostly just paranoia sicne the register is rarely "busy" anyway
1258 * but is needed for correctness.
1259 */
1260 spin_lock(&lanai->endtxlock);
1261 /*
1262 * We need to check if the "butt busy" bit is set before
1263 * updating the butt register. In theory this should
1264 * never happen because the ATM card is plenty fast at
1265 * updating the register. Still, we should make sure
1266 */
1267 for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
1268 if (unlikely(i > 50)) {
1269 printk(KERN_ERR DEV_LABEL "(itf %d): butt register "
1270 "always busy!\n", lanai->number);
1271 break;
1272 }
1273 udelay(5);
1274 }
1275 /*
1276 * Before we tall the card to start work we need to be sure 100% of
1277 * the info in the service buffer has been written before we tell
1278 * the card about it
1279 */
1280 wmb();
1281 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
1282 spin_unlock(&lanai->endtxlock);
1283}
1284
1285/*
1286 * Add one AAL5 PDU to lvcc's transmit buffer. Caller garauntees there's
1287 * space available. "pdusize" is the number of bytes the PDU will take
1288 */
1289static void lanai_send_one_aal5(struct lanai_dev *lanai,
1290 struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize)
1291{
1292 int pad;
1293 APRINTK(pdusize == aal5_size(skb->len),
1294 "lanai_send_one_aal5: wrong size packet (%d != %d)\n",
1295 pdusize, aal5_size(skb->len));
1296 vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize);
1297 pad = pdusize - skb->len - 8;
1298 APRINTK(pad >= 0, "pad is negative (%d)\n", pad);
1299 APRINTK(pad < 48, "pad is too big (%d)\n", pad);
1300 vcc_tx_memcpy(lvcc, skb->data, skb->len);
1301 vcc_tx_memzero(lvcc, pad);
1302 vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0);
1303 lanai_endtx(lanai, lvcc);
1304 lanai_free_skb(lvcc->tx.atmvcc, skb);
1305 atomic_inc(&lvcc->tx.atmvcc->stats->tx);
1306}
1307
1308/* Try to fill the buffer - don't call unless there is backlog */
1309static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
1310 struct lanai_vcc *lvcc, int endptr)
1311{
1312 int n;
1313 struct sk_buff *skb;
1314 int space = vcc_tx_space(lvcc, endptr);
1315 APRINTK(vcc_is_backlogged(lvcc),
1316 "vcc_tx_unqueue() called with empty backlog (vci=%d)\n",
1317 lvcc->vci);
1318 while (space >= 64) {
1319 skb = skb_dequeue(&lvcc->tx.backlog);
1320 if (skb == NULL)
1321 goto no_backlog;
1322 n = aal5_size(skb->len);
1323 if (n + 16 > space) {
1324 /* No room for this packet - put it back on queue */
1325 skb_queue_head(&lvcc->tx.backlog, skb);
1326 return;
1327 }
1328 lanai_send_one_aal5(lanai, lvcc, skb, n);
1329 space -= n + 16;
1330 }
1331 if (!vcc_is_backlogged(lvcc)) {
1332 no_backlog:
1333 __clear_bit(lvcc->vci, lanai->backlog_vccs);
1334 }
1335}
1336
1337/* Given an skb that we want to transmit either send it now or queue */
1338static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1339 struct sk_buff *skb)
1340{
1341 int space, n;
1342 if (vcc_is_backlogged(lvcc)) /* Already backlogged */
1343 goto queue_it;
1344 space = vcc_tx_space(lvcc,
1345 TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)));
1346 n = aal5_size(skb->len);
1347 APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n);
1348 if (space < n + 16) { /* No space for this PDU */
1349 __set_bit(lvcc->vci, lanai->backlog_vccs);
1350 queue_it:
1351 skb_queue_tail(&lvcc->tx.backlog, skb);
1352 return;
1353 }
1354 lanai_send_one_aal5(lanai, lvcc, skb, n);
1355}
1356
1357static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
1358 struct lanai_vcc *lvcc, int endptr)
1359{
1360 printk(KERN_INFO DEV_LABEL
1361 ": vcc_tx_unqueue_aal0: not implemented\n");
1362}
1363
1364static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1365 struct sk_buff *skb)
1366{
1367 printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n");
1368 /* Remember to increment lvcc->tx.atmvcc->stats->tx */
1369 lanai_free_skb(lvcc->tx.atmvcc, skb);
1370}
1371
1372/* -------------------- VCC RX BUFFER UTILITIES: */
1373
1374/* unlike the _tx_ cousins, this doesn't update ptr */
1375static inline void vcc_rx_memcpy(unsigned char *dest,
1376 const struct lanai_vcc *lvcc, int n)
1377{
1378 int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n -
1379 ((const unsigned char *) (lvcc->rx.buf.end));
1380 if (m < 0)
1381 m = 0;
1382 memcpy(dest, lvcc->rx.buf.ptr, n - m);
1383 memcpy(dest + n - m, lvcc->rx.buf.start, m);
1384 /* Make sure that these copies don't get reordered */
1385 barrier();
1386}
1387
1388/* Receive AAL5 data on a VCC with a particular endptr */
1389static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr)
1390{
1391 int size;
1392 struct sk_buff *skb;
c22c28f6
MBJ		 1393 const u32 *x;
1394 u32 *end = &lvcc->rx.buf.start[endptr * 4];
1da177e4
LT		 1395 int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr);
1396 if (n < 0)
1397 n += lanai_buf_size(&lvcc->rx.buf);
1398 APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15),
1399 "vcc_rx_aal5: n out of range (%d/%Zu)\n",
1400 n, lanai_buf_size(&lvcc->rx.buf));
1401 /* Recover the second-to-last word to get true pdu length */
1402 if ((x = &end[-2]) < lvcc->rx.buf.start)
1403 x = &lvcc->rx.buf.end[-2];
1404 /*
1405 * Before we actually read from the buffer, make sure the memory
1406 * changes have arrived
1407 */
1408 rmb();
1409 size = be32_to_cpup(x) & 0xffff;
1410 if (unlikely(n != aal5_size(size))) {
1411 /* Make sure size matches padding */
1412 printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length "
1413 "on vci=%d - size=%d n=%d\n",
1414 lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n);
1415 lvcc->stats.x.aal5.rx_badlen++;
1416 goto out;
1417 }
1418 skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC);
1419 if (unlikely(skb == NULL)) {
1420 lvcc->stats.rx_nomem++;
1421 goto out;
1422 }
1423 skb_put(skb, size);
1424 vcc_rx_memcpy(skb->data, lvcc, size);
1425 ATM_SKB(skb)->vcc = lvcc->rx.atmvcc;
a61bbcf2 1426 __net_timestamp(skb);
1da177e4
LT		 1427 lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb);
1428 atomic_inc(&lvcc->rx.atmvcc->stats->rx);
1429 out:
1430 lvcc->rx.buf.ptr = end;
1431 cardvcc_write(lvcc, endptr, vcc_rxreadptr);
1432}
1433
1434static void vcc_rx_aal0(struct lanai_dev *lanai)
1435{
1436 printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n");
1437 /* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */
1438 /* Remember to increment lvcc->rx.atmvcc->stats->rx */
1439}
1440
1441/* -------------------- MANAGING HOST-BASED VCC TABLE: */
1442
1443/* Decide whether to use vmalloc or get_zeroed_page for VCC table */
1444#if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE
1445#define VCCTABLE_GETFREEPAGE
1446#else
1447#include <linux/vmalloc.h>
1448#endif
1449
1450static int __devinit vcc_table_allocate(struct lanai_dev *lanai)
1451{
1452#ifdef VCCTABLE_GETFREEPAGE
1453 APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
1454 "vcc table > PAGE_SIZE!");
1455 lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);
1456 return (lanai->vccs == NULL) ? -ENOMEM : 0;
1457#else
1458 int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
1459 lanai->vccs = (struct lanai_vcc **) vmalloc(bytes);
1460 if (unlikely(lanai->vccs == NULL))
1461 return -ENOMEM;
1462 memset(lanai->vccs, 0, bytes);
1463 return 0;
1464#endif
1465}
1466
1467static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
1468{
1469#ifdef VCCTABLE_GETFREEPAGE
1470 free_page((unsigned long) lanai->vccs);
1471#else
1472 vfree(lanai->vccs);
1473#endif
1474}
1475
1476/* Allocate a fresh lanai_vcc, with the appropriate things cleared */
1477static inline struct lanai_vcc *new_lanai_vcc(void)
1478{
1479 struct lanai_vcc *lvcc;
0c1cca1d 1480 lvcc = kzalloc(sizeof(*lvcc), GFP_KERNEL);
1da177e4 1481 if (likely(lvcc != NULL)) {
1da177e4
LT		 1482 skb_queue_head_init(&lvcc->tx.backlog);
1483#ifdef DEBUG
1da177e4
LT		 1484 lvcc->vci = -1;
1485#endif
1486 }
1487 return lvcc;
1488}
1489
1490static int lanai_get_sized_buffer(struct lanai_dev *lanai,
1491 struct lanai_buffer *buf, int max_sdu, int multiplier,
1492 const char *name)
1493{
1494 int size;
1495 if (unlikely(max_sdu < 1))
1496 max_sdu = 1;
1497 max_sdu = aal5_size(max_sdu);
1498 size = (max_sdu + 16) * multiplier + 16;
1499 lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);
1500 if (unlikely(buf->start == NULL))
1501 return -ENOMEM;
1502 if (unlikely(lanai_buf_size(buf) < size))
1503 printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes "
1504 "for %s buffer, got only %Zu\n", lanai->number, size,
1505 name, lanai_buf_size(buf));
1506 DPRINTK("Allocated %Zu byte %s buffer\n", lanai_buf_size(buf), name);
1507 return 0;
1508}
1509
1510/* Setup a RX buffer for a currently unbound AAL5 vci */
1511static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,
1512 struct lanai_vcc *lvcc, const struct atm_qos *qos)
1513{
1514 return lanai_get_sized_buffer(lanai, &lvcc->rx.buf,
1515 qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX");
1516}
1517
1518/* Setup a TX buffer for a currently unbound AAL5 vci */
1519static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1520 const struct atm_qos *qos)
1521{
1522 int max_sdu, multiplier;
1523 if (qos->aal == ATM_AAL0) {
1524 lvcc->tx.unqueue = vcc_tx_unqueue_aal0;
1525 max_sdu = ATM_CELL_SIZE - 1;
1526 multiplier = AAL0_TX_MULTIPLIER;
1527 } else {
1528 lvcc->tx.unqueue = vcc_tx_unqueue_aal5;
1529 max_sdu = qos->txtp.max_sdu;
1530 multiplier = AAL5_TX_MULTIPLIER;
1531 }
1532 return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,
1533 multiplier, "TX");
1534}
1535
1536static inline void host_vcc_bind(struct lanai_dev *lanai,
1537 struct lanai_vcc *lvcc, vci_t vci)
1538{
1539 if (lvcc->vbase != NULL)
1540 return; /* We already were bound in the other direction */
1541 DPRINTK("Binding vci %d\n", vci);
1542#ifdef USE_POWERDOWN
1543 if (lanai->nbound++ == 0) {
1544 DPRINTK("Coming out of powerdown\n");
1545 lanai->conf1 &= ~CONFIG1_POWERDOWN;
1546 conf1_write(lanai);
1547 conf2_write(lanai);
1548 }
1549#endif
1550 lvcc->vbase = cardvcc_addr(lanai, vci);
1551 lanai->vccs[lvcc->vci = vci] = lvcc;
1552}
1553
1554static inline void host_vcc_unbind(struct lanai_dev *lanai,
1555 struct lanai_vcc *lvcc)
1556{
1557 if (lvcc->vbase == NULL)
1558 return; /* This vcc was never bound */
1559 DPRINTK("Unbinding vci %d\n", lvcc->vci);
1560 lvcc->vbase = NULL;
1561 lanai->vccs[lvcc->vci] = NULL;
1562#ifdef USE_POWERDOWN
1563 if (--lanai->nbound == 0) {
1564 DPRINTK("Going into powerdown\n");
1565 lanai->conf1 |= CONFIG1_POWERDOWN;
1566 conf1_write(lanai);
1567 }
1568#endif
1569}
1570
1571/* -------------------- RESET CARD: */
1572
1573static void lanai_reset(struct lanai_dev *lanai)
1574{
1575 printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* reseting - not "
1576 "implemented\n", lanai->number);
1577 /* TODO */
1578 /* The following is just a hack until we write the real
1579 * resetter - at least ack whatever interrupt sent us
1580 * here
1581 */
1582 reg_write(lanai, INT_ALL, IntAck_Reg);
1583 lanai->stats.card_reset++;
1584}
1585
1586/* -------------------- SERVICE LIST UTILITIES: */
1587
1588/*
1589 * Allocate service buffer and tell card about it
1590 */
1591static int __devinit service_buffer_allocate(struct lanai_dev *lanai)
1592{
1593 lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,
1594 lanai->pci);
1595 if (unlikely(lanai->service.start == NULL))
1596 return -ENOMEM;
1597 DPRINTK("allocated service buffer at 0x%08lX, size %Zu(%d)\n",
1598 (unsigned long) lanai->service.start,
1599 lanai_buf_size(&lanai->service),
1600 lanai_buf_size_cardorder(&lanai->service));
1601 /* Clear ServWrite register to be safe */
1602 reg_write(lanai, 0, ServWrite_Reg);
1603 /* ServiceStuff register contains size and address of buffer */
1604 reg_write(lanai,
1605 SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
1606 SSTUFF_SET_ADDR(lanai->service.dmaaddr),
1607 ServiceStuff_Reg);
1608 return 0;
1609}
1610
1611static inline void service_buffer_deallocate(struct lanai_dev *lanai)
1612{
1613 lanai_buf_deallocate(&lanai->service, lanai->pci);
1614}
1615
1616/* Bitfields in service list */
1617#define SERVICE_TX (0x80000000) /* Was from transmission */
1618#define SERVICE_TRASH (0x40000000) /* RXed PDU was trashed */
1619#define SERVICE_CRCERR (0x20000000) /* RXed PDU had CRC error */
1620#define SERVICE_CI (0x10000000) /* RXed PDU had CI set */
1621#define SERVICE_CLP (0x08000000) /* RXed PDU had CLP set */
1622#define SERVICE_STREAM (0x04000000) /* RX Stream mode */
1623#define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF)
1624#define SERVICE_GET_END(x) ((x)&0x1FFF)
1625
1626/* Handle one thing from the service list - returns true if it marked a
1627 * VCC ready for xmit
1628 */
1629static int handle_service(struct lanai_dev *lanai, u32 s)
1630{
1631 vci_t vci = SERVICE_GET_VCI(s);
1632 struct lanai_vcc *lvcc;
1633 read_lock(&vcc_sklist_lock);
1634 lvcc = lanai->vccs[vci];
1635 if (unlikely(lvcc == NULL)) {
1636 read_unlock(&vcc_sklist_lock);
1637 DPRINTK("(itf %d) got service entry 0x%X for nonexistent "
1638 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1639 if (s & SERVICE_TX)
1640 lanai->stats.service_notx++;
1641 else
1642 lanai->stats.service_norx++;
1643 return 0;
1644 }
1645 if (s & SERVICE_TX) { /* segmentation interrupt */
1646 if (unlikely(lvcc->tx.atmvcc == NULL)) {
1647 read_unlock(&vcc_sklist_lock);
1648 DPRINTK("(itf %d) got service entry 0x%X for non-TX "
1649 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1650 lanai->stats.service_notx++;
1651 return 0;
1652 }
1653 __set_bit(vci, lanai->transmit_ready);
1654 lvcc->tx.endptr = SERVICE_GET_END(s);
1655 read_unlock(&vcc_sklist_lock);
1656 return 1;
1657 }
1658 if (unlikely(lvcc->rx.atmvcc == NULL)) {
1659 read_unlock(&vcc_sklist_lock);
1660 DPRINTK("(itf %d) got service entry 0x%X for non-RX "
1661 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1662 lanai->stats.service_norx++;
1663 return 0;
1664 }
1665 if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) {
1666 read_unlock(&vcc_sklist_lock);
1667 DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 "
1668 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1669 lanai->stats.service_rxnotaal5++;
1670 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1671 return 0;
1672 }
1673 if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) {
1674 vcc_rx_aal5(lvcc, SERVICE_GET_END(s));
1675 read_unlock(&vcc_sklist_lock);
1676 return 0;
1677 }
1678 if (s & SERVICE_TRASH) {
1679 int bytes;
1680 read_unlock(&vcc_sklist_lock);
1681 DPRINTK("got trashed rx pdu on vci %d\n", vci);
1682 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1683 lvcc->stats.x.aal5.service_trash++;
1684 bytes = (SERVICE_GET_END(s) * 16) -
1685 (((unsigned long) lvcc->rx.buf.ptr) -
1686 ((unsigned long) lvcc->rx.buf.start)) + 47;
1687 if (bytes < 0)
1688 bytes += lanai_buf_size(&lvcc->rx.buf);
1689 lanai->stats.ovfl_trash += (bytes / 48);
1690 return 0;
1691 }
1692 if (s & SERVICE_STREAM) {
1693 read_unlock(&vcc_sklist_lock);
1694 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1695 lvcc->stats.x.aal5.service_stream++;
1696 printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream "
1697 "PDU on VCI %d!\n", lanai->number, vci);
1698 lanai_reset(lanai);
1699 return 0;
1700 }
1701 DPRINTK("got rx crc error on vci %d\n", vci);
1702 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1703 lvcc->stats.x.aal5.service_rxcrc++;
1704 lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4];
1705 cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr);
1706 read_unlock(&vcc_sklist_lock);
1707 return 0;
1708}
1709
1710/* Try transmitting on all VCIs that we marked ready to serve */
1711static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
1712{
1713 struct lanai_vcc *lvcc = lanai->vccs[vci];
1714 if (vcc_is_backlogged(lvcc))
1715 lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
1716}
1717
1718/* Run service queue -- called from interrupt context or with
1719 * interrupts otherwise disabled and with the lanai->servicelock
1720 * lock held
1721 */
1722static void run_service(struct lanai_dev *lanai)
1723{
1724 int ntx = 0;
1725 u32 wreg = reg_read(lanai, ServWrite_Reg);
1726 const u32 *end = lanai->service.start + wreg;
1727 while (lanai->service.ptr != end) {
1728 ntx += handle_service(lanai,
1729 le32_to_cpup(lanai->service.ptr++));
1730 if (lanai->service.ptr >= lanai->service.end)
1731 lanai->service.ptr = lanai->service.start;
1732 }
1733 reg_write(lanai, wreg, ServRead_Reg);
1734 if (ntx != 0) {
1735 read_lock(&vcc_sklist_lock);
1736 vci_bitfield_iterate(lanai, lanai->transmit_ready,
1737 iter_transmit);
1738 bitmap_zero(lanai->transmit_ready, NUM_VCI);
1739 read_unlock(&vcc_sklist_lock);
1740 }
1741}
1742
1743/* -------------------- GATHER STATISTICS: */
1744
1745static void get_statistics(struct lanai_dev *lanai)
1746{
1747 u32 statreg = reg_read(lanai, Statistics_Reg);
1748 lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
1749 lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
1750 lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
1751 lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
1752}
1753
1754/* -------------------- POLLING TIMER: */
1755
1756#ifndef DEBUG_RW
1757/* Try to undequeue 1 backlogged vcc */
1758static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
1759{
1760 struct lanai_vcc *lvcc = lanai->vccs[vci];
1761 int endptr;
1762 if (lvcc == NULL || lvcc->tx.atmvcc == NULL ||
1763 !vcc_is_backlogged(lvcc)) {
1764 __clear_bit(vci, lanai->backlog_vccs);
1765 return;
1766 }
1767 endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
1768 lvcc->tx.unqueue(lanai, lvcc, endptr);
1769}
1770#endif /* !DEBUG_RW */
1771
1772static void lanai_timed_poll(unsigned long arg)
1773{
1774 struct lanai_dev *lanai = (struct lanai_dev *) arg;
1775#ifndef DEBUG_RW
1776 unsigned long flags;
1777#ifdef USE_POWERDOWN
1778 if (lanai->conf1 & CONFIG1_POWERDOWN)
1779 return;
1780#endif /* USE_POWERDOWN */
1781 local_irq_save(flags);
1782 /* If we can grab the spinlock, check if any services need to be run */
1783 if (spin_trylock(&lanai->servicelock)) {
1784 run_service(lanai);
1785 spin_unlock(&lanai->servicelock);
1786 }
1787 /* ...and see if any backlogged VCs can make progress */
1788 /* unfortunately linux has no read_trylock() currently */
1789 read_lock(&vcc_sklist_lock);
1790 vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);
1791 read_unlock(&vcc_sklist_lock);
1792 local_irq_restore(flags);
1793
1794 get_statistics(lanai);
1795#endif /* !DEBUG_RW */
1796 mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
1797}
1798
1799static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
1800{
1801 init_timer(&lanai->timer);
1802 lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
1803 lanai->timer.data = (unsigned long) lanai;
1804 lanai->timer.function = lanai_timed_poll;
1805 add_timer(&lanai->timer);
1806}
1807
1808static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
1809{
1810 del_timer_sync(&lanai->timer);
1811}
1812
1813/* -------------------- INTERRUPT SERVICE: */
1814
1815static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
1816{
1817 u32 ack = 0;
1818 if (reason & INT_SERVICE) {
1819 ack = INT_SERVICE;
1820 spin_lock(&lanai->servicelock);
1821 run_service(lanai);
1822 spin_unlock(&lanai->servicelock);
1823 }
1824 if (reason & (INT_AAL0_STR | INT_AAL0)) {
1825 ack |= reason & (INT_AAL0_STR | INT_AAL0);
1826 vcc_rx_aal0(lanai);
1827 }
1828 /* The rest of the interrupts are pretty rare */
1829 if (ack == reason)
1830 goto done;
1831 if (reason & INT_STATS) {
1832 reason &= ~INT_STATS; /* No need to ack */
1833 get_statistics(lanai);
1834 }
1835 if (reason & INT_STATUS) {
1836 ack |= reason & INT_STATUS;
1837 lanai_check_status(lanai);
1838 }
1839 if (unlikely(reason & INT_DMASHUT)) {
1840 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA "
1841 "shutdown, reason=0x%08X, address=0x%08X\n",
1842 lanai->number, (unsigned int) (reason & INT_DMASHUT),
1843 (unsigned int) reg_read(lanai, DMA_Addr_Reg));
1844 if (reason & INT_TABORTBM) {
1845 lanai_reset(lanai);
1846 return;
1847 }
1848 ack |= (reason & INT_DMASHUT);
1849 printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n",
1850 lanai->number);
1851 conf1_write(lanai);
1852 lanai->stats.dma_reenable++;
1853 pcistatus_check(lanai, 0);
1854 }
1855 if (unlikely(reason & INT_TABORTSENT)) {
1856 ack |= (reason & INT_TABORTSENT);
1857 printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n",
1858 lanai->number);
1859 pcistatus_check(lanai, 0);
1860 }
1861 if (unlikely(reason & INT_SEGSHUT)) {
1862 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1863 "segmentation shutdown, reason=0x%08X\n", lanai->number,
1864 (unsigned int) (reason & INT_SEGSHUT));
1865 lanai_reset(lanai);
1866 return;
1867 }
1868 if (unlikely(reason & (INT_PING | INT_WAKE))) {
1869 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1870 "unexpected interrupt 0x%08X, resetting\n",
1871 lanai->number,
1872 (unsigned int) (reason & (INT_PING | INT_WAKE)));
1873 lanai_reset(lanai);
1874 return;
1875 }
1876#ifdef DEBUG
1877 if (unlikely(ack != reason)) {
1878 DPRINTK("unacked ints: 0x%08X\n",
1879 (unsigned int) (reason & ~ack));
1880 ack = reason;
1881 }
1882#endif
1883 done:
1884 if (ack != 0)
1885 reg_write(lanai, ack, IntAck_Reg);
1886}
1887
7d12e780 1888static irqreturn_t lanai_int(int irq, void *devid)
1da177e4 1889{
c7bec5ab 1890 struct lanai_dev *lanai = devid;
1da177e4
LT		 1891 u32 reason;
1892
1da177e4
LT		 1893#ifdef USE_POWERDOWN
1894 /*
1895 * If we're powered down we shouldn't be generating any interrupts -
1896 * so assume that this is a shared interrupt line and it's for someone
1897 * else
1898 */
1899 if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))
1900 return IRQ_NONE;
1901#endif
1902
1903 reason = intr_pending(lanai);
1904 if (reason == 0)
1905 return IRQ_NONE; /* Must be for someone else */
1906
1907 do {
1908 if (unlikely(reason == 0xFFFFFFFF))
1909 break; /* Maybe we've been unplugged? */
1910 lanai_int_1(lanai, reason);
1911 reason = intr_pending(lanai);
1912 } while (reason != 0);
1913
1914 return IRQ_HANDLED;
1915}
1916
1917/* TODO - it would be nice if we could use the "delayed interrupt" system
1918 * to some advantage
1919 */
1920
1921/* -------------------- CHECK BOARD ID/REV: */
1922
1923/*
1924 * The board id and revision are stored both in the reset register and
1925 * in the PCI configuration space - the documentation says to check
1926 * each of them. If revp!=NULL we store the revision there
1927 */
1928static int check_board_id_and_rev(const char *name, u32 val, int *revp)
1929{
1930 DPRINTK("%s says board_id=%d, board_rev=%d\n", name,
1931 (int) RESET_GET_BOARD_ID(val),
1932 (int) RESET_GET_BOARD_REV(val));
1933 if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) {
1934 printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a "
1935 "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val));
1936 return -ENODEV;
1937 }
1938 if (revp != NULL)
1939 *revp = RESET_GET_BOARD_REV(val);
1940 return 0;
1941}
1942
1943/* -------------------- PCI INITIALIZATION/SHUTDOWN: */
1944
1945static int __devinit lanai_pci_start(struct lanai_dev *lanai)
1946{
1947 struct pci_dev *pci = lanai->pci;
1948 int result;
1949 u16 w;
1950
1951 if (pci_enable_device(pci) != 0) {
1952 printk(KERN_ERR DEV_LABEL "(itf %d): can't enable "
1953 "PCI device", lanai->number);
1954 return -ENXIO;
1955 }
1956 pci_set_master(pci);
284901a9 1957 if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) != 0) {
1da177e4
LT		 1958 printk(KERN_WARNING DEV_LABEL
1959 "(itf %d): No suitable DMA available.\n", lanai->number);
1960 return -EBUSY;
1961 }
284901a9 1962 if (pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)) != 0) {
1da177e4
LT		 1963 printk(KERN_WARNING DEV_LABEL
1964 "(itf %d): No suitable DMA available.\n", lanai->number);
1965 return -EBUSY;
1966 }
1da177e4
LT		 1967 result = pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &w);
1968 if (result != PCIBIOS_SUCCESSFUL) {
1969 printk(KERN_ERR DEV_LABEL "(itf %d): can't read "
1970 "PCI_SUBSYSTEM_ID: %d\n", lanai->number, result);
1971 return -EINVAL;
1972 }
1973 result = check_board_id_and_rev("PCI", w, NULL);
1974 if (result != 0)
1975 return result;
1976 /* Set latency timer to zero as per lanai docs */
1977 result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0);
1978 if (result != PCIBIOS_SUCCESSFUL) {
1979 printk(KERN_ERR DEV_LABEL "(itf %d): can't write "
1980 "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
1981 return -EINVAL;
1982 }
1983 pcistatus_check(lanai, 1);
1984 pcistatus_check(lanai, 0);
1985 return 0;
1986}
1987
1988/* -------------------- VPI/VCI ALLOCATION: */
1989
1990/*
1991 * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll
1992 * get a CBRZERO interrupt), and we can use it only if noone is receiving
1993 * AAL0 traffic (since they will use the same queue) - according to the
1994 * docs we shouldn't even use it for AAL0 traffic
1995 */
1996static inline int vci0_is_ok(struct lanai_dev *lanai,
1997 const struct atm_qos *qos)
1998{
1999 if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0)
2000 return 0;
2001 if (qos->rxtp.traffic_class != ATM_NONE) {
2002 if (lanai->naal0 != 0)
2003 return 0;
2004 lanai->conf2 |= CONFIG2_VCI0_NORMAL;
2005 conf2_write_if_powerup(lanai);
2006 }
2007 return 1;
2008}
2009
2010/* return true if vci is currently unused, or if requested qos is
2011 * compatible
2012 */
2013static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
2014 const struct atm_vcc *atmvcc)
2015{
2016 const struct atm_qos *qos = &atmvcc->qos;
2017 const struct lanai_vcc *lvcc = lanai->vccs[vci];
2018 if (vci == 0 && !vci0_is_ok(lanai, qos))
2019 return 0;
2020 if (unlikely(lvcc != NULL)) {
2021 if (qos->rxtp.traffic_class != ATM_NONE &&
2022 lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc)
2023 return 0;
2024 if (qos->txtp.traffic_class != ATM_NONE &&
2025 lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc)
2026 return 0;
2027 if (qos->txtp.traffic_class == ATM_CBR &&
2028 lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
2029 return 0;
2030 }
2031 if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
2032 qos->rxtp.traffic_class != ATM_NONE) {
2033 const struct lanai_vcc *vci0 = lanai->vccs[0];
2034 if (vci0 != NULL && vci0->rx.atmvcc != NULL)
2035 return 0;
2036 lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
2037 conf2_write_if_powerup(lanai);
2038 }
2039 return 1;
2040}
2041
2042static int lanai_normalize_ci(struct lanai_dev *lanai,
2043 const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip)
2044{
2045 switch (*vpip) {
2046 case ATM_VPI_ANY:
2047 *vpip = 0;
2048 /* FALLTHROUGH */
2049 case 0:
2050 break;
2051 default:
2052 return -EADDRINUSE;
2053 }
2054 switch (*vcip) {
2055 case ATM_VCI_ANY:
2056 for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
2057 (*vcip)++)
2058 if (vci_is_ok(lanai, *vcip, atmvcc))
2059 return 0;
2060 return -EADDRINUSE;
2061 default:
2062 if (*vcip >= lanai->num_vci || *vcip < 0 ||
2063 !vci_is_ok(lanai, *vcip, atmvcc))
2064 return -EADDRINUSE;
2065 }
2066 return 0;
2067}
2068
2069/* -------------------- MANAGE CBR: */
2070
2071/*
2072 * CBR ICG is stored as a fixed-point number with 4 fractional bits.
2073 * Note that storing a number greater than 2046.0 will result in
2074 * incorrect shaping
2075 */
2076#define CBRICG_FRAC_BITS (4)
2077#define CBRICG_MAX (2046 << CBRICG_FRAC_BITS)
2078
2079/*
2080 * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1)
2081 * where MAXPCR is (according to the docs) 25600000/(54*8),
2082 * which is equal to (3125<<9)/27.
2083 *
2084 * Solving for ICG, we get:
2085 * ICG = MAXPCR/PCR - 1
2086 * ICG = (3125<<9)/(27*PCR) - 1
2087 * ICG = ((3125<<9) - (27*PCR)) / (27*PCR)
2088 *
2089 * The end result is supposed to be a fixed-point number with FRAC_BITS
2090 * bits of a fractional part, so we keep everything in the numerator
2091 * shifted by that much as we compute
2092 *
2093 */
c22c28f6 2094static int pcr_to_cbricg(const struct atm_qos *qos)
1da177e4
LT		 2095{
2096 int rounddown = 0; /* 1 = Round PCR down, i.e. round ICG _up_ */
2097 int x, icg, pcr = atm_pcr_goal(&qos->txtp);
2098 if (pcr == 0) /* Use maximum bandwidth */
2099 return 0;
2100 if (pcr < 0) {
2101 rounddown = 1;
2102 pcr = -pcr;
2103 }
2104 x = pcr * 27;
2105 icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS);
2106 if (rounddown)
2107 icg += x - 1;
2108 icg /= x;
2109 if (icg > CBRICG_MAX)
2110 icg = CBRICG_MAX;
2111 DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n",
2112 pcr, rounddown ? 'Y' : 'N', icg);
2113 return icg;
2114}
2115
2116static inline void lanai_cbr_setup(struct lanai_dev *lanai)
2117{
2118 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
2119 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
2120 lanai->conf2 |= CONFIG2_CBR_ENABLE;
2121 conf2_write(lanai);
2122}
2123
2124static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
2125{
2126 lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
2127 conf2_write(lanai);
2128}
2129
2130/* -------------------- OPERATIONS: */
2131
2132/* setup a newly detected device */
2133static int __devinit lanai_dev_open(struct atm_dev *atmdev)
2134{
2135 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2136 unsigned long raw_base;
2137 int result;
2138
2139 DPRINTK("In lanai_dev_open()\n");
2140 /* Basic device fields */
2141 lanai->number = atmdev->number;
2142 lanai->num_vci = NUM_VCI;
2143 bitmap_zero(lanai->backlog_vccs, NUM_VCI);
2144 bitmap_zero(lanai->transmit_ready, NUM_VCI);
2145 lanai->naal0 = 0;
2146#ifdef USE_POWERDOWN
2147 lanai->nbound = 0;
2148#endif
2149 lanai->cbrvcc = NULL;
2150 memset(&lanai->stats, 0, sizeof lanai->stats);
2151 spin_lock_init(&lanai->endtxlock);
2152 spin_lock_init(&lanai->servicelock);
2153 atmdev->ci_range.vpi_bits = 0;
2154 atmdev->ci_range.vci_bits = 0;
2155 while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
2156 atmdev->ci_range.vci_bits++;
2157 atmdev->link_rate = ATM_25_PCR;
2158
2159 /* 3.2: PCI initialization */
2160 if ((result = lanai_pci_start(lanai)) != 0)
2161 goto error;
2162 raw_base = lanai->pci->resource[0].start;
2163 lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
2164 if (lanai->base == NULL) {
2165 printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n");
2166 goto error_pci;
2167 }
2168 /* 3.3: Reset lanai and PHY */
2169 reset_board(lanai);
2170 lanai->conf1 = reg_read(lanai, Config1_Reg);
2171 lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
2172 CONFIG1_MASK_LEDMODE);
2173 lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
2174 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2175 udelay(1000);
2176 conf1_write(lanai);
2177
2178 /*
2179 * 3.4: Turn on endian mode for big-endian hardware
2180 * We don't actually want to do this - the actual bit fields
2181 * in the endian register are not documented anywhere.
2182 * Instead we do the bit-flipping ourselves on big-endian
2183 * hardware.
2184 *
2185 * 3.5: get the board ID/rev by reading the reset register
2186 */
2187 result = check_board_id_and_rev("register",
2188 reg_read(lanai, Reset_Reg), &lanai->board_rev);
2189 if (result != 0)
2190 goto error_unmap;
2191
2192 /* 3.6: read EEPROM */
2193 if ((result = eeprom_read(lanai)) != 0)
2194 goto error_unmap;
2195 if ((result = eeprom_validate(lanai)) != 0)
2196 goto error_unmap;
2197
2198 /* 3.7: re-reset PHY, do loopback tests, setup PHY */
2199 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2200 udelay(1000);
2201 conf1_write(lanai);
2202 /* TODO - loopback tests */
2203 lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
2204 conf1_write(lanai);
2205
2206 /* 3.8/3.9: test and initialize card SRAM */
2207 if ((result = sram_test_and_clear(lanai)) != 0)
2208 goto error_unmap;
2209
2210 /* 3.10: initialize lanai registers */
2211 lanai->conf1 |= CONFIG1_DMA_ENABLE;
2212 conf1_write(lanai);
2213 if ((result = service_buffer_allocate(lanai)) != 0)
2214 goto error_unmap;
2215 if ((result = vcc_table_allocate(lanai)) != 0)
2216 goto error_service;
2217 lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
2218 CONFIG2_HEC_DROP | /* ??? */ CONFIG2_PTI7_MODE;
2219 conf2_write(lanai);
2220 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
2221 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */
dace1453 2222 if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,
1da177e4
LT		 2223 DEV_LABEL, lanai)) != 0) {
2224 printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n");
2225 goto error_vcctable;
2226 }
2227 mb(); /* Make sure that all that made it */
2228 intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
2229 /* 3.11: initialize loop mode (i.e. turn looping off) */
2230 lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
2231 CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) |
2232 CONFIG1_GPOUT2 | CONFIG1_GPOUT3;
2233 conf1_write(lanai);
2234 lanai->status = reg_read(lanai, Status_Reg);
2235 /* We're now done initializing this card */
2236#ifdef USE_POWERDOWN
2237 lanai->conf1 |= CONFIG1_POWERDOWN;
2238 conf1_write(lanai);
2239#endif
2240 memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
2241 lanai_timed_poll_start(lanai);
2242 printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u "
2243 "(%02X-%02X-%02X-%02X-%02X-%02X)\n", lanai->number,
44c10138 2244 (int) lanai->pci->revision, (unsigned long) lanai->base,
1da177e4
LT		 2245 lanai->pci->irq,
2246 atmdev->esi[0], atmdev->esi[1], atmdev->esi[2],
2247 atmdev->esi[3], atmdev->esi[4], atmdev->esi[5]);
2248 printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%u(0x%X), "
2249 "board_rev=%d\n", lanai->number,
2250 lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno,
2251 (unsigned int) lanai->serialno, lanai->board_rev);
2252 return 0;
2253
2254 error_vcctable:
2255 vcc_table_deallocate(lanai);
2256 error_service:
2257 service_buffer_deallocate(lanai);
2258 error_unmap:
2259 reset_board(lanai);
2260#ifdef USE_POWERDOWN
2261 lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
2262 conf1_write(lanai);
2263#endif
2264 iounmap(lanai->base);
2265 error_pci:
2266 pci_disable_device(lanai->pci);
2267 error:
2268 return result;
2269}
2270
2271/* called when device is being shutdown, and all vcc's are gone - higher
2272 * levels will deallocate the atm device for us
2273 */
2274static void lanai_dev_close(struct atm_dev *atmdev)
2275{
2276 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2277 printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n",
2278 lanai->number);
2279 lanai_timed_poll_stop(lanai);
2280#ifdef USE_POWERDOWN
2281 lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
2282 conf1_write(lanai);
2283#endif
2284 intr_disable(lanai, INT_ALL);
2285 free_irq(lanai->pci->irq, lanai);
2286 reset_board(lanai);
2287#ifdef USE_POWERDOWN
2288 lanai->conf1 |= CONFIG1_POWERDOWN;
2289 conf1_write(lanai);
2290#endif
2291 pci_disable_device(lanai->pci);
2292 vcc_table_deallocate(lanai);
2293 service_buffer_deallocate(lanai);
2294 iounmap(lanai->base);
2295 kfree(lanai);
2296}
2297
2298/* close a vcc */
2299static void lanai_close(struct atm_vcc *atmvcc)
2300{
2301 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2302 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2303 if (lvcc == NULL)
2304 return;
2305 clear_bit(ATM_VF_READY, &atmvcc->flags);
2306 clear_bit(ATM_VF_PARTIAL, &atmvcc->flags);
2307 if (lvcc->rx.atmvcc == atmvcc) {
2308 lanai_shutdown_rx_vci(lvcc);
2309 if (atmvcc->qos.aal == ATM_AAL0) {
2310 if (--lanai->naal0 <= 0)
2311 aal0_buffer_free(lanai);
2312 } else
2313 lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);
2314 lvcc->rx.atmvcc = NULL;
2315 }
2316 if (lvcc->tx.atmvcc == atmvcc) {
2317 if (atmvcc == lanai->cbrvcc) {
2318 if (lvcc->vbase != NULL)
2319 lanai_cbr_shutdown(lanai);
2320 lanai->cbrvcc = NULL;
2321 }
2322 lanai_shutdown_tx_vci(lanai, lvcc);
2323 lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);
2324 lvcc->tx.atmvcc = NULL;
2325 }
2326 if (--lvcc->nref == 0) {
2327 host_vcc_unbind(lanai, lvcc);
2328 kfree(lvcc);
2329 }
2330 atmvcc->dev_data = NULL;
2331 clear_bit(ATM_VF_ADDR, &atmvcc->flags);
2332}
2333
2334/* open a vcc on the card to vpi/vci */
2335static int lanai_open(struct atm_vcc *atmvcc)
2336{
2337 struct lanai_dev *lanai;
2338 struct lanai_vcc *lvcc;
2339 int result = 0;
2340 int vci = atmvcc->vci;
2341 short vpi = atmvcc->vpi;
2342 /* we don't support partial open - it's not really useful anyway */
2343 if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) ||
2344 (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC))
2345 return -EINVAL;
2346 lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2347 result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);
2348 if (unlikely(result != 0))
2349 goto out;
2350 set_bit(ATM_VF_ADDR, &atmvcc->flags);
2351 if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5)
2352 return -EINVAL;
2353 DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number,
2354 (int) vpi, vci);
2355 lvcc = lanai->vccs[vci];
2356 if (lvcc == NULL) {
2357 lvcc = new_lanai_vcc();
2358 if (unlikely(lvcc == NULL))
2359 return -ENOMEM;
2360 atmvcc->dev_data = lvcc;
2361 }
2362 lvcc->nref++;
2363 if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) {
2364 APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n",
2365 vci);
2366 if (atmvcc->qos.aal == ATM_AAL0) {
2367 if (lanai->naal0 == 0)
2368 result = aal0_buffer_allocate(lanai);
2369 } else
2370 result = lanai_setup_rx_vci_aal5(
2371 lanai, lvcc, &atmvcc->qos);
2372 if (unlikely(result != 0))
2373 goto out_free;
2374 lvcc->rx.atmvcc = atmvcc;
2375 lvcc->stats.rx_nomem = 0;
2376 lvcc->stats.x.aal5.rx_badlen = 0;
2377 lvcc->stats.x.aal5.service_trash = 0;
2378 lvcc->stats.x.aal5.service_stream = 0;
2379 lvcc->stats.x.aal5.service_rxcrc = 0;
2380 if (atmvcc->qos.aal == ATM_AAL0)
2381 lanai->naal0++;
2382 }
2383 if (atmvcc->qos.txtp.traffic_class != ATM_NONE) {
2384 APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n",
2385 vci);
2386 result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);
2387 if (unlikely(result != 0))
2388 goto out_free;
2389 lvcc->tx.atmvcc = atmvcc;
2390 if (atmvcc->qos.txtp.traffic_class == ATM_CBR) {
2391 APRINTK(lanai->cbrvcc == NULL,
2392 "cbrvcc!=NULL, vci=%d\n", vci);
2393 lanai->cbrvcc = atmvcc;
2394 }
2395 }
2396 host_vcc_bind(lanai, lvcc, vci);
2397 /*
2398 * Make sure everything made it to RAM before we tell the card about
2399 * the VCC
2400 */
2401 wmb();
2402 if (atmvcc == lvcc->rx.atmvcc)
2403 host_vcc_start_rx(lvcc);
2404 if (atmvcc == lvcc->tx.atmvcc) {
2405 host_vcc_start_tx(lvcc);
2406 if (lanai->cbrvcc == atmvcc)
2407 lanai_cbr_setup(lanai);
2408 }
2409 set_bit(ATM_VF_READY, &atmvcc->flags);
2410 return 0;
2411 out_free:
2412 lanai_close(atmvcc);
2413 out:
2414 return result;
2415}
2416
1da177e4
LT		 2417static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb)
2418{
2419 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2420 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2421 unsigned long flags;
2422 if (unlikely(lvcc == NULL || lvcc->vbase == NULL ||
2423 lvcc->tx.atmvcc != atmvcc))
2424 goto einval;
2425#ifdef DEBUG
2426 if (unlikely(skb == NULL)) {
2427 DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci);
2428 goto einval;
2429 }
2430 if (unlikely(lanai == NULL)) {
2431 DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
2432 goto einval;
2433 }
2434#endif
2435 ATM_SKB(skb)->vcc = atmvcc;
2436 switch (atmvcc->qos.aal) {
2437 case ATM_AAL5:
2438 read_lock_irqsave(&vcc_sklist_lock, flags);
2439 vcc_tx_aal5(lanai, lvcc, skb);
2440 read_unlock_irqrestore(&vcc_sklist_lock, flags);
2441 return 0;
2442 case ATM_AAL0:
2443 if (unlikely(skb->len != ATM_CELL_SIZE-1))
2444 goto einval;
2445 /* NOTE - this next line is technically invalid - we haven't unshared skb */
2446 cpu_to_be32s((u32 *) skb->data);
2447 read_lock_irqsave(&vcc_sklist_lock, flags);
2448 vcc_tx_aal0(lanai, lvcc, skb);
2449 read_unlock_irqrestore(&vcc_sklist_lock, flags);
2450 return 0;
2451 }
2452 DPRINTK("lanai_send: bad aal=%d on vci=%d\n", (int) atmvcc->qos.aal,
2453 atmvcc->vci);
2454 einval:
2455 lanai_free_skb(atmvcc, skb);
2456 return -EINVAL;
2457}
2458
2459static int lanai_change_qos(struct atm_vcc *atmvcc,
2460 /*const*/ struct atm_qos *qos, int flags)
2461{
2462 return -EBUSY; /* TODO: need to write this */
2463}
2464
2465#ifndef CONFIG_PROC_FS
2466#define lanai_proc_read NULL
2467#else
2468static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)
2469{
2470 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2471 loff_t left = *pos;
2472 struct lanai_vcc *lvcc;
2473 if (left-- == 0)
2474 return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, "
2475 "serial=%u, magic=0x%08X, num_vci=%d\n",
2476 atmdev->number, lanai->type==lanai2 ? "2" : "HB",
2477 (unsigned int) lanai->serialno,
2478 (unsigned int) lanai->magicno, lanai->num_vci);
2479 if (left-- == 0)
2480 return sprintf(page, "revision: board=%d, pci_if=%d\n",
44c10138 2481 lanai->board_rev, (int) lanai->pci->revision);
1da177e4 2482 if (left-- == 0)
8d9ded23 2483 return sprintf(page, "EEPROM ESI: %pM\n",
2484 &lanai->eeprom[EEPROM_MAC]);
1da177e4
LT		 2485 if (left-- == 0)
2486 return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, "
2487 "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
2488 (lanai->status & STATUS_LOCD) ? 1 : 0,
2489 (lanai->status & STATUS_LED) ? 1 : 0,
2490 (lanai->status & STATUS_GPIN) ? 1 : 0);
2491 if (left-- == 0)
2492 return sprintf(page, "global buffer sizes: service=%Zu, "
2493 "aal0_rx=%Zu\n", lanai_buf_size(&lanai->service),
2494 lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
2495 if (left-- == 0) {
2496 get_statistics(lanai);
2497 return sprintf(page, "cells in error: overflow=%u, "
2498 "closed_vci=%u, bad_HEC=%u, rx_fifo=%u\n",
2499 lanai->stats.ovfl_trash, lanai->stats.vci_trash,
2500 lanai->stats.hec_err, lanai->stats.atm_ovfl);
2501 }
2502 if (left-- == 0)
2503 return sprintf(page, "PCI errors: parity_detect=%u, "
2504 "master_abort=%u, master_target_abort=%u,\n",
2505 lanai->stats.pcierr_parity_detect,
2506 lanai->stats.pcierr_serr_set,
2507 lanai->stats.pcierr_m_target_abort);
2508 if (left-- == 0)
2509 return sprintf(page, " slave_target_abort=%u, "
2510 "master_parity=%u\n", lanai->stats.pcierr_s_target_abort,
2511 lanai->stats.pcierr_master_parity);
2512 if (left-- == 0)
2513 return sprintf(page, " no_tx=%u, "
2514 "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx,
2515 lanai->stats.service_notx,
2516 lanai->stats.service_rxnotaal5);
2517 if (left-- == 0)
2518 return sprintf(page, "resets: dma=%u, card=%u\n",
2519 lanai->stats.dma_reenable, lanai->stats.card_reset);
2520 /* At this point, "left" should be the VCI we're looking for */
2521 read_lock(&vcc_sklist_lock);
2522 for (; ; left++) {
2523 if (left >= NUM_VCI) {
2524 left = 0;
2525 goto out;
2526 }
2527 if ((lvcc = lanai->vccs[left]) != NULL)
2528 break;
2529 (*pos)++;
2530 }
2531 /* Note that we re-use "left" here since we're done with it */
2532 left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%u", (vci_t) left,
2533 lvcc->nref, lvcc->stats.rx_nomem);
2534 if (lvcc->rx.atmvcc != NULL) {
2535 left += sprintf(&page[left], ",\n rx_AAL=%d",
2536 lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0);
2537 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5)
2538 left += sprintf(&page[left], ", rx_buf_size=%Zu, "
2539 "rx_bad_len=%u,\n rx_service_trash=%u, "
2540 "rx_service_stream=%u, rx_bad_crc=%u",
2541 lanai_buf_size(&lvcc->rx.buf),
2542 lvcc->stats.x.aal5.rx_badlen,
2543 lvcc->stats.x.aal5.service_trash,
2544 lvcc->stats.x.aal5.service_stream,
2545 lvcc->stats.x.aal5.service_rxcrc);
2546 }
2547 if (lvcc->tx.atmvcc != NULL)
2548 left += sprintf(&page[left], ",\n tx_AAL=%d, "
2549 "tx_buf_size=%Zu, tx_qos=%cBR, tx_backlogged=%c",
2550 lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0,
2551 lanai_buf_size(&lvcc->tx.buf),
2552 lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
2553 vcc_is_backlogged(lvcc) ? 'Y' : 'N');
2554 page[left++] = '\n';
2555 page[left] = '\0';
2556 out:
2557 read_unlock(&vcc_sklist_lock);
2558 return left;
2559}
2560#endif /* CONFIG_PROC_FS */
2561
2562/* -------------------- HOOKS: */
2563
2564static const struct atmdev_ops ops = {
2565 .dev_close = lanai_dev_close,
2566 .open = lanai_open,
2567 .close = lanai_close,
1da177e4
LT		 2568 .getsockopt = NULL,
2569 .setsockopt = NULL,
2570 .send = lanai_send,
2571 .phy_put = NULL,
2572 .phy_get = NULL,
2573 .change_qos = lanai_change_qos,
2574 .proc_read = lanai_proc_read,
2575 .owner = THIS_MODULE
2576};
2577
2578/* initialize one probed card */
2579static int __devinit lanai_init_one(struct pci_dev *pci,
2580 const struct pci_device_id *ident)
2581{
2582 struct lanai_dev *lanai;
2583 struct atm_dev *atmdev;
2584 int result;
2585
5cbded58 2586 lanai = kmalloc(sizeof(*lanai), GFP_KERNEL);
1da177e4
LT		 2587 if (lanai == NULL) {
2588 printk(KERN_ERR DEV_LABEL
2589 ": couldn't allocate dev_data structure!\n");
2590 return -ENOMEM;
2591 }
2592
2593 atmdev = atm_dev_register(DEV_LABEL, &ops, -1, NULL);
2594 if (atmdev == NULL) {
2595 printk(KERN_ERR DEV_LABEL
2596 ": couldn't register atm device!\n");
2597 kfree(lanai);
2598 return -EBUSY;
2599 }
2600
2601 atmdev->dev_data = lanai;
2602 lanai->pci = pci;
2603 lanai->type = (enum lanai_type) ident->device;
2604
2605 result = lanai_dev_open(atmdev);
2606 if (result != 0) {
2607 DPRINTK("lanai_start() failed, err=%d\n", -result);
2608 atm_dev_deregister(atmdev);
2609 kfree(lanai);
2610 }
2611 return result;
2612}
2613
2614static struct pci_device_id lanai_pci_tbl[] = {
1d0ed384
JS		 2615 { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) },
2616 { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) },
1da177e4
LT		 2617 { 0, } /* terminal entry */
2618};
2619MODULE_DEVICE_TABLE(pci, lanai_pci_tbl);
2620
2621static struct pci_driver lanai_driver = {
2622 .name = DEV_LABEL,
2623 .id_table = lanai_pci_tbl,
2624 .probe = lanai_init_one,
2625};
2626
2627static int __init lanai_module_init(void)
2628{
2629 int x;
2630
2631 x = pci_register_driver(&lanai_driver);
2632 if (x != 0)
2633 printk(KERN_ERR DEV_LABEL ": no adapter found\n");
2634 return x;
2635}
2636
2637static void __exit lanai_module_exit(void)
2638{
2639 /* We'll only get called when all the interfaces are already
2640 * gone, so there isn't much to do
2641 */
2642 DPRINTK("cleanup_module()\n");
fd22f1e0 2643 pci_unregister_driver(&lanai_driver);
1da177e4
LT		 2644}
2645
2646module_init(lanai_module_init);
2647module_exit(lanai_module_exit);
2648
2649MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>");
2650MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver");
2651MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)