[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / sata_vsc.c

/*
 *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
 *
 *  Maintained by:  Jeremy Higdon @ SGI
 * 		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 SGI
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Vitesse hardware documentation presumably available under NDA.
 *  Intel 31244 (same hardware interface) documentation presumably
 *  available from http://developer.intel.com/
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_vsc"
#define DRV_VERSION	"2.3"

enum {
	VSC_MMIO_BAR			= 0,

	/* Interrupt register offsets (from chip base address) */
	VSC_SATA_INT_STAT_OFFSET	= 0x00,
	VSC_SATA_INT_MASK_OFFSET	= 0x04,

	/* Taskfile registers offsets */
	VSC_SATA_TF_CMD_OFFSET		= 0x00,
	VSC_SATA_TF_DATA_OFFSET		= 0x00,
	VSC_SATA_TF_ERROR_OFFSET	= 0x04,
	VSC_SATA_TF_FEATURE_OFFSET	= 0x06,
	VSC_SATA_TF_NSECT_OFFSET	= 0x08,
	VSC_SATA_TF_LBAL_OFFSET		= 0x0c,
	VSC_SATA_TF_LBAM_OFFSET		= 0x10,
	VSC_SATA_TF_LBAH_OFFSET		= 0x14,
	VSC_SATA_TF_DEVICE_OFFSET	= 0x18,
	VSC_SATA_TF_STATUS_OFFSET	= 0x1c,
	VSC_SATA_TF_COMMAND_OFFSET	= 0x1d,
	VSC_SATA_TF_ALTSTATUS_OFFSET	= 0x28,
	VSC_SATA_TF_CTL_OFFSET		= 0x29,

	/* DMA base */
	VSC_SATA_UP_DESCRIPTOR_OFFSET	= 0x64,
	VSC_SATA_UP_DATA_BUFFER_OFFSET	= 0x6C,
	VSC_SATA_DMA_CMD_OFFSET		= 0x70,

	/* SCRs base */
	VSC_SATA_SCR_STATUS_OFFSET	= 0x100,
	VSC_SATA_SCR_ERROR_OFFSET	= 0x104,
	VSC_SATA_SCR_CONTROL_OFFSET	= 0x108,

	/* Port stride */
	VSC_SATA_PORT_OFFSET		= 0x200,

	/* Error interrupt status bit offsets */
	VSC_SATA_INT_ERROR_CRC		= 0x40,
	VSC_SATA_INT_ERROR_T		= 0x20,
	VSC_SATA_INT_ERROR_P		= 0x10,
	VSC_SATA_INT_ERROR_R		= 0x8,
	VSC_SATA_INT_ERROR_E		= 0x4,
	VSC_SATA_INT_ERROR_M		= 0x2,
	VSC_SATA_INT_PHY_CHANGE		= 0x1,
	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
			      VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
			      VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
			      VSC_SATA_INT_PHY_CHANGE),
};

static int vsc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int vsc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static void vsc_freeze(struct ata_port *ap)
{
	void __iomem *mask_addr;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;

	writeb(0, mask_addr);
}


static void vsc_thaw(struct ata_port *ap)
{
	void __iomem *mask_addr;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;

	writeb(0xff, mask_addr);
}


static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
{
	void __iomem *mask_addr;
	u8 mask;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	mask = readb(mask_addr);
	if (ctl & ATA_NIEN)
		mask |= 0x80;
	else
		mask &= 0x7F;
	writeb(mask, mask_addr);
}


static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	/*
	 * The only thing the ctl register is used for is SRST.
	 * That is not enabled or disabled via tf_load.
	 * However, if ATA_NIEN is changed, then we need to change the interrupt register.
	 */
	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
		ap->last_ctl = tf->ctl;
		vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = ata_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
        }
}

static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
{
	if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
		ata_port_freeze(ap);
	else
		ata_port_abort(ap);
}

static void vsc_port_intr(u8 port_status, struct ata_port *ap)
{
	struct ata_queued_cmd *qc;
	int handled = 0;

	if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
		vsc_error_intr(port_status, ap);
		return;
	}

	qc = ata_qc_from_tag(ap, ap->link.active_tag);
	if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
		handled = ata_host_intr(ap, qc);

	/* We received an interrupt during a polled command,
	 * or some other spurious condition.  Interrupt reporting
	 * with this hardware is fairly reliable so it is safe to
	 * simply clear the interrupt
	 */
	if (unlikely(!handled))
		ata_chk_status(ap);
}

/*
 * vsc_sata_interrupt
 *
 * Read the interrupt register and process for the devices that have them pending.
 */
static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	unsigned int i;
	unsigned int handled = 0;
	u32 status;

	status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);

	if (unlikely(status == 0xffffffff || status == 0)) {
		if (status)
			dev_printk(KERN_ERR, host->dev,
				": IRQ status == 0xffffffff, "
				"PCI fault or device removal?\n");
		goto out;
	}

	spin_lock(&host->lock);

	for (i = 0; i < host->n_ports; i++) {
		u8 port_status = (status >> (8 * i)) & 0xff;
		if (port_status) {
			struct ata_port *ap = host->ports[i];

			if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
				vsc_port_intr(port_status, ap);
				handled++;
			} else
				dev_printk(KERN_ERR, host->dev,
					": interrupt from disabled port %d\n", i);
		}
	}

	spin_unlock(&host->lock);
out:
	return IRQ_RETVAL(handled);
}


static struct scsi_host_template vsc_sata_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};


static const struct ata_port_operations vsc_sata_ops = {
	.tf_load		= vsc_sata_tf_load,
	.tf_read		= vsc_sata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,
	.freeze			= vsc_freeze,
	.thaw			= vsc_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.scr_read		= vsc_sata_scr_read,
	.scr_write		= vsc_sata_scr_write,
	.port_start		= ata_port_start,
};

static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
					  void __iomem *base)
{
	port->cmd_addr		= base + VSC_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + VSC_SATA_TF_DATA_OFFSET;
	port->error_addr	= base + VSC_SATA_TF_ERROR_OFFSET;
	port->feature_addr	= base + VSC_SATA_TF_FEATURE_OFFSET;
	port->nsect_addr	= base + VSC_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + VSC_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + VSC_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + VSC_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + VSC_SATA_TF_DEVICE_OFFSET;
	port->status_addr	= base + VSC_SATA_TF_STATUS_OFFSET;
	port->command_addr	= base + VSC_SATA_TF_COMMAND_OFFSET;
	port->altstatus_addr	= base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	port->ctl_addr		= base + VSC_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + VSC_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + VSC_SATA_SCR_STATUS_OFFSET;
	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
}


static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static const struct ata_port_info pi = {
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,
		.mwdma_mask	= 0x07,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &vsc_sata_ops,
	};
	const struct ata_port_info *ppi[] = { &pi, NULL };
	static int printed_version;
	struct ata_host *host;
	void __iomem *mmio_base;
	int i, rc;
	u8 cls;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	/* allocate host */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
	if (!host)
		return -ENOMEM;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* check if we have needed resource mapped */
	if (pci_resource_len(pdev, 0) == 0)
		return -ENODEV;

	/* map IO regions and intialize host accordingly */
	rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);

	mmio_base = host->iomap[VSC_MMIO_BAR];

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;

		vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
		ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
	}

	/*
	 * Use 32 bit DMA mask, because 64 bit address support is poor.
	 */
	rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
	if (rc)
		return rc;

	/*
	 * Due to a bug in the chip, the default cache line size can't be
	 * used (unless the default is non-zero).
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
	if (cls == 0x00)
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);

	if (pci_enable_msi(pdev) == 0)
		pci_intx(pdev, 0);

	/*
	 * Config offset 0x98 is "Extended Control and Status Register 0"
	 * Default value is (1 << 28).  All bits except bit 28 are reserved in
	 * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
	 * If bit 28 is clear, each port has its own LED.
	 */
	pci_write_config_dword(pdev, 0x98, 0);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
				 IRQF_SHARED, &vsc_sata_sht);
}

static const struct pci_device_id vsc_sata_pci_tbl[] = {
	{ PCI_VENDOR_ID_VITESSE, 0x7174,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
	{ PCI_VENDOR_ID_INTEL, 0x3200,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },

	{ }	/* terminate list */
};

static struct pci_driver vsc_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= vsc_sata_pci_tbl,
	.probe			= vsc_sata_init_one,
	.remove			= ata_pci_remove_one,
};

static int __init vsc_sata_init(void)
{
	return pci_register_driver(&vsc_sata_pci_driver);
}

static void __exit vsc_sata_exit(void)
{
	pci_unregister_driver(&vsc_sata_pci_driver);
}

MODULE_AUTHOR("Jeremy Higdon");
MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(vsc_sata_init);
module_exit(vsc_sata_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
	3	*
	4	* Maintained by: Jeremy Higdon @ SGI
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 SGI
	9	*
	10	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	11	*
af36d7f0 JG	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2, or (at your option)
	16	* any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; see the file COPYING. If not, write to
	25	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	26	*
	27	*
	28	* libata documentation is available via 'make {ps\|pdf}docs',
	29	* as Documentation/DocBook/libata.*
	30	*
	31	* Vitesse hardware documentation presumably available under NDA.
	32	* Intel 31244 (same hardware interface) documentation presumably
	33	* available from http://developer.intel.com/
	34	*
1da177e4 LT	35	*/
	36
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
	40	#include <linux/init.h>
	41	#include <linux/blkdev.h>
	42	#include <linux/delay.h>
	43	#include <linux/interrupt.h>
7003c05d	44	#include <linux/dma-mapping.h>
a9524a76	45	#include <linux/device.h>
1da177e4 LT	46	#include <scsi/scsi_host.h>
	47	#include <linux/libata.h>
	48
	49	#define DRV_NAME "sata_vsc"
2a3103ce	50	#define DRV_VERSION "2.3"
1da177e4	51
55cca65e	52	enum {
0d5ff566 TH	53	VSC_MMIO_BAR = 0,
0d5ff566 TH	54
55cca65e JG	55	/* Interrupt register offsets (from chip base address) */
	56	VSC_SATA_INT_STAT_OFFSET = 0x00,
	57	VSC_SATA_INT_MASK_OFFSET = 0x04,
1da177e4	58
55cca65e JG	59	/* Taskfile registers offsets */
	60	VSC_SATA_TF_CMD_OFFSET = 0x00,
	61	VSC_SATA_TF_DATA_OFFSET = 0x00,
	62	VSC_SATA_TF_ERROR_OFFSET = 0x04,
	63	VSC_SATA_TF_FEATURE_OFFSET = 0x06,
	64	VSC_SATA_TF_NSECT_OFFSET = 0x08,
	65	VSC_SATA_TF_LBAL_OFFSET = 0x0c,
	66	VSC_SATA_TF_LBAM_OFFSET = 0x10,
	67	VSC_SATA_TF_LBAH_OFFSET = 0x14,
	68	VSC_SATA_TF_DEVICE_OFFSET = 0x18,
	69	VSC_SATA_TF_STATUS_OFFSET = 0x1c,
	70	VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
	71	VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
	72	VSC_SATA_TF_CTL_OFFSET = 0x29,
1da177e4	73
55cca65e JG	74	/* DMA base */
	75	VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
	76	VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
	77	VSC_SATA_DMA_CMD_OFFSET = 0x70,
1da177e4	78
55cca65e JG	79	/* SCRs base */
	80	VSC_SATA_SCR_STATUS_OFFSET = 0x100,
	81	VSC_SATA_SCR_ERROR_OFFSET = 0x104,
	82	VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
1da177e4	83
55cca65e JG	84	/* Port stride */
	85	VSC_SATA_PORT_OFFSET = 0x200,
	86
	87	/* Error interrupt status bit offsets */
	88	VSC_SATA_INT_ERROR_CRC = 0x40,
	89	VSC_SATA_INT_ERROR_T = 0x20,
	90	VSC_SATA_INT_ERROR_P = 0x10,
	91	VSC_SATA_INT_ERROR_R = 0x8,
	92	VSC_SATA_INT_ERROR_E = 0x4,
	93	VSC_SATA_INT_ERROR_M = 0x2,
	94	VSC_SATA_INT_PHY_CHANGE = 0x1,
	95	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC \| VSC_SATA_INT_ERROR_T \| \
	96	VSC_SATA_INT_ERROR_P \| VSC_SATA_INT_ERROR_R \| \
	97	VSC_SATA_INT_ERROR_E \| VSC_SATA_INT_ERROR_M \| \
	98	VSC_SATA_INT_PHY_CHANGE),
7cbaa86b	99	};
c962990a	100
da3dbb17	101	static int vsc_sata_scr_read(struct ata_port ap, unsigned int sc_reg, u32 val)
1da177e4 LT	102	{
1da177e4 LT	103	if (sc_reg > SCR_CONTROL)
da3dbb17 TH	104	return -EINVAL;
	105	val = readl(ap->ioaddr.scr_addr + (sc_reg 4));
	106	return 0;
1da177e4 LT	107	}
	108
	109
da3dbb17	110	static int vsc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4 LT	111	{
1da177e4 LT	112	if (sc_reg > SCR_CONTROL)
da3dbb17	113	return -EINVAL;
0d5ff566	114	writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	115	return 0;
1da177e4 LT	116	}
	117
	118
ea34e45a DW	119	static void vsc_freeze(struct ata_port *ap)
	120	{
	121	void __iomem *mask_addr;
	122
	123	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
	124	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	125
	126	writeb(0, mask_addr);
	127	}
	128
	129
	130	static void vsc_thaw(struct ata_port *ap)
	131	{
	132	void __iomem *mask_addr;
	133
	134	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
	135	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	136
	137	writeb(0xff, mask_addr);
	138	}
	139
	140
1da177e4 LT	141	static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
1da177e4 LT	142	{
307e4dc2	143	void __iomem *mask_addr;
1da177e4 LT	144	u8 mask;
1da177e4 LT	145
0d5ff566	146	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
1da177e4 LT	147	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	148	mask = readb(mask_addr);
	149	if (ctl & ATA_NIEN)
	150	mask \|= 0x80;
	151	else
	152	mask &= 0x7F;
	153	writeb(mask, mask_addr);
	154	}
	155
	156
057ace5e	157	static void vsc_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	158	{
	159	struct ata_ioports *ioaddr = &ap->ioaddr;
	160	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	161
	162	/*
	163	* The only thing the ctl register is used for is SRST.
	164	* That is not enabled or disabled via tf_load.
	165	* However, if ATA_NIEN is changed, then we need to change the interrupt register.
	166	*/
	167	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
	168	ap->last_ctl = tf->ctl;
	169	vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	170	}
	171	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	172	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	173	ioaddr->feature_addr);
850a9d8a	174	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	175	ioaddr->nsect_addr);
850a9d8a	176	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	177	ioaddr->lbal_addr);
850a9d8a	178	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	179	ioaddr->lbam_addr);
850a9d8a	180	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	181	ioaddr->lbah_addr);
1da177e4	182	} else if (is_addr) {
0d5ff566 TH	183	writew(tf->feature, ioaddr->feature_addr);
	184	writew(tf->nsect, ioaddr->nsect_addr);
	185	writew(tf->lbal, ioaddr->lbal_addr);
	186	writew(tf->lbam, ioaddr->lbam_addr);
	187	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	188	}
	189
	190	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	191	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	192
	193	ata_wait_idle(ap);
	194	}
	195
	196
	197	static void vsc_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	198	{
	199	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	200	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	201
ac19bff2	202	tf->command = ata_check_status(ap);
0d5ff566 TH	203	tf->device = readw(ioaddr->device_addr);
	204	feature = readw(ioaddr->error_addr);
	205	nsect = readw(ioaddr->nsect_addr);
	206	lbal = readw(ioaddr->lbal_addr);
	207	lbam = readw(ioaddr->lbam_addr);
	208	lbah = readw(ioaddr->lbah_addr);
ac19bff2 JG	209
	210	tf->feature = feature;
	211	tf->nsect = nsect;
	212	tf->lbal = lbal;
	213	tf->lbam = lbam;
	214	tf->lbah = lbah;
1da177e4 LT	215
1da177e4 LT	216	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	217	tf->hob_feature = feature >> 8;
1da177e4 LT	218	tf->hob_nsect = nsect >> 8;
	219	tf->hob_lbal = lbal >> 8;
	220	tf->hob_lbam = lbam >> 8;
	221	tf->hob_lbah = lbah >> 8;
	222	}
	223	}
	224
ea34e45a DW	225	static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
	226	{
	227	if (port_status & (VSC_SATA_INT_PHY_CHANGE \| VSC_SATA_INT_ERROR_M))
	228	ata_port_freeze(ap);
	229	else
	230	ata_port_abort(ap);
	231	}
	232
	233	static void vsc_port_intr(u8 port_status, struct ata_port *ap)
	234	{
	235	struct ata_queued_cmd *qc;
	236	int handled = 0;
	237
	238	if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
	239	vsc_error_intr(port_status, ap);
	240	return;
	241	}
	242
9af5c9c9	243	qc = ata_qc_from_tag(ap, ap->link.active_tag);
ea34e45a DW	244	if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
	245	handled = ata_host_intr(ap, qc);
	246
	247	/* We received an interrupt during a polled command,
	248	* or some other spurious condition. Interrupt reporting
	249	* with this hardware is fairly reliable so it is safe to
	250	* simply clear the interrupt
	251	*/
	252	if (unlikely(!handled))
	253	ata_chk_status(ap);
	254	}
1da177e4 LT	255
	256	/*
	257	* vsc_sata_interrupt
	258	*
	259	* Read the interrupt register and process for the devices that have them pending.
	260	*/
7d12e780	261	static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
1da177e4	262	{
cca3974e	263	struct ata_host *host = dev_instance;
1da177e4 LT	264	unsigned int i;
1da177e4 LT	265	unsigned int handled = 0;
ea34e45a	266	u32 status;
1da177e4	267
ea34e45a	268	status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
1da177e4	269
ea34e45a DW	270	if (unlikely(status == 0xffffffff \|\| status == 0)) {
	271	if (status)
	272	dev_printk(KERN_ERR, host->dev,
	273	": IRQ status == 0xffffffff, "
	274	"PCI fault or device removal?\n");
	275	goto out;
	276	}
1da177e4	277
ea34e45a	278	spin_lock(&host->lock);
2ae5b30f	279
ea34e45a DW	280	for (i = 0; i < host->n_ports; i++) {
	281	u8 port_status = (status >> (8 * i)) & 0xff;
	282	if (port_status) {
	283	struct ata_port *ap = host->ports[i];
2ae5b30f	284
029f5468	285	if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
ea34e45a DW	286	vsc_port_intr(port_status, ap);
	287	handled++;
	288	} else
	289	dev_printk(KERN_ERR, host->dev,
	290	": interrupt from disabled port %d\n", i);
1da177e4 LT	291	}
	292	}
	293
cca3974e	294	spin_unlock(&host->lock);
ea34e45a	295	out:
1da177e4 LT	296	return IRQ_RETVAL(handled);
	297	}
	298
	299
193515d5	300	static struct scsi_host_template vsc_sata_sht = {
1da177e4 LT	301	.module = THIS_MODULE,
	302	.name = DRV_NAME,
	303	.ioctl = ata_scsi_ioctl,
	304	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	305	.can_queue = ATA_DEF_QUEUE,
	306	.this_id = ATA_SHT_THIS_ID,
	307	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	308	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	309	.emulated = ATA_SHT_EMULATED,
	310	.use_clustering = ATA_SHT_USE_CLUSTERING,
	311	.proc_name = DRV_NAME,
	312	.dma_boundary = ATA_DMA_BOUNDARY,
	313	.slave_configure = ata_scsi_slave_config,
ccf68c34	314	.slave_destroy = ata_scsi_slave_destroy,
1da177e4	315	.bios_param = ata_std_bios_param,
1da177e4 LT	316	};
	317
	318
057ace5e	319	static const struct ata_port_operations vsc_sata_ops = {
1da177e4 LT	320	.tf_load = vsc_sata_tf_load,
	321	.tf_read = vsc_sata_tf_read,
	322	.exec_command = ata_exec_command,
	323	.check_status = ata_check_status,
	324	.dev_select = ata_std_dev_select,
1da177e4 LT	325	.bmdma_setup = ata_bmdma_setup,
	326	.bmdma_start = ata_bmdma_start,
	327	.bmdma_stop = ata_bmdma_stop,
	328	.bmdma_status = ata_bmdma_status,
	329	.qc_prep = ata_qc_prep,
	330	.qc_issue = ata_qc_issue_prot,
0d5ff566	331	.data_xfer = ata_data_xfer,
ea34e45a DW	332	.freeze = vsc_freeze,
ea34e45a DW	333	.thaw = vsc_thaw,
d7a80dad TH	334	.error_handler = ata_bmdma_error_handler,
d7a80dad TH	335	.post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4	336	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	337	.irq_on = ata_irq_on,
1da177e4 LT	338	.scr_read = vsc_sata_scr_read,
	339	.scr_write = vsc_sata_scr_write,
	340	.port_start = ata_port_start,
1da177e4 LT	341	};
1da177e4 LT	342
0d5ff566 TH	343	static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
0d5ff566 TH	344	void __iomem *base)
1da177e4 LT	345	{
	346	port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
	347	port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
	348	port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
	349	port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
	350	port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
	351	port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
	352	port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
	353	port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
	354	port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
	355	port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
	356	port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
	357	port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	358	port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
	359	port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
	360	port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
0d5ff566 TH	361	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
0d5ff566 TH	362	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
1da177e4 LT	363	}
	364
	365
	366	static int __devinit vsc_sata_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	367	{
4447d351 TH	368	static const struct ata_port_info pi = {
	369	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	370	ATA_FLAG_MMIO,
	371	.pio_mask = 0x1f,
	372	.mwdma_mask = 0x07,
bf6263a8	373	.udma_mask = ATA_UDMA6,
4447d351 TH	374	.port_ops = &vsc_sata_ops,
	375	};
	376	const struct ata_port_info *ppi[] = { &pi, NULL };
1da177e4	377	static int printed_version;
4447d351	378	struct ata_host *host;
307e4dc2	379	void __iomem *mmio_base;
4447d351	380	int i, rc;
7de970e1	381	u8 cls;
1da177e4 LT	382
1da177e4 LT	383	if (!printed_version++)
a9524a76	384	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4	385
4447d351 TH	386	/* allocate host */
	387	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
	388	if (!host)
	389	return -ENOMEM;
	390
24dc5f33	391	rc = pcim_enable_device(pdev);
1da177e4 LT	392	if (rc)
	393	return rc;
	394
4447d351	395	/* check if we have needed resource mapped */
24dc5f33 TH	396	if (pci_resource_len(pdev, 0) == 0)
24dc5f33 TH	397	return -ENODEV;
1da177e4	398
4447d351	399	/* map IO regions and intialize host accordingly */
0d5ff566 TH	400	rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
0d5ff566 TH	401	if (rc == -EBUSY)
24dc5f33	402	pcim_pin_device(pdev);
0d5ff566	403	if (rc)
24dc5f33	404	return rc;
4447d351 TH	405	host->iomap = pcim_iomap_table(pdev);
	406
	407	mmio_base = host->iomap[VSC_MMIO_BAR];
	408
cbcdd875 TH	409	for (i = 0; i < host->n_ports; i++) {
	410	struct ata_port *ap = host->ports[i];
	411	unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;
	412
	413	vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	414
	415	ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
	416	ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
	417	}
1da177e4 LT	418
	419	/*
	420	* Use 32 bit DMA mask, because 64 bit address support is poor.
	421	*/
	422	rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
	423	if (rc)
24dc5f33	424	return rc;
1da177e4 LT	425	rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 LT	426	if (rc)
24dc5f33	427	return rc;
7cbaa86b	428
1da177e4	429	/*
7de970e1 ND	430	* Due to a bug in the chip, the default cache line size can't be
7de970e1 ND	431	* used (unless the default is non-zero).
1da177e4	432	*/
7de970e1 ND	433	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
	434	if (cls == 0x00)
	435	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
1da177e4	436
24dc5f33	437	if (pci_enable_msi(pdev) == 0)
7cbaa86b	438	pci_intx(pdev, 0);
1da177e4	439
8a60a071	440	/*
1da177e4 LT	441	* Config offset 0x98 is "Extended Control and Status Register 0"
	442	* Default value is (1 << 28). All bits except bit 28 are reserved in
	443	* DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
	444	* If bit 28 is clear, each port has its own LED.
	445	*/
	446	pci_write_config_dword(pdev, 0x98, 0);
	447
4447d351 TH	448	pci_set_master(pdev);
	449	return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
	450	IRQF_SHARED, &vsc_sata_sht);
1da177e4 LT	451	}
1da177e4 LT	452
3b7d697d	453	static const struct pci_device_id vsc_sata_pci_tbl[] = {
438bc9c3	454	{ PCI_VENDOR_ID_VITESSE, 0x7174,
74d0a988	455	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
438bc9c3	456	{ PCI_VENDOR_ID_INTEL, 0x3200,
74d0a988	457	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
2d2744fc	458
438bc9c3	459	{ } /* terminate list */
1da177e4 LT	460	};
1da177e4 LT	461
1da177e4 LT	462	static struct pci_driver vsc_sata_pci_driver = {
	463	.name = DRV_NAME,
	464	.id_table = vsc_sata_pci_tbl,
	465	.probe = vsc_sata_init_one,
	466	.remove = ata_pci_remove_one,
	467	};
	468
1da177e4 LT	469	static int __init vsc_sata_init(void)
1da177e4 LT	470	{
b7887196	471	return pci_register_driver(&vsc_sata_pci_driver);
1da177e4 LT	472	}
1da177e4 LT	473
1da177e4 LT	474	static void __exit vsc_sata_exit(void)
	475	{
	476	pci_unregister_driver(&vsc_sata_pci_driver);
	477	}
	478
1da177e4 LT	479	MODULE_AUTHOR("Jeremy Higdon");
	480	MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
	481	MODULE_LICENSE("GPL");
	482	MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
	483	MODULE_VERSION(DRV_VERSION);
	484
	485	module_init(vsc_sata_init);
	486	module_exit(vsc_sata_exit);