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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ericvh...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / sata_sx4.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
af36d7f0
JG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
1da177e4
LT		 30 *
31 */
32
a09060ff
JG		 33/*
34 Theory of operation
35 -------------------
36
37 The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
38 engine, DIMM memory, and four ATA engines (one per SATA port).
39 Data is copied to/from DIMM memory by the HDMA engine, before
40 handing off to one (or more) of the ATA engines. The ATA
41 engines operate solely on DIMM memory.
42
43 The SX4 behaves like a PATA chip, with no SATA controls or
44 knowledge whatsoever, leading to the presumption that
45 PATA<->SATA bridges exist on SX4 boards, external to the
46 PDC20621 chip itself.
47
48 The chip is quite capable, supporting an XOR engine and linked
49 hardware commands (permits a string to transactions to be
50 submitted and waited-on as a single unit), and an optional
51 microprocessor.
52
53 The limiting factor is largely software. This Linux driver was
54 written to multiplex the single HDMA engine to copy disk
55 transactions into a fixed DIMM memory space, from where an ATA
56 engine takes over. As a result, each WRITE looks like this:
57
58 submit HDMA packet to hardware
59 hardware copies data from system memory to DIMM
60 hardware raises interrupt
61
62 submit ATA packet to hardware
63 hardware executes ATA WRITE command, w/ data in DIMM
64 hardware raises interrupt
65
66 and each READ looks like this:
67
68 submit ATA packet to hardware
69 hardware executes ATA READ command, w/ data in DIMM
70 hardware raises interrupt
71
72 submit HDMA packet to hardware
73 hardware copies data from DIMM to system memory
74 hardware raises interrupt
75
76 This is a very slow, lock-step way of doing things that can
77 certainly be improved by motivated kernel hackers.
78
79 */
80
1da177e4
LT		 81#include <linux/kernel.h>
82#include <linux/module.h>
83#include <linux/pci.h>
84#include <linux/init.h>
85#include <linux/blkdev.h>
86#include <linux/delay.h>
87#include <linux/interrupt.h>
a9524a76 88#include <linux/device.h>
1da177e4 89#include <scsi/scsi_host.h>
193515d5 90#include <scsi/scsi_cmnd.h>
1da177e4 91#include <linux/libata.h>
1da177e4
LT		 92#include "sata_promise.h"
93
94#define DRV_NAME "sata_sx4"
2a3103ce 95#define DRV_VERSION "0.12"
1da177e4
LT		 96
97
98enum {
0d5ff566
TH		 99 PDC_MMIO_BAR = 3,
100 PDC_DIMM_BAR = 4,
101
1da177e4
LT		 102 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
103
104 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
105 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
106 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
107 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
108
a09060ff
JG		 109 PDC_CTLSTAT = 0x60, /* IDEn control / status */
110
1da177e4
LT		 111 PDC_20621_SEQCTL = 0x400,
112 PDC_20621_SEQMASK = 0x480,
113 PDC_20621_GENERAL_CTL = 0x484,
114 PDC_20621_PAGE_SIZE = (32 * 1024),
115
116 /* chosen, not constant, values; we design our own DIMM mem map */
117 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
118 PDC_20621_DIMM_BASE = 0x00200000,
119 PDC_20621_DIMM_DATA = (64 * 1024),
120 PDC_DIMM_DATA_STEP = (256 * 1024),
121 PDC_DIMM_WINDOW_STEP = (8 * 1024),
122 PDC_DIMM_HOST_PRD = (6 * 1024),
123 PDC_DIMM_HOST_PKT = (128 * 0),
124 PDC_DIMM_HPKT_PRD = (128 * 1),
125 PDC_DIMM_ATA_PKT = (128 * 2),
126 PDC_DIMM_APKT_PRD = (128 * 3),
127 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
128 PDC_PAGE_WINDOW = 0x40,
129 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
130 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
131 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
132
133 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
134
135 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
136 (1<<23),
137
138 board_20621 = 0, /* FastTrak S150 SX4 */
139
b2d46b61
JG		 140 PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
141 PDC_RESET = (1 << 11), /* HDMA/ATA reset */
a09060ff 142 PDC_DMA_ENABLE = (1 << 7), /* DMA start/stop */
1da177e4
LT		 143
144 PDC_MAX_HDMA = 32,
145 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
146
b2d46b61
JG		 147 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
148 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
149 PDC_I2C_CONTROL = 0x48,
150 PDC_I2C_ADDR_DATA = 0x4C,
151 PDC_DIMM0_CONTROL = 0x80,
152 PDC_DIMM1_CONTROL = 0x84,
153 PDC_SDRAM_CONTROL = 0x88,
154 PDC_I2C_WRITE = 0, /* master -> slave */
155 PDC_I2C_READ = (1 << 6), /* master <- slave */
156 PDC_I2C_START = (1 << 7), /* start I2C proto */
157 PDC_I2C_MASK_INT = (1 << 5), /* mask I2C interrupt */
158 PDC_I2C_COMPLETE = (1 << 16), /* I2C normal compl. */
159 PDC_I2C_NO_ACK = (1 << 20), /* slave no-ack addr */
160 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
161 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
162 PDC_DIMM_SPD_ROW_NUM = 3,
163 PDC_DIMM_SPD_COLUMN_NUM = 4,
164 PDC_DIMM_SPD_MODULE_ROW = 5,
165 PDC_DIMM_SPD_TYPE = 11,
166 PDC_DIMM_SPD_FRESH_RATE = 12,
167 PDC_DIMM_SPD_BANK_NUM = 17,
168 PDC_DIMM_SPD_CAS_LATENCY = 18,
169 PDC_DIMM_SPD_ATTRIBUTE = 21,
170 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
171 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
172 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
173 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
174 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
175 PDC_CTL_STATUS = 0x08,
176 PDC_DIMM_WINDOW_CTLR = 0x0C,
177 PDC_TIME_CONTROL = 0x3C,
178 PDC_TIME_PERIOD = 0x40,
179 PDC_TIME_COUNTER = 0x44,
180 PDC_GENERAL_CTLR = 0x484,
181 PCI_PLL_INIT = 0x8A531824,
182 PCI_X_TCOUNT = 0xEE1E5CFF,
183
184 /* PDC_TIME_CONTROL bits */
185 PDC_TIMER_BUZZER = (1 << 10),
186 PDC_TIMER_MODE_PERIODIC = 0, /* bits 9:8 == 00 */
187 PDC_TIMER_MODE_ONCE = (1 << 8), /* bits 9:8 == 01 */
188 PDC_TIMER_ENABLE = (1 << 7),
189 PDC_TIMER_MASK_INT = (1 << 5),
190 PDC_TIMER_SEQ_MASK = 0x1f, /* SEQ ID for timer */
191 PDC_TIMER_DEFAULT = PDC_TIMER_MODE_ONCE |
192 PDC_TIMER_ENABLE |
193 PDC_TIMER_MASK_INT,
1da177e4
LT		 194};
195
196
197struct pdc_port_priv {
198 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
199 u8 *pkt;
200 dma_addr_t pkt_dma;
201};
202
203struct pdc_host_priv {
1da177e4
LT		 204 unsigned int doing_hdma;
205 unsigned int hdma_prod;
206 unsigned int hdma_cons;
207 struct {
208 struct ata_queued_cmd *qc;
209 unsigned int seq;
210 unsigned long pkt_ofs;
211 } hdma[32];
212};
213
214
215static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
1da177e4
LT		 216static void pdc_eng_timeout(struct ata_port *ap);
217static void pdc_20621_phy_reset (struct ata_port *ap);
218static int pdc_port_start(struct ata_port *ap);
1da177e4 219static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
057ace5e
JG		 220static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
221static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
4447d351
TH		 222static unsigned int pdc20621_dimm_init(struct ata_host *host);
223static int pdc20621_detect_dimm(struct ata_host *host);
224static unsigned int pdc20621_i2c_read(struct ata_host *host,
1da177e4 225 u32 device, u32 subaddr, u32 *pdata);
4447d351
TH		 226static int pdc20621_prog_dimm0(struct ata_host *host);
227static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
1da177e4 228#ifdef ATA_VERBOSE_DEBUG
4447d351 229static void pdc20621_get_from_dimm(struct ata_host *host,
1da177e4
LT		 230 void *psource, u32 offset, u32 size);
231#endif
4447d351 232static void pdc20621_put_to_dimm(struct ata_host *host,
1da177e4
LT		 233 void *psource, u32 offset, u32 size);
234static void pdc20621_irq_clear(struct ata_port *ap);
9a3d9eb0 235static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
1da177e4
LT		 236
237
193515d5 238static struct scsi_host_template pdc_sata_sht = {
1da177e4
LT		 239 .module = THIS_MODULE,
240 .name = DRV_NAME,
241 .ioctl = ata_scsi_ioctl,
242 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 243 .can_queue = ATA_DEF_QUEUE,
244 .this_id = ATA_SHT_THIS_ID,
245 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 246 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
247 .emulated = ATA_SHT_EMULATED,
248 .use_clustering = ATA_SHT_USE_CLUSTERING,
249 .proc_name = DRV_NAME,
250 .dma_boundary = ATA_DMA_BOUNDARY,
251 .slave_configure = ata_scsi_slave_config,
ccf68c34 252 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 253 .bios_param = ata_std_bios_param,
1da177e4
LT		 254};
255
057ace5e 256static const struct ata_port_operations pdc_20621_ops = {
1da177e4
LT		 257 .tf_load = pdc_tf_load_mmio,
258 .tf_read = ata_tf_read,
259 .check_status = ata_check_status,
260 .exec_command = pdc_exec_command_mmio,
261 .dev_select = ata_std_dev_select,
262 .phy_reset = pdc_20621_phy_reset,
263 .qc_prep = pdc20621_qc_prep,
264 .qc_issue = pdc20621_qc_issue_prot,
0d5ff566 265 .data_xfer = ata_data_xfer,
1da177e4 266 .eng_timeout = pdc_eng_timeout,
1da177e4 267 .irq_clear = pdc20621_irq_clear,
246ce3b6 268 .irq_on = ata_irq_on,
1da177e4 269 .port_start = pdc_port_start,
1da177e4
LT		 270};
271
98ac62de 272static const struct ata_port_info pdc_port_info[] = {
1da177e4
LT		 273 /* board_20621 */
274 {
cca3974e 275 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
50630195 276 ATA_FLAG_SRST | ATA_FLAG_MMIO |
1f3461a7 277 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
1da177e4
LT		 278 .pio_mask = 0x1f, /* pio0-4 */
279 .mwdma_mask = 0x07, /* mwdma0-2 */
469248ab 280 .udma_mask = ATA_UDMA6,
1da177e4
LT		 281 .port_ops = &pdc_20621_ops,
282 },
283
284};
285
3b7d697d 286static const struct pci_device_id pdc_sata_pci_tbl[] = {
54bb3a94
JG		 287 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
288
1da177e4
LT		 289 { } /* terminate list */
290};
291
1da177e4
LT		 292static struct pci_driver pdc_sata_pci_driver = {
293 .name = DRV_NAME,
294 .id_table = pdc_sata_pci_tbl,
295 .probe = pdc_sata_init_one,
296 .remove = ata_pci_remove_one,
297};
298
299
1da177e4
LT		 300static int pdc_port_start(struct ata_port *ap)
301{
cca3974e 302 struct device *dev = ap->host->dev;
1da177e4
LT		 303 struct pdc_port_priv *pp;
304 int rc;
305
306 rc = ata_port_start(ap);
307 if (rc)
308 return rc;
309
24dc5f33
TH		 310 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
311 if (!pp)
312 return -ENOMEM;
1da177e4 313
24dc5f33
TH		 314 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
315 if (!pp->pkt)
316 return -ENOMEM;
1da177e4
LT		 317
318 ap->private_data = pp;
319
320 return 0;
1da177e4
LT		 321}
322
1da177e4
LT		 323static void pdc_20621_phy_reset (struct ata_port *ap)
324{
325 VPRINTK("ENTER\n");
326 ap->cbl = ATA_CBL_SATA;
327 ata_port_probe(ap);
328 ata_bus_reset(ap);
329}
330
331static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
332 unsigned int portno,
333 unsigned int total_len)
334{
335 u32 addr;
336 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
337 u32 *buf32 = (u32 *) buf;
338
339 /* output ATA packet S/G table */
340 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
341 (PDC_DIMM_DATA_STEP * portno);
342 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
343 buf32[dw] = cpu_to_le32(addr);
344 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
345
346 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
347 PDC_20621_DIMM_BASE +
348 (PDC_DIMM_WINDOW_STEP * portno) +
349 PDC_DIMM_APKT_PRD,
350 buf32[dw], buf32[dw + 1]);
351}
352
353static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
354 unsigned int portno,
355 unsigned int total_len)
356{
357 u32 addr;
358 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
359 u32 *buf32 = (u32 *) buf;
360
361 /* output Host DMA packet S/G table */
362 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
363 (PDC_DIMM_DATA_STEP * portno);
364
365 buf32[dw] = cpu_to_le32(addr);
366 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
367
368 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
369 PDC_20621_DIMM_BASE +
370 (PDC_DIMM_WINDOW_STEP * portno) +
371 PDC_DIMM_HPKT_PRD,
372 buf32[dw], buf32[dw + 1]);
373}
374
375static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
376 unsigned int devno, u8 *buf,
377 unsigned int portno)
378{
379 unsigned int i, dw;
380 u32 *buf32 = (u32 *) buf;
381 u8 dev_reg;
382
383 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
384 (PDC_DIMM_WINDOW_STEP * portno) +
385 PDC_DIMM_APKT_PRD;
386 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
387
388 i = PDC_DIMM_ATA_PKT;
389
390 /*
391 * Set up ATA packet
392 */
393 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
394 buf[i++] = PDC_PKT_READ;
395 else if (tf->protocol == ATA_PROT_NODATA)
396 buf[i++] = PDC_PKT_NODATA;
397 else
398 buf[i++] = 0;
399 buf[i++] = 0; /* reserved */
400 buf[i++] = portno + 1; /* seq. id */
401 buf[i++] = 0xff; /* delay seq. id */
402
403 /* dimm dma S/G, and next-pkt */
404 dw = i >> 2;
405 if (tf->protocol == ATA_PROT_NODATA)
406 buf32[dw] = 0;
407 else
408 buf32[dw] = cpu_to_le32(dimm_sg);
409 buf32[dw + 1] = 0;
410 i += 8;
411
412 if (devno == 0)
413 dev_reg = ATA_DEVICE_OBS;
414 else
415 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
416
417 /* select device */
418 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
419 buf[i++] = dev_reg;
420
421 /* device control register */
422 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
423 buf[i++] = tf->ctl;
424
425 return i;
426}
427
428static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
429 unsigned int portno)
430{
431 unsigned int dw;
432 u32 tmp, *buf32 = (u32 *) buf;
433
434 unsigned int host_sg = PDC_20621_DIMM_BASE +
435 (PDC_DIMM_WINDOW_STEP * portno) +
436 PDC_DIMM_HOST_PRD;
437 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
438 (PDC_DIMM_WINDOW_STEP * portno) +
439 PDC_DIMM_HPKT_PRD;
440 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
441 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
442
443 dw = PDC_DIMM_HOST_PKT >> 2;
444
445 /*
446 * Set up Host DMA packet
447 */
448 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
449 tmp = PDC_PKT_READ;
450 else
451 tmp = 0;
452 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
453 tmp |= (0xff << 24); /* delay seq. id */
454 buf32[dw + 0] = cpu_to_le32(tmp);
455 buf32[dw + 1] = cpu_to_le32(host_sg);
456 buf32[dw + 2] = cpu_to_le32(dimm_sg);
457 buf32[dw + 3] = 0;
458
459 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
460 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
461 PDC_DIMM_HOST_PKT,
462 buf32[dw + 0],
463 buf32[dw + 1],
464 buf32[dw + 2],
465 buf32[dw + 3]);
466}
467
468static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
469{
cedc9a47 470 struct scatterlist *sg;
1da177e4
LT		 471 struct ata_port *ap = qc->ap;
472 struct pdc_port_priv *pp = ap->private_data;
0d5ff566
TH		 473 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
474 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
1da177e4 475 unsigned int portno = ap->port_no;
cedc9a47 476 unsigned int i, idx, total_len = 0, sgt_len;
1da177e4
LT		 477 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
478
beec7dbc 479 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
1da177e4 480
44877b4e 481 VPRINTK("ata%u: ENTER\n", ap->print_id);
1da177e4
LT		 482
483 /* hard-code chip #0 */
484 mmio += PDC_CHIP0_OFS;
485
486 /*
487 * Build S/G table
488 */
1da177e4 489 idx = 0;
cedc9a47
JG		 490 ata_for_each_sg(sg, qc) {
491 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
492 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
493 total_len += sg_dma_len(sg);
1da177e4
LT		 494 }
495 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
496 sgt_len = idx * 4;
497
498 /*
499 * Build ATA, host DMA packets
500 */
501 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
502 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
503
504 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
505 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
506
507 if (qc->tf.flags & ATA_TFLAG_LBA48)
508 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
509 else
510 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
511
512 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
513
514 /* copy three S/G tables and two packets to DIMM MMIO window */
515 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
516 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
517 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
518 PDC_DIMM_HOST_PRD,
519 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
520
521 /* force host FIFO dump */
522 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
523
524 readl(dimm_mmio); /* MMIO PCI posting flush */
525
526 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
527}
528
529static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
530{
531 struct ata_port *ap = qc->ap;
532 struct pdc_port_priv *pp = ap->private_data;
0d5ff566
TH		 533 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
534 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
1da177e4
LT		 535 unsigned int portno = ap->port_no;
536 unsigned int i;
537
44877b4e 538 VPRINTK("ata%u: ENTER\n", ap->print_id);
1da177e4
LT		 539
540 /* hard-code chip #0 */
541 mmio += PDC_CHIP0_OFS;
542
543 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
544
545 if (qc->tf.flags & ATA_TFLAG_LBA48)
546 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
547 else
548 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
549
550 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
551
552 /* copy three S/G tables and two packets to DIMM MMIO window */
553 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
554 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
555
556 /* force host FIFO dump */
557 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
558
559 readl(dimm_mmio); /* MMIO PCI posting flush */
560
561 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
562}
563
564static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
565{
566 switch (qc->tf.protocol) {
567 case ATA_PROT_DMA:
568 pdc20621_dma_prep(qc);
569 break;
570 case ATA_PROT_NODATA:
571 pdc20621_nodata_prep(qc);
572 break;
573 default:
574 break;
575 }
576}
577
578static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
579 unsigned int seq,
580 u32 pkt_ofs)
581{
582 struct ata_port *ap = qc->ap;
cca3974e 583 struct ata_host *host = ap->host;
0d5ff566 584 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 585
586 /* hard-code chip #0 */
587 mmio += PDC_CHIP0_OFS;
588
589 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
590 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
591
592 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
593 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
594}
595
596static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
597 unsigned int seq,
598 u32 pkt_ofs)
599{
600 struct ata_port *ap = qc->ap;
cca3974e 601 struct pdc_host_priv *pp = ap->host->private_data;
1da177e4
LT		 602 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
603
604 if (!pp->doing_hdma) {
605 __pdc20621_push_hdma(qc, seq, pkt_ofs);
606 pp->doing_hdma = 1;
607 return;
608 }
609
610 pp->hdma[idx].qc = qc;
611 pp->hdma[idx].seq = seq;
612 pp->hdma[idx].pkt_ofs = pkt_ofs;
613 pp->hdma_prod++;
614}
615
616static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
617{
618 struct ata_port *ap = qc->ap;
cca3974e 619 struct pdc_host_priv *pp = ap->host->private_data;
1da177e4
LT		 620 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
621
622 /* if nothing on queue, we're done */
623 if (pp->hdma_prod == pp->hdma_cons) {
624 pp->doing_hdma = 0;
625 return;
626 }
627
628 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
629 pp->hdma[idx].pkt_ofs);
630 pp->hdma_cons++;
631}
632
633#ifdef ATA_VERBOSE_DEBUG
634static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
635{
636 struct ata_port *ap = qc->ap;
637 unsigned int port_no = ap->port_no;
0d5ff566 638 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
1da177e4
LT		 639
640 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
641 dimm_mmio += PDC_DIMM_HOST_PKT;
642
643 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
644 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
645 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
646 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
647}
648#else
649static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
650#endif /* ATA_VERBOSE_DEBUG */
651
652static void pdc20621_packet_start(struct ata_queued_cmd *qc)
653{
654 struct ata_port *ap = qc->ap;
cca3974e 655 struct ata_host *host = ap->host;
1da177e4 656 unsigned int port_no = ap->port_no;
0d5ff566 657 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 658 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
659 u8 seq = (u8) (port_no + 1);
660 unsigned int port_ofs;
661
662 /* hard-code chip #0 */
663 mmio += PDC_CHIP0_OFS;
664
44877b4e 665 VPRINTK("ata%u: ENTER\n", ap->print_id);
1da177e4
LT		 666
667 wmb(); /* flush PRD, pkt writes */
668
669 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
670
671 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
672 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
673 seq += 4;
674
675 pdc20621_dump_hdma(qc);
676 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
677 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
678 port_ofs + PDC_DIMM_HOST_PKT,
679 port_ofs + PDC_DIMM_HOST_PKT,
680 seq);
681 } else {
682 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
683 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
684
685 writel(port_ofs + PDC_DIMM_ATA_PKT,
0d5ff566
TH		 686 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
687 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
1da177e4
LT		 688 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
689 port_ofs + PDC_DIMM_ATA_PKT,
690 port_ofs + PDC_DIMM_ATA_PKT,
691 seq);
692 }
693}
694
9a3d9eb0 695static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 696{
697 switch (qc->tf.protocol) {
698 case ATA_PROT_DMA:
699 case ATA_PROT_NODATA:
700 pdc20621_packet_start(qc);
701 return 0;
702
703 case ATA_PROT_ATAPI_DMA:
704 BUG();
705 break;
706
707 default:
708 break;
709 }
710
711 return ata_qc_issue_prot(qc);
712}
713
714static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
715 struct ata_queued_cmd *qc,
716 unsigned int doing_hdma,
ea6ba10b 717 void __iomem *mmio)
1da177e4
LT		 718{
719 unsigned int port_no = ap->port_no;
720 unsigned int port_ofs =
721 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
722 u8 status;
723 unsigned int handled = 0;
724
725 VPRINTK("ENTER\n");
726
727 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
728 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
729
730 /* step two - DMA from DIMM to host */
731 if (doing_hdma) {
44877b4e 732 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
1da177e4
LT		 733 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
734 /* get drive status; clear intr; complete txn */
a22e2eb0
AL		 735 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
736 ata_qc_complete(qc);
1da177e4
LT		 737 pdc20621_pop_hdma(qc);
738 }
739
740 /* step one - exec ATA command */
741 else {
742 u8 seq = (u8) (port_no + 1 + 4);
44877b4e 743 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
1da177e4
LT		 744 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
745
746 /* submit hdma pkt */
747 pdc20621_dump_hdma(qc);
748 pdc20621_push_hdma(qc, seq,
749 port_ofs + PDC_DIMM_HOST_PKT);
750 }
751 handled = 1;
752
753 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
754
755 /* step one - DMA from host to DIMM */
756 if (doing_hdma) {
757 u8 seq = (u8) (port_no + 1);
44877b4e 758 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
1da177e4
LT		 759 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
760
761 /* submit ata pkt */
762 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
763 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
764 writel(port_ofs + PDC_DIMM_ATA_PKT,
0d5ff566
TH		 765 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
766 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
1da177e4
LT		 767 }
768
769 /* step two - execute ATA command */
770 else {
44877b4e 771 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
1da177e4
LT		 772 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
773 /* get drive status; clear intr; complete txn */
a22e2eb0
AL		 774 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
775 ata_qc_complete(qc);
1da177e4
LT		 776 pdc20621_pop_hdma(qc);
777 }
778 handled = 1;
779
780 /* command completion, but no data xfer */
781 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
782
783 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
784 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
a22e2eb0
AL		 785 qc->err_mask |= ac_err_mask(status);
786 ata_qc_complete(qc);
1da177e4
LT		 787 handled = 1;
788
789 } else {
790 ap->stats.idle_irq++;
791 }
792
793 return handled;
794}
795
796static void pdc20621_irq_clear(struct ata_port *ap)
797{
cca3974e 798 struct ata_host *host = ap->host;
0d5ff566 799 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 800
801 mmio += PDC_CHIP0_OFS;
802
803 readl(mmio + PDC_20621_SEQMASK);
804}
805
7d12e780 806static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
1da177e4 807{
cca3974e 808 struct ata_host *host = dev_instance;
1da177e4
LT		 809 struct ata_port *ap;
810 u32 mask = 0;
811 unsigned int i, tmp, port_no;
812 unsigned int handled = 0;
ea6ba10b 813 void __iomem *mmio_base;
1da177e4
LT		 814
815 VPRINTK("ENTER\n");
816
0d5ff566 817 if (!host || !host->iomap[PDC_MMIO_BAR]) {
1da177e4
LT		 818 VPRINTK("QUICK EXIT\n");
819 return IRQ_NONE;
820 }
821
0d5ff566 822 mmio_base = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 823
824 /* reading should also clear interrupts */
825 mmio_base += PDC_CHIP0_OFS;
826 mask = readl(mmio_base + PDC_20621_SEQMASK);
827 VPRINTK("mask == 0x%x\n", mask);
828
829 if (mask == 0xffffffff) {
830 VPRINTK("QUICK EXIT 2\n");
831 return IRQ_NONE;
832 }
833 mask &= 0xffff; /* only 16 tags possible */
834 if (!mask) {
835 VPRINTK("QUICK EXIT 3\n");
836 return IRQ_NONE;
837 }
838
cca3974e 839 spin_lock(&host->lock);
1da177e4
LT		 840
841 for (i = 1; i < 9; i++) {
842 port_no = i - 1;
843 if (port_no > 3)
844 port_no -= 4;
cca3974e 845 if (port_no >= host->n_ports)
1da177e4
LT		 846 ap = NULL;
847 else
cca3974e 848 ap = host->ports[port_no];
1da177e4
LT		 849 tmp = mask & (1 << i);
850 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
c1389503 851 if (tmp && ap &&
029f5468 852 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 853 struct ata_queued_cmd *qc;
854
9af5c9c9 855 qc = ata_qc_from_tag(ap, ap->link.active_tag);
e50362ec 856 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1da177e4
LT		 857 handled += pdc20621_host_intr(ap, qc, (i > 4),
858 mmio_base);
859 }
860 }
861
cca3974e 862 spin_unlock(&host->lock);
1da177e4
LT		 863
864 VPRINTK("mask == 0x%x\n", mask);
865
866 VPRINTK("EXIT\n");
867
868 return IRQ_RETVAL(handled);
869}
870
871static void pdc_eng_timeout(struct ata_port *ap)
872{
873 u8 drv_stat;
cca3974e 874 struct ata_host *host = ap->host;
1da177e4 875 struct ata_queued_cmd *qc;
b8f6153e 876 unsigned long flags;
1da177e4
LT		 877
878 DPRINTK("ENTER\n");
879
cca3974e 880 spin_lock_irqsave(&host->lock, flags);
b8f6153e 881
9af5c9c9 882 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1da177e4 883
1da177e4
LT		 884 switch (qc->tf.protocol) {
885 case ATA_PROT_DMA:
886 case ATA_PROT_NODATA:
f15a1daf 887 ata_port_printk(ap, KERN_ERR, "command timeout\n");
a22e2eb0 888 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
1da177e4
LT		 889 break;
890
891 default:
892 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
893
f15a1daf
TH		 894 ata_port_printk(ap, KERN_ERR,
895 "unknown timeout, cmd 0x%x stat 0x%x\n",
896 qc->tf.command, drv_stat);
1da177e4 897
a22e2eb0 898 qc->err_mask |= ac_err_mask(drv_stat);
1da177e4
LT		 899 break;
900 }
901
cca3974e 902 spin_unlock_irqrestore(&host->lock, flags);
f6379020 903 ata_eh_qc_complete(qc);
1da177e4
LT		 904 DPRINTK("EXIT\n");
905}
906
057ace5e 907static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 908{
909 WARN_ON (tf->protocol == ATA_PROT_DMA ||
910 tf->protocol == ATA_PROT_NODATA);
911 ata_tf_load(ap, tf);
912}
913
914
057ace5e 915static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 916{
917 WARN_ON (tf->protocol == ATA_PROT_DMA ||
918 tf->protocol == ATA_PROT_NODATA);
919 ata_exec_command(ap, tf);
920}
921
922
0d5ff566 923static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
1da177e4
LT		 924{
925 port->cmd_addr = base;
926 port->data_addr = base;
927 port->feature_addr =
928 port->error_addr = base + 0x4;
929 port->nsect_addr = base + 0x8;
930 port->lbal_addr = base + 0xc;
931 port->lbam_addr = base + 0x10;
932 port->lbah_addr = base + 0x14;
933 port->device_addr = base + 0x18;
934 port->command_addr =
935 port->status_addr = base + 0x1c;
936 port->altstatus_addr =
937 port->ctl_addr = base + 0x38;
938}
939
940
941#ifdef ATA_VERBOSE_DEBUG
4447d351 942static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
1da177e4
LT		 943 u32 offset, u32 size)
944{
945 u32 window_size;
946 u16 idx;
947 u8 page_mask;
948 long dist;
4447d351
TH		 949 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
950 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1da177e4
LT		 951
952 /* hard-code chip #0 */
953 mmio += PDC_CHIP0_OFS;
954
8a60a071
JG		 955 page_mask = 0x00;
956 window_size = 0x2000 * 4; /* 32K byte uchar size */
957 idx = (u16) (offset / window_size);
1da177e4
LT		 958
959 writel(0x01, mmio + PDC_GENERAL_CTLR);
960 readl(mmio + PDC_GENERAL_CTLR);
961 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
962 readl(mmio + PDC_DIMM_WINDOW_CTLR);
963
964 offset -= (idx * window_size);
965 idx++;
8a60a071 966 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
1da177e4 967 (long) (window_size - offset);
8a60a071 968 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
1da177e4
LT		 969 dist);
970
8a60a071 971 psource += dist;
1da177e4
LT		 972 size -= dist;
973 for (; (long) size >= (long) window_size ;) {
974 writel(0x01, mmio + PDC_GENERAL_CTLR);
975 readl(mmio + PDC_GENERAL_CTLR);
976 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
977 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 978 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1da177e4
LT		 979 window_size / 4);
980 psource += window_size;
981 size -= window_size;
982 idx ++;
983 }
984
985 if (size) {
986 writel(0x01, mmio + PDC_GENERAL_CTLR);
987 readl(mmio + PDC_GENERAL_CTLR);
988 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
989 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 990 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1da177e4
LT		 991 size / 4);
992 }
993}
994#endif
995
996
4447d351 997static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
1da177e4
LT		 998 u32 offset, u32 size)
999{
1000 u32 window_size;
1001 u16 idx;
1002 u8 page_mask;
1003 long dist;
4447d351
TH		 1004 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1005 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1da177e4 1006
8a60a071 1007 /* hard-code chip #0 */
1da177e4
LT		 1008 mmio += PDC_CHIP0_OFS;
1009
8a60a071
JG		 1010 page_mask = 0x00;
1011 window_size = 0x2000 * 4; /* 32K byte uchar size */
1da177e4
LT		 1012 idx = (u16) (offset / window_size);
1013
1014 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1015 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 1016 offset -= (idx * window_size);
1da177e4
LT		 1017 idx++;
1018 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1019 (long) (window_size - offset);
a9afd7cd 1020 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1da177e4
LT		 1021 writel(0x01, mmio + PDC_GENERAL_CTLR);
1022 readl(mmio + PDC_GENERAL_CTLR);
1023
8a60a071 1024 psource += dist;
1da177e4
LT		 1025 size -= dist;
1026 for (; (long) size >= (long) window_size ;) {
1027 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1028 readl(mmio + PDC_DIMM_WINDOW_CTLR);
a9afd7cd 1029 memcpy_toio(dimm_mmio, psource, window_size / 4);
1da177e4
LT		 1030 writel(0x01, mmio + PDC_GENERAL_CTLR);
1031 readl(mmio + PDC_GENERAL_CTLR);
1032 psource += window_size;
1033 size -= window_size;
1034 idx ++;
1035 }
8a60a071 1036
1da177e4
LT		 1037 if (size) {
1038 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1039 readl(mmio + PDC_DIMM_WINDOW_CTLR);
a9afd7cd 1040 memcpy_toio(dimm_mmio, psource, size / 4);
1da177e4
LT		 1041 writel(0x01, mmio + PDC_GENERAL_CTLR);
1042 readl(mmio + PDC_GENERAL_CTLR);
1043 }
1044}
1045
1046
4447d351 1047static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
1da177e4
LT		 1048 u32 subaddr, u32 *pdata)
1049{
4447d351 1050 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4 1051 u32 i2creg = 0;
8a60a071 1052 u32 status;
1da177e4
LT		 1053 u32 count =0;
1054
1055 /* hard-code chip #0 */
1056 mmio += PDC_CHIP0_OFS;
1057
1058 i2creg |= device << 24;
1059 i2creg |= subaddr << 16;
1060
1061 /* Set the device and subaddress */
b2d46b61
JG		 1062 writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1063 readl(mmio + PDC_I2C_ADDR_DATA);
1da177e4
LT		 1064
1065 /* Write Control to perform read operation, mask int */
8a60a071 1066 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
b2d46b61 1067 mmio + PDC_I2C_CONTROL);
1da177e4
LT		 1068
1069 for (count = 0; count <= 1000; count ++) {
b2d46b61 1070 status = readl(mmio + PDC_I2C_CONTROL);
1da177e4 1071 if (status & PDC_I2C_COMPLETE) {
b2d46b61 1072 status = readl(mmio + PDC_I2C_ADDR_DATA);
1da177e4
LT		 1073 break;
1074 } else if (count == 1000)
1075 return 0;
1076 }
1077
1078 *pdata = (status >> 8) & 0x000000ff;
8a60a071 1079 return 1;
1da177e4
LT		 1080}
1081
1082
4447d351 1083static int pdc20621_detect_dimm(struct ata_host *host)
1da177e4
LT		 1084{
1085 u32 data=0 ;
4447d351 1086 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4
LT		 1087 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1088 if (data == 100)
1089 return 100;
1090 } else
1091 return 0;
8a60a071 1092
4447d351 1093 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
8a60a071 1094 if(data <= 0x75)
1da177e4
LT		 1095 return 133;
1096 } else
1097 return 0;
8a60a071 1098
1da177e4
LT		 1099 return 0;
1100}
1101
1102
4447d351 1103static int pdc20621_prog_dimm0(struct ata_host *host)
1da177e4
LT		 1104{
1105 u32 spd0[50];
1106 u32 data = 0;
1107 int size, i;
8a60a071 1108 u8 bdimmsize;
4447d351 1109 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 1110 static const struct {
1111 unsigned int reg;
1112 unsigned int ofs;
1113 } pdc_i2c_read_data [] = {
8a60a071 1114 { PDC_DIMM_SPD_TYPE, 11 },
1da177e4 1115 { PDC_DIMM_SPD_FRESH_RATE, 12 },
8a60a071 1116 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1da177e4
LT		 1117 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1118 { PDC_DIMM_SPD_ROW_NUM, 3 },
1119 { PDC_DIMM_SPD_BANK_NUM, 17 },
1120 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1121 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1122 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1123 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1124 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
8a60a071 1125 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1da177e4
LT		 1126 };
1127
1128 /* hard-code chip #0 */
1129 mmio += PDC_CHIP0_OFS;
1130
1131 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
4447d351 1132 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
8a60a071 1133 pdc_i2c_read_data[i].reg,
1da177e4 1134 &spd0[pdc_i2c_read_data[i].ofs]);
8a60a071 1135
1da177e4 1136 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
8a60a071 1137 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1da177e4 1138 ((((spd0[27] + 9) / 10) - 1) << 8) ;
8a60a071
JG		 1139 data |= (((((spd0[29] > spd0[28])
1140 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1da177e4 1141 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
8a60a071
JG		 1142
1143 if (spd0[18] & 0x08)
1da177e4
LT		 1144 data |= ((0x03) << 14);
1145 else if (spd0[18] & 0x04)
1146 data |= ((0x02) << 14);
1147 else if (spd0[18] & 0x01)
1148 data |= ((0x01) << 14);
1149 else
1150 data |= (0 << 14);
1151
8a60a071 1152 /*
1da177e4
LT		 1153 Calculate the size of bDIMMSize (power of 2) and
1154 merge the DIMM size by program start/end address.
1155 */
1156
1157 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1158 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1159 data |= (((size / 16) - 1) << 16);
1160 data |= (0 << 23);
1161 data |= 8;
b2d46b61
JG		 1162 writel(data, mmio + PDC_DIMM0_CONTROL);
1163 readl(mmio + PDC_DIMM0_CONTROL);
8a60a071 1164 return size;
1da177e4
LT		 1165}
1166
1167
4447d351 1168static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1da177e4
LT		 1169{
1170 u32 data, spd0;
0d5ff566 1171 int error, i;
4447d351 1172 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 1173
1174 /* hard-code chip #0 */
1175 mmio += PDC_CHIP0_OFS;
1176
1177 /*
1178 Set To Default : DIMM Module Global Control Register (0x022259F1)
1179 DIMM Arbitration Disable (bit 20)
1180 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1181 Refresh Enable (bit 17)
1182 */
1183
8a60a071 1184 data = 0x022259F1;
b2d46b61
JG		 1185 writel(data, mmio + PDC_SDRAM_CONTROL);
1186 readl(mmio + PDC_SDRAM_CONTROL);
1da177e4
LT		 1187
1188 /* Turn on for ECC */
4447d351 1189 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4
LT		 1190 PDC_DIMM_SPD_TYPE, &spd0);
1191 if (spd0 == 0x02) {
1192 data |= (0x01 << 16);
b2d46b61
JG		 1193 writel(data, mmio + PDC_SDRAM_CONTROL);
1194 readl(mmio + PDC_SDRAM_CONTROL);
1da177e4
LT		 1195 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1196 }
1197
1198 /* DIMM Initialization Select/Enable (bit 18/19) */
1199 data &= (~(1<<18));
1200 data |= (1<<19);
b2d46b61 1201 writel(data, mmio + PDC_SDRAM_CONTROL);
1da177e4 1202
8a60a071 1203 error = 1;
1da177e4 1204 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
b2d46b61 1205 data = readl(mmio + PDC_SDRAM_CONTROL);
1da177e4
LT		 1206 if (!(data & (1<<19))) {
1207 error = 0;
8a60a071 1208 break;
1da177e4
LT		 1209 }
1210 msleep(i*100);
1211 }
1212 return error;
1213}
8a60a071 1214
1da177e4 1215
4447d351 1216static unsigned int pdc20621_dimm_init(struct ata_host *host)
1da177e4 1217{
8a60a071 1218 int speed, size, length;
1da177e4
LT		 1219 u32 addr,spd0,pci_status;
1220 u32 tmp=0;
1221 u32 time_period=0;
1222 u32 tcount=0;
1223 u32 ticks=0;
1224 u32 clock=0;
1225 u32 fparam=0;
4447d351 1226 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 1227
1228 /* hard-code chip #0 */
1229 mmio += PDC_CHIP0_OFS;
1230
1231 /* Initialize PLL based upon PCI Bus Frequency */
1232
1233 /* Initialize Time Period Register */
1234 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1235 time_period = readl(mmio + PDC_TIME_PERIOD);
1236 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1237
1238 /* Enable timer */
b2d46b61 1239 writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1da177e4
LT		 1240 readl(mmio + PDC_TIME_CONTROL);
1241
1242 /* Wait 3 seconds */
1243 msleep(3000);
1244
8a60a071 1245 /*
1da177e4
LT		 1246 When timer is enabled, counter is decreased every internal
1247 clock cycle.
1248 */
1249
1250 tcount = readl(mmio + PDC_TIME_COUNTER);
1251 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1252
8a60a071 1253 /*
1da177e4
LT		 1254 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1255 register should be >= (0xffffffff - 3x10^8).
1256 */
1257 if(tcount >= PCI_X_TCOUNT) {
1258 ticks = (time_period - tcount);
1259 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
8a60a071 1260
1da177e4
LT		 1261 clock = (ticks / 300000);
1262 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
8a60a071 1263
1da177e4
LT		 1264 clock = (clock * 33);
1265 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1266
1267 /* PLL F Param (bit 22:16) */
1268 fparam = (1400000 / clock) - 2;
1269 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
8a60a071 1270
1da177e4
LT		 1271 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1272 pci_status = (0x8a001824 | (fparam << 16));
1273 } else
1274 pci_status = PCI_PLL_INIT;
1275
1276 /* Initialize PLL. */
1277 VPRINTK("pci_status: 0x%x\n", pci_status);
1278 writel(pci_status, mmio + PDC_CTL_STATUS);
1279 readl(mmio + PDC_CTL_STATUS);
1280
8a60a071 1281 /*
1da177e4
LT		 1282 Read SPD of DIMM by I2C interface,
1283 and program the DIMM Module Controller.
1284 */
4447d351 1285 if (!(speed = pdc20621_detect_dimm(host))) {
8a60a071 1286 printk(KERN_ERR "Detect Local DIMM Fail\n");
1da177e4
LT		 1287 return 1; /* DIMM error */
1288 }
1289 VPRINTK("Local DIMM Speed = %d\n", speed);
1290
8a60a071 1291 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
4447d351 1292 size = pdc20621_prog_dimm0(host);
1da177e4
LT		 1293 VPRINTK("Local DIMM Size = %dMB\n",size);
1294
8a60a071 1295 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
4447d351 1296 if (pdc20621_prog_dimm_global(host)) {
1da177e4
LT		 1297 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1298 return 1;
1299 }
1300
1301#ifdef ATA_VERBOSE_DEBUG
1302 {
1303 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1304 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1305 '1','.','1','0',
1306 '9','8','0','3','1','6','1','2',0,0};
1307 u8 test_parttern2[40] = {0};
1308
4447d351
TH		 1309 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x10040, 40);
1310 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x40, 40);
1da177e4 1311
4447d351
TH		 1312 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x10040, 40);
1313 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
8a60a071 1314 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1da177e4 1315 test_parttern2[1], &(test_parttern2[2]));
4447d351 1316 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x10040,
1da177e4 1317 40);
8a60a071 1318 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1da177e4
LT		 1319 test_parttern2[1], &(test_parttern2[2]));
1320
4447d351
TH		 1321 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x40, 40);
1322 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
8a60a071 1323 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1da177e4
LT		 1324 test_parttern2[1], &(test_parttern2[2]));
1325 }
1326#endif
1327
1328 /* ECC initiliazation. */
1329
4447d351 1330 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4
LT		 1331 PDC_DIMM_SPD_TYPE, &spd0);
1332 if (spd0 == 0x02) {
1333 VPRINTK("Start ECC initialization\n");
1334 addr = 0;
1335 length = size * 1024 * 1024;
1336 while (addr < length) {
4447d351 1337 pdc20621_put_to_dimm(host, (void *) &tmp, addr,
1da177e4
LT		 1338 sizeof(u32));
1339 addr += sizeof(u32);
1340 }
1341 VPRINTK("Finish ECC initialization\n");
1342 }
1343 return 0;
1344}
1345
1346
4447d351 1347static void pdc_20621_init(struct ata_host *host)
1da177e4
LT		 1348{
1349 u32 tmp;
4447d351 1350 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 1351
1352 /* hard-code chip #0 */
1353 mmio += PDC_CHIP0_OFS;
1354
1355 /*
1356 * Select page 0x40 for our 32k DIMM window
1357 */
1358 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1359 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1360 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1361
1362 /*
1363 * Reset Host DMA
1364 */
1365 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1366 tmp |= PDC_RESET;
1367 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1368 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1369
1370 udelay(10);
1371
1372 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1373 tmp &= ~PDC_RESET;
1374 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1375 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1376}
1377
1378static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1379{
1380 static int printed_version;
4447d351
TH		 1381 const struct ata_port_info *ppi[] =
1382 { &pdc_port_info[ent->driver_data], NULL };
1383 struct ata_host *host;
24dc5f33 1384 struct pdc_host_priv *hpriv;
cbcdd875 1385 int i, rc;
1da177e4
LT		 1386
1387 if (!printed_version++)
a9524a76 1388 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1389
4447d351
TH		 1390 /* allocate host */
1391 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1392 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1393 if (!host || !hpriv)
1394 return -ENOMEM;
1395
1396 host->private_data = hpriv;
1397
1398 /* acquire resources and fill host */
24dc5f33 1399 rc = pcim_enable_device(pdev);
1da177e4
LT		 1400 if (rc)
1401 return rc;
1402
0d5ff566
TH		 1403 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1404 DRV_NAME);
1405 if (rc == -EBUSY)
24dc5f33 1406 pcim_pin_device(pdev);
0d5ff566 1407 if (rc)
24dc5f33 1408 return rc;
4447d351
TH		 1409 host->iomap = pcim_iomap_table(pdev);
1410
cbcdd875
TH		 1411 for (i = 0; i < 4; i++) {
1412 struct ata_port *ap = host->ports[i];
1413 void __iomem *base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1414 unsigned int offset = 0x200 + i * 0x80;
1415
1416 pdc_sata_setup_port(&ap->ioaddr, base + offset);
1417
1418 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1419 ata_port_pbar_desc(ap, PDC_DIMM_BAR, -1, "dimm");
1420 ata_port_pbar_desc(ap, PDC_MMIO_BAR, offset, "port");
1421 }
1da177e4 1422
4447d351 1423 /* configure and activate */
1da177e4
LT		 1424 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1425 if (rc)
24dc5f33 1426 return rc;
1da177e4
LT		 1427 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1428 if (rc)
24dc5f33 1429 return rc;
1da177e4 1430
4447d351 1431 if (pdc20621_dimm_init(host))
24dc5f33 1432 return -ENOMEM;
4447d351 1433 pdc_20621_init(host);
1da177e4
LT		 1434
1435 pci_set_master(pdev);
4447d351
TH		 1436 return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1437 IRQF_SHARED, &pdc_sata_sht);
1da177e4
LT		 1438}
1439
1440
1441static int __init pdc_sata_init(void)
1442{
b7887196 1443 return pci_register_driver(&pdc_sata_pci_driver);
1da177e4
LT		 1444}
1445
1446
1447static void __exit pdc_sata_exit(void)
1448{
1449 pci_unregister_driver(&pdc_sata_pci_driver);
1450}
1451
1452
1453MODULE_AUTHOR("Jeff Garzik");
1454MODULE_DESCRIPTION("Promise SATA low-level driver");
1455MODULE_LICENSE("GPL");
1456MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1457MODULE_VERSION(DRV_VERSION);
1458
1459module_init(pdc_sata_init);
1460module_exit(pdc_sata_exit);
kernel source for telekom puls (alcatel/mediatek)