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1da177e4 LT |
1 | /* |
2 | * sata_svw.c - ServerWorks / Apple K2 SATA | |
3 | * | |
4 | * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and | |
5 | * Jeff Garzik <jgarzik@pobox.com> | |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
10 | * | |
11 | * Bits from Jeff Garzik, Copyright RedHat, Inc. | |
12 | * | |
13 | * This driver probably works with non-Apple versions of the | |
14 | * Broadcom chipset... | |
15 | * | |
af36d7f0 JG |
16 | * |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License as published by | |
19 | * the Free Software Foundation; either version 2, or (at your option) | |
20 | * any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; see the file COPYING. If not, write to | |
29 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | * | |
32 | * libata documentation is available via 'make {ps|pdf}docs', | |
33 | * as Documentation/DocBook/libata.* | |
34 | * | |
35 | * Hardware documentation available under NDA. | |
1da177e4 LT |
36 | * |
37 | */ | |
38 | ||
1da177e4 LT |
39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/blkdev.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/interrupt.h> | |
a9524a76 | 46 | #include <linux/device.h> |
1da177e4 LT |
47 | #include <scsi/scsi_host.h> |
48 | #include <linux/libata.h> | |
49 | ||
50 | #ifdef CONFIG_PPC_OF | |
51 | #include <asm/prom.h> | |
52 | #include <asm/pci-bridge.h> | |
53 | #endif /* CONFIG_PPC_OF */ | |
54 | ||
55 | #define DRV_NAME "sata_svw" | |
8676ce07 | 56 | #define DRV_VERSION "2.0" |
1da177e4 | 57 | |
55cca65e | 58 | enum { |
c10340ac JG |
59 | K2_FLAG_NO_ATAPI_DMA = (1 << 29), |
60 | ||
55cca65e JG |
61 | /* Taskfile registers offsets */ |
62 | K2_SATA_TF_CMD_OFFSET = 0x00, | |
63 | K2_SATA_TF_DATA_OFFSET = 0x00, | |
64 | K2_SATA_TF_ERROR_OFFSET = 0x04, | |
65 | K2_SATA_TF_NSECT_OFFSET = 0x08, | |
66 | K2_SATA_TF_LBAL_OFFSET = 0x0c, | |
67 | K2_SATA_TF_LBAM_OFFSET = 0x10, | |
68 | K2_SATA_TF_LBAH_OFFSET = 0x14, | |
69 | K2_SATA_TF_DEVICE_OFFSET = 0x18, | |
70 | K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, | |
71 | K2_SATA_TF_CTL_OFFSET = 0x20, | |
1da177e4 | 72 | |
55cca65e JG |
73 | /* DMA base */ |
74 | K2_SATA_DMA_CMD_OFFSET = 0x30, | |
1da177e4 | 75 | |
55cca65e JG |
76 | /* SCRs base */ |
77 | K2_SATA_SCR_STATUS_OFFSET = 0x40, | |
78 | K2_SATA_SCR_ERROR_OFFSET = 0x44, | |
79 | K2_SATA_SCR_CONTROL_OFFSET = 0x48, | |
1da177e4 | 80 | |
55cca65e JG |
81 | /* Others */ |
82 | K2_SATA_SICR1_OFFSET = 0x80, | |
83 | K2_SATA_SICR2_OFFSET = 0x84, | |
84 | K2_SATA_SIM_OFFSET = 0x88, | |
1da177e4 | 85 | |
55cca65e JG |
86 | /* Port stride */ |
87 | K2_SATA_PORT_OFFSET = 0x100, | |
c10340ac JG |
88 | |
89 | board_svw4 = 0, | |
90 | board_svw8 = 1, | |
91 | }; | |
92 | ||
93 | static const struct k2_board_info { | |
94 | unsigned int n_ports; | |
95 | unsigned long port_flags; | |
96 | } k2_board_info[] = { | |
97 | /* board_svw4 */ | |
98 | { 4, K2_FLAG_NO_ATAPI_DMA }, | |
99 | ||
100 | /* board_svw8 */ | |
101 | { 8, K2_FLAG_NO_ATAPI_DMA }, | |
55cca65e | 102 | }; |
1da177e4 | 103 | |
ac19bff2 JG |
104 | static u8 k2_stat_check_status(struct ata_port *ap); |
105 | ||
1da177e4 | 106 | |
c10340ac JG |
107 | static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
108 | { | |
109 | if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA) | |
110 | return -1; /* ATAPI DMA not supported */ | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
1da177e4 LT |
115 | static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
116 | { | |
117 | if (sc_reg > SCR_CONTROL) | |
118 | return 0xffffffffU; | |
119 | return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4)); | |
120 | } | |
121 | ||
122 | ||
123 | static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
124 | u32 val) | |
125 | { | |
126 | if (sc_reg > SCR_CONTROL) | |
127 | return; | |
128 | writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4)); | |
129 | } | |
130 | ||
131 | ||
057ace5e | 132 | static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
133 | { |
134 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
135 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
136 | ||
137 | if (tf->ctl != ap->last_ctl) { | |
138 | writeb(tf->ctl, ioaddr->ctl_addr); | |
139 | ap->last_ctl = tf->ctl; | |
140 | ata_wait_idle(ap); | |
141 | } | |
142 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
143 | writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr); | |
144 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr); | |
145 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr); | |
146 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr); | |
147 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr); | |
148 | } else if (is_addr) { | |
149 | writew(tf->feature, ioaddr->feature_addr); | |
150 | writew(tf->nsect, ioaddr->nsect_addr); | |
151 | writew(tf->lbal, ioaddr->lbal_addr); | |
152 | writew(tf->lbam, ioaddr->lbam_addr); | |
153 | writew(tf->lbah, ioaddr->lbah_addr); | |
154 | } | |
155 | ||
156 | if (tf->flags & ATA_TFLAG_DEVICE) | |
157 | writeb(tf->device, ioaddr->device_addr); | |
158 | ||
159 | ata_wait_idle(ap); | |
160 | } | |
161 | ||
162 | ||
163 | static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
164 | { | |
165 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
ac19bff2 | 166 | u16 nsect, lbal, lbam, lbah, feature; |
1da177e4 | 167 | |
ac19bff2 | 168 | tf->command = k2_stat_check_status(ap); |
1da177e4 | 169 | tf->device = readw(ioaddr->device_addr); |
ac19bff2 JG |
170 | feature = readw(ioaddr->error_addr); |
171 | nsect = readw(ioaddr->nsect_addr); | |
172 | lbal = readw(ioaddr->lbal_addr); | |
173 | lbam = readw(ioaddr->lbam_addr); | |
174 | lbah = readw(ioaddr->lbah_addr); | |
175 | ||
176 | tf->feature = feature; | |
177 | tf->nsect = nsect; | |
178 | tf->lbal = lbal; | |
179 | tf->lbam = lbam; | |
180 | tf->lbah = lbah; | |
1da177e4 LT |
181 | |
182 | if (tf->flags & ATA_TFLAG_LBA48) { | |
ac19bff2 | 183 | tf->hob_feature = feature >> 8; |
1da177e4 LT |
184 | tf->hob_nsect = nsect >> 8; |
185 | tf->hob_lbal = lbal >> 8; | |
186 | tf->hob_lbam = lbam >> 8; | |
187 | tf->hob_lbah = lbah >> 8; | |
188 | } | |
189 | } | |
190 | ||
191 | /** | |
192 | * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) | |
193 | * @qc: Info associated with this ATA transaction. | |
194 | * | |
195 | * LOCKING: | |
cca3974e | 196 | * spin_lock_irqsave(host lock) |
1da177e4 LT |
197 | */ |
198 | ||
199 | static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc) | |
200 | { | |
201 | struct ata_port *ap = qc->ap; | |
202 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
203 | u8 dmactl; | |
04b1add1 | 204 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; |
1da177e4 LT |
205 | /* load PRD table addr. */ |
206 | mb(); /* make sure PRD table writes are visible to controller */ | |
207 | writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); | |
208 | ||
209 | /* specify data direction, triple-check start bit is clear */ | |
210 | dmactl = readb(mmio + ATA_DMA_CMD); | |
211 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
212 | if (!rw) | |
213 | dmactl |= ATA_DMA_WR; | |
214 | writeb(dmactl, mmio + ATA_DMA_CMD); | |
215 | ||
216 | /* issue r/w command if this is not a ATA DMA command*/ | |
217 | if (qc->tf.protocol != ATA_PROT_DMA) | |
218 | ap->ops->exec_command(ap, &qc->tf); | |
219 | } | |
220 | ||
221 | /** | |
222 | * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) | |
223 | * @qc: Info associated with this ATA transaction. | |
224 | * | |
225 | * LOCKING: | |
cca3974e | 226 | * spin_lock_irqsave(host lock) |
1da177e4 LT |
227 | */ |
228 | ||
229 | static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc) | |
230 | { | |
231 | struct ata_port *ap = qc->ap; | |
04b1add1 | 232 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; |
1da177e4 LT |
233 | u8 dmactl; |
234 | ||
235 | /* start host DMA transaction */ | |
236 | dmactl = readb(mmio + ATA_DMA_CMD); | |
237 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); | |
8a60a071 JG |
238 | /* There is a race condition in certain SATA controllers that can |
239 | be seen when the r/w command is given to the controller before the | |
1da177e4 LT |
240 | host DMA is started. On a Read command, the controller would initiate |
241 | the command to the drive even before it sees the DMA start. When there | |
8a60a071 | 242 | are very fast drives connected to the controller, or when the data request |
1da177e4 LT |
243 | hits in the drive cache, there is the possibility that the drive returns a part |
244 | or all of the requested data to the controller before the DMA start is issued. | |
245 | In this case, the controller would become confused as to what to do with the data. | |
246 | In the worst case when all the data is returned back to the controller, the | |
247 | controller could hang. In other cases it could return partial data returning | |
248 | in data corruption. This problem has been seen in PPC systems and can also appear | |
8a60a071 | 249 | on an system with very fast disks, where the SATA controller is sitting behind a |
1da177e4 LT |
250 | number of bridges, and hence there is significant latency between the r/w command |
251 | and the start command. */ | |
252 | /* issue r/w command if the access is to ATA*/ | |
253 | if (qc->tf.protocol == ATA_PROT_DMA) | |
254 | ap->ops->exec_command(ap, &qc->tf); | |
255 | } | |
256 | ||
8a60a071 | 257 | |
1da177e4 LT |
258 | static u8 k2_stat_check_status(struct ata_port *ap) |
259 | { | |
260 | return readl((void *) ap->ioaddr.status_addr); | |
261 | } | |
262 | ||
263 | #ifdef CONFIG_PPC_OF | |
264 | /* | |
265 | * k2_sata_proc_info | |
266 | * inout : decides on the direction of the dataflow and the meaning of the | |
267 | * variables | |
268 | * buffer: If inout==FALSE data is being written to it else read from it | |
269 | * *start: If inout==FALSE start of the valid data in the buffer | |
270 | * offset: If inout==FALSE offset from the beginning of the imaginary file | |
271 | * from which we start writing into the buffer | |
272 | * length: If inout==FALSE max number of bytes to be written into the buffer | |
273 | * else number of bytes in the buffer | |
274 | */ | |
275 | static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start, | |
276 | off_t offset, int count, int inout) | |
277 | { | |
278 | struct ata_port *ap; | |
279 | struct device_node *np; | |
280 | int len, index; | |
281 | ||
282 | /* Find the ata_port */ | |
35bb94b1 | 283 | ap = ata_shost_to_port(shost); |
1da177e4 LT |
284 | if (ap == NULL) |
285 | return 0; | |
286 | ||
287 | /* Find the OF node for the PCI device proper */ | |
cca3974e | 288 | np = pci_device_to_OF_node(to_pci_dev(ap->host->dev)); |
1da177e4 LT |
289 | if (np == NULL) |
290 | return 0; | |
291 | ||
292 | /* Match it to a port node */ | |
cca3974e | 293 | index = (ap == ap->host->ports[0]) ? 0 : 1; |
1da177e4 | 294 | for (np = np->child; np != NULL; np = np->sibling) { |
af5f92d8 | 295 | const u32 *reg = get_property(np, "reg", NULL); |
1da177e4 LT |
296 | if (!reg) |
297 | continue; | |
298 | if (index == *reg) | |
299 | break; | |
300 | } | |
301 | if (np == NULL) | |
302 | return 0; | |
303 | ||
304 | len = sprintf(page, "devspec: %s\n", np->full_name); | |
305 | ||
306 | return len; | |
307 | } | |
308 | #endif /* CONFIG_PPC_OF */ | |
309 | ||
310 | ||
193515d5 | 311 | static struct scsi_host_template k2_sata_sht = { |
1da177e4 LT |
312 | .module = THIS_MODULE, |
313 | .name = DRV_NAME, | |
314 | .ioctl = ata_scsi_ioctl, | |
315 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
316 | .can_queue = ATA_DEF_QUEUE, |
317 | .this_id = ATA_SHT_THIS_ID, | |
318 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
319 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
320 | .emulated = ATA_SHT_EMULATED, | |
321 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
322 | .proc_name = DRV_NAME, | |
323 | .dma_boundary = ATA_DMA_BOUNDARY, | |
324 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 325 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 LT |
326 | #ifdef CONFIG_PPC_OF |
327 | .proc_info = k2_sata_proc_info, | |
328 | #endif | |
329 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
330 | }; |
331 | ||
332 | ||
057ace5e | 333 | static const struct ata_port_operations k2_sata_ops = { |
1da177e4 LT |
334 | .port_disable = ata_port_disable, |
335 | .tf_load = k2_sata_tf_load, | |
336 | .tf_read = k2_sata_tf_read, | |
337 | .check_status = k2_stat_check_status, | |
338 | .exec_command = ata_exec_command, | |
339 | .dev_select = ata_std_dev_select, | |
c10340ac | 340 | .check_atapi_dma = k2_sata_check_atapi_dma, |
1da177e4 LT |
341 | .bmdma_setup = k2_bmdma_setup_mmio, |
342 | .bmdma_start = k2_bmdma_start_mmio, | |
343 | .bmdma_stop = ata_bmdma_stop, | |
344 | .bmdma_status = ata_bmdma_status, | |
345 | .qc_prep = ata_qc_prep, | |
346 | .qc_issue = ata_qc_issue_prot, | |
a6b2c5d4 | 347 | .data_xfer = ata_mmio_data_xfer, |
d7a80dad TH |
348 | .freeze = ata_bmdma_freeze, |
349 | .thaw = ata_bmdma_thaw, | |
350 | .error_handler = ata_bmdma_error_handler, | |
351 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
1da177e4 LT |
352 | .irq_handler = ata_interrupt, |
353 | .irq_clear = ata_bmdma_irq_clear, | |
354 | .scr_read = k2_sata_scr_read, | |
355 | .scr_write = k2_sata_scr_write, | |
356 | .port_start = ata_port_start, | |
357 | .port_stop = ata_port_stop, | |
374b1873 | 358 | .host_stop = ata_pci_host_stop, |
1da177e4 LT |
359 | }; |
360 | ||
361 | static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base) | |
362 | { | |
363 | port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; | |
364 | port->data_addr = base + K2_SATA_TF_DATA_OFFSET; | |
365 | port->feature_addr = | |
366 | port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; | |
367 | port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; | |
368 | port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; | |
369 | port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; | |
370 | port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; | |
371 | port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; | |
372 | port->command_addr = | |
373 | port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; | |
374 | port->altstatus_addr = | |
375 | port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; | |
376 | port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; | |
377 | port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; | |
378 | } | |
379 | ||
380 | ||
381 | static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
382 | { | |
383 | static int printed_version; | |
384 | struct ata_probe_ent *probe_ent = NULL; | |
385 | unsigned long base; | |
ea6ba10b | 386 | void __iomem *mmio_base; |
c10340ac JG |
387 | const struct k2_board_info *board_info = |
388 | &k2_board_info[ent->driver_data]; | |
1da177e4 LT |
389 | int pci_dev_busy = 0; |
390 | int rc; | |
60bf09a3 | 391 | int i; |
1da177e4 LT |
392 | |
393 | if (!printed_version++) | |
a9524a76 | 394 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
395 | |
396 | /* | |
397 | * If this driver happens to only be useful on Apple's K2, then | |
398 | * we should check that here as it has a normal Serverworks ID | |
399 | */ | |
400 | rc = pci_enable_device(pdev); | |
401 | if (rc) | |
402 | return rc; | |
403 | /* | |
404 | * Check if we have resources mapped at all (second function may | |
405 | * have been disabled by firmware) | |
406 | */ | |
407 | if (pci_resource_len(pdev, 5) == 0) | |
408 | return -ENODEV; | |
409 | ||
410 | /* Request PCI regions */ | |
411 | rc = pci_request_regions(pdev, DRV_NAME); | |
412 | if (rc) { | |
413 | pci_dev_busy = 1; | |
414 | goto err_out; | |
415 | } | |
416 | ||
417 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
418 | if (rc) | |
419 | goto err_out_regions; | |
420 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
421 | if (rc) | |
422 | goto err_out_regions; | |
423 | ||
424 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
425 | if (probe_ent == NULL) { | |
426 | rc = -ENOMEM; | |
427 | goto err_out_regions; | |
428 | } | |
429 | ||
430 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
431 | probe_ent->dev = pci_dev_to_dev(pdev); | |
432 | INIT_LIST_HEAD(&probe_ent->node); | |
433 | ||
374b1873 | 434 | mmio_base = pci_iomap(pdev, 5, 0); |
1da177e4 LT |
435 | if (mmio_base == NULL) { |
436 | rc = -ENOMEM; | |
437 | goto err_out_free_ent; | |
438 | } | |
439 | base = (unsigned long) mmio_base; | |
440 | ||
441 | /* Clear a magic bit in SCR1 according to Darwin, those help | |
442 | * some funky seagate drives (though so far, those were already | |
104e5010 | 443 | * set by the firmware on the machines I had access to) |
1da177e4 LT |
444 | */ |
445 | writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, | |
446 | mmio_base + K2_SATA_SICR1_OFFSET); | |
447 | ||
448 | /* Clear SATA error & interrupts we don't use */ | |
449 | writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); | |
450 | writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); | |
451 | ||
452 | probe_ent->sht = &k2_sata_sht; | |
cca3974e | 453 | probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
c10340ac | 454 | ATA_FLAG_MMIO | board_info->port_flags; |
1da177e4 LT |
455 | probe_ent->port_ops = &k2_sata_ops; |
456 | probe_ent->n_ports = 4; | |
457 | probe_ent->irq = pdev->irq; | |
1d6f359a | 458 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
459 | probe_ent->mmio_base = mmio_base; |
460 | ||
461 | /* We don't care much about the PIO/UDMA masks, but the core won't like us | |
462 | * if we don't fill these | |
463 | */ | |
464 | probe_ent->pio_mask = 0x1f; | |
465 | probe_ent->mwdma_mask = 0x7; | |
466 | probe_ent->udma_mask = 0x7f; | |
467 | ||
60bf09a3 NS |
468 | /* different controllers have different number of ports - currently 4 or 8 */ |
469 | /* All ports are on the same function. Multi-function device is no | |
470 | * longer available. This should not be seen in any system. */ | |
c10340ac | 471 | for (i = 0; i < board_info->n_ports; i++) |
60bf09a3 | 472 | k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET); |
1da177e4 LT |
473 | |
474 | pci_set_master(pdev); | |
475 | ||
476 | /* FIXME: check ata_device_add return value */ | |
477 | ata_device_add(probe_ent); | |
478 | kfree(probe_ent); | |
479 | ||
480 | return 0; | |
481 | ||
482 | err_out_free_ent: | |
483 | kfree(probe_ent); | |
484 | err_out_regions: | |
485 | pci_release_regions(pdev); | |
486 | err_out: | |
487 | if (!pci_dev_busy) | |
488 | pci_disable_device(pdev); | |
489 | return rc; | |
490 | } | |
491 | ||
60bf09a3 NS |
492 | /* 0x240 is device ID for Apple K2 device |
493 | * 0x241 is device ID for Serverworks Frodo4 | |
494 | * 0x242 is device ID for Serverworks Frodo8 | |
495 | * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA | |
496 | * controller | |
497 | * */ | |
3b7d697d | 498 | static const struct pci_device_id k2_sata_pci_tbl[] = { |
c10340ac JG |
499 | { PCI_VDEVICE(SERVERWORKS, 0x0240), board_svw4 }, |
500 | { PCI_VDEVICE(SERVERWORKS, 0x0241), board_svw4 }, | |
501 | { PCI_VDEVICE(SERVERWORKS, 0x0242), board_svw8 }, | |
502 | { PCI_VDEVICE(SERVERWORKS, 0x024a), board_svw4 }, | |
503 | { PCI_VDEVICE(SERVERWORKS, 0x024b), board_svw4 }, | |
2d2744fc | 504 | |
1da177e4 LT |
505 | { } |
506 | }; | |
507 | ||
1da177e4 LT |
508 | static struct pci_driver k2_sata_pci_driver = { |
509 | .name = DRV_NAME, | |
510 | .id_table = k2_sata_pci_tbl, | |
511 | .probe = k2_sata_init_one, | |
512 | .remove = ata_pci_remove_one, | |
513 | }; | |
514 | ||
1da177e4 LT |
515 | static int __init k2_sata_init(void) |
516 | { | |
b7887196 | 517 | return pci_register_driver(&k2_sata_pci_driver); |
1da177e4 LT |
518 | } |
519 | ||
1da177e4 LT |
520 | static void __exit k2_sata_exit(void) |
521 | { | |
522 | pci_unregister_driver(&k2_sata_pci_driver); | |
523 | } | |
524 | ||
1da177e4 LT |
525 | MODULE_AUTHOR("Benjamin Herrenschmidt"); |
526 | MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); | |
527 | MODULE_LICENSE("GPL"); | |
528 | MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); | |
529 | MODULE_VERSION(DRV_VERSION); | |
530 | ||
531 | module_init(k2_sata_init); | |
532 | module_exit(k2_sata_exit); |