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1da177e4 LT |
1 | /* |
2 | * sata_svw.c - ServerWorks / Apple K2 SATA | |
3 | * | |
4 | * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and | |
5 | * Jeff Garzik <jgarzik@pobox.com> | |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
10 | * | |
11 | * Bits from Jeff Garzik, Copyright RedHat, Inc. | |
12 | * | |
13 | * This driver probably works with non-Apple versions of the | |
14 | * Broadcom chipset... | |
15 | * | |
af36d7f0 JG |
16 | * |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License as published by | |
19 | * the Free Software Foundation; either version 2, or (at your option) | |
20 | * any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; see the file COPYING. If not, write to | |
29 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | * | |
32 | * libata documentation is available via 'make {ps|pdf}docs', | |
33 | * as Documentation/DocBook/libata.* | |
34 | * | |
35 | * Hardware documentation available under NDA. | |
1da177e4 LT |
36 | * |
37 | */ | |
38 | ||
1da177e4 LT |
39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/blkdev.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/interrupt.h> | |
a9524a76 | 46 | #include <linux/device.h> |
1da177e4 LT |
47 | #include <scsi/scsi_host.h> |
48 | #include <linux/libata.h> | |
49 | ||
50 | #ifdef CONFIG_PPC_OF | |
51 | #include <asm/prom.h> | |
52 | #include <asm/pci-bridge.h> | |
53 | #endif /* CONFIG_PPC_OF */ | |
54 | ||
55 | #define DRV_NAME "sata_svw" | |
8bc3fc47 | 56 | #define DRV_VERSION "2.2" |
1da177e4 | 57 | |
55cca65e | 58 | enum { |
4447d351 TH |
59 | /* ap->flags bits */ |
60 | K2_FLAG_SATA_8_PORTS = (1 << 24), | |
61 | K2_FLAG_NO_ATAPI_DMA = (1 << 25), | |
c10340ac | 62 | |
55cca65e JG |
63 | /* Taskfile registers offsets */ |
64 | K2_SATA_TF_CMD_OFFSET = 0x00, | |
65 | K2_SATA_TF_DATA_OFFSET = 0x00, | |
66 | K2_SATA_TF_ERROR_OFFSET = 0x04, | |
67 | K2_SATA_TF_NSECT_OFFSET = 0x08, | |
68 | K2_SATA_TF_LBAL_OFFSET = 0x0c, | |
69 | K2_SATA_TF_LBAM_OFFSET = 0x10, | |
70 | K2_SATA_TF_LBAH_OFFSET = 0x14, | |
71 | K2_SATA_TF_DEVICE_OFFSET = 0x18, | |
72 | K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, | |
73 | K2_SATA_TF_CTL_OFFSET = 0x20, | |
1da177e4 | 74 | |
55cca65e JG |
75 | /* DMA base */ |
76 | K2_SATA_DMA_CMD_OFFSET = 0x30, | |
1da177e4 | 77 | |
55cca65e JG |
78 | /* SCRs base */ |
79 | K2_SATA_SCR_STATUS_OFFSET = 0x40, | |
80 | K2_SATA_SCR_ERROR_OFFSET = 0x44, | |
81 | K2_SATA_SCR_CONTROL_OFFSET = 0x48, | |
1da177e4 | 82 | |
55cca65e JG |
83 | /* Others */ |
84 | K2_SATA_SICR1_OFFSET = 0x80, | |
85 | K2_SATA_SICR2_OFFSET = 0x84, | |
86 | K2_SATA_SIM_OFFSET = 0x88, | |
1da177e4 | 87 | |
55cca65e JG |
88 | /* Port stride */ |
89 | K2_SATA_PORT_OFFSET = 0x100, | |
c10340ac JG |
90 | |
91 | board_svw4 = 0, | |
92 | board_svw8 = 1, | |
93 | }; | |
94 | ||
ac19bff2 JG |
95 | static u8 k2_stat_check_status(struct ata_port *ap); |
96 | ||
1da177e4 | 97 | |
c10340ac JG |
98 | static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
99 | { | |
100 | if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA) | |
101 | return -1; /* ATAPI DMA not supported */ | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
1da177e4 LT |
106 | static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
107 | { | |
108 | if (sc_reg > SCR_CONTROL) | |
109 | return 0xffffffffU; | |
92ccc5f7 | 110 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
111 | } |
112 | ||
113 | ||
114 | static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
115 | u32 val) | |
116 | { | |
117 | if (sc_reg > SCR_CONTROL) | |
118 | return; | |
92ccc5f7 | 119 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
120 | } |
121 | ||
122 | ||
057ace5e | 123 | static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
124 | { |
125 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
126 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
127 | ||
128 | if (tf->ctl != ap->last_ctl) { | |
0d5ff566 | 129 | writeb(tf->ctl, ioaddr->ctl_addr); |
1da177e4 LT |
130 | ap->last_ctl = tf->ctl; |
131 | ata_wait_idle(ap); | |
132 | } | |
133 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
850a9d8a | 134 | writew(tf->feature | (((u16)tf->hob_feature) << 8), |
0d5ff566 | 135 | ioaddr->feature_addr); |
850a9d8a | 136 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), |
0d5ff566 | 137 | ioaddr->nsect_addr); |
850a9d8a | 138 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), |
0d5ff566 | 139 | ioaddr->lbal_addr); |
850a9d8a | 140 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), |
0d5ff566 | 141 | ioaddr->lbam_addr); |
850a9d8a | 142 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), |
0d5ff566 | 143 | ioaddr->lbah_addr); |
1da177e4 | 144 | } else if (is_addr) { |
0d5ff566 TH |
145 | writew(tf->feature, ioaddr->feature_addr); |
146 | writew(tf->nsect, ioaddr->nsect_addr); | |
147 | writew(tf->lbal, ioaddr->lbal_addr); | |
148 | writew(tf->lbam, ioaddr->lbam_addr); | |
149 | writew(tf->lbah, ioaddr->lbah_addr); | |
1da177e4 LT |
150 | } |
151 | ||
152 | if (tf->flags & ATA_TFLAG_DEVICE) | |
0d5ff566 | 153 | writeb(tf->device, ioaddr->device_addr); |
1da177e4 LT |
154 | |
155 | ata_wait_idle(ap); | |
156 | } | |
157 | ||
158 | ||
159 | static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
160 | { | |
161 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
ac19bff2 | 162 | u16 nsect, lbal, lbam, lbah, feature; |
1da177e4 | 163 | |
ac19bff2 | 164 | tf->command = k2_stat_check_status(ap); |
0d5ff566 TH |
165 | tf->device = readw(ioaddr->device_addr); |
166 | feature = readw(ioaddr->error_addr); | |
167 | nsect = readw(ioaddr->nsect_addr); | |
168 | lbal = readw(ioaddr->lbal_addr); | |
169 | lbam = readw(ioaddr->lbam_addr); | |
170 | lbah = readw(ioaddr->lbah_addr); | |
ac19bff2 JG |
171 | |
172 | tf->feature = feature; | |
173 | tf->nsect = nsect; | |
174 | tf->lbal = lbal; | |
175 | tf->lbam = lbam; | |
176 | tf->lbah = lbah; | |
1da177e4 LT |
177 | |
178 | if (tf->flags & ATA_TFLAG_LBA48) { | |
ac19bff2 | 179 | tf->hob_feature = feature >> 8; |
1da177e4 LT |
180 | tf->hob_nsect = nsect >> 8; |
181 | tf->hob_lbal = lbal >> 8; | |
182 | tf->hob_lbam = lbam >> 8; | |
183 | tf->hob_lbah = lbah >> 8; | |
184 | } | |
185 | } | |
186 | ||
187 | /** | |
188 | * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) | |
189 | * @qc: Info associated with this ATA transaction. | |
190 | * | |
191 | * LOCKING: | |
cca3974e | 192 | * spin_lock_irqsave(host lock) |
1da177e4 LT |
193 | */ |
194 | ||
195 | static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc) | |
196 | { | |
197 | struct ata_port *ap = qc->ap; | |
198 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
199 | u8 dmactl; | |
04b1add1 | 200 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; |
1da177e4 LT |
201 | /* load PRD table addr. */ |
202 | mb(); /* make sure PRD table writes are visible to controller */ | |
203 | writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); | |
204 | ||
205 | /* specify data direction, triple-check start bit is clear */ | |
206 | dmactl = readb(mmio + ATA_DMA_CMD); | |
207 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
208 | if (!rw) | |
209 | dmactl |= ATA_DMA_WR; | |
210 | writeb(dmactl, mmio + ATA_DMA_CMD); | |
211 | ||
212 | /* issue r/w command if this is not a ATA DMA command*/ | |
213 | if (qc->tf.protocol != ATA_PROT_DMA) | |
214 | ap->ops->exec_command(ap, &qc->tf); | |
215 | } | |
216 | ||
217 | /** | |
218 | * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) | |
219 | * @qc: Info associated with this ATA transaction. | |
220 | * | |
221 | * LOCKING: | |
cca3974e | 222 | * spin_lock_irqsave(host lock) |
1da177e4 LT |
223 | */ |
224 | ||
225 | static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc) | |
226 | { | |
227 | struct ata_port *ap = qc->ap; | |
04b1add1 | 228 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; |
1da177e4 LT |
229 | u8 dmactl; |
230 | ||
231 | /* start host DMA transaction */ | |
232 | dmactl = readb(mmio + ATA_DMA_CMD); | |
233 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); | |
8a60a071 JG |
234 | /* There is a race condition in certain SATA controllers that can |
235 | be seen when the r/w command is given to the controller before the | |
1da177e4 LT |
236 | host DMA is started. On a Read command, the controller would initiate |
237 | the command to the drive even before it sees the DMA start. When there | |
8a60a071 | 238 | are very fast drives connected to the controller, or when the data request |
1da177e4 LT |
239 | hits in the drive cache, there is the possibility that the drive returns a part |
240 | or all of the requested data to the controller before the DMA start is issued. | |
241 | In this case, the controller would become confused as to what to do with the data. | |
242 | In the worst case when all the data is returned back to the controller, the | |
243 | controller could hang. In other cases it could return partial data returning | |
244 | in data corruption. This problem has been seen in PPC systems and can also appear | |
8a60a071 | 245 | on an system with very fast disks, where the SATA controller is sitting behind a |
1da177e4 LT |
246 | number of bridges, and hence there is significant latency between the r/w command |
247 | and the start command. */ | |
248 | /* issue r/w command if the access is to ATA*/ | |
249 | if (qc->tf.protocol == ATA_PROT_DMA) | |
250 | ap->ops->exec_command(ap, &qc->tf); | |
251 | } | |
252 | ||
8a60a071 | 253 | |
1da177e4 LT |
254 | static u8 k2_stat_check_status(struct ata_port *ap) |
255 | { | |
92ccc5f7 | 256 | return readl((void __iomem *) ap->ioaddr.status_addr); |
1da177e4 LT |
257 | } |
258 | ||
259 | #ifdef CONFIG_PPC_OF | |
260 | /* | |
261 | * k2_sata_proc_info | |
262 | * inout : decides on the direction of the dataflow and the meaning of the | |
263 | * variables | |
264 | * buffer: If inout==FALSE data is being written to it else read from it | |
265 | * *start: If inout==FALSE start of the valid data in the buffer | |
266 | * offset: If inout==FALSE offset from the beginning of the imaginary file | |
267 | * from which we start writing into the buffer | |
268 | * length: If inout==FALSE max number of bytes to be written into the buffer | |
269 | * else number of bytes in the buffer | |
270 | */ | |
271 | static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start, | |
272 | off_t offset, int count, int inout) | |
273 | { | |
274 | struct ata_port *ap; | |
275 | struct device_node *np; | |
276 | int len, index; | |
277 | ||
278 | /* Find the ata_port */ | |
35bb94b1 | 279 | ap = ata_shost_to_port(shost); |
1da177e4 LT |
280 | if (ap == NULL) |
281 | return 0; | |
282 | ||
283 | /* Find the OF node for the PCI device proper */ | |
cca3974e | 284 | np = pci_device_to_OF_node(to_pci_dev(ap->host->dev)); |
1da177e4 LT |
285 | if (np == NULL) |
286 | return 0; | |
287 | ||
288 | /* Match it to a port node */ | |
cca3974e | 289 | index = (ap == ap->host->ports[0]) ? 0 : 1; |
1da177e4 | 290 | for (np = np->child; np != NULL; np = np->sibling) { |
40cd3a45 | 291 | const u32 *reg = of_get_property(np, "reg", NULL); |
1da177e4 LT |
292 | if (!reg) |
293 | continue; | |
294 | if (index == *reg) | |
295 | break; | |
296 | } | |
297 | if (np == NULL) | |
298 | return 0; | |
299 | ||
300 | len = sprintf(page, "devspec: %s\n", np->full_name); | |
301 | ||
302 | return len; | |
303 | } | |
304 | #endif /* CONFIG_PPC_OF */ | |
305 | ||
306 | ||
193515d5 | 307 | static struct scsi_host_template k2_sata_sht = { |
1da177e4 LT |
308 | .module = THIS_MODULE, |
309 | .name = DRV_NAME, | |
310 | .ioctl = ata_scsi_ioctl, | |
311 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
312 | .can_queue = ATA_DEF_QUEUE, |
313 | .this_id = ATA_SHT_THIS_ID, | |
314 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
315 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
316 | .emulated = ATA_SHT_EMULATED, | |
317 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
318 | .proc_name = DRV_NAME, | |
319 | .dma_boundary = ATA_DMA_BOUNDARY, | |
320 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 321 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 LT |
322 | #ifdef CONFIG_PPC_OF |
323 | .proc_info = k2_sata_proc_info, | |
324 | #endif | |
325 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
326 | }; |
327 | ||
328 | ||
057ace5e | 329 | static const struct ata_port_operations k2_sata_ops = { |
1da177e4 LT |
330 | .port_disable = ata_port_disable, |
331 | .tf_load = k2_sata_tf_load, | |
332 | .tf_read = k2_sata_tf_read, | |
333 | .check_status = k2_stat_check_status, | |
334 | .exec_command = ata_exec_command, | |
335 | .dev_select = ata_std_dev_select, | |
c10340ac | 336 | .check_atapi_dma = k2_sata_check_atapi_dma, |
1da177e4 LT |
337 | .bmdma_setup = k2_bmdma_setup_mmio, |
338 | .bmdma_start = k2_bmdma_start_mmio, | |
339 | .bmdma_stop = ata_bmdma_stop, | |
340 | .bmdma_status = ata_bmdma_status, | |
341 | .qc_prep = ata_qc_prep, | |
342 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 343 | .data_xfer = ata_data_xfer, |
d7a80dad TH |
344 | .freeze = ata_bmdma_freeze, |
345 | .thaw = ata_bmdma_thaw, | |
346 | .error_handler = ata_bmdma_error_handler, | |
347 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
1da177e4 | 348 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 AI |
349 | .irq_on = ata_irq_on, |
350 | .irq_ack = ata_irq_ack, | |
1da177e4 LT |
351 | .scr_read = k2_sata_scr_read, |
352 | .scr_write = k2_sata_scr_write, | |
353 | .port_start = ata_port_start, | |
1da177e4 LT |
354 | }; |
355 | ||
4447d351 TH |
356 | static const struct ata_port_info k2_port_info[] = { |
357 | /* board_svw4 */ | |
358 | { | |
359 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
360 | ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA, | |
361 | .pio_mask = 0x1f, | |
362 | .mwdma_mask = 0x07, | |
363 | .udma_mask = 0x7f, | |
364 | .port_ops = &k2_sata_ops, | |
365 | }, | |
366 | /* board_svw8 */ | |
367 | { | |
368 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
369 | ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA | | |
370 | K2_FLAG_SATA_8_PORTS, | |
371 | .pio_mask = 0x1f, | |
372 | .mwdma_mask = 0x07, | |
373 | .udma_mask = 0x7f, | |
374 | .port_ops = &k2_sata_ops, | |
375 | }, | |
376 | }; | |
377 | ||
0d5ff566 | 378 | static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) |
1da177e4 LT |
379 | { |
380 | port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; | |
381 | port->data_addr = base + K2_SATA_TF_DATA_OFFSET; | |
382 | port->feature_addr = | |
383 | port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; | |
384 | port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; | |
385 | port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; | |
386 | port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; | |
387 | port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; | |
388 | port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; | |
389 | port->command_addr = | |
390 | port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; | |
391 | port->altstatus_addr = | |
392 | port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; | |
393 | port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; | |
394 | port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; | |
395 | } | |
396 | ||
397 | ||
398 | static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
399 | { | |
400 | static int printed_version; | |
4447d351 TH |
401 | const struct ata_port_info *ppi[] = |
402 | { &k2_port_info[ent->driver_data], NULL }; | |
403 | struct ata_host *host; | |
ea6ba10b | 404 | void __iomem *mmio_base; |
4447d351 | 405 | int n_ports, i, rc; |
1da177e4 LT |
406 | |
407 | if (!printed_version++) | |
a9524a76 | 408 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 409 | |
4447d351 TH |
410 | /* allocate host */ |
411 | n_ports = 4; | |
412 | if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS) | |
413 | n_ports = 8; | |
414 | ||
415 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
416 | if (!host) | |
417 | return -ENOMEM; | |
418 | ||
1da177e4 LT |
419 | /* |
420 | * If this driver happens to only be useful on Apple's K2, then | |
421 | * we should check that here as it has a normal Serverworks ID | |
422 | */ | |
24dc5f33 | 423 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
424 | if (rc) |
425 | return rc; | |
4447d351 | 426 | |
1da177e4 LT |
427 | /* |
428 | * Check if we have resources mapped at all (second function may | |
429 | * have been disabled by firmware) | |
430 | */ | |
431 | if (pci_resource_len(pdev, 5) == 0) | |
432 | return -ENODEV; | |
433 | ||
0d5ff566 TH |
434 | /* Request and iomap PCI regions */ |
435 | rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); | |
436 | if (rc == -EBUSY) | |
24dc5f33 | 437 | pcim_pin_device(pdev); |
0d5ff566 | 438 | if (rc) |
24dc5f33 | 439 | return rc; |
4447d351 TH |
440 | host->iomap = pcim_iomap_table(pdev); |
441 | mmio_base = host->iomap[5]; | |
442 | ||
443 | /* different controllers have different number of ports - currently 4 or 8 */ | |
444 | /* All ports are on the same function. Multi-function device is no | |
445 | * longer available. This should not be seen in any system. */ | |
446 | for (i = 0; i < host->n_ports; i++) | |
447 | k2_sata_setup_port(&host->ports[i]->ioaddr, | |
448 | mmio_base + i * K2_SATA_PORT_OFFSET); | |
1da177e4 LT |
449 | |
450 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
451 | if (rc) | |
24dc5f33 | 452 | return rc; |
1da177e4 LT |
453 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
454 | if (rc) | |
24dc5f33 | 455 | return rc; |
1da177e4 | 456 | |
0d5ff566 TH |
457 | /* Clear a magic bit in SCR1 according to Darwin, those help |
458 | * some funky seagate drives (though so far, those were already | |
459 | * set by the firmware on the machines I had access to) | |
460 | */ | |
461 | writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, | |
462 | mmio_base + K2_SATA_SICR1_OFFSET); | |
463 | ||
464 | /* Clear SATA error & interrupts we don't use */ | |
465 | writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); | |
466 | writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); | |
1da177e4 LT |
467 | |
468 | pci_set_master(pdev); | |
4447d351 TH |
469 | return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED, |
470 | &k2_sata_sht); | |
1da177e4 LT |
471 | } |
472 | ||
60bf09a3 NS |
473 | /* 0x240 is device ID for Apple K2 device |
474 | * 0x241 is device ID for Serverworks Frodo4 | |
475 | * 0x242 is device ID for Serverworks Frodo8 | |
476 | * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA | |
477 | * controller | |
478 | * */ | |
3b7d697d | 479 | static const struct pci_device_id k2_sata_pci_tbl[] = { |
c10340ac JG |
480 | { PCI_VDEVICE(SERVERWORKS, 0x0240), board_svw4 }, |
481 | { PCI_VDEVICE(SERVERWORKS, 0x0241), board_svw4 }, | |
482 | { PCI_VDEVICE(SERVERWORKS, 0x0242), board_svw8 }, | |
483 | { PCI_VDEVICE(SERVERWORKS, 0x024a), board_svw4 }, | |
484 | { PCI_VDEVICE(SERVERWORKS, 0x024b), board_svw4 }, | |
2d2744fc | 485 | |
1da177e4 LT |
486 | { } |
487 | }; | |
488 | ||
1da177e4 LT |
489 | static struct pci_driver k2_sata_pci_driver = { |
490 | .name = DRV_NAME, | |
491 | .id_table = k2_sata_pci_tbl, | |
492 | .probe = k2_sata_init_one, | |
493 | .remove = ata_pci_remove_one, | |
494 | }; | |
495 | ||
1da177e4 LT |
496 | static int __init k2_sata_init(void) |
497 | { | |
b7887196 | 498 | return pci_register_driver(&k2_sata_pci_driver); |
1da177e4 LT |
499 | } |
500 | ||
1da177e4 LT |
501 | static void __exit k2_sata_exit(void) |
502 | { | |
503 | pci_unregister_driver(&k2_sata_pci_driver); | |
504 | } | |
505 | ||
1da177e4 LT |
506 | MODULE_AUTHOR("Benjamin Herrenschmidt"); |
507 | MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); | |
508 | MODULE_LICENSE("GPL"); | |
509 | MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); | |
510 | MODULE_VERSION(DRV_VERSION); | |
511 | ||
512 | module_init(k2_sata_init); | |
513 | module_exit(k2_sata_exit); |