[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / sata_sis.c

/*
 *  sata_sis.c - Silicon Integrated Systems SATA
 *
 *  Maintained by:  Uwe Koziolek
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 Uwe Koziolek
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include "sis.h"

#define DRV_NAME	"sata_sis"
#define DRV_VERSION	"1.0"

enum {
	sis_180			= 0,
	SIS_SCR_PCI_BAR		= 5,

	/* PCI configuration registers */
	SIS_GENCTL		= 0x54, /* IDE General Control register */
	SIS_SCR_BASE		= 0xc0, /* sata0 phy SCR registers */
	SIS180_SATA1_OFS	= 0x10, /* offset from sata0->sata1 phy regs */
	SIS182_SATA1_OFS	= 0x20, /* offset from sata0->sata1 phy regs */
	SIS_PMR			= 0x90, /* port mapping register */
	SIS_PMR_COMBINED	= 0x30,

	/* random bits */
	SIS_FLAG_CFGSCR		= (1 << 30), /* host flag: SCRs via PCI cfg */

	GENCTL_IOMAPPED_SCR	= (1 << 26), /* if set, SCRs are in IO space */
};

static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);

static const struct pci_device_id sis_pci_tbl[] = {
	{ PCI_VDEVICE(SI, 0x0180), sis_180 },	/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0181), sis_180 },	/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0182), sis_180 },	/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x0183), sis_180 },	/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x1182), sis_180 },	/* SiS 966/680 */
	{ PCI_VDEVICE(SI, 0x1183), sis_180 },	/* SiS 966/966L/968/680 */

	{ }	/* terminate list */
};

static struct pci_driver sis_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sis_pci_tbl,
	.probe			= sis_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template sis_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations sis_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.scr_read		= sis_scr_read,
	.scr_write		= sis_scr_write,
};

static const struct ata_port_info sis_port_info = {
	.flags		= ATA_FLAG_SATA,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &sis_ops,
};

MODULE_AUTHOR("Uwe Koziolek");
MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
	u8 pmr;

	if (ap->port_no)  {
		switch (pdev->device) {
		case 0x0180:
		case 0x0181:
			pci_read_config_byte(pdev, SIS_PMR, &pmr);
			if ((pmr & SIS_PMR_COMBINED) == 0)
				addr += SIS180_SATA1_OFS;
			break;

		case 0x0182:
		case 0x0183:
		case 0x1182:
			addr += SIS182_SATA1_OFS;
			break;
		}
	}
	if (link->pmp)
		addr += 0x10;

	return addr;
}

static u32 sis_scr_cfg_read(struct ata_link *link,
			    unsigned int sc_reg, u32 *val)
{
	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return -EINVAL;

	pci_read_config_dword(pdev, cfg_addr, val);
	return 0;
}

static int sis_scr_cfg_write(struct ata_link *link,
			     unsigned int sc_reg, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);

	pci_write_config_dword(pdev, cfg_addr, val);
	return 0;
}

static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
{
	struct ata_port *ap = link->ap;
	void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;

	if (sc_reg > SCR_CONTROL)
		return -EINVAL;

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_read(link, sc_reg, val);

	*val = ioread32(base + sc_reg * 4);
	return 0;
}

static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
{
	struct ata_port *ap = link->ap;
	void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;

	if (sc_reg > SCR_CONTROL)
		return -EINVAL;

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_write(link, sc_reg, val);

	iowrite32(val, base + (sc_reg * 4));
	return 0;
}

static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct ata_port_info pi = sis_port_info;
	const struct ata_port_info *ppi[] = { &pi, &pi };
	struct ata_host *host;
	u32 genctl, val;
	u8 pmr;
	u8 port2_start = 0x20;
	int i, rc;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* check and see if the SCRs are in IO space or PCI cfg space */
	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
		pi.flags |= SIS_FLAG_CFGSCR;

	/* if hardware thinks SCRs are in IO space, but there are
	 * no IO resources assigned, change to PCI cfg space.
	 */
	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
	    ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
	     (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
		genctl &= ~GENCTL_IOMAPPED_SCR;
		pci_write_config_dword(pdev, SIS_GENCTL, genctl);
		pi.flags |= SIS_FLAG_CFGSCR;
	}

	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	switch (ent->device) {
	case 0x0180:
	case 0x0181:

		/* The PATA-handling is provided by pata_sis */
		switch (pmr & 0x30) {
		case 0x10:
			ppi[1] = &sis_info133_for_sata;
			break;

		case 0x30:
			ppi[0] = &sis_info133_for_sata;
			break;
		}
		if ((pmr & SIS_PMR_COMBINED) == 0) {
			dev_info(&pdev->dev,
				 "Detected SiS 180/181/964 chipset in SATA mode\n");
			port2_start = 64;
		} else {
			dev_info(&pdev->dev,
				 "Detected SiS 180/181 chipset in combined mode\n");
			port2_start = 0;
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		}
		break;

	case 0x0182:
	case 0x0183:
		pci_read_config_dword(pdev, 0x6C, &val);
		if (val & (1L << 31)) {
			dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		} else {
			dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
		}
		break;

	case 0x1182:
		dev_info(&pdev->dev,
			 "Detected SiS 1182/966/680 SATA controller\n");
		pi.flags |= ATA_FLAG_SLAVE_POSS;
		break;

	case 0x1183:
		dev_info(&pdev->dev,
			 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
		ppi[0] = &sis_info133_for_sata;
		ppi[1] = &sis_info133_for_sata;
		break;
	}

	rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
	if (rc)
		return rc;

	for (i = 0; i < 2; i++) {
		struct ata_port *ap = host->ports[i];

		if (ap->flags & ATA_FLAG_SATA &&
		    ap->flags & ATA_FLAG_SLAVE_POSS) {
			rc = ata_slave_link_init(ap);
			if (rc)
				return rc;
		}
	}

	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
		void __iomem *mmio;

		rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
		if (rc)
			return rc;
		mmio = host->iomap[SIS_SCR_PCI_BAR];

		host->ports[0]->ioaddr.scr_addr = mmio;
		host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
	}

	pci_set_master(pdev);
	pci_intx(pdev, 1);
	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &sis_sht);
}

module_pci_driver(sis_pci_driver);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sis.c - Silicon Integrated Systems SATA
	3	*
	4	* Maintained by: Uwe Koziolek
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 Uwe Koziolek
	9	*
af36d7f0 JG	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; see the file COPYING. If not, write to
	23	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	24	*
	25	*
	26	* libata documentation is available via 'make {ps\|pdf}docs',
	27	* as Documentation/DocBook/libata.*
	28	*
	29	* Hardware documentation available under NDA.
1da177e4 LT	30	*
	31	*/
	32
1da177e4 LT	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/pci.h>
	36	#include <linux/init.h>
	37	#include <linux/blkdev.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
a9524a76	40	#include <linux/device.h>
1da177e4 LT	41	#include <scsi/scsi_host.h>
1da177e4 LT	42	#include <linux/libata.h>
4bb64fb9	43	#include "sis.h"
1da177e4 LT	44
1da177e4 LT	45	#define DRV_NAME "sata_sis"
2a3103ce	46	#define DRV_VERSION "1.0"
1da177e4 LT	47
	48	enum {
	49	sis_180 = 0,
	50	SIS_SCR_PCI_BAR = 5,
	51
	52	/* PCI configuration registers */
	53	SIS_GENCTL = 0x54, /* IDE General Control register */
	54	SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
f2c853bc AP	55	SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
	56	SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
	57	SIS_PMR = 0x90, /* port mapping register */
8add7885	58	SIS_PMR_COMBINED = 0x30,
1da177e4 LT	59
	60	/* random bits */
	61	SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
	62
	63	GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
	64	};
	65
5796d1c4	66	static int sis_init_one(struct pci_dev pdev, const struct pci_device_id ent);
82ef04fb TH	67	static int sis_scr_read(struct ata_link link, unsigned int sc_reg, u32 val);
82ef04fb TH	68	static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
1da177e4	69
3b7d697d	70	static const struct pci_device_id sis_pci_tbl[] = {
5796d1c4 JG	71	{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
	72	{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
	73	{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
	74	{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
	75	{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
	76	{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
2d2744fc	77
1da177e4 LT	78	{ } /* terminate list */
	79	};
	80
1da177e4 LT	81	static struct pci_driver sis_pci_driver = {
	82	.name = DRV_NAME,
	83	.id_table = sis_pci_tbl,
	84	.probe = sis_init_one,
	85	.remove = ata_pci_remove_one,
	86	};
	87
193515d5	88	static struct scsi_host_template sis_sht = {
68d1d07b	89	ATA_BMDMA_SHT(DRV_NAME),
1da177e4 LT	90	};
1da177e4 LT	91
029cfd6b TH	92	static struct ata_port_operations sis_ops = {
029cfd6b TH	93	.inherits = &ata_bmdma_port_ops,
1da177e4 LT	94	.scr_read = sis_scr_read,
1da177e4 LT	95	.scr_write = sis_scr_write,
1da177e4 LT	96	};
1da177e4 LT	97
1626aeb8	98	static const struct ata_port_info sis_port_info = {
9cbe056f	99	.flags = ATA_FLAG_SATA,
14bdef98 EIB	100	.pio_mask = ATA_PIO4,
14bdef98 EIB	101	.mwdma_mask = ATA_MWDMA2,
bf6263a8	102	.udma_mask = ATA_UDMA6,
1da177e4 LT	103	.port_ops = &sis_ops,
	104	};
	105
1da177e4	106	MODULE_AUTHOR("Uwe Koziolek");
142924cf	107	MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
1da177e4 LT	108	MODULE_LICENSE("GPL");
	109	MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
	110	MODULE_VERSION(DRV_VERSION);
	111
72fee382	112	static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
1da177e4	113	{
72fee382	114	struct ata_port *ap = link->ap;
9b14dec5	115	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4	116	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
9b14dec5	117	u8 pmr;
1da177e4	118
9b14dec5	119	if (ap->port_no) {
3f3e7313	120	switch (pdev->device) {
5796d1c4 JG	121	case 0x0180:
	122	case 0x0181:
	123	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	124	if ((pmr & SIS_PMR_COMBINED) == 0)
	125	addr += SIS180_SATA1_OFS;
	126	break;
	127
	128	case 0x0182:
	129	case 0x0183:
	130	case 0x1182:
	131	addr += SIS182_SATA1_OFS;
	132	break;
3f3e7313	133	}
8add7885	134	}
72fee382 TH	135	if (link->pmp)
	136	addr += 0x10;
	137
1da177e4 LT	138	return addr;
	139	}
	140
82ef04fb TH	141	static u32 sis_scr_cfg_read(struct ata_link *link,
82ef04fb TH	142	unsigned int sc_reg, u32 *val)
1da177e4	143	{
82ef04fb	144	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
72fee382	145	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
1da177e4 LT	146
1da177e4 LT	147	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
8e5443a0	148	return -EINVAL;
f2c853bc	149
aaa092a1	150	pci_read_config_dword(pdev, cfg_addr, val);
aaa092a1	151	return 0;
1da177e4 LT	152	}
1da177e4 LT	153
82ef04fb TH	154	static int sis_scr_cfg_write(struct ata_link *link,
82ef04fb TH	155	unsigned int sc_reg, u32 val)
1da177e4	156	{
82ef04fb	157	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
72fee382	158	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
8add7885	159
1da177e4	160	pci_write_config_dword(pdev, cfg_addr, val);
8e5443a0	161	return 0;
1da177e4 LT	162	}
1da177e4 LT	163
82ef04fb	164	static int sis_scr_read(struct ata_link link, unsigned int sc_reg, u32 val)
1da177e4	165	{
82ef04fb	166	struct ata_port *ap = link->ap;
72fee382	167	void __iomem base = ap->ioaddr.scr_addr + link->pmp 0x10;
f2c853bc	168
1da177e4	169	if (sc_reg > SCR_CONTROL)
da3dbb17	170	return -EINVAL;
1da177e4 LT	171
1da177e4 LT	172	if (ap->flags & SIS_FLAG_CFGSCR)
82ef04fb	173	return sis_scr_cfg_read(link, sc_reg, val);
f2c853bc	174
72fee382	175	val = ioread32(base + sc_reg 4);
da3dbb17	176	return 0;
1da177e4 LT	177	}
1da177e4 LT	178
82ef04fb	179	static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
1da177e4	180	{
82ef04fb	181	struct ata_port *ap = link->ap;
72fee382	182	void __iomem base = ap->ioaddr.scr_addr + link->pmp 0x10;
f2c853bc	183
1da177e4	184	if (sc_reg > SCR_CONTROL)
da3dbb17	185	return -EINVAL;
1da177e4 LT	186
1da177e4 LT	187	if (ap->flags & SIS_FLAG_CFGSCR)
82ef04fb	188	return sis_scr_cfg_write(link, sc_reg, val);
72fee382 TH	189
	190	iowrite32(val, base + (sc_reg * 4));
	191	return 0;
1da177e4 LT	192	}
1da177e4 LT	193
5796d1c4	194	static int sis_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4	195	{
9a829ccf	196	struct ata_port_info pi = sis_port_info;
ddfc87a0	197	const struct ata_port_info *ppi[] = { &pi, &pi };
9a829ccf	198	struct ata_host *host;
4adccf6f	199	u32 genctl, val;
f2c853bc	200	u8 pmr;
3f3e7313	201	u8 port2_start = 0x20;
72fee382	202	int i, rc;
1da177e4	203
06296a1e	204	ata_print_version_once(&pdev->dev, DRV_VERSION);
a9524a76	205
24dc5f33	206	rc = pcim_enable_device(pdev);
1da177e4 LT	207	if (rc)
	208	return rc;
	209
1da177e4 LT	210	/* check and see if the SCRs are in IO space or PCI cfg space */
	211	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	212	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
cf0e812f	213	pi.flags \|= SIS_FLAG_CFGSCR;
8a60a071	214
1da177e4 LT	215	/* if hardware thinks SCRs are in IO space, but there are
	216	* no IO resources assigned, change to PCI cfg space.
	217	*/
cf0e812f	218	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
1da177e4 LT	219	((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) \|\|
	220	(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
	221	genctl &= ~GENCTL_IOMAPPED_SCR;
	222	pci_write_config_dword(pdev, SIS_GENCTL, genctl);
cf0e812f	223	pi.flags \|= SIS_FLAG_CFGSCR;
1da177e4 LT	224	}
1da177e4 LT	225
f2c853bc	226	pci_read_config_byte(pdev, SIS_PMR, &pmr);
3f3e7313 UK	227	switch (ent->device) {
	228	case 0x0180:
	229	case 0x0181:
9b14dec5 AC	230
	231	/* The PATA-handling is provided by pata_sis */
	232	switch (pmr & 0x30) {
	233	case 0x10:
a3cabb27	234	ppi[1] = &sis_info133_for_sata;
9b14dec5	235	break;
a84471fe	236
9b14dec5	237	case 0x30:
a3cabb27	238	ppi[0] = &sis_info133_for_sata;
9b14dec5 AC	239	break;
9b14dec5 AC	240	}
f2c853bc	241	if ((pmr & SIS_PMR_COMBINED) == 0) {
a44fec1f JP	242	dev_info(&pdev->dev,
a44fec1f JP	243	"Detected SiS 180/181/964 chipset in SATA mode\n");
39eb936c	244	port2_start = 64;
3f3e7313	245	} else {
a44fec1f JP	246	dev_info(&pdev->dev,
a44fec1f JP	247	"Detected SiS 180/181 chipset in combined mode\n");
5796d1c4	248	port2_start = 0;
4adccf6f	249	pi.flags \|= ATA_FLAG_SLAVE_POSS;
f2c853bc	250	}
3f3e7313	251	break;
f20b16ff	252
3f3e7313 UK	253	case 0x0182:
3f3e7313 UK	254	case 0x0183:
5796d1c4	255	pci_read_config_dword(pdev, 0x6C, &val);
4adccf6f	256	if (val & (1L << 31)) {
a44fec1f	257	dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
4adccf6f	258	pi.flags \|= ATA_FLAG_SLAVE_POSS;
3f3e7313	259	} else {
a44fec1f	260	dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
3f3e7313 UK	261	}
	262	break;
	263
	264	case 0x1182:
a44fec1f JP	265	dev_info(&pdev->dev,
a44fec1f JP	266	"Detected SiS 1182/966/680 SATA controller\n");
a3cabb27 UK	267	pi.flags \|= ATA_FLAG_SLAVE_POSS;
	268	break;
	269
3f3e7313	270	case 0x1183:
a44fec1f JP	271	dev_info(&pdev->dev,
a44fec1f JP	272	"Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
a3cabb27 UK	273	ppi[0] = &sis_info133_for_sata;
a3cabb27 UK	274	ppi[1] = &sis_info133_for_sata;
3f3e7313	275	break;
f2c853bc AP	276	}
f2c853bc AP	277
1c5afdf7	278	rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
9a829ccf TH	279	if (rc)
9a829ccf TH	280	return rc;
cf0e812f	281
72fee382 TH	282	for (i = 0; i < 2; i++) {
	283	struct ata_port *ap = host->ports[i];
	284
	285	if (ap->flags & ATA_FLAG_SATA &&
	286	ap->flags & ATA_FLAG_SLAVE_POSS) {
	287	rc = ata_slave_link_init(ap);
	288	if (rc)
	289	return rc;
	290	}
	291	}
	292
9a829ccf	293	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
edceec3d	294	void __iomem *mmio;
0d5ff566	295
9a829ccf TH	296	rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
	297	if (rc)
	298	return rc;
	299	mmio = host->iomap[SIS_SCR_PCI_BAR];
0d5ff566	300
9a829ccf TH	301	host->ports[0]->ioaddr.scr_addr = mmio;
9a829ccf TH	302	host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
1da177e4 LT	303	}
	304
	305	pci_set_master(pdev);
a04ce0ff	306	pci_intx(pdev, 1);
c3b28894	307	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382	308	IRQF_SHARED, &sis_sht);
1da177e4 LT	309	}
1da177e4 LT	310
2fc75da0	311	module_pci_driver(sis_pci_driver);