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libata: implement and use SHT initializers
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ata / sata_sil.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
af36d7f0 8 * Copyright 2003-2005 Red Hat, Inc.
1da177e4
LT		 9 * Copyright 2003 Benjamin Herrenschmidt
10 *
af36d7f0
JG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
1da177e4 29 *
953d1137
JG		 30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
1da177e4
LT		 35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/blkdev.h>
42#include <linux/delay.h>
43#include <linux/interrupt.h>
a9524a76 44#include <linux/device.h>
1da177e4
LT		 45#include <scsi/scsi_host.h>
46#include <linux/libata.h>
47
48#define DRV_NAME "sata_sil"
2a3103ce 49#define DRV_VERSION "2.3"
1da177e4
LT		 50
51enum {
0d5ff566
TH		 52 SIL_MMIO_BAR = 5,
53
e653a1e6
TH		 54 /*
55 * host flags
56 */
201ce859 57 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
e4e10e3e 58 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
e4deec63 59 SIL_FLAG_MOD15WRITE = (1 << 30),
20888d83 60
cca3974e 61 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
0c88758b 62 ATA_FLAG_MMIO,
e4deec63 63
e653a1e6
TH		 64 /*
65 * Controller IDs
66 */
1da177e4 67 sil_3112 = 0,
201ce859
TH		 68 sil_3112_no_sata_irq = 1,
69 sil_3512 = 2,
70 sil_3114 = 3,
1da177e4 71
e653a1e6
TH		 72 /*
73 * Register offsets
74 */
1da177e4 75 SIL_SYSCFG = 0x48,
e653a1e6
TH		 76
77 /*
78 * Register bits
79 */
80 /* SYSCFG */
1da177e4
LT		 81 SIL_MASK_IDE0_INT = (1 << 22),
82 SIL_MASK_IDE1_INT = (1 << 23),
83 SIL_MASK_IDE2_INT = (1 << 24),
84 SIL_MASK_IDE3_INT = (1 << 25),
85 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
86 SIL_MASK_4PORT = SIL_MASK_2PORT |
87 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
88
e653a1e6 89 /* BMDMA/BMDMA2 */
1da177e4 90 SIL_INTR_STEERING = (1 << 1),
e653a1e6 91
20888d83
TH		 92 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
93 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
94 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
95 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
96 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
97 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
98 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
99 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
100 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
101 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
102
103 /* SIEN */
104 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
105
e653a1e6
TH		 106 /*
107 * Others
108 */
1da177e4
LT		 109 SIL_QUIRK_MOD15WRITE = (1 << 0),
110 SIL_QUIRK_UDMA5MAX = (1 << 1),
111};
112
5796d1c4 113static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
281d426c 114#ifdef CONFIG_PM
afb5a7cb 115static int sil_pci_device_resume(struct pci_dev *pdev);
281d426c 116#endif
cd0d3bbc 117static void sil_dev_config(struct ata_device *dev);
da3dbb17
TH		 118static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
119static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
0260731f 120static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
f6aae27e
TH		 121static void sil_freeze(struct ata_port *ap);
122static void sil_thaw(struct ata_port *ap);
1da177e4 123
374b1873 124
3b7d697d 125static const struct pci_device_id sil_pci_tbl[] = {
54bb3a94
JG		 126 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
127 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
128 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
129 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
130 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
131 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
132 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
133
1da177e4
LT		 134 { } /* terminate list */
135};
136
137
138/* TODO firmware versions should be added - eric */
139static const struct sil_drivelist {
5796d1c4 140 const char *product;
1da177e4
LT		 141 unsigned int quirk;
142} sil_blacklist [] = {
143 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
144 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
145 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
146 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
1da177e4
LT		 147 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
148 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
1da177e4
LT		 149 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
150 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
154 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
155 { }
156};
157
158static struct pci_driver sil_pci_driver = {
159 .name = DRV_NAME,
160 .id_table = sil_pci_tbl,
161 .probe = sil_init_one,
162 .remove = ata_pci_remove_one,
281d426c 163#ifdef CONFIG_PM
afb5a7cb
TH		 164 .suspend = ata_pci_device_suspend,
165 .resume = sil_pci_device_resume,
281d426c 166#endif
1da177e4
LT		 167};
168
193515d5 169static struct scsi_host_template sil_sht = {
68d1d07b 170 ATA_BMDMA_SHT(DRV_NAME),
1da177e4
LT		 171};
172
057ace5e 173static const struct ata_port_operations sil_ops = {
1da177e4
LT		 174 .dev_config = sil_dev_config,
175 .tf_load = ata_tf_load,
176 .tf_read = ata_tf_read,
177 .check_status = ata_check_status,
178 .exec_command = ata_exec_command,
179 .dev_select = ata_std_dev_select,
9d2c7c75 180 .set_mode = sil_set_mode,
6bd99b4e 181 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 182 .bmdma_setup = ata_bmdma_setup,
183 .bmdma_start = ata_bmdma_start,
184 .bmdma_stop = ata_bmdma_stop,
185 .bmdma_status = ata_bmdma_status,
186 .qc_prep = ata_qc_prep,
187 .qc_issue = ata_qc_issue_prot,
0d5ff566 188 .data_xfer = ata_data_xfer,
f6aae27e
TH		 189 .freeze = sil_freeze,
190 .thaw = sil_thaw,
191 .error_handler = ata_bmdma_error_handler,
192 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4 193 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 194 .irq_on = ata_irq_on,
1da177e4
LT		 195 .scr_read = sil_scr_read,
196 .scr_write = sil_scr_write,
6bd99b4e 197 .port_start = ata_sff_port_start,
1da177e4
LT		 198};
199
98ac62de 200static const struct ata_port_info sil_port_info[] = {
1da177e4 201 /* sil_3112 */
e4deec63 202 {
cca3974e 203 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
e4deec63
TH		 204 .pio_mask = 0x1f, /* pio0-4 */
205 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 206 .udma_mask = ATA_UDMA5,
e4deec63 207 .port_ops = &sil_ops,
0ee304d5 208 },
201ce859
TH		 209 /* sil_3112_no_sata_irq */
210 {
cca3974e 211 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
201ce859
TH		 212 SIL_FLAG_NO_SATA_IRQ,
213 .pio_mask = 0x1f, /* pio0-4 */
214 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 215 .udma_mask = ATA_UDMA5,
201ce859
TH		 216 .port_ops = &sil_ops,
217 },
0ee304d5 218 /* sil_3512 */
1da177e4 219 {
cca3974e 220 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
0ee304d5
TH		 221 .pio_mask = 0x1f, /* pio0-4 */
222 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 223 .udma_mask = ATA_UDMA5,
0ee304d5
TH		 224 .port_ops = &sil_ops,
225 },
226 /* sil_3114 */
1da177e4 227 {
cca3974e 228 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
1da177e4
LT		 229 .pio_mask = 0x1f, /* pio0-4 */
230 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 231 .udma_mask = ATA_UDMA5,
1da177e4
LT		 232 .port_ops = &sil_ops,
233 },
234};
235
236/* per-port register offsets */
237/* TODO: we can probably calculate rather than use a table */
238static const struct {
239 unsigned long tf; /* ATA taskfile register block */
240 unsigned long ctl; /* ATA control/altstatus register block */
241 unsigned long bmdma; /* DMA register block */
20888d83 242 unsigned long bmdma2; /* DMA register block #2 */
48d4ef2a 243 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
1da177e4
LT		 244 unsigned long scr; /* SATA control register block */
245 unsigned long sien; /* SATA Interrupt Enable register */
246 unsigned long xfer_mode;/* data transfer mode register */
e4e10e3e 247 unsigned long sfis_cfg; /* SATA FIS reception config register */
1da177e4
LT		 248} sil_port[] = {
249 /* port 0 ... */
5bcd7a00
JG		 250 /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
251 { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
252 { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
20888d83
TH		 253 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
254 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
1da177e4
LT		 255 /* ... port 3 */
256};
257
258MODULE_AUTHOR("Jeff Garzik");
259MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
260MODULE_LICENSE("GPL");
261MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
262MODULE_VERSION(DRV_VERSION);
263
5796d1c4 264static int slow_down;
51e9f2ff
JG		 265module_param(slow_down, int, 0444);
266MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
267
374b1873 268
1da177e4
LT		 269static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
270{
271 u8 cache_line = 0;
272 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
273 return cache_line;
274}
275
9d2c7c75
AC		 276/**
277 * sil_set_mode - wrap set_mode functions
0260731f 278 * @link: link to set up
9d2c7c75
AC		 279 * @r_failed: returned device when we fail
280 *
281 * Wrap the libata method for device setup as after the setup we need
282 * to inspect the results and do some configuration work
283 */
284
0260731f 285static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
1da177e4 286{
0260731f
TH		 287 struct ata_port *ap = link->ap;
288 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
0d5ff566 289 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
0260731f 290 struct ata_device *dev;
f58229f8 291 u32 tmp, dev_mode[2] = { };
9d2c7c75 292 int rc;
a617c09f 293
0260731f 294 rc = ata_do_set_mode(link, r_failed);
9d2c7c75
AC		 295 if (rc)
296 return rc;
1da177e4 297
0260731f 298 ata_link_for_each_dev(dev, link) {
e1211e3f 299 if (!ata_dev_enabled(dev))
f58229f8 300 dev_mode[dev->devno] = 0; /* PIO0/1/2 */
1da177e4 301 else if (dev->flags & ATA_DFLAG_PIO)
f58229f8 302 dev_mode[dev->devno] = 1; /* PIO3/4 */
1da177e4 303 else
f58229f8 304 dev_mode[dev->devno] = 3; /* UDMA */
1da177e4
LT		 305 /* value 2 indicates MDMA */
306 }
307
308 tmp = readl(addr);
309 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
310 tmp |= dev_mode[0];
311 tmp |= (dev_mode[1] << 4);
312 writel(tmp, addr);
313 readl(addr); /* flush */
9d2c7c75 314 return 0;
1da177e4
LT		 315}
316
5796d1c4
JG		 317static inline void __iomem *sil_scr_addr(struct ata_port *ap,
318 unsigned int sc_reg)
1da177e4 319{
0d5ff566 320 void __iomem *offset = ap->ioaddr.scr_addr;
1da177e4
LT		 321
322 switch (sc_reg) {
323 case SCR_STATUS:
324 return offset + 4;
325 case SCR_ERROR:
326 return offset + 8;
327 case SCR_CONTROL:
328 return offset;
329 default:
330 /* do nothing */
331 break;
332 }
333
8d9db2d2 334 return NULL;
1da177e4
LT		 335}
336
da3dbb17 337static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 338{
0d5ff566 339 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
da3dbb17
TH		 340
341 if (mmio) {
342 *val = readl(mmio);
343 return 0;
344 }
345 return -EINVAL;
1da177e4
LT		 346}
347
da3dbb17 348static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4 349{
0d5ff566 350 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
da3dbb17
TH		 351
352 if (mmio) {
1da177e4 353 writel(val, mmio);
da3dbb17
TH		 354 return 0;
355 }
356 return -EINVAL;
1da177e4
LT		 357}
358
cbe88fbc
TH		 359static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
360{
9af5c9c9
TH		 361 struct ata_eh_info *ehi = &ap->link.eh_info;
362 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
cbe88fbc
TH		 363 u8 status;
364
e573890b 365 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
d4c85325
TH		 366 u32 serror;
367
368 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
369 * controllers continue to assert IRQ as long as
370 * SError bits are pending. Clear SError immediately.
371 */
da3dbb17 372 sil_scr_read(ap, SCR_ERROR, &serror);
d4c85325
TH		 373 sil_scr_write(ap, SCR_ERROR, serror);
374
8cf32ac6
TH		 375 /* Sometimes spurious interrupts occur, double check
376 * it's PHYRDY CHG.
d4c85325 377 */
8cf32ac6 378 if (serror & SERR_PHYRDY_CHG) {
f7fe7ad4 379 ap->link.eh_info.serror |= serror;
8cf32ac6 380 goto freeze;
d4c85325
TH		 381 }
382
8cf32ac6
TH		 383 if (!(bmdma2 & SIL_DMA_COMPLETE))
384 return;
e573890b
TH		 385 }
386
8cf32ac6 387 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
e2f8fb72
TH		 388 /* this sometimes happens, just clear IRQ */
389 ata_chk_status(ap);
390 return;
391 }
392
cbe88fbc
TH		 393 /* Check whether we are expecting interrupt in this state */
394 switch (ap->hsm_task_state) {
395 case HSM_ST_FIRST:
396 /* Some pre-ATAPI-4 devices assert INTRQ
397 * at this state when ready to receive CDB.
398 */
399
400 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
405e66b3
TH		 401 * The flag was turned on only for atapi devices. No
402 * need to check ata_is_atapi(qc->tf.protocol) again.
cbe88fbc
TH		 403 */
404 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
405 goto err_hsm;
406 break;
407 case HSM_ST_LAST:
405e66b3 408 if (ata_is_dma(qc->tf.protocol)) {
cbe88fbc
TH		 409 /* clear DMA-Start bit */
410 ap->ops->bmdma_stop(qc);
411
412 if (bmdma2 & SIL_DMA_ERROR) {
413 qc->err_mask |= AC_ERR_HOST_BUS;
414 ap->hsm_task_state = HSM_ST_ERR;
415 }
416 }
417 break;
418 case HSM_ST:
419 break;
420 default:
421 goto err_hsm;
422 }
423
424 /* check main status, clearing INTRQ */
425 status = ata_chk_status(ap);
426 if (unlikely(status & ATA_BUSY))
427 goto err_hsm;
428
429 /* ack bmdma irq events */
430 ata_bmdma_irq_clear(ap);
431
432 /* kick HSM in the ass */
433 ata_hsm_move(ap, qc, status, 0);
434
405e66b3 435 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
ea54763f
TH		 436 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
437
cbe88fbc
TH		 438 return;
439
440 err_hsm:
441 qc->err_mask |= AC_ERR_HSM;
442 freeze:
443 ata_port_freeze(ap);
444}
445
7d12e780 446static irqreturn_t sil_interrupt(int irq, void *dev_instance)
cbe88fbc 447{
cca3974e 448 struct ata_host *host = dev_instance;
0d5ff566 449 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
cbe88fbc
TH		 450 int handled = 0;
451 int i;
452
cca3974e 453 spin_lock(&host->lock);
cbe88fbc 454
cca3974e
JG		 455 for (i = 0; i < host->n_ports; i++) {
456 struct ata_port *ap = host->ports[i];
cbe88fbc
TH		 457 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
458
459 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
460 continue;
461
201ce859
TH		 462 /* turn off SATA_IRQ if not supported */
463 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
464 bmdma2 &= ~SIL_DMA_SATA_IRQ;
465
23fa9618
TH		 466 if (bmdma2 == 0xffffffff ||
467 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
cbe88fbc
TH		 468 continue;
469
470 sil_host_intr(ap, bmdma2);
471 handled = 1;
472 }
473
cca3974e 474 spin_unlock(&host->lock);
cbe88fbc
TH		 475
476 return IRQ_RETVAL(handled);
477}
478
f6aae27e
TH		 479static void sil_freeze(struct ata_port *ap)
480{
0d5ff566 481 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
f6aae27e
TH		 482 u32 tmp;
483
e573890b
TH		 484 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
485 writel(0, mmio_base + sil_port[ap->port_no].sien);
486
f6aae27e
TH		 487 /* plug IRQ */
488 tmp = readl(mmio_base + SIL_SYSCFG);
489 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
490 writel(tmp, mmio_base + SIL_SYSCFG);
491 readl(mmio_base + SIL_SYSCFG); /* flush */
492}
493
494static void sil_thaw(struct ata_port *ap)
495{
0d5ff566 496 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
f6aae27e
TH		 497 u32 tmp;
498
499 /* clear IRQ */
500 ata_chk_status(ap);
501 ata_bmdma_irq_clear(ap);
502
201ce859
TH		 503 /* turn on SATA IRQ if supported */
504 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
505 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
e573890b 506
f6aae27e
TH		 507 /* turn on IRQ */
508 tmp = readl(mmio_base + SIL_SYSCFG);
509 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
510 writel(tmp, mmio_base + SIL_SYSCFG);
511}
512
1da177e4
LT		 513/**
514 * sil_dev_config - Apply device/host-specific errata fixups
1da177e4
LT		 515 * @dev: Device to be examined
516 *
517 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
518 * device is known to be present, this function is called.
519 * We apply two errata fixups which are specific to Silicon Image,
520 * a Seagate and a Maxtor fixup.
521 *
522 * For certain Seagate devices, we must limit the maximum sectors
523 * to under 8K.
524 *
525 * For certain Maxtor devices, we must not program the drive
526 * beyond udma5.
527 *
528 * Both fixups are unfairly pessimistic. As soon as I get more
529 * information on these errata, I will create a more exhaustive
530 * list, and apply the fixups to only the specific
531 * devices/hosts/firmwares that need it.
532 *
533 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
534 * The Maxtor quirk is in the blacklist, but I'm keeping the original
535 * pessimistic fix for the following reasons...
536 * - There seems to be less info on it, only one device gleaned off the
537 * Windows driver, maybe only one is affected. More info would be greatly
538 * appreciated.
539 * - But then again UDMA5 is hardly anything to complain about
540 */
cd0d3bbc 541static void sil_dev_config(struct ata_device *dev)
1da177e4 542{
9af5c9c9
TH		 543 struct ata_port *ap = dev->link->ap;
544 int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO;
1da177e4 545 unsigned int n, quirks = 0;
a0cf733b 546 unsigned char model_num[ATA_ID_PROD_LEN + 1];
1da177e4 547
a0cf733b 548 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
1da177e4 549
8a60a071 550 for (n = 0; sil_blacklist[n].product; n++)
2e02671d 551 if (!strcmp(sil_blacklist[n].product, model_num)) {
1da177e4
LT		 552 quirks = sil_blacklist[n].quirk;
553 break;
554 }
8a60a071 555
1da177e4 556 /* limit requests to 15 sectors */
51e9f2ff
JG		 557 if (slow_down ||
558 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
559 (quirks & SIL_QUIRK_MOD15WRITE))) {
efdaedc4
TH		 560 if (print_info)
561 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
562 "errata fix (mod15write workaround)\n");
b00eec1d 563 dev->max_sectors = 15;
1da177e4
LT		 564 return;
565 }
566
567 /* limit to udma5 */
568 if (quirks & SIL_QUIRK_UDMA5MAX) {
efdaedc4
TH		 569 if (print_info)
570 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
571 "errata fix %s\n", model_num);
5a529139 572 dev->udma_mask &= ATA_UDMA5;
1da177e4
LT		 573 return;
574 }
575}
576
4447d351 577static void sil_init_controller(struct ata_host *host)
3d8ec913 578{
4447d351
TH		 579 struct pci_dev *pdev = to_pci_dev(host->dev);
580 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
3d8ec913
TH		 581 u8 cls;
582 u32 tmp;
583 int i;
584
585 /* Initialize FIFO PCI bus arbitration */
586 cls = sil_get_device_cache_line(pdev);
587 if (cls) {
588 cls >>= 3;
589 cls++; /* cls = (line_size/8)+1 */
4447d351 590 for (i = 0; i < host->n_ports; i++)
3d8ec913
TH		 591 writew(cls << 8 | cls,
592 mmio_base + sil_port[i].fifo_cfg);
593 } else
594 dev_printk(KERN_WARNING, &pdev->dev,
595 "cache line size not set. Driver may not function\n");
596
597 /* Apply R_ERR on DMA activate FIS errata workaround */
4447d351 598 if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
3d8ec913
TH		 599 int cnt;
600
4447d351 601 for (i = 0, cnt = 0; i < host->n_ports; i++) {
3d8ec913
TH		 602 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
603 if ((tmp & 0x3) != 0x01)
604 continue;
605 if (!cnt)
606 dev_printk(KERN_INFO, &pdev->dev,
607 "Applying R_ERR on DMA activate "
608 "FIS errata fix\n");
609 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
610 cnt++;
611 }
612 }
613
4447d351 614 if (host->n_ports == 4) {
3d8ec913
TH		 615 /* flip the magic "make 4 ports work" bit */
616 tmp = readl(mmio_base + sil_port[2].bmdma);
617 if ((tmp & SIL_INTR_STEERING) == 0)
618 writel(tmp | SIL_INTR_STEERING,
619 mmio_base + sil_port[2].bmdma);
620 }
621}
622
5796d1c4 623static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 624{
625 static int printed_version;
4447d351
TH		 626 int board_id = ent->driver_data;
627 const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL };
628 struct ata_host *host;
ea6ba10b 629 void __iomem *mmio_base;
4447d351 630 int n_ports, rc;
1da177e4 631 unsigned int i;
1da177e4
LT		 632
633 if (!printed_version++)
a9524a76 634 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 635
4447d351
TH		 636 /* allocate host */
637 n_ports = 2;
638 if (board_id == sil_3114)
639 n_ports = 4;
640
641 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
642 if (!host)
643 return -ENOMEM;
644
645 /* acquire resources and fill host */
24dc5f33 646 rc = pcim_enable_device(pdev);
1da177e4
LT		 647 if (rc)
648 return rc;
649
0d5ff566
TH		 650 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
651 if (rc == -EBUSY)
24dc5f33 652 pcim_pin_device(pdev);
0d5ff566 653 if (rc)
24dc5f33 654 return rc;
4447d351 655 host->iomap = pcim_iomap_table(pdev);
1da177e4
LT		 656
657 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
658 if (rc)
24dc5f33 659 return rc;
1da177e4
LT		 660 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
661 if (rc)
24dc5f33 662 return rc;
1da177e4 663
4447d351 664 mmio_base = host->iomap[SIL_MMIO_BAR];
1da177e4 665
4447d351 666 for (i = 0; i < host->n_ports; i++) {
cbcdd875
TH		 667 struct ata_port *ap = host->ports[i];
668 struct ata_ioports *ioaddr = &ap->ioaddr;
4447d351
TH		 669
670 ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
671 ioaddr->altstatus_addr =
672 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
673 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
674 ioaddr->scr_addr = mmio_base + sil_port[i].scr;
675 ata_std_ports(ioaddr);
cbcdd875
TH		 676
677 ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio");
678 ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf");
1da177e4
LT		 679 }
680
4447d351
TH		 681 /* initialize and activate */
682 sil_init_controller(host);
1da177e4 683
1da177e4 684 pci_set_master(pdev);
4447d351
TH		 685 return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
686 &sil_sht);
1da177e4
LT		 687}
688
281d426c 689#ifdef CONFIG_PM
afb5a7cb
TH		 690static int sil_pci_device_resume(struct pci_dev *pdev)
691{
cca3974e 692 struct ata_host *host = dev_get_drvdata(&pdev->dev);
553c4aa6
TH		 693 int rc;
694
695 rc = ata_pci_device_do_resume(pdev);
696 if (rc)
697 return rc;
afb5a7cb 698
4447d351 699 sil_init_controller(host);
cca3974e 700 ata_host_resume(host);
afb5a7cb
TH		 701
702 return 0;
703}
281d426c 704#endif
afb5a7cb 705
1da177e4
LT		 706static int __init sil_init(void)
707{
b7887196 708 return pci_register_driver(&sil_pci_driver);
1da177e4
LT		 709}
710
711static void __exit sil_exit(void)
712{
713 pci_unregister_driver(&sil_pci_driver);
714}
715
716
717module_init(sil_init);
718module_exit(sil_exit);