[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / sata_highbank.c

/*
 * Calxeda Highbank AHCI SATA platform driver
 * Copyright 2012 Calxeda, Inc.
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include <linux/ahci_platform.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/export.h>
#include "ahci.h"

#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
#define SERDES_CR_CTL			0x80a0
#define SERDES_CR_ADDR			0x80a1
#define SERDES_CR_DATA			0x80a2
#define CR_BUSY				0x0001
#define CR_START			0x0001
#define CR_WR_RDN			0x0002
#define CPHY_RX_INPUT_STS		0x2002
#define CPHY_SATA_OVERRIDE	 	0x4000
#define CPHY_OVERRIDE			0x2005
#define SPHY_LANE			0x100
#define SPHY_HALF_RATE			0x0001
#define CPHY_SATA_DPLL_MODE		0x0700
#define CPHY_SATA_DPLL_SHIFT		8
#define CPHY_SATA_DPLL_RESET		(1 << 11)
#define CPHY_PHY_COUNT			6
#define CPHY_LANE_COUNT			4
#define CPHY_PORT_COUNT			(CPHY_PHY_COUNT * CPHY_LANE_COUNT)

static DEFINE_SPINLOCK(cphy_lock);
/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
 * sata ports to their phys and then to their lanes within the phys
 */
struct phy_lane_info {
	void __iomem *phy_base;
	u8 lane_mapping;
	u8 phy_devs;
};
static struct phy_lane_info port_data[CPHY_PORT_COUNT];

static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
{
	u32 data;
	u8 dev = port_data[sata_port].phy_devs;
	spin_lock(&cphy_lock);
	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
	spin_unlock(&cphy_lock);
	return data;
}

static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
{
	u8 dev = port_data[sata_port].phy_devs;
	spin_lock(&cphy_lock);
	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
	spin_unlock(&cphy_lock);
}

static void combo_phy_wait_for_ready(u8 sata_port)
{
	while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
		udelay(5);
}

static u32 combo_phy_read(u8 sata_port, u32 addr)
{
	combo_phy_wait_for_ready(sata_port);
	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
	combo_phy_wait_for_ready(sata_port);
	return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
}

static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
{
	combo_phy_wait_for_ready(sata_port);
	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START);
}

static void highbank_cphy_disable_overrides(u8 sata_port)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp;
	if (unlikely(port_data[sata_port].phy_base == NULL))
		return;
	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
	tmp &= ~CPHY_SATA_OVERRIDE;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
}

static void cphy_override_rx_mode(u8 sata_port, u32 val)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp;
	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
	tmp &= ~CPHY_SATA_OVERRIDE;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp |= CPHY_SATA_OVERRIDE;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp &= ~CPHY_SATA_DPLL_MODE;
	tmp |= val << CPHY_SATA_DPLL_SHIFT;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp |= CPHY_SATA_DPLL_RESET;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp &= ~CPHY_SATA_DPLL_RESET;
	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);

	msleep(15);
}

static void highbank_cphy_override_lane(u8 sata_port)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp, k = 0;

	if (unlikely(port_data[sata_port].phy_base == NULL))
		return;
	do {
		tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
						lane * SPHY_LANE);
	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
	cphy_override_rx_mode(sata_port, 3);
}

static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
{
	struct device_node *sata_node = dev->of_node;
	int phy_count = 0, phy, port = 0;
	void __iomem *cphy_base[CPHY_PHY_COUNT];
	struct device_node *phy_nodes[CPHY_PHY_COUNT];
	memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
	memset(phy_nodes, 0, sizeof(struct device_node*) * CPHY_PHY_COUNT);

	do {
		u32 tmp;
		struct of_phandle_args phy_data;
		if (of_parse_phandle_with_args(sata_node,
				"calxeda,port-phys", "#phy-cells",
				port, &phy_data))
			break;
		for (phy = 0; phy < phy_count; phy++) {
			if (phy_nodes[phy] == phy_data.np)
				break;
		}
		if (phy_nodes[phy] == NULL) {
			phy_nodes[phy] = phy_data.np;
			cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
			if (cphy_base[phy] == NULL) {
				return 0;
			}
			phy_count += 1;
		}
		port_data[port].lane_mapping = phy_data.args[0];
		of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
		port_data[port].phy_devs = tmp;
		port_data[port].phy_base = cphy_base[phy];
		of_node_put(phy_data.np);
		port += 1;
	} while (port < CPHY_PORT_COUNT);
	return 0;
}

/*
 * The Calxeda SATA phy intermittently fails to bring up a link with Gen3
 * Retrying the phy hard reset can work around the issue, but the drive
 * may fail again. In less than 150 out of 15000 test runs, it took more
 * than 10 tries for the link to be established (but never more than 35).
 * Triple the maximum observed retry count to provide plenty of margin for
 * rare events and to guarantee that the link is established.
 *
 * Also, the default 2 second time-out on a failed drive is too long in
 * this situation. The uboot implementation of the same driver function
 * uses a much shorter time-out period and never experiences a time out
 * issue. Reducing the time-out to 500ms improves the responsiveness.
 * The other timing constants were kept the same as the stock AHCI driver.
 * This change was also tested 15000 times on 24 drives and none of them
 * experienced a time out.
 */
static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline)
{
	static const unsigned long timing[] = { 5, 100, 500};
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	u32 sstatus;
	int rc;
	int retry = 100;

	ahci_stop_engine(ap);

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	do {
		highbank_cphy_disable_overrides(link->ap->port_no);
		rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
		highbank_cphy_override_lane(link->ap->port_no);

		/* If the status is 1, we are connected, but the link did not
		 * come up. So retry resetting the link again.
		 */
		if (sata_scr_read(link, SCR_STATUS, &sstatus))
			break;
		if (!(sstatus & 0x3))
			break;
	} while (!online && retry--);

	ahci_start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);

	return rc;
}

static struct ata_port_operations ahci_highbank_ops = {
	.inherits		= &ahci_ops,
	.hardreset		= ahci_highbank_hardreset,
};

static const struct ata_port_info ahci_highbank_port_info = {
	.flags          = AHCI_FLAG_COMMON,
	.pio_mask       = ATA_PIO4,
	.udma_mask      = ATA_UDMA6,
	.port_ops       = &ahci_highbank_ops,
};

static struct scsi_host_template ahci_highbank_platform_sht = {
	AHCI_SHT("sata_highbank"),
};

static const struct of_device_id ahci_of_match[] = {
	{ .compatible = "calxeda,hb-ahci" },
	{},
};
MODULE_DEVICE_TABLE(of, ahci_of_match);

static int ahci_highbank_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ata_host *host;
	struct resource *mem;
	int irq;
	int n_ports;
	int i;
	int rc;
	struct ata_port_info pi = ahci_highbank_port_info;
	const struct ata_port_info *ppi[] = { &pi, NULL };

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(dev, "no mmio space\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq <= 0) {
		dev_err(dev, "no irq\n");
		return -EINVAL;
	}

	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	if (!hpriv) {
		dev_err(dev, "can't alloc ahci_host_priv\n");
		return -ENOMEM;
	}

	hpriv->flags |= (unsigned long)pi.private_data;

	hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
	if (!hpriv->mmio) {
		dev_err(dev, "can't map %pR\n", mem);
		return -ENOMEM;
	}

	rc = highbank_initialize_phys(dev, hpriv->mmio);
	if (rc)
		return rc;


	ahci_save_initial_config(dev, hpriv, 0, 0);

	/* prepare host */
	if (hpriv->cap & HOST_CAP_NCQ)
		pi.flags |= ATA_FLAG_NCQ;

	if (hpriv->cap & HOST_CAP_PMP)
		pi.flags |= ATA_FLAG_PMP;

	ahci_set_em_messages(hpriv, &pi);

	/* CAP.NP sometimes indicate the index of the last enabled
	 * port, at other times, that of the last possible port, so
	 * determining the maximum port number requires looking at
	 * both CAP.NP and port_map.
	 */
	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));

	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
	if (!host) {
		rc = -ENOMEM;
		goto err0;
	}

	host->private_data = hpriv;

	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
		host->flags |= ATA_HOST_PARALLEL_SCAN;

	if (pi.flags & ATA_FLAG_EM)
		ahci_reset_em(host);

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];

		ata_port_desc(ap, "mmio %pR", mem);
		ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);

		/* set enclosure management message type */
		if (ap->flags & ATA_FLAG_EM)
			ap->em_message_type = hpriv->em_msg_type;

		/* disabled/not-implemented port */
		if (!(hpriv->port_map & (1 << i)))
			ap->ops = &ata_dummy_port_ops;
	}

	rc = ahci_reset_controller(host);
	if (rc)
		goto err0;

	ahci_init_controller(host);
	ahci_print_info(host, "platform");

	rc = ata_host_activate(host, irq, ahci_interrupt, 0,
					&ahci_highbank_platform_sht);
	if (rc)
		goto err0;

	return 0;
err0:
	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_highbank_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	u32 ctl;
	int rc;

	if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
		dev_err(dev, "firmware update required for suspend/resume\n");
		return -EIO;
	}

	/*
	 * AHCI spec rev1.1 section 8.3.3:
	 * Software must disable interrupts prior to requesting a
	 * transition of the HBA to D3 state.
	 */
	ctl = readl(mmio + HOST_CTL);
	ctl &= ~HOST_IRQ_EN;
	writel(ctl, mmio + HOST_CTL);
	readl(mmio + HOST_CTL); /* flush */

	rc = ata_host_suspend(host, PMSG_SUSPEND);
	if (rc)
		return rc;

	return 0;
}

static int ahci_highbank_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	int rc;

	if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
		rc = ahci_reset_controller(host);
		if (rc)
			return rc;

		ahci_init_controller(host);
	}

	ata_host_resume(host);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
		  ahci_highbank_suspend, ahci_highbank_resume);

static struct platform_driver ahci_highbank_driver = {
	.remove = ata_platform_remove_one,
        .driver = {
                .name = "highbank-ahci",
                .owner = THIS_MODULE,
                .of_match_table = ahci_of_match,
                .pm = &ahci_highbank_pm_ops,
        },
	.probe = ahci_highbank_probe,
};

module_platform_driver(ahci_highbank_driver);

MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("sata:highbank");
Commit	Line	Data
8996b89d ML	1	/*
	2	* Calxeda Highbank AHCI SATA platform driver
	3	* Copyright 2012 Calxeda, Inc.
	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#include <linux/kernel.h>
	20	#include <linux/gfp.h>
	21	#include <linux/module.h>
	22	#include <linux/init.h>
	23	#include <linux/types.h>
	24	#include <linux/err.h>
	25	#include <linux/io.h>
	26	#include <linux/spinlock.h>
	27	#include <linux/device.h>
	28	#include <linux/of_device.h>
	29	#include <linux/of_address.h>
	30	#include <linux/platform_device.h>
	31	#include <linux/libata.h>
	32	#include <linux/ahci_platform.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/delay.h>
	35	#include <linux/export.h>
	36	#include "ahci.h"
	37
	38	#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) \| (((addr) >> 9) & 0x7f))
	39	#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
	40	#define SERDES_CR_CTL 0x80a0
	41	#define SERDES_CR_ADDR 0x80a1
	42	#define SERDES_CR_DATA 0x80a2
	43	#define CR_BUSY 0x0001
	44	#define CR_START 0x0001
	45	#define CR_WR_RDN 0x0002
	46	#define CPHY_RX_INPUT_STS 0x2002
	47	#define CPHY_SATA_OVERRIDE 0x4000
	48	#define CPHY_OVERRIDE 0x2005
	49	#define SPHY_LANE 0x100
	50	#define SPHY_HALF_RATE 0x0001
	51	#define CPHY_SATA_DPLL_MODE 0x0700
	52	#define CPHY_SATA_DPLL_SHIFT 8
	53	#define CPHY_SATA_DPLL_RESET (1 << 11)
	54	#define CPHY_PHY_COUNT 6
	55	#define CPHY_LANE_COUNT 4
	56	#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
	57
	58	static DEFINE_SPINLOCK(cphy_lock);
	59	/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
	60	* sata ports to their phys and then to their lanes within the phys
	61	*/
	62	struct phy_lane_info {
	63	void __iomem *phy_base;
	64	u8 lane_mapping;
65	u8 phy_devs;
66	};
67	static struct phy_lane_info port_data[CPHY_PORT_COUNT];
68
69	static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
70	{
71	u32 data;
72	u8 dev = port_data[sata_port].phy_devs;
73	spin_lock(&cphy_lock);
74	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
75	data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
76	spin_unlock(&cphy_lock);
77	return data;
78	}
79
80	static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
81	{
82	u8 dev = port_data[sata_port].phy_devs;
83	spin_lock(&cphy_lock);
84	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
85	writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
86	spin_unlock(&cphy_lock);
87	}
88
89	static void combo_phy_wait_for_ready(u8 sata_port)
90	{
91	while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
92	udelay(5);
93	}
94
95	static u32 combo_phy_read(u8 sata_port, u32 addr)
96	{
97	combo_phy_wait_for_ready(sata_port);
98	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
99	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
100	combo_phy_wait_for_ready(sata_port);
101	return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
102	}
103
104	static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
105	{
106	combo_phy_wait_for_ready(sata_port);
107	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
108	__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
109	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN \| CR_START);
110	}
111
112	static void highbank_cphy_disable_overrides(u8 sata_port)
113	{
114	u8 lane = port_data[sata_port].lane_mapping;
115	u32 tmp;
116	if (unlikely(port_data[sata_port].phy_base == NULL))
117	return;
118	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
119	tmp &= ~CPHY_SATA_OVERRIDE;
120	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
121	}
122
123	static void cphy_override_rx_mode(u8 sata_port, u32 val)
124	{
125	u8 lane = port_data[sata_port].lane_mapping;
126	u32 tmp;
127	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
128	tmp &= ~CPHY_SATA_OVERRIDE;
129	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
130
131	tmp \|= CPHY_SATA_OVERRIDE;
132	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
133
134	tmp &= ~CPHY_SATA_DPLL_MODE;
135	tmp \|= val << CPHY_SATA_DPLL_SHIFT;
136	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
137
138	tmp \|= CPHY_SATA_DPLL_RESET;
139	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
140
141	tmp &= ~CPHY_SATA_DPLL_RESET;
142	combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
143
144	msleep(15);
145	}
146
147	static void highbank_cphy_override_lane(u8 sata_port)
148	{
149	u8 lane = port_data[sata_port].lane_mapping;
150	u32 tmp, k = 0;
151
152	if (unlikely(port_data[sata_port].phy_base == NULL))
153	return;
154	do {
155	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
156	lane * SPHY_LANE);
157	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
158	cphy_override_rx_mode(sata_port, 3);
159	}
160
161	static int highbank_initialize_phys(struct device dev, void __iomem addr)
162	{
163	struct device_node *sata_node = dev->of_node;
164	int phy_count = 0, phy, port = 0;
165	void __iomem *cphy_base[CPHY_PHY_COUNT];
166	struct device_node *phy_nodes[CPHY_PHY_COUNT];
167	memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
168	memset(phy_nodes, 0, sizeof(struct device_node) CPHY_PHY_COUNT);
169
170	do {
171	u32 tmp;
172	struct of_phandle_args phy_data;
173	if (of_parse_phandle_with_args(sata_node,
174	"calxeda,port-phys", "#phy-cells",
175	port, &phy_data))
176	break;
177	for (phy = 0; phy < phy_count; phy++) {
178	if (phy_nodes[phy] == phy_data.np)
179	break;
180	}
181	if (phy_nodes[phy] == NULL) {
182	phy_nodes[phy] = phy_data.np;
183	cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
184	if (cphy_base[phy] == NULL) {
185	return 0;
186	}
187	phy_count += 1;
188	}
189	port_data[port].lane_mapping = phy_data.args[0];
190	of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
191	port_data[port].phy_devs = tmp;
192	port_data[port].phy_base = cphy_base[phy];
193	of_node_put(phy_data.np);
194	port += 1;
195	} while (port < CPHY_PORT_COUNT);
196	return 0;
197	}
198
31c1a76d ML	199	/*
	200	* The Calxeda SATA phy intermittently fails to bring up a link with Gen3
	201	* Retrying the phy hard reset can work around the issue, but the drive
	202	* may fail again. In less than 150 out of 15000 test runs, it took more
	203	* than 10 tries for the link to be established (but never more than 35).
	204	* Triple the maximum observed retry count to provide plenty of margin for
	205	* rare events and to guarantee that the link is established.
	206	*
	207	* Also, the default 2 second time-out on a failed drive is too long in
	208	* this situation. The uboot implementation of the same driver function
	209	* uses a much shorter time-out period and never experiences a time out
	210	* issue. Reducing the time-out to 500ms improves the responsiveness.
	211	* The other timing constants were kept the same as the stock AHCI driver.
	212	* This change was also tested 15000 times on 24 drives and none of them
	213	* experienced a time out.
	214	*/
8996b89d ML	215	static int ahci_highbank_hardreset(struct ata_link link, unsigned int class,
	216	unsigned long deadline)
	217	{
31c1a76d	218	static const unsigned long timing[] = { 5, 100, 500};
8996b89d ML	219	struct ata_port *ap = link->ap;
	220	struct ahci_port_priv *pp = ap->private_data;
	221	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	222	struct ata_taskfile tf;
	223	bool online;
	224	u32 sstatus;
	225	int rc;
31c1a76d	226	int retry = 100;
8996b89d ML	227
	228	ahci_stop_engine(ap);
	229
	230	/* clear D2H reception area to properly wait for D2H FIS */
	231	ata_tf_init(link->device, &tf);
121650a5	232	tf.command = ATA_BUSY;
8996b89d ML	233	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	234
	235	do {
	236	highbank_cphy_disable_overrides(link->ap->port_no);
	237	rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
	238	highbank_cphy_override_lane(link->ap->port_no);
	239
	240	/* If the status is 1, we are connected, but the link did not
	241	* come up. So retry resetting the link again.
	242	*/
	243	if (sata_scr_read(link, SCR_STATUS, &sstatus))
	244	break;
	245	if (!(sstatus & 0x3))
	246	break;
	247	} while (!online && retry--);
	248
	249	ahci_start_engine(ap);
	250
	251	if (online)
	252	*class = ahci_dev_classify(ap);
	253
	254	return rc;
	255	}
	256
	257	static struct ata_port_operations ahci_highbank_ops = {
	258	.inherits = &ahci_ops,
	259	.hardreset = ahci_highbank_hardreset,
	260	};
	261
	262	static const struct ata_port_info ahci_highbank_port_info = {
	263	.flags = AHCI_FLAG_COMMON,
	264	.pio_mask = ATA_PIO4,
	265	.udma_mask = ATA_UDMA6,
	266	.port_ops = &ahci_highbank_ops,
	267	};
	268
	269	static struct scsi_host_template ahci_highbank_platform_sht = {
2cc1144a	270	AHCI_SHT("sata_highbank"),
8996b89d ML	271	};
	272
	273	static const struct of_device_id ahci_of_match[] = {
	274	{ .compatible = "calxeda,hb-ahci" },
	275	{},
	276	};
	277	MODULE_DEVICE_TABLE(of, ahci_of_match);
	278
0ec24914	279	static int ahci_highbank_probe(struct platform_device *pdev)
8996b89d ML	280	{
	281	struct device *dev = &pdev->dev;
	282	struct ahci_host_priv *hpriv;
	283	struct ata_host *host;
	284	struct resource *mem;
	285	int irq;
	286	int n_ports;
	287	int i;
	288	int rc;
	289	struct ata_port_info pi = ahci_highbank_port_info;
	290	const struct ata_port_info *ppi[] = { &pi, NULL };
	291
	292	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	293	if (!mem) {
	294	dev_err(dev, "no mmio space\n");
	295	return -EINVAL;
	296	}
	297
	298	irq = platform_get_irq(pdev, 0);
	299	if (irq <= 0) {
	300	dev_err(dev, "no irq\n");
	301	return -EINVAL;
	302	}
	303
	304	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	305	if (!hpriv) {
	306	dev_err(dev, "can't alloc ahci_host_priv\n");
	307	return -ENOMEM;
	308	}
	309
	310	hpriv->flags \|= (unsigned long)pi.private_data;
	311
	312	hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
	313	if (!hpriv->mmio) {
	314	dev_err(dev, "can't map %pR\n", mem);
	315	return -ENOMEM;
	316	}
	317
	318	rc = highbank_initialize_phys(dev, hpriv->mmio);
	319	if (rc)
	320	return rc;
	321
	322
	323	ahci_save_initial_config(dev, hpriv, 0, 0);
	324
	325	/* prepare host */
	326	if (hpriv->cap & HOST_CAP_NCQ)
	327	pi.flags \|= ATA_FLAG_NCQ;
	328
	329	if (hpriv->cap & HOST_CAP_PMP)
	330	pi.flags \|= ATA_FLAG_PMP;
	331
	332	ahci_set_em_messages(hpriv, &pi);
	333
	334	/* CAP.NP sometimes indicate the index of the last enabled
	335	* port, at other times, that of the last possible port, so
	336	* determining the maximum port number requires looking at
	337	* both CAP.NP and port_map.
	338	*/
	339	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
	340
	341	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
	342	if (!host) {
	343	rc = -ENOMEM;
344	goto err0;
345	}
346
347	host->private_data = hpriv;
348
349	if (!(hpriv->cap & HOST_CAP_SSS) \|\| ahci_ignore_sss)
350	host->flags \|= ATA_HOST_PARALLEL_SCAN;
351
352	if (pi.flags & ATA_FLAG_EM)
353	ahci_reset_em(host);
354
355	for (i = 0; i < host->n_ports; i++) {
356	struct ata_port *ap = host->ports[i];
357
358	ata_port_desc(ap, "mmio %pR", mem);
359	ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
360
361	/* set enclosure management message type */
362	if (ap->flags & ATA_FLAG_EM)
363	ap->em_message_type = hpriv->em_msg_type;
364
365	/* disabled/not-implemented port */
366	if (!(hpriv->port_map & (1 << i)))
367	ap->ops = &ata_dummy_port_ops;
368	}
369
370	rc = ahci_reset_controller(host);
371	if (rc)
372	goto err0;
373
374	ahci_init_controller(host);
375	ahci_print_info(host, "platform");
376
377	rc = ata_host_activate(host, irq, ahci_interrupt, 0,
378	&ahci_highbank_platform_sht);
379	if (rc)
380	goto err0;
381
382	return 0;
383	err0:
384	return rc;
385	}
386
29448ec1	387	#ifdef CONFIG_PM_SLEEP
8996b89d ML	388	static int ahci_highbank_suspend(struct device *dev)
	389	{
	390	struct ata_host *host = dev_get_drvdata(dev);
	391	struct ahci_host_priv *hpriv = host->private_data;
	392	void __iomem *mmio = hpriv->mmio;
	393	u32 ctl;
	394	int rc;
	395
	396	if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
	397	dev_err(dev, "firmware update required for suspend/resume\n");
	398	return -EIO;
	399	}
	400
	401	/*
	402	* AHCI spec rev1.1 section 8.3.3:
	403	* Software must disable interrupts prior to requesting a
	404	* transition of the HBA to D3 state.
	405	*/
	406	ctl = readl(mmio + HOST_CTL);
	407	ctl &= ~HOST_IRQ_EN;
	408	writel(ctl, mmio + HOST_CTL);
	409	readl(mmio + HOST_CTL); /* flush */
	410
	411	rc = ata_host_suspend(host, PMSG_SUSPEND);
	412	if (rc)
	413	return rc;
	414
	415	return 0;
	416	}
	417
	418	static int ahci_highbank_resume(struct device *dev)
	419	{
	420	struct ata_host *host = dev_get_drvdata(dev);
	421	int rc;
	422
	423	if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
	424	rc = ahci_reset_controller(host);
	425	if (rc)
	426	return rc;
	427
	428	ahci_init_controller(host);
	429	}
	430
	431	ata_host_resume(host);
	432
	433	return 0;
	434	}
	435	#endif
	436
b1a72d60	437	static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
8996b89d ML	438	ahci_highbank_suspend, ahci_highbank_resume);
	439
	440	static struct platform_driver ahci_highbank_driver = {
e2ec1817	441	.remove = ata_platform_remove_one,
8996b89d ML	442	.driver = {
	443	.name = "highbank-ahci",
	444	.owner = THIS_MODULE,
	445	.of_match_table = ahci_of_match,
	446	.pm = &ahci_highbank_pm_ops,
	447	},
	448	.probe = ahci_highbank_probe,
	449	};
	450
	451	module_platform_driver(ahci_highbank_driver);
	452
	453	MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
	454	MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
	455	MODULE_LICENSE("GPL");
	456	MODULE_ALIAS("sata:highbank");