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libata: kill ATA_LFLAG_SKIP_D2H_BSY
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / sata_fsl.c
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faf0b2e5
LY		 1/*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21
22#include <scsi/scsi_host.h>
23#include <scsi/scsi_cmnd.h>
24#include <linux/libata.h>
25#include <asm/io.h>
26#include <linux/of_platform.h>
27
28/* Controller information */
29enum {
30 SATA_FSL_QUEUE_DEPTH = 16,
31 SATA_FSL_MAX_PRD = 63,
32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
34
35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
1bf617b7 37 ATA_FLAG_NCQ),
faf0b2e5
LY		 38
39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
42
43 /*
44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
45 * chained indirect PRDEs upto a max count of 63.
46 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
47 * be setup as an indirect descriptor, pointing to it's next
48 * (contigious) PRDE. Though chained indirect PRDE arrays are
49 * supported,it will be more efficient to use a direct PRDT and
50 * a single chain/link to indirect PRDE array/PRDT.
51 */
52
53 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
54 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
56 SATA_FSL_CMD_DESC_RSRVD = 16,
57
58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
59 SATA_FSL_CMD_DESC_SFIS_SZ +
60 SATA_FSL_CMD_DESC_ACMD_SZ +
61 SATA_FSL_CMD_DESC_RSRVD +
62 SATA_FSL_MAX_PRD * 16),
63
64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
65 (SATA_FSL_CMD_DESC_CFIS_SZ +
66 SATA_FSL_CMD_DESC_SFIS_SZ +
67 SATA_FSL_CMD_DESC_ACMD_SZ +
68 SATA_FSL_CMD_DESC_RSRVD),
69
70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
72 SATA_FSL_CMD_DESC_AR_SZ),
73
74 /*
75 * MPC8315 has two SATA controllers, SATA1 & SATA2
76 * (one port per controller)
77 * MPC837x has 2/4 controllers, one port per controller
78 */
79
80 SATA_FSL_MAX_PORTS = 1,
81
82 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
83};
84
85/*
86* Host Controller command register set - per port
87*/
88enum {
89 CQ = 0,
90 CA = 8,
91 CC = 0x10,
92 CE = 0x18,
93 DE = 0x20,
94 CHBA = 0x24,
95 HSTATUS = 0x28,
96 HCONTROL = 0x2C,
97 CQPMP = 0x30,
98 SIGNATURE = 0x34,
99 ICC = 0x38,
100
101 /*
102 * Host Status Register (HStatus) bitdefs
103 */
104 ONLINE = (1 << 31),
105 GOING_OFFLINE = (1 << 30),
106 BIST_ERR = (1 << 29),
107
108 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
109 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
110 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
111 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
112 FATAL_ERR_DATA_OVERRUN = (1 << 12),
113 FATAL_ERR_CRC_ERR_TX = (1 << 11),
114 FATAL_ERR_CRC_ERR_RX = (1 << 10),
115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
117
118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
119 FATAL_ERR_PARITY_ERR_TX |
120 FATAL_ERR_PARITY_ERR_RX |
121 FATAL_ERR_DATA_UNDERRUN |
122 FATAL_ERR_DATA_OVERRUN |
123 FATAL_ERR_CRC_ERR_TX |
124 FATAL_ERR_CRC_ERR_RX |
125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
126
127 INT_ON_FATAL_ERR = (1 << 5),
128 INT_ON_PHYRDY_CHG = (1 << 4),
129
130 INT_ON_SIGNATURE_UPDATE = (1 << 3),
131 INT_ON_SNOTIFY_UPDATE = (1 << 2),
132 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
133 INT_ON_CMD_COMPLETE = 1,
134
135 INT_ON_ERROR = INT_ON_FATAL_ERR |
136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
137
138 /*
139 * Host Control Register (HControl) bitdefs
140 */
141 HCONTROL_ONLINE_PHY_RST = (1 << 31),
142 HCONTROL_FORCE_OFFLINE = (1 << 30),
143 HCONTROL_PARITY_PROT_MOD = (1 << 14),
144 HCONTROL_DPATH_PARITY = (1 << 12),
145 HCONTROL_SNOOP_ENABLE = (1 << 10),
146 HCONTROL_PMP_ATTACHED = (1 << 9),
147 HCONTROL_COPYOUT_STATFIS = (1 << 8),
148 IE_ON_FATAL_ERR = (1 << 5),
149 IE_ON_PHYRDY_CHG = (1 << 4),
150 IE_ON_SIGNATURE_UPDATE = (1 << 3),
151 IE_ON_SNOTIFY_UPDATE = (1 << 2),
152 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
153 IE_ON_CMD_COMPLETE = 1,
154
155 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
156 IE_ON_SIGNATURE_UPDATE |
157 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
158
159 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
160 DATA_SNOOP_ENABLE = (1 << 22),
161};
162
163/*
164 * SATA Superset Registers
165 */
166enum {
167 SSTATUS = 0,
168 SERROR = 4,
169 SCONTROL = 8,
170 SNOTIFY = 0xC,
171};
172
173/*
174 * Control Status Register Set
175 */
176enum {
177 TRANSCFG = 0,
178 TRANSSTATUS = 4,
179 LINKCFG = 8,
180 LINKCFG1 = 0xC,
181 LINKCFG2 = 0x10,
182 LINKSTATUS = 0x14,
183 LINKSTATUS1 = 0x18,
184 PHYCTRLCFG = 0x1C,
185 COMMANDSTAT = 0x20,
186};
187
188/* PHY (link-layer) configuration control */
189enum {
190 PHY_BIST_ENABLE = 0x01,
191};
192
193/*
194 * Command Header Table entry, i.e, command slot
195 * 4 Dwords per command slot, command header size == 64 Dwords.
196 */
197struct cmdhdr_tbl_entry {
198 u32 cda;
199 u32 prde_fis_len;
200 u32 ttl;
201 u32 desc_info;
202};
203
204/*
205 * Description information bitdefs
206 */
207enum {
208 VENDOR_SPECIFIC_BIST = (1 << 10),
209 CMD_DESC_SNOOP_ENABLE = (1 << 9),
210 FPDMA_QUEUED_CMD = (1 << 8),
211 SRST_CMD = (1 << 7),
212 BIST = (1 << 6),
213 ATAPI_CMD = (1 << 5),
214};
215
216/*
217 * Command Descriptor
218 */
219struct command_desc {
220 u8 cfis[8 * 4];
221 u8 sfis[8 * 4];
222 u8 acmd[4 * 4];
223 u8 fill[4 * 4];
224 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
225 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
226};
227
228/*
229 * Physical region table descriptor(PRD)
230 */
231
232struct prde {
233 u32 dba;
234 u8 fill[2 * 4];
235 u32 ddc_and_ext;
236};
237
238/*
239 * ata_port private data
240 * This is our per-port instance data.
241 */
242struct sata_fsl_port_priv {
243 struct cmdhdr_tbl_entry *cmdslot;
244 dma_addr_t cmdslot_paddr;
245 struct command_desc *cmdentry;
246 dma_addr_t cmdentry_paddr;
247
248 /*
249 * SATA FSL controller has a Status FIS which should contain the
250 * received D2H FIS & taskfile registers. This SFIS is present in
251 * the command descriptor, and to have a ready reference to it,
252 * we are caching it here, quite similar to what is done in H/W on
253 * AHCI compliant devices by copying taskfile fields to a 32-bit
254 * register.
255 */
256
257 struct ata_taskfile tf;
258};
259
260/*
261 * ata_port->host_set private data
262 */
263struct sata_fsl_host_priv {
264 void __iomem *hcr_base;
265 void __iomem *ssr_base;
266 void __iomem *csr_base;
79b3edc9 267 int irq;
faf0b2e5
LY		 268};
269
270static inline unsigned int sata_fsl_tag(unsigned int tag,
520d3a1a 271 void __iomem *hcr_base)
faf0b2e5
LY		 272{
273 /* We let libATA core do actual (queue) tag allocation */
274
275 /* all non NCQ/queued commands should have tag#0 */
276 if (ata_tag_internal(tag)) {
277 DPRINTK("mapping internal cmds to tag#0\n");
278 return 0;
279 }
280
281 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
282 DPRINTK("tag %d invalid : out of range\n", tag);
283 return 0;
284 }
285
286 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
287 DPRINTK("tag %d invalid : in use!!\n", tag);
288 return 0;
289 }
290
291 return tag;
292}
293
294static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
295 unsigned int tag, u32 desc_info,
296 u32 data_xfer_len, u8 num_prde,
297 u8 fis_len)
298{
299 dma_addr_t cmd_descriptor_address;
300
301 cmd_descriptor_address = pp->cmdentry_paddr +
302 tag * SATA_FSL_CMD_DESC_SIZE;
303
304 /* NOTE: both data_xfer_len & fis_len are Dword counts */
305
306 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
307 pp->cmdslot[tag].prde_fis_len =
308 cpu_to_le32((num_prde << 16) | (fis_len << 2));
309 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
520d3a1a 310 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
faf0b2e5
LY		 311
312 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
313 pp->cmdslot[tag].cda,
314 pp->cmdslot[tag].prde_fis_len,
315 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
316
317}
318
319static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
520d3a1a 320 u32 *ttl, dma_addr_t cmd_desc_paddr)
faf0b2e5
LY		 321{
322 struct scatterlist *sg;
323 unsigned int num_prde = 0;
324 u32 ttl_dwords = 0;
325
326 /*
327 * NOTE : direct & indirect prdt's are contigiously allocated
328 */
329 struct prde *prd = (struct prde *)&((struct command_desc *)
330 cmd_desc)->prdt;
331
332 struct prde *prd_ptr_to_indirect_ext = NULL;
333 unsigned indirect_ext_segment_sz = 0;
334 dma_addr_t indirect_ext_segment_paddr;
ff2aeb1e 335 unsigned int si;
faf0b2e5 336
b1f5dc48 337 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
faf0b2e5
LY		 338
339 indirect_ext_segment_paddr = cmd_desc_paddr +
340 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
341
ff2aeb1e 342 for_each_sg(qc->sg, sg, qc->n_elem, si) {
faf0b2e5
LY		 343 dma_addr_t sg_addr = sg_dma_address(sg);
344 u32 sg_len = sg_dma_len(sg);
345
346 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
347 sg_addr, sg_len);
348
349 /* warn if each s/g element is not dword aligned */
350 if (sg_addr & 0x03)
351 ata_port_printk(qc->ap, KERN_ERR,
352 "s/g addr unaligned : 0x%x\n", sg_addr);
353 if (sg_len & 0x03)
354 ata_port_printk(qc->ap, KERN_ERR,
355 "s/g len unaligned : 0x%x\n", sg_len);
356
37198e30
JB		 357 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
358 sg_next(sg) != NULL) {
faf0b2e5
LY		 359 VPRINTK("setting indirect prde\n");
360 prd_ptr_to_indirect_ext = prd;
361 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
362 indirect_ext_segment_sz = 0;
363 ++prd;
364 ++num_prde;
365 }
366
367 ttl_dwords += sg_len;
368 prd->dba = cpu_to_le32(sg_addr);
369 prd->ddc_and_ext =
370 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
371
372 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
373 ttl_dwords, prd->dba, prd->ddc_and_ext);
374
375 ++num_prde;
376 ++prd;
377 if (prd_ptr_to_indirect_ext)
378 indirect_ext_segment_sz += sg_len;
379 }
380
381 if (prd_ptr_to_indirect_ext) {
382 /* set indirect extension flag along with indirect ext. size */
383 prd_ptr_to_indirect_ext->ddc_and_ext =
384 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
385 DATA_SNOOP_ENABLE |
386 (indirect_ext_segment_sz & ~0x03)));
387 }
388
389 *ttl = ttl_dwords;
390 return num_prde;
391}
392
393static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
394{
395 struct ata_port *ap = qc->ap;
396 struct sata_fsl_port_priv *pp = ap->private_data;
397 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
398 void __iomem *hcr_base = host_priv->hcr_base;
399 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
400 struct command_desc *cd;
401 u32 desc_info = CMD_DESC_SNOOP_ENABLE;
402 u32 num_prde = 0;
403 u32 ttl_dwords = 0;
404 dma_addr_t cd_paddr;
405
406 cd = (struct command_desc *)pp->cmdentry + tag;
407 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
408
520d3a1a 409 ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) &cd->cfis);
faf0b2e5
LY		 410
411 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
412 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
413
414 if (qc->tf.protocol == ATA_PROT_NCQ) {
415 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
416 cd->cfis[3], cd->cfis[11]);
417 }
418
419 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
405e66b3 420 if (ata_is_atapi(qc->tf.protocol)) {
faf0b2e5
LY		 421 desc_info |= ATAPI_CMD;
422 memset((void *)&cd->acmd, 0, 32);
423 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
424 }
425
426 if (qc->flags & ATA_QCFLAG_DMAMAP)
427 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
428 &ttl_dwords, cd_paddr);
429
430 if (qc->tf.protocol == ATA_PROT_NCQ)
431 desc_info |= FPDMA_QUEUED_CMD;
432
433 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
434 num_prde, 5);
435
436 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
437 desc_info, ttl_dwords, num_prde);
438}
439
440static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
441{
442 struct ata_port *ap = qc->ap;
443 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
444 void __iomem *hcr_base = host_priv->hcr_base;
445 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
446
447 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
448 ioread32(CQ + hcr_base),
449 ioread32(CA + hcr_base),
450 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
451
452 /* Simply queue command to the controller/device */
453 iowrite32(1 << tag, CQ + hcr_base);
454
455 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
456 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
457
458 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
459 ioread32(CE + hcr_base),
460 ioread32(DE + hcr_base),
b1f5dc48
AV		 461 ioread32(CC + hcr_base),
462 ioread32(COMMANDSTAT + host_priv->csr_base));
faf0b2e5
LY		 463
464 return 0;
465}
466
467static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
468 u32 val)
469{
470 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
471 void __iomem *ssr_base = host_priv->ssr_base;
472 unsigned int sc_reg;
473
474 switch (sc_reg_in) {
475 case SCR_STATUS:
faf0b2e5 476 case SCR_ERROR:
faf0b2e5 477 case SCR_CONTROL:
faf0b2e5 478 case SCR_ACTIVE:
9465d532 479 sc_reg = sc_reg_in;
faf0b2e5
LY		 480 break;
481 default:
482 return -EINVAL;
483 }
484
485 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
486
2a52e8d4 487 iowrite32(val, ssr_base + (sc_reg * 4));
faf0b2e5
LY		 488 return 0;
489}
490
491static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in,
492 u32 *val)
493{
494 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
495 void __iomem *ssr_base = host_priv->ssr_base;
496 unsigned int sc_reg;
497
498 switch (sc_reg_in) {
499 case SCR_STATUS:
faf0b2e5 500 case SCR_ERROR:
faf0b2e5 501 case SCR_CONTROL:
faf0b2e5 502 case SCR_ACTIVE:
9465d532 503 sc_reg = sc_reg_in;
faf0b2e5
LY		 504 break;
505 default:
506 return -EINVAL;
507 }
508
509 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
510
2a52e8d4 511 *val = ioread32(ssr_base + (sc_reg * 4));
faf0b2e5
LY		 512 return 0;
513}
514
515static void sata_fsl_freeze(struct ata_port *ap)
516{
517 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
518 void __iomem *hcr_base = host_priv->hcr_base;
519 u32 temp;
520
521 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
522 ioread32(CQ + hcr_base),
523 ioread32(CA + hcr_base),
524 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
b1f5dc48
AV		 525 VPRINTK("CmdStat = 0x%x\n",
526 ioread32(host_priv->csr_base + COMMANDSTAT));
faf0b2e5
LY		 527
528 /* disable interrupts on the controller/port */
529 temp = ioread32(hcr_base + HCONTROL);
530 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
531
532 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
533 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
534}
535
536static void sata_fsl_thaw(struct ata_port *ap)
537{
538 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
539 void __iomem *hcr_base = host_priv->hcr_base;
540 u32 temp;
541
542 /* ack. any pending IRQs for this controller/port */
543 temp = ioread32(hcr_base + HSTATUS);
544
545 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
546
547 if (temp & 0x3F)
548 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
549
550 /* enable interrupts on the controller/port */
551 temp = ioread32(hcr_base + HCONTROL);
552 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
553
554 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
555 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
556}
557
558/*
559 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor.
560 */
561static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd
562 *qc,
563 struct ata_port *ap)
564{
565 struct sata_fsl_port_priv *pp = ap->private_data;
faf0b2e5
LY		 566 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
567 void __iomem *hcr_base = host_priv->hcr_base;
568 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
569 struct command_desc *cd;
570
571 cd = pp->cmdentry + tag;
572
25ce945a 573 ata_tf_from_fis(cd->sfis, &pp->tf);
faf0b2e5
LY		 574}
575
576static u8 sata_fsl_check_status(struct ata_port *ap)
577{
578 struct sata_fsl_port_priv *pp = ap->private_data;
579
580 return pp->tf.command;
581}
582
583static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
584{
585 struct sata_fsl_port_priv *pp = ap->private_data;
586
587 *tf = pp->tf;
588}
589
590static int sata_fsl_port_start(struct ata_port *ap)
591{
592 struct device *dev = ap->host->dev;
593 struct sata_fsl_port_priv *pp;
594 int retval;
595 void *mem;
596 dma_addr_t mem_dma;
597 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
598 void __iomem *hcr_base = host_priv->hcr_base;
599 u32 temp;
600
601 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
602 if (!pp)
603 return -ENOMEM;
604
faf0b2e5
LY		 605 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
606 GFP_KERNEL);
607 if (!mem) {
faf0b2e5
LY		 608 kfree(pp);
609 return -ENOMEM;
610 }
611 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
612
613 pp->cmdslot = mem;
614 pp->cmdslot_paddr = mem_dma;
615
616 mem += SATA_FSL_CMD_SLOT_SIZE;
617 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
618
619 pp->cmdentry = mem;
620 pp->cmdentry_paddr = mem_dma;
621
622 ap->private_data = pp;
623
624 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
625 pp->cmdslot_paddr, pp->cmdentry_paddr);
626
627 /* Now, update the CHBA register in host controller cmd register set */
628 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
629
630 /*
631 * Now, we can bring the controller on-line & also initiate
632 * the COMINIT sequence, we simply return here and the boot-probing
633 * & device discovery process is re-initiated by libATA using a
634 * Softreset EH (dummy) session. Hence, boot probing and device
635 * discovey will be part of sata_fsl_softreset() callback.
636 */
637
638 temp = ioread32(hcr_base + HCONTROL);
639 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
640
641 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
642 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
643 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
644
e7eac96e 645#ifdef CONFIG_MPC8315_DS
faf0b2e5
LY		 646 /*
647 * Workaround for 8315DS board 3gbps link-up issue,
648 * currently limit SATA port to GEN1 speed
649 */
650 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
651 temp &= ~(0xF << 4);
652 temp |= (0x1 << 4);
653 sata_fsl_scr_write(ap, SCR_CONTROL, temp);
654
655 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
656 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
657 temp);
e7eac96e 658#endif
faf0b2e5
LY		 659
660 return 0;
661}
662
663static void sata_fsl_port_stop(struct ata_port *ap)
664{
665 struct device *dev = ap->host->dev;
666 struct sata_fsl_port_priv *pp = ap->private_data;
667 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
668 void __iomem *hcr_base = host_priv->hcr_base;
669 u32 temp;
670
671 /*
672 * Force host controller to go off-line, aborting current operations
673 */
674 temp = ioread32(hcr_base + HCONTROL);
675 temp &= ~HCONTROL_ONLINE_PHY_RST;
676 temp |= HCONTROL_FORCE_OFFLINE;
677 iowrite32(temp, hcr_base + HCONTROL);
678
679 /* Poll for controller to go offline - should happen immediately */
680 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
681
682 ap->private_data = NULL;
683 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
684 pp->cmdslot, pp->cmdslot_paddr);
685
faf0b2e5
LY		 686 kfree(pp);
687}
688
689static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
690{
691 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
692 void __iomem *hcr_base = host_priv->hcr_base;
693 struct ata_taskfile tf;
694 u32 temp;
695
696 temp = ioread32(hcr_base + SIGNATURE);
697
698 VPRINTK("raw sig = 0x%x\n", temp);
699 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
700 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
701
702 tf.lbah = (temp >> 24) & 0xff;
703 tf.lbam = (temp >> 16) & 0xff;
704 tf.lbal = (temp >> 8) & 0xff;
705 tf.nsect = temp & 0xff;
706
707 return ata_dev_classify(&tf);
708}
709
1bf617b7 710static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
faf0b2e5
LY		 711 unsigned long deadline)
712{
1bf617b7 713 struct ata_port *ap = link->ap;
faf0b2e5
LY		 714 struct sata_fsl_port_priv *pp = ap->private_data;
715 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
716 void __iomem *hcr_base = host_priv->hcr_base;
717 u32 temp;
718 struct ata_taskfile tf;
719 u8 *cfis;
720 u32 Serror;
721 int i = 0;
faf0b2e5
LY		 722 unsigned long start_jiffies;
723
724 DPRINTK("in xx_softreset\n");
725
726try_offline_again:
727 /*
728 * Force host controller to go off-line, aborting current operations
729 */
730 temp = ioread32(hcr_base + HCONTROL);
731 temp &= ~HCONTROL_ONLINE_PHY_RST;
732 iowrite32(temp, hcr_base + HCONTROL);
733
734 /* Poll for controller to go offline */
735 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
736
737 if (temp & ONLINE) {
738 ata_port_printk(ap, KERN_ERR,
739 "Softreset failed, not off-lined %d\n", i);
740
741 /*
742 * Try to offline controller atleast twice
743 */
744 i++;
745 if (i == 2)
746 goto err;
747 else
748 goto try_offline_again;
749 }
750
751 DPRINTK("softreset, controller off-lined\n");
752 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
753 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
754
755 /*
756 * PHY reset should remain asserted for atleast 1ms
757 */
758 msleep(1);
759
760 /*
761 * Now, bring the host controller online again, this can take time
762 * as PHY reset and communication establishment, 1st D2H FIS and
763 * device signature update is done, on safe side assume 500ms
764 * NOTE : Host online status may be indicated immediately!!
765 */
766
767 temp = ioread32(hcr_base + HCONTROL);
768 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
769 iowrite32(temp, hcr_base + HCONTROL);
770
771 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
772
773 if (!(temp & ONLINE)) {
774 ata_port_printk(ap, KERN_ERR,
775 "Softreset failed, not on-lined\n");
776 goto err;
777 }
778
779 DPRINTK("softreset, controller off-lined & on-lined\n");
780 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
781 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
782
783 /*
784 * First, wait for the PHYRDY change to occur before waiting for
785 * the signature, and also verify if SStatus indicates device
786 * presence
787 */
788
789 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
1bf617b7 790 if ((!(temp & 0x10)) || ata_link_offline(link)) {
faf0b2e5
LY		 791 ata_port_printk(ap, KERN_WARNING,
792 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
793 ioread32(hcr_base + HSTATUS));
794 goto err;
795 }
796
797 /*
798 * Wait for the first D2H from device,i.e,signature update notification
799 */
800 start_jiffies = jiffies;
801 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
802 500, jiffies_to_msecs(deadline - start_jiffies));
803
804 if ((temp & 0xFF) != 0x18) {
805 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
806 goto err;
807 } else {
808 ata_port_printk(ap, KERN_INFO,
809 "Signature Update detected @ %d msecs\n",
810 jiffies_to_msecs(jiffies - start_jiffies));
811 }
812
813 /*
814 * Send a device reset (SRST) explicitly on command slot #0
815 * Check : will the command queue (reg) be cleared during offlining ??
816 * Also we will be online only if Phy commn. has been established
817 * and device presence has been detected, therefore if we have
818 * reached here, we can send a command to the target device
819 */
820
faf0b2e5
LY		 821 DPRINTK("Sending SRST/device reset\n");
822
1bf617b7 823 ata_tf_init(link->device, &tf);
520d3a1a 824 cfis = (u8 *) &pp->cmdentry->cfis;
faf0b2e5
LY		 825
826 /* device reset/SRST is a control register update FIS, uses tag0 */
827 sata_fsl_setup_cmd_hdr_entry(pp, 0,
828 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
829
830 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
831 ata_tf_to_fis(&tf, 0, 0, cfis);
832
833 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
834 cfis[0], cfis[1], cfis[2], cfis[3]);
835
836 /*
837 * Queue SRST command to the controller/device, ensure that no
838 * other commands are active on the controller/device
839 */
840
841 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
842 ioread32(CQ + hcr_base),
843 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
844
845 iowrite32(0xFFFF, CC + hcr_base);
846 iowrite32(1, CQ + hcr_base);
847
848 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
849 if (temp & 0x1) {
850 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
851
852 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
853 ioread32(CQ + hcr_base),
854 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
855
856 sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
857
858 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
859 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
860 DPRINTK("Serror = 0x%x\n", Serror);
861 goto err;
862 }
863
864 msleep(1);
865
866 /*
867 * SATA device enters reset state after receving a Control register
868 * FIS with SRST bit asserted and it awaits another H2D Control reg.
869 * FIS with SRST bit cleared, then the device does internal diags &
870 * initialization, followed by indicating it's initialization status
871 * using ATA signature D2H register FIS to the host controller.
872 */
873
874 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
875
876 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
877 ata_tf_to_fis(&tf, 0, 0, cfis);
878
879 iowrite32(1, CQ + hcr_base);
880 msleep(150); /* ?? */
881
882 /*
883 * The above command would have signalled an interrupt on command
884 * complete, which needs special handling, by clearing the Nth
885 * command bit of the CCreg
886 */
887 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
faf0b2e5
LY		 888
889 DPRINTK("SATA FSL : Now checking device signature\n");
890
891 *class = ATA_DEV_NONE;
892
893 /* Verify if SStatus indicates device presence */
1bf617b7 894 if (ata_link_online(link)) {
faf0b2e5
LY		 895 /*
896 * if we are here, device presence has been detected,
897 * 1st D2H FIS would have been received, but sfis in
898 * command desc. is not updated, but signature register
899 * would have been updated
900 */
901
902 *class = sata_fsl_dev_classify(ap);
903
904 DPRINTK("class = %d\n", *class);
905 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
906 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
907 }
908
909 return 0;
910
911err:
912 return -EIO;
913}
914
faf0b2e5
LY		 915static void sata_fsl_error_handler(struct ata_port *ap)
916{
917
918 DPRINTK("in xx_error_handler\n");
919
920 /* perform recovery */
066ce4db 921 ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_std_hardreset,
faf0b2e5
LY		 922 ata_std_postreset);
923}
924
925static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
926{
927 if (qc->flags & ATA_QCFLAG_FAILED)
928 qc->err_mask |= AC_ERR_OTHER;
929
930 if (qc->err_mask) {
931 /* make DMA engine forget about the failed command */
932
933 }
934}
935
936static void sata_fsl_irq_clear(struct ata_port *ap)
937{
938 /* unused */
939}
940
941static void sata_fsl_error_intr(struct ata_port *ap)
942{
1bf617b7
LY		 943 struct ata_link *link = &ap->link;
944 struct ata_eh_info *ehi = &link->eh_info;
faf0b2e5
LY		 945 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
946 void __iomem *hcr_base = host_priv->hcr_base;
947 u32 hstatus, dereg, cereg = 0, SError = 0;
948 unsigned int err_mask = 0, action = 0;
949 struct ata_queued_cmd *qc;
950 int freeze = 0;
951
952 hstatus = ioread32(hcr_base + HSTATUS);
953 cereg = ioread32(hcr_base + CE);
954
955 ata_ehi_clear_desc(ehi);
956
957 /*
958 * Handle & Clear SError
959 */
960
961 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
962 if (unlikely(SError & 0xFFFF0000)) {
963 sata_fsl_scr_write(ap, SCR_ERROR, SError);
964 err_mask |= AC_ERR_ATA_BUS;
965 }
966
967 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
968 hstatus, cereg, ioread32(hcr_base + DE), SError);
969
970 /* handle single device errors */
971 if (cereg) {
972 /*
973 * clear the command error, also clears queue to the device
974 * in error, and we can (re)issue commands to this device.
975 * When a device is in error all commands queued into the
976 * host controller and at the device are considered aborted
977 * and the queue for that device is stopped. Now, after
978 * clearing the device error, we can issue commands to the
979 * device to interrogate it to find the source of the error.
980 */
981 dereg = ioread32(hcr_base + DE);
982 iowrite32(dereg, hcr_base + DE);
983 iowrite32(cereg, hcr_base + CE);
984
985 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
986 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
987 /*
988 * We should consider this as non fatal error, and TF must
989 * be updated as done below.
990 */
991
992 err_mask |= AC_ERR_DEV;
993 }
994
995 /* handle fatal errors */
996 if (hstatus & FATAL_ERROR_DECODE) {
997 err_mask |= AC_ERR_ATA_BUS;
cf480626 998 action |= ATA_EH_RESET;
faf0b2e5
LY		 999 /* how will fatal error interrupts be completed ?? */
1000 freeze = 1;
1001 }
1002
1003 /* Handle PHYRDY change notification */
1004 if (hstatus & INT_ON_PHYRDY_CHG) {
1005 DPRINTK("SATA FSL: PHYRDY change indication\n");
1006
1007 /* Setup a soft-reset EH action */
1008 ata_ehi_hotplugged(ehi);
1009 freeze = 1;
1010 }
1011
1012 /* record error info */
1bf617b7 1013 qc = ata_qc_from_tag(ap, link->active_tag);
faf0b2e5
LY		 1014
1015 if (qc) {
1016 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1017 qc->err_mask |= err_mask;
1018 } else
1019 ehi->err_mask |= err_mask;
1020
1021 ehi->action |= action;
1022 ehi->serror |= SError;
1023
1024 /* freeze or abort */
1025 if (freeze)
1026 ata_port_freeze(ap);
1027 else
1028 ata_port_abort(ap);
1029}
1030
1031static void sata_fsl_qc_complete(struct ata_queued_cmd *qc)
1032{
1033 if (qc->flags & ATA_QCFLAG_RESULT_TF) {
1034 DPRINTK("xx_qc_complete called\n");
1035 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1036 }
1037}
1038
1039static void sata_fsl_host_intr(struct ata_port *ap)
1040{
1bf617b7 1041 struct ata_link *link = &ap->link;
faf0b2e5
LY		 1042 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1043 void __iomem *hcr_base = host_priv->hcr_base;
1044 u32 hstatus, qc_active = 0;
1045 struct ata_queued_cmd *qc;
1046 u32 SError;
1047
1048 hstatus = ioread32(hcr_base + HSTATUS);
1049
1050 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
1051
1052 if (unlikely(SError & 0xFFFF0000)) {
1053 DPRINTK("serror @host_intr : 0x%x\n", SError);
1054 sata_fsl_error_intr(ap);
1055
1056 }
1057
1058 if (unlikely(hstatus & INT_ON_ERROR)) {
1059 DPRINTK("error interrupt!!\n");
1060 sata_fsl_error_intr(ap);
1061 return;
1062 }
1063
1bf617b7 1064 if (link->sactive) { /* only true for NCQ commands */
faf0b2e5
LY		 1065 int i;
1066 /* Read command completed register */
1067 qc_active = ioread32(hcr_base + CC);
1068 /* clear CC bit, this will also complete the interrupt */
1069 iowrite32(qc_active, hcr_base + CC);
1070
1071 DPRINTK("Status of all queues :\n");
1072 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1073 qc_active, ioread32(hcr_base + CA),
1074 ioread32(hcr_base + CE));
1075
1076 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1077 if (qc_active & (1 << i)) {
1078 qc = ata_qc_from_tag(ap, i);
1079 if (qc) {
1080 sata_fsl_qc_complete(qc);
1081 ata_qc_complete(qc);
1082 }
1083 DPRINTK
1084 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1085 i, ioread32(hcr_base + CC),
1086 ioread32(hcr_base + CA));
1087 }
1088 }
1089 return;
1090
1091 } else if (ap->qc_active) {
1092 iowrite32(1, hcr_base + CC);
1bf617b7 1093 qc = ata_qc_from_tag(ap, link->active_tag);
faf0b2e5
LY		 1094
1095 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
1bf617b7 1096 link->active_tag, ioread32(hcr_base + CC));
faf0b2e5
LY		 1097
1098 if (qc) {
1099 sata_fsl_qc_complete(qc);
1100 ata_qc_complete(qc);
1101 }
1102 } else {
1103 /* Spurious Interrupt!! */
1104 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1105 ioread32(hcr_base + CC));
1106 return;
1107 }
1108}
1109
1110static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1111{
1112 struct ata_host *host = dev_instance;
1113 struct sata_fsl_host_priv *host_priv = host->private_data;
1114 void __iomem *hcr_base = host_priv->hcr_base;
1115 u32 interrupt_enables;
1116 unsigned handled = 0;
1117 struct ata_port *ap;
1118
1119 /* ack. any pending IRQs for this controller/port */
1120 interrupt_enables = ioread32(hcr_base + HSTATUS);
1121 interrupt_enables &= 0x3F;
1122
1123 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1124
1125 if (!interrupt_enables)
1126 return IRQ_NONE;
1127
1128 spin_lock(&host->lock);
1129
1130 /* Assuming one port per host controller */
1131
1132 ap = host->ports[0];
1133 if (ap) {
1134 sata_fsl_host_intr(ap);
1135 } else {
1136 dev_printk(KERN_WARNING, host->dev,
1137 "interrupt on disabled port 0\n");
1138 }
1139
1140 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1141 handled = 1;
1142
1143 spin_unlock(&host->lock);
1144
1145 return IRQ_RETVAL(handled);
1146}
1147
1148/*
1149 * Multiple ports are represented by multiple SATA controllers with
1150 * one port per controller
1151 */
1152static int sata_fsl_init_controller(struct ata_host *host)
1153{
1154 struct sata_fsl_host_priv *host_priv = host->private_data;
1155 void __iomem *hcr_base = host_priv->hcr_base;
1156 u32 temp;
1157
1158 /*
1159 * NOTE : We cannot bring the controller online before setting
1160 * the CHBA, hence main controller initialization is done as
1161 * part of the port_start() callback
1162 */
1163
1164 /* ack. any pending IRQs for this controller/port */
1165 temp = ioread32(hcr_base + HSTATUS);
1166 if (temp & 0x3F)
1167 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1168
1169 /* Keep interrupts disabled on the controller */
1170 temp = ioread32(hcr_base + HCONTROL);
1171 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1172
1173 /* Disable interrupt coalescing control(icc), for the moment */
1174 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1175 iowrite32(0x01000000, hcr_base + ICC);
1176
1177 /* clear error registers, SError is cleared by libATA */
1178 iowrite32(0x00000FFFF, hcr_base + CE);
1179 iowrite32(0x00000FFFF, hcr_base + DE);
1180
1181 /* initially assuming no Port multiplier, set CQPMP to 0 */
1182 iowrite32(0x0, hcr_base + CQPMP);
1183
1184 /*
1185 * host controller will be brought on-line, during xx_port_start()
1186 * callback, that should also initiate the OOB, COMINIT sequence
1187 */
1188
1189 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1190 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1191
1192 return 0;
1193}
1194
1195/*
1196 * scsi mid-layer and libata interface structures
1197 */
1198static struct scsi_host_template sata_fsl_sht = {
1199 .module = THIS_MODULE,
1200 .name = "sata_fsl",
1201 .ioctl = ata_scsi_ioctl,
1202 .queuecommand = ata_scsi_queuecmd,
1203 .change_queue_depth = ata_scsi_change_queue_depth,
1204 .can_queue = SATA_FSL_QUEUE_DEPTH,
1205 .this_id = ATA_SHT_THIS_ID,
1206 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1207 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
1208 .emulated = ATA_SHT_EMULATED,
1209 .use_clustering = ATA_SHT_USE_CLUSTERING,
1210 .proc_name = "sata_fsl",
1211 .dma_boundary = ATA_DMA_BOUNDARY,
1212 .slave_configure = ata_scsi_slave_config,
1213 .slave_destroy = ata_scsi_slave_destroy,
1214 .bios_param = ata_std_bios_param,
faf0b2e5
LY		 1215};
1216
1217static const struct ata_port_operations sata_fsl_ops = {
faf0b2e5
LY		 1218 .check_status = sata_fsl_check_status,
1219 .check_altstatus = sata_fsl_check_status,
1220 .dev_select = ata_noop_dev_select,
1221
1222 .tf_read = sata_fsl_tf_read,
1223
1224 .qc_prep = sata_fsl_qc_prep,
1225 .qc_issue = sata_fsl_qc_issue,
1226 .irq_clear = sata_fsl_irq_clear,
faf0b2e5
LY		 1227
1228 .scr_read = sata_fsl_scr_read,
1229 .scr_write = sata_fsl_scr_write,
1230
1231 .freeze = sata_fsl_freeze,
1232 .thaw = sata_fsl_thaw,
1233 .error_handler = sata_fsl_error_handler,
1234 .post_internal_cmd = sata_fsl_post_internal_cmd,
1235
1236 .port_start = sata_fsl_port_start,
1237 .port_stop = sata_fsl_port_stop,
1238};
1239
1240static const struct ata_port_info sata_fsl_port_info[] = {
1241 {
1242 .flags = SATA_FSL_HOST_FLAGS,
1243 .pio_mask = 0x1f, /* pio 0-4 */
1244 .udma_mask = 0x7f, /* udma 0-6 */
1245 .port_ops = &sata_fsl_ops,
1246 },
1247};
1248
1249static int sata_fsl_probe(struct of_device *ofdev,
1250 const struct of_device_id *match)
1251{
1252 int retval = 0;
1253 void __iomem *hcr_base = NULL;
1254 void __iomem *ssr_base = NULL;
1255 void __iomem *csr_base = NULL;
1256 struct sata_fsl_host_priv *host_priv = NULL;
faf0b2e5
LY		 1257 int irq;
1258 struct ata_host *host;
1259
1260 struct ata_port_info pi = sata_fsl_port_info[0];
1261 const struct ata_port_info *ppi[] = { &pi, NULL };
1262
1263 dev_printk(KERN_INFO, &ofdev->dev,
1264 "Sata FSL Platform/CSB Driver init\n");
1265
faf0b2e5
LY		 1266 hcr_base = of_iomap(ofdev->node, 0);
1267 if (!hcr_base)
1268 goto error_exit_with_cleanup;
1269
1270 ssr_base = hcr_base + 0x100;
1271 csr_base = hcr_base + 0x140;
1272
1273 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1274 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1275 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1276
1277 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1278 if (!host_priv)
1279 goto error_exit_with_cleanup;
1280
1281 host_priv->hcr_base = hcr_base;
1282 host_priv->ssr_base = ssr_base;
1283 host_priv->csr_base = csr_base;
1284
1285 irq = irq_of_parse_and_map(ofdev->node, 0);
1286 if (irq < 0) {
1287 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1288 goto error_exit_with_cleanup;
1289 }
79b3edc9 1290 host_priv->irq = irq;
faf0b2e5
LY		 1291
1292 /* allocate host structure */
1293 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1294
1295 /* host->iomap is not used currently */
1296 host->private_data = host_priv;
1297
1298 /* setup port(s) */
1299
1300 host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base;
1301 host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base;
1302
1303 /* initialize host controller */
1304 sata_fsl_init_controller(host);
1305
1306 /*
1307 * Now, register with libATA core, this will also initiate the
1308 * device discovery process, invoking our port_start() handler &
1309 * error_handler() to execute a dummy Softreset EH session
1310 */
1311 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1312 &sata_fsl_sht);
1313
1314 dev_set_drvdata(&ofdev->dev, host);
1315
1316 return 0;
1317
1318error_exit_with_cleanup:
1319
1320 if (hcr_base)
1321 iounmap(hcr_base);
1322 if (host_priv)
1323 kfree(host_priv);
1324
1325 return retval;
1326}
1327
1328static int sata_fsl_remove(struct of_device *ofdev)
1329{
1330 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1331 struct sata_fsl_host_priv *host_priv = host->private_data;
1332
1333 ata_host_detach(host);
1334
1335 dev_set_drvdata(&ofdev->dev, NULL);
1336
79b3edc9 1337 irq_dispose_mapping(host_priv->irq);
faf0b2e5
LY		 1338 iounmap(host_priv->hcr_base);
1339 kfree(host_priv);
1340
1341 return 0;
1342}
1343
1344static struct of_device_id fsl_sata_match[] = {
1345 {
96ce1b6d 1346 .compatible = "fsl,pq-sata",
faf0b2e5
LY		 1347 },
1348 {},
1349};
1350
1351MODULE_DEVICE_TABLE(of, fsl_sata_match);
1352
1353static struct of_platform_driver fsl_sata_driver = {
1354 .name = "fsl-sata",
1355 .match_table = fsl_sata_match,
1356 .probe = sata_fsl_probe,
1357 .remove = sata_fsl_remove,
1358};
1359
1360static int __init sata_fsl_init(void)
1361{
1362 of_register_platform_driver(&fsl_sata_driver);
1363 return 0;
1364}
1365
1366static void __exit sata_fsl_exit(void)
1367{
1368 of_unregister_platform_driver(&fsl_sata_driver);
1369}
1370
1371MODULE_LICENSE("GPL");
1372MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1373MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1374MODULE_VERSION("1.10");
1375
1376module_init(sata_fsl_init);
1377module_exit(sata_fsl_exit);
kernel source for telekom puls (alcatel/mediatek)