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ata: sata_dwc_460ex: use readl/writel_relaxed()
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ata / sata_dwc_460ex.c
CommitLineData
62936009
RS		 1/*
2 * drivers/ata/sata_dwc_460ex.c
3 *
4 * Synopsys DesignWare Cores (DWC) SATA host driver
5 *
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
7 *
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
10 *
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifdef CONFIG_SATA_DWC_DEBUG
22#define DEBUG
23#endif
24
25#ifdef CONFIG_SATA_DWC_VDEBUG
26#define VERBOSE_DEBUG
27#define DEBUG_NCQ
28#endif
29
30#include <linux/kernel.h>
31#include <linux/module.h>
62936009 32#include <linux/device.h>
50b43375 33#include <linux/dmaengine.h>
c11eede6
RH		 34#include <linux/of_address.h>
35#include <linux/of_irq.h>
62936009
RS		 36#include <linux/of_platform.h>
37#include <linux/platform_device.h>
0f48debd 38#include <linux/phy/phy.h>
62936009
RS		 39#include <linux/libata.h>
40#include <linux/slab.h>
8b344485 41
62936009
RS		 42#include "libata.h"
43
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46
c211962d
SS		 47/* These two are defined in "libata.h" */
48#undef DRV_NAME
49#undef DRV_VERSION
72d5f2da 50
62936009 51#define DRV_NAME "sata-dwc"
84b47e3b 52#define DRV_VERSION "1.3"
62936009 53
ee81d6cc
MR		 54#define sata_dwc_writel(a, v) writel_relaxed(v, a)
55#define sata_dwc_readl(a) readl_relaxed(a)
84683a7e
AS		 56
57#ifndef NO_IRQ
58#define NO_IRQ 0
59#endif
60
4ea8c205 61#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
62936009 62
62936009 63enum {
62936009
RS		 64 SATA_DWC_MAX_PORTS = 1,
65
66 SATA_DWC_SCR_OFFSET = 0x24,
67 SATA_DWC_REG_OFFSET = 0x64,
68};
69
70/* DWC SATA Registers */
71struct sata_dwc_regs {
72 u32 fptagr; /* 1st party DMA tag */
73 u32 fpbor; /* 1st party DMA buffer offset */
74 u32 fptcr; /* 1st party DMA Xfr count */
75 u32 dmacr; /* DMA Control */
76 u32 dbtsr; /* DMA Burst Transac size */
77 u32 intpr; /* Interrupt Pending */
78 u32 intmr; /* Interrupt Mask */
79 u32 errmr; /* Error Mask */
80 u32 llcr; /* Link Layer Control */
81 u32 phycr; /* PHY Control */
82 u32 physr; /* PHY Status */
83 u32 rxbistpd; /* Recvd BIST pattern def register */
84 u32 rxbistpd1; /* Recvd BIST data dword1 */
85 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
86 u32 txbistpd; /* Trans BIST pattern def register */
87 u32 txbistpd1; /* Trans BIST data dword1 */
88 u32 txbistpd2; /* Trans BIST data dword2 */
89 u32 bistcr; /* BIST Control Register */
90 u32 bistfctr; /* BIST FIS Count Register */
91 u32 bistsr; /* BIST Status Register */
92 u32 bistdecr; /* BIST Dword Error count register */
93 u32 res[15]; /* Reserved locations */
94 u32 testr; /* Test Register */
95 u32 versionr; /* Version Register */
96 u32 idr; /* ID Register */
97 u32 unimpl[192]; /* Unimplemented */
98 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
99};
100
101enum {
102 SCR_SCONTROL_DET_ENABLE = 0x00000001,
103 SCR_SSTATUS_DET_PRESENT = 0x00000001,
104 SCR_SERROR_DIAG_X = 0x04000000,
105/* DWC SATA Register Operations */
106 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
107 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
108 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
109 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
110 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
111 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
112 SATA_DWC_INTPR_DMAT = 0x00000001,
113 SATA_DWC_INTPR_NEWFP = 0x00000002,
114 SATA_DWC_INTPR_PMABRT = 0x00000004,
115 SATA_DWC_INTPR_ERR = 0x00000008,
116 SATA_DWC_INTPR_NEWBIST = 0x00000010,
117 SATA_DWC_INTPR_IPF = 0x10000000,
118 SATA_DWC_INTMR_DMATM = 0x00000001,
119 SATA_DWC_INTMR_NEWFPM = 0x00000002,
120 SATA_DWC_INTMR_PMABRTM = 0x00000004,
121 SATA_DWC_INTMR_ERRM = 0x00000008,
122 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
123 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
124 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
125 SATA_DWC_LLCR_RPDEN = 0x00000004,
126/* This is all error bits, zero's are reserved fields. */
127 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
128};
129
130#define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
131#define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
132 SATA_DWC_DMACR_TMOD_TXCHEN)
133#define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
134 SATA_DWC_DMACR_TMOD_TXCHEN)
135#define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
136#define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
137 << 16)
138struct sata_dwc_device {
139 struct device *dev; /* generic device struct */
140 struct ata_probe_ent *pe; /* ptr to probe-ent */
141 struct ata_host *host;
d7c256e8 142 u8 __iomem *reg_base;
adc64ecf 143 struct sata_dwc_regs __iomem *sata_dwc_regs; /* DW SATA specific */
2d20da00
MR		 144 u32 sactive_issued;
145 u32 sactive_queued;
0f48debd 146 struct phy *phy;
50b43375 147#ifdef CONFIG_SATA_DWC_OLD_DMA
8b344485 148 struct dw_dma_chip *dma;
50b43375 149#endif
62936009
RS		 150};
151
152#define SATA_DWC_QCMD_MAX 32
153
154struct sata_dwc_device_port {
155 struct sata_dwc_device *hsdev;
156 int cmd_issued[SATA_DWC_QCMD_MAX];
62936009 157 int dma_pending[SATA_DWC_QCMD_MAX];
8b344485
AS		 158
159 /* DMA info */
8b344485
AS		 160 struct dma_chan *chan;
161 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
162 u32 dma_interrupt_count;
62936009
RS		 163};
164
165/*
4bb41be5 166 * Commonly used DWC SATA driver macros
62936009 167 */
4bb41be5
AS		 168#define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
169#define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
170#define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
171#define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
172#define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
62936009
RS		 173
174enum {
175 SATA_DWC_CMD_ISSUED_NOT = 0,
176 SATA_DWC_CMD_ISSUED_PEND = 1,
177 SATA_DWC_CMD_ISSUED_EXEC = 2,
178 SATA_DWC_CMD_ISSUED_NODATA = 3,
179
180 SATA_DWC_DMA_PENDING_NONE = 0,
181 SATA_DWC_DMA_PENDING_TX = 1,
182 SATA_DWC_DMA_PENDING_RX = 2,
183};
184
62936009
RS		 185/*
186 * Prototypes
187 */
188static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
189static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
190 u32 check_status);
191static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
192static void sata_dwc_port_stop(struct ata_port *ap);
193static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
62936009 194
50b43375
MR		 195#ifdef CONFIG_SATA_DWC_OLD_DMA
196
197#include <linux/platform_data/dma-dw.h>
198#include <linux/dma/dw.h>
199
200static struct dw_dma_slave sata_dwc_dma_dws = {
201 .src_id = 0,
202 .dst_id = 0,
203 .m_master = 1,
204 .p_master = 0,
205};
206
207static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
208{
209 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
210
211 if (dws->dma_dev != chan->device->dev)
212 return false;
213
214 chan->private = dws;
215 return true;
216}
217
218static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
219{
220 struct sata_dwc_device *hsdev = hsdevp->hsdev;
221 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
222 dma_cap_mask_t mask;
223
224 dws->dma_dev = hsdev->dev;
225
226 dma_cap_zero(mask);
227 dma_cap_set(DMA_SLAVE, mask);
228
229 /* Acquire DMA channel */
230 hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
231 if (!hsdevp->chan) {
232 dev_err(hsdev->dev, "%s: dma channel unavailable\n",
233 __func__);
234 return -EAGAIN;
235 }
236
237 return 0;
238}
239
240static int sata_dwc_dma_init_old(struct platform_device *pdev,
241 struct sata_dwc_device *hsdev)
242{
243 struct device_node *np = pdev->dev.of_node;
244 int err;
245
246 hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL);
247 if (!hsdev->dma)
248 return -ENOMEM;
249
250 hsdev->dma->dev = &pdev->dev;
251
252 /* Get SATA DMA interrupt number */
253 hsdev->dma->irq = irq_of_parse_and_map(np, 1);
254 if (hsdev->dma->irq == NO_IRQ) {
255 dev_err(&pdev->dev, "no SATA DMA irq\n");
256 return -ENODEV;
257 }
258
259 /* Get physical SATA DMA register base address */
260 hsdev->dma->regs = of_iomap(np, 1);
261 if (!hsdev->dma->regs) {
262 dev_err(&pdev->dev,
263 "ioremap failed for AHBDMA register address\n");
264 return -ENODEV;
265 }
266
267 /* Initialize AHB DMAC */
268 err = dw_dma_probe(hsdev->dma);
269 if (err) {
270 iounmap(hsdev->dma->regs);
271 return err;
272 }
273
274 return 0;
275}
276
277static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
278{
279 if (!hsdev->dma)
280 return;
281
282 dw_dma_remove(hsdev->dma);
283 iounmap(hsdev->dma->regs);
284}
285
286#endif
287
84b47e3b
SS		 288static const char *get_prot_descript(u8 protocol)
289{
290 switch ((enum ata_tf_protocols)protocol) {
291 case ATA_PROT_NODATA:
292 return "ATA no data";
293 case ATA_PROT_PIO:
294 return "ATA PIO";
295 case ATA_PROT_DMA:
296 return "ATA DMA";
297 case ATA_PROT_NCQ:
298 return "ATA NCQ";
299 case ATAPI_PROT_NODATA:
300 return "ATAPI no data";
301 case ATAPI_PROT_PIO:
302 return "ATAPI PIO";
303 case ATAPI_PROT_DMA:
304 return "ATAPI DMA";
305 default:
306 return "unknown";
307 }
308}
309
310static const char *get_dma_dir_descript(int dma_dir)
311{
312 switch ((enum dma_data_direction)dma_dir) {
313 case DMA_BIDIRECTIONAL:
314 return "bidirectional";
315 case DMA_TO_DEVICE:
316 return "to device";
317 case DMA_FROM_DEVICE:
318 return "from device";
319 default:
320 return "none";
321 }
322}
323
db7a657f 324static void sata_dwc_tf_dump(struct ata_port *ap, struct ata_taskfile *tf)
62936009 325{
db7a657f 326 dev_vdbg(ap->dev,
d578514b
AS		 327 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
328 tf->command, get_prot_descript(tf->protocol), tf->flags,
329 tf->device);
db7a657f 330 dev_vdbg(ap->dev,
d578514b
AS		 331 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
332 tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
db7a657f 333 dev_vdbg(ap->dev,
d578514b 334 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
62936009
RS		 335 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
336 tf->hob_lbah);
337}
338
8b344485 339static void dma_dwc_xfer_done(void *hsdev_instance)
62936009 340{
62936009 341 unsigned long flags;
d5185d65 342 struct sata_dwc_device *hsdev = hsdev_instance;
62936009
RS		 343 struct ata_host *host = (struct ata_host *)hsdev->host;
344 struct ata_port *ap;
345 struct sata_dwc_device_port *hsdevp;
346 u8 tag = 0;
347 unsigned int port = 0;
348
349 spin_lock_irqsave(&host->lock, flags);
350 ap = host->ports[port];
351 hsdevp = HSDEVP_FROM_AP(ap);
352 tag = ap->link.active_tag;
353
62936009 354 /*
8b344485
AS		 355 * Each DMA command produces 2 interrupts. Only
356 * complete the command after both interrupts have been
357 * seen. (See sata_dwc_isr())
62936009 358 */
8b344485
AS		 359 hsdevp->dma_interrupt_count++;
360 sata_dwc_clear_dmacr(hsdevp, tag);
62936009 361
8b344485
AS		 362 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
363 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
364 tag, hsdevp->dma_pending[tag]);
62936009
RS		 365 }
366
8b344485 367 if ((hsdevp->dma_interrupt_count % 2) == 0)
8d5fe8d5 368 sata_dwc_dma_xfer_complete(ap, 1);
62936009 369
8b344485 370 spin_unlock_irqrestore(&host->lock, flags);
62936009
RS		 371}
372
8b344485 373static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
62936009 374{
8b344485
AS		 375 struct ata_port *ap = qc->ap;
376 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
377 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
378 dma_addr_t addr = (dma_addr_t)&hsdev->sata_dwc_regs->dmadr;
379 struct dma_slave_config sconf;
380 struct dma_async_tx_descriptor *desc;
381
382 if (qc->dma_dir == DMA_DEV_TO_MEM) {
383 sconf.src_addr = addr;
59a75cef 384 sconf.device_fc = false;
8b344485
AS		 385 } else { /* DMA_MEM_TO_DEV */
386 sconf.dst_addr = addr;
387 sconf.device_fc = false;
62936009
RS		 388 }
389
8b344485 390 sconf.direction = qc->dma_dir;
4ea8c205
AS		 391 sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
392 sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
8b344485
AS		 393 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
394 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
62936009 395
8b344485 396 dmaengine_slave_config(hsdevp->chan, &sconf);
62936009 397
8b344485
AS		 398 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
399 desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
400 qc->dma_dir,
401 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
62936009 402
8b344485
AS		 403 if (!desc)
404 return NULL;
62936009 405
8b344485
AS		 406 desc->callback = dma_dwc_xfer_done;
407 desc->callback_param = hsdev;
62936009 408
db7a657f 409 dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pad\n",
8b344485 410 __func__, qc->sg, qc->n_elem, &addr);
62936009 411
8b344485 412 return desc;
62936009
RS		 413}
414
415static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
416{
417 if (scr > SCR_NOTIFICATION) {
418 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
419 __func__, scr);
420 return -EINVAL;
421 }
422
ee81d6cc 423 *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
62936009
RS		 424 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
425 __func__, link->ap->print_id, scr, *val);
426
427 return 0;
428}
429
430static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
431{
432 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
433 __func__, link->ap->print_id, scr, val);
434 if (scr > SCR_NOTIFICATION) {
435 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
436 __func__, scr);
437 return -EINVAL;
438 }
ee81d6cc 439 sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
62936009
RS		 440
441 return 0;
442}
443
2d20da00 444static void clear_serror(struct ata_port *ap)
62936009
RS		 445{
446 u32 val;
2d20da00
MR		 447 sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
448 sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
62936009
RS		 449}
450
451static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
452{
ee81d6cc
MR		 453 sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
454 sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
62936009
RS		 455}
456
457static u32 qcmd_tag_to_mask(u8 tag)
458{
459 return 0x00000001 << (tag & 0x1f);
460}
461
462/* See ahci.c */
463static void sata_dwc_error_intr(struct ata_port *ap,
464 struct sata_dwc_device *hsdev, uint intpr)
465{
466 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
467 struct ata_eh_info *ehi = &ap->link.eh_info;
468 unsigned int err_mask = 0, action = 0;
469 struct ata_queued_cmd *qc;
470 u32 serror;
471 u8 status, tag;
62936009
RS		 472
473 ata_ehi_clear_desc(ehi);
474
2d20da00 475 sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
62936009
RS		 476 status = ap->ops->sff_check_status(ap);
477
62936009
RS		 478 tag = ap->link.active_tag;
479
8b344485
AS		 480 dev_err(ap->dev,
481 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
482 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
483 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
62936009
RS		 484
485 /* Clear error register and interrupt bit */
2d20da00 486 clear_serror(ap);
62936009
RS		 487 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
488
489 /* This is the only error happening now. TODO check for exact error */
490
491 err_mask |= AC_ERR_HOST_BUS;
492 action |= ATA_EH_RESET;
493
494 /* Pass this on to EH */
495 ehi->serror |= serror;
496 ehi->action |= action;
497
498 qc = ata_qc_from_tag(ap, tag);
499 if (qc)
500 qc->err_mask |= err_mask;
501 else
502 ehi->err_mask |= err_mask;
503
504 ata_port_abort(ap);
505}
506
507/*
508 * Function : sata_dwc_isr
509 * arguments : irq, void *dev_instance, struct pt_regs *regs
510 * Return value : irqreturn_t - status of IRQ
511 * This Interrupt handler called via port ops registered function.
512 * .irq_handler = sata_dwc_isr
513 */
514static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
515{
516 struct ata_host *host = (struct ata_host *)dev_instance;
517 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
518 struct ata_port *ap;
519 struct ata_queued_cmd *qc;
520 unsigned long flags;
521 u8 status, tag;
522 int handled, num_processed, port = 0;
523 uint intpr, sactive, sactive2, tag_mask;
524 struct sata_dwc_device_port *hsdevp;
2d20da00 525 hsdev->sactive_issued = 0;
62936009
RS		 526
527 spin_lock_irqsave(&host->lock, flags);
528
529 /* Read the interrupt register */
ee81d6cc 530 intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
62936009
RS		 531
532 ap = host->ports[port];
533 hsdevp = HSDEVP_FROM_AP(ap);
534
535 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
536 ap->link.active_tag);
537
538 /* Check for error interrupt */
539 if (intpr & SATA_DWC_INTPR_ERR) {
540 sata_dwc_error_intr(ap, hsdev, intpr);
541 handled = 1;
542 goto DONE;
543 }
544
545 /* Check for DMA SETUP FIS (FP DMA) interrupt */
546 if (intpr & SATA_DWC_INTPR_NEWFP) {
547 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
548
ee81d6cc 549 tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
62936009
RS		 550 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
551 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
552 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
553
2d20da00 554 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
62936009
RS		 555
556 qc = ata_qc_from_tag(ap, tag);
557 /*
558 * Start FP DMA for NCQ command. At this point the tag is the
559 * active tag. It is the tag that matches the command about to
560 * be completed.
561 */
562 qc->ap->link.active_tag = tag;
563 sata_dwc_bmdma_start_by_tag(qc, tag);
564
565 handled = 1;
566 goto DONE;
567 }
2d20da00
MR		 568 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
569 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
62936009
RS		 570
571 /* If no sactive issued and tag_mask is zero then this is not NCQ */
2d20da00 572 if (hsdev->sactive_issued == 0 && tag_mask == 0) {
62936009
RS		 573 if (ap->link.active_tag == ATA_TAG_POISON)
574 tag = 0;
575 else
576 tag = ap->link.active_tag;
577 qc = ata_qc_from_tag(ap, tag);
578
579 /* DEV interrupt w/ no active qc? */
580 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
d578514b
AS		 581 dev_err(ap->dev,
582 "%s interrupt with no active qc qc=%p\n",
583 __func__, qc);
62936009
RS		 584 ap->ops->sff_check_status(ap);
585 handled = 1;
586 goto DONE;
587 }
588 status = ap->ops->sff_check_status(ap);
589
590 qc->ap->link.active_tag = tag;
591 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
592
593 if (status & ATA_ERR) {
594 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
595 sata_dwc_qc_complete(ap, qc, 1);
596 handled = 1;
597 goto DONE;
598 }
599
600 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
84b47e3b 601 __func__, get_prot_descript(qc->tf.protocol));
62936009
RS		 602DRVSTILLBUSY:
603 if (ata_is_dma(qc->tf.protocol)) {
604 /*
605 * Each DMA transaction produces 2 interrupts. The DMAC
606 * transfer complete interrupt and the SATA controller
607 * operation done interrupt. The command should be
608 * completed only after both interrupts are seen.
609 */
8b344485 610 hsdevp->dma_interrupt_count++;
62936009
RS		 611 if (hsdevp->dma_pending[tag] == \
612 SATA_DWC_DMA_PENDING_NONE) {
d578514b
AS		 613 dev_err(ap->dev,
614 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
615 __func__, intpr, status,
62936009
RS		 616 hsdevp->dma_pending[tag]);
617 }
618
8b344485 619 if ((hsdevp->dma_interrupt_count % 2) == 0)
62936009
RS		 620 sata_dwc_dma_xfer_complete(ap, 1);
621 } else if (ata_is_pio(qc->tf.protocol)) {
622 ata_sff_hsm_move(ap, qc, status, 0);
623 handled = 1;
624 goto DONE;
625 } else {
626 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
627 goto DRVSTILLBUSY;
628 }
629
630 handled = 1;
631 goto DONE;
632 }
633
634 /*
635 * This is a NCQ command. At this point we need to figure out for which
636 * tags we have gotten a completion interrupt. One interrupt may serve
637 * as completion for more than one operation when commands are queued
638 * (NCQ). We need to process each completed command.
639 */
640
641 /* process completed commands */
2d20da00
MR		 642 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
643 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
62936009 644
2d20da00 645 if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
d578514b
AS		 646 dev_dbg(ap->dev,
647 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
2d20da00 648 __func__, sactive, hsdev->sactive_issued, tag_mask);
62936009
RS		 649 }
650
2d20da00 651 if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
d578514b 652 dev_warn(ap->dev,
2d20da00
MR		 653 "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
654 sactive, hsdev->sactive_issued, tag_mask);
62936009
RS		 655 }
656
657 /* read just to clear ... not bad if currently still busy */
658 status = ap->ops->sff_check_status(ap);
659 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
660
661 tag = 0;
662 num_processed = 0;
663 while (tag_mask) {
664 num_processed++;
665 while (!(tag_mask & 0x00000001)) {
666 tag++;
667 tag_mask <<= 1;
668 }
669
670 tag_mask &= (~0x00000001);
671 qc = ata_qc_from_tag(ap, tag);
672
673 /* To be picked up by completion functions */
674 qc->ap->link.active_tag = tag;
675 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
676
677 /* Let libata/scsi layers handle error */
678 if (status & ATA_ERR) {
679 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
680 status);
681 sata_dwc_qc_complete(ap, qc, 1);
682 handled = 1;
683 goto DONE;
684 }
685
686 /* Process completed command */
687 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
84b47e3b 688 get_prot_descript(qc->tf.protocol));
62936009 689 if (ata_is_dma(qc->tf.protocol)) {
8b344485 690 hsdevp->dma_interrupt_count++;
62936009
RS		 691 if (hsdevp->dma_pending[tag] == \
692 SATA_DWC_DMA_PENDING_NONE)
693 dev_warn(ap->dev, "%s: DMA not pending?\n",
694 __func__);
8b344485 695 if ((hsdevp->dma_interrupt_count % 2) == 0)
62936009
RS		 696 sata_dwc_dma_xfer_complete(ap, 1);
697 } else {
698 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
699 goto STILLBUSY;
700 }
701 continue;
702
703STILLBUSY:
704 ap->stats.idle_irq++;
705 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
706 ap->print_id);
707 } /* while tag_mask */
708
709 /*
710 * Check to see if any commands completed while we were processing our
711 * initial set of completed commands (read status clears interrupts,
712 * so we might miss a completed command interrupt if one came in while
713 * we were processing --we read status as part of processing a completed
714 * command).
715 */
2d20da00 716 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
62936009 717 if (sactive2 != sactive) {
d578514b
AS		 718 dev_dbg(ap->dev,
719 "More completed - sactive=0x%x sactive2=0x%x\n",
720 sactive, sactive2);
62936009
RS		 721 }
722 handled = 1;
723
724DONE:
725 spin_unlock_irqrestore(&host->lock, flags);
726 return IRQ_RETVAL(handled);
727}
728
729static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
730{
731 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
732
733 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
ee81d6cc
MR		 734 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
735 SATA_DWC_DMACR_RX_CLEAR(
736 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr)));
62936009 737 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
ee81d6cc
MR		 738 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
739 SATA_DWC_DMACR_TX_CLEAR(
740 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr)));
62936009
RS		 741 } else {
742 /*
743 * This should not happen, it indicates the driver is out of
744 * sync. If it does happen, clear dmacr anyway.
745 */
db7a657f 746 dev_err(hsdev->dev,
d578514b
AS		 747 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
748 __func__, tag, hsdevp->dma_pending[tag],
ee81d6cc
MR		 749 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
750 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
751 SATA_DWC_DMACR_TXRXCH_CLEAR);
62936009
RS		 752 }
753}
754
755static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
756{
757 struct ata_queued_cmd *qc;
758 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
759 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
760 u8 tag = 0;
761
762 tag = ap->link.active_tag;
763 qc = ata_qc_from_tag(ap, tag);
764 if (!qc) {
765 dev_err(ap->dev, "failed to get qc");
766 return;
767 }
768
769#ifdef DEBUG_NCQ
770 if (tag > 0) {
d578514b
AS		 771 dev_info(ap->dev,
772 "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
773 __func__, qc->tag, qc->tf.command,
84b47e3b
SS		 774 get_dma_dir_descript(qc->dma_dir),
775 get_prot_descript(qc->tf.protocol),
ee81d6cc 776 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
62936009
RS		 777 }
778#endif
779
780 if (ata_is_dma(qc->tf.protocol)) {
781 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
d578514b
AS		 782 dev_err(ap->dev,
783 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
784 __func__,
ee81d6cc 785 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
62936009
RS		 786 }
787
788 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
789 sata_dwc_qc_complete(ap, qc, check_status);
790 ap->link.active_tag = ATA_TAG_POISON;
791 } else {
792 sata_dwc_qc_complete(ap, qc, check_status);
793 }
794}
795
796static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
797 u32 check_status)
798{
799 u8 status = 0;
800 u32 mask = 0x0;
801 u8 tag = qc->tag;
2d20da00 802 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
62936009 803 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
2d20da00 804 hsdev->sactive_queued = 0;
62936009
RS		 805 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
806
807 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
808 dev_err(ap->dev, "TX DMA PENDING\n");
809 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
810 dev_err(ap->dev, "RX DMA PENDING\n");
d578514b
AS		 811 dev_dbg(ap->dev,
812 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
813 qc->tf.command, status, ap->print_id, qc->tf.protocol);
62936009
RS		 814
815 /* clear active bit */
816 mask = (~(qcmd_tag_to_mask(tag)));
2d20da00
MR		 817 hsdev->sactive_queued = hsdev->sactive_queued & mask;
818 hsdev->sactive_issued = hsdev->sactive_issued & mask;
62936009
RS		 819 ata_qc_complete(qc);
820 return 0;
821}
822
823static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
824{
825 /* Enable selective interrupts by setting the interrupt maskregister*/
ee81d6cc
MR		 826 sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
827 SATA_DWC_INTMR_ERRM |
828 SATA_DWC_INTMR_NEWFPM |
829 SATA_DWC_INTMR_PMABRTM |
830 SATA_DWC_INTMR_DMATM);
62936009
RS		 831 /*
832 * Unmask the error bits that should trigger an error interrupt by
833 * setting the error mask register.
834 */
ee81d6cc 835 sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
62936009 836
db7a657f 837 dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
ee81d6cc
MR		 838 __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
839 sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
62936009
RS		 840}
841
ae95d951 842static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
62936009 843{
ae95d951
MR		 844 port->cmd_addr = base + 0x00;
845 port->data_addr = base + 0x00;
62936009 846
ae95d951
MR		 847 port->error_addr = base + 0x04;
848 port->feature_addr = base + 0x04;
62936009 849
ae95d951 850 port->nsect_addr = base + 0x08;
62936009 851
ae95d951
MR		 852 port->lbal_addr = base + 0x0c;
853 port->lbam_addr = base + 0x10;
854 port->lbah_addr = base + 0x14;
62936009 855
ae95d951
MR		 856 port->device_addr = base + 0x18;
857 port->command_addr = base + 0x1c;
858 port->status_addr = base + 0x1c;
62936009 859
ae95d951
MR		 860 port->altstatus_addr = base + 0x20;
861 port->ctl_addr = base + 0x20;
62936009
RS		 862}
863
50b43375
MR		 864static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
865{
866 struct sata_dwc_device *hsdev = hsdevp->hsdev;
867 struct device *dev = hsdev->dev;
868
869#ifdef CONFIG_SATA_DWC_OLD_DMA
870 if (!of_find_property(dev->of_node, "dmas", NULL))
871 return sata_dwc_dma_get_channel_old(hsdevp);
872#endif
873
874 hsdevp->chan = dma_request_chan(dev, "sata-dma");
875 if (IS_ERR(hsdevp->chan)) {
876 dev_err(dev, "failed to allocate dma channel: %ld\n",
877 PTR_ERR(hsdevp->chan));
878 return PTR_ERR(hsdevp->chan);
879 }
880
881 return 0;
882}
883
62936009
RS		 884/*
885 * Function : sata_dwc_port_start
886 * arguments : struct ata_ioports *port
887 * Return value : returns 0 if success, error code otherwise
888 * This function allocates the scatter gather LLI table for AHB DMA
889 */
890static int sata_dwc_port_start(struct ata_port *ap)
891{
892 int err = 0;
893 struct sata_dwc_device *hsdev;
894 struct sata_dwc_device_port *hsdevp = NULL;
895 struct device *pdev;
896 int i;
897
898 hsdev = HSDEV_FROM_AP(ap);
899
900 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
901
902 hsdev->host = ap->host;
903 pdev = ap->host->dev;
904 if (!pdev) {
905 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
906 err = -ENODEV;
907 goto CLEANUP;
908 }
909
910 /* Allocate Port Struct */
911 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
912 if (!hsdevp) {
913 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
914 err = -ENOMEM;
915 goto CLEANUP;
916 }
917 hsdevp->hsdev = hsdev;
918
50b43375
MR		 919 err = sata_dwc_dma_get_channel(hsdevp);
920 if (err)
8b344485 921 goto CLEANUP_ALLOC;
8b344485 922
0f48debd
MR		 923 err = phy_power_on(hsdev->phy);
924 if (err)
925 goto CLEANUP_ALLOC;
926
62936009
RS		 927 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
928 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
929
d7c256e8 930 ap->bmdma_prd = NULL; /* set these so libata doesn't use them */
62936009
RS		 931 ap->bmdma_prd_dma = 0;
932
62936009
RS		 933 if (ap->port_no == 0) {
934 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
935 __func__);
ee81d6cc
MR		 936 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
937 SATA_DWC_DMACR_TXRXCH_CLEAR);
62936009
RS		 938
939 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
940 __func__);
ee81d6cc
MR		 941 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
942 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
943 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
62936009
RS		 944 }
945
946 /* Clear any error bits before libata starts issuing commands */
2d20da00 947 clear_serror(ap);
62936009 948 ap->private_data = hsdevp;
a081da63
JL		 949 dev_dbg(ap->dev, "%s: done\n", __func__);
950 return 0;
62936009 951
a081da63
JL		 952CLEANUP_ALLOC:
953 kfree(hsdevp);
62936009 954CLEANUP:
a081da63 955 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
62936009
RS		 956 return err;
957}
958
959static void sata_dwc_port_stop(struct ata_port *ap)
960{
62936009 961 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
0f48debd 962 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
62936009
RS		 963
964 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
965
9e8b855e 966 dmaengine_terminate_sync(hsdevp->chan);
8b344485 967 dma_release_channel(hsdevp->chan);
0f48debd 968 phy_power_off(hsdev->phy);
62936009 969
8b344485 970 kfree(hsdevp);
62936009
RS		 971 ap->private_data = NULL;
972}
973
974/*
975 * Function : sata_dwc_exec_command_by_tag
976 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
977 * Return value : None
978 * This function keeps track of individual command tag ids and calls
979 * ata_exec_command in libata
980 */
981static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
982 struct ata_taskfile *tf,
983 u8 tag, u32 cmd_issued)
984{
62936009
RS		 985 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
986
987 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
c211962d 988 ata_get_cmd_descript(tf->command), tag);
62936009 989
62936009 990 hsdevp->cmd_issued[tag] = cmd_issued;
55e610cd 991
62936009
RS		 992 /*
993 * Clear SError before executing a new command.
994 * sata_dwc_scr_write and read can not be used here. Clearing the PM
995 * managed SError register for the disk needs to be done before the
996 * task file is loaded.
997 */
2d20da00 998 clear_serror(ap);
62936009
RS		 999 ata_sff_exec_command(ap, tf);
1000}
1001
1002static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1003{
1004 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1005 SATA_DWC_CMD_ISSUED_PEND);
1006}
1007
1008static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1009{
1010 u8 tag = qc->tag;
1011
1012 if (ata_is_ncq(qc->tf.protocol)) {
1013 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1014 __func__, qc->ap->link.sactive, tag);
1015 } else {
1016 tag = 0;
1017 }
1018 sata_dwc_bmdma_setup_by_tag(qc, tag);
1019}
1020
1021static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1022{
1023 int start_dma;
8b344485 1024 u32 reg;
62936009
RS		 1025 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1026 struct ata_port *ap = qc->ap;
1027 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
8b344485 1028 struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
62936009 1029 int dir = qc->dma_dir;
62936009
RS		 1030
1031 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1032 start_dma = 1;
1033 if (dir == DMA_TO_DEVICE)
1034 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1035 else
1036 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1037 } else {
d578514b
AS		 1038 dev_err(ap->dev,
1039 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
1040 __func__, hsdevp->cmd_issued[tag], tag);
62936009
RS		 1041 start_dma = 0;
1042 }
1043
d578514b
AS		 1044 dev_dbg(ap->dev,
1045 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
1046 __func__, qc, tag, qc->tf.command,
84b47e3b 1047 get_dma_dir_descript(qc->dma_dir), start_dma);
db7a657f 1048 sata_dwc_tf_dump(ap, &qc->tf);
62936009
RS		 1049
1050 if (start_dma) {
2d20da00 1051 sata_dwc_scr_read(&ap->link, SCR_ERROR, &reg);
62936009
RS		 1052 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1053 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1054 __func__, reg);
1055 }
1056
1057 if (dir == DMA_TO_DEVICE)
ee81d6cc
MR		 1058 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1059 SATA_DWC_DMACR_TXCHEN);
62936009 1060 else
ee81d6cc
MR		 1061 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1062 SATA_DWC_DMACR_RXCHEN);
62936009
RS		 1063
1064 /* Enable AHB DMA transfer on the specified channel */
8b344485
AS		 1065 dmaengine_submit(desc);
1066 dma_async_issue_pending(hsdevp->chan);
62936009
RS		 1067 }
1068}
1069
1070static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1071{
1072 u8 tag = qc->tag;
1073
1074 if (ata_is_ncq(qc->tf.protocol)) {
1075 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1076 __func__, qc->ap->link.sactive, tag);
1077 } else {
1078 tag = 0;
1079 }
1080 dev_dbg(qc->ap->dev, "%s\n", __func__);
1081 sata_dwc_bmdma_start_by_tag(qc, tag);
1082}
1083
62936009
RS		 1084static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1085{
1086 u32 sactive;
1087 u8 tag = qc->tag;
1088 struct ata_port *ap = qc->ap;
ae4c3485 1089 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
62936009
RS		 1090
1091#ifdef DEBUG_NCQ
1092 if (qc->tag > 0 || ap->link.sactive > 1)
d578514b
AS		 1093 dev_info(ap->dev,
1094 "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
62936009 1095 __func__, ap->print_id, qc->tf.command,
c211962d 1096 ata_get_cmd_descript(qc->tf.command),
84b47e3b 1097 qc->tag, get_prot_descript(qc->tf.protocol),
62936009
RS		 1098 ap->link.active_tag, ap->link.sactive);
1099#endif
1100
1101 if (!ata_is_ncq(qc->tf.protocol))
1102 tag = 0;
ae4c3485
MR		 1103
1104 if (ata_is_dma(qc->tf.protocol)) {
1105 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1106 if (!hsdevp->desc[tag])
1107 return AC_ERR_SYSTEM;
1108 } else {
1109 hsdevp->desc[tag] = NULL;
1110 }
62936009
RS		 1111
1112 if (ata_is_ncq(qc->tf.protocol)) {
2d20da00 1113 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
62936009 1114 sactive |= (0x00000001 << tag);
2d20da00 1115 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
62936009 1116
d578514b
AS		 1117 dev_dbg(qc->ap->dev,
1118 "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1119 __func__, tag, qc->ap->link.sactive, sactive);
62936009
RS		 1120
1121 ap->ops->sff_tf_load(ap, &qc->tf);
077028ec 1122 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
62936009
RS		 1123 SATA_DWC_CMD_ISSUED_PEND);
1124 } else {
077028ec 1125 return ata_bmdma_qc_issue(qc);
62936009
RS		 1126 }
1127 return 0;
1128}
1129
62936009
RS		 1130static void sata_dwc_error_handler(struct ata_port *ap)
1131{
62936009
RS		 1132 ata_sff_error_handler(ap);
1133}
1134
d7c256e8
AS		 1135static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1136 unsigned long deadline)
3a8b788f
TN		 1137{
1138 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1139 int ret;
1140
1141 ret = sata_sff_hardreset(link, class, deadline);
1142
1143 sata_dwc_enable_interrupts(hsdev);
1144
1145 /* Reconfigure the DMA control register */
ee81d6cc
MR		 1146 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1147 SATA_DWC_DMACR_TXRXCH_CLEAR);
3a8b788f
TN		 1148
1149 /* Reconfigure the DMA Burst Transaction Size register */
ee81d6cc
MR		 1150 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
1151 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1152 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
3a8b788f
TN		 1153
1154 return ret;
1155}
1156
a7e6de54
CL		 1157static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1158{
1159 /* SATA DWC is master only */
1160}
1161
62936009
RS		 1162/*
1163 * scsi mid-layer and libata interface structures
1164 */
1165static struct scsi_host_template sata_dwc_sht = {
1166 ATA_NCQ_SHT(DRV_NAME),
1167 /*
1168 * test-only: Currently this driver doesn't handle NCQ
1169 * correctly. We enable NCQ but set the queue depth to a
1170 * max of 1. This will get fixed in in a future release.
1171 */
1172 .sg_tablesize = LIBATA_MAX_PRD,
d7c256e8 1173 /* .can_queue = ATA_MAX_QUEUE, */
6689dfac
AS		 1174 /*
1175 * Make sure a LLI block is not created that will span 8K max FIS
1176 * boundary. If the block spans such a FIS boundary, there is a chance
1177 * that a DMA burst will cross that boundary -- this results in an
1178 * error in the host controller.
1179 */
1180 .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
62936009
RS		 1181};
1182
1183static struct ata_port_operations sata_dwc_ops = {
1184 .inherits = &ata_sff_port_ops,
1185
1186 .error_handler = sata_dwc_error_handler,
3a8b788f 1187 .hardreset = sata_dwc_hardreset,
62936009 1188
62936009
RS		 1189 .qc_issue = sata_dwc_qc_issue,
1190
1191 .scr_read = sata_dwc_scr_read,
1192 .scr_write = sata_dwc_scr_write,
1193
1194 .port_start = sata_dwc_port_start,
1195 .port_stop = sata_dwc_port_stop,
1196
a7e6de54
CL		 1197 .sff_dev_select = sata_dwc_dev_select,
1198
62936009
RS		 1199 .bmdma_setup = sata_dwc_bmdma_setup,
1200 .bmdma_start = sata_dwc_bmdma_start,
1201};
1202
1203static const struct ata_port_info sata_dwc_port_info[] = {
1204 {
9cbe056f 1205 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
b83a4c39 1206 .pio_mask = ATA_PIO4,
62936009
RS		 1207 .udma_mask = ATA_UDMA6,
1208 .port_ops = &sata_dwc_ops,
1209 },
1210};
1211
1c48a5c9 1212static int sata_dwc_probe(struct platform_device *ofdev)
62936009
RS		 1213{
1214 struct sata_dwc_device *hsdev;
1215 u32 idr, versionr;
1216 char *ver = (char *)&versionr;
175553ed 1217 void __iomem *base;
62936009 1218 int err = 0;
4aaa7187 1219 int irq;
62936009
RS		 1220 struct ata_host *host;
1221 struct ata_port_info pi = sata_dwc_port_info[0];
1222 const struct ata_port_info *ppi[] = { &pi, NULL };
dc7f71f4 1223 struct device_node *np = ofdev->dev.of_node;
62936009
RS		 1224
1225 /* Allocate DWC SATA device */
d537fc0c
AS		 1226 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1227 hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
1228 if (!host || !hsdev)
c592b74f 1229 return -ENOMEM;
62936009 1230
d537fc0c
AS		 1231 host->private_data = hsdev;
1232
62936009 1233 /* Ioremap SATA registers */
9037908f 1234 base = of_iomap(np, 0);
62936009 1235 if (!base) {
d578514b
AS		 1236 dev_err(&ofdev->dev,
1237 "ioremap failed for SATA register address\n");
d537fc0c 1238 return -ENODEV;
62936009
RS		 1239 }
1240 hsdev->reg_base = base;
1241 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1242
1243 /* Synopsys DWC SATA specific Registers */
175553ed 1244 hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
62936009 1245
62936009
RS		 1246 /* Setup port */
1247 host->ports[0]->ioaddr.cmd_addr = base;
1248 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
ae95d951 1249 sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
62936009
RS		 1250
1251 /* Read the ID and Version Registers */
ee81d6cc
MR		 1252 idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
1253 versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
62936009
RS		 1254 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1255 idr, ver[0], ver[1], ver[2]);
1256
62936009 1257 /* Save dev for later use in dev_xxx() routines */
db7a657f 1258 hsdev->dev = &ofdev->dev;
62936009 1259
62936009
RS		 1260 /* Enable SATA Interrupts */
1261 sata_dwc_enable_interrupts(hsdev);
1262
1263 /* Get SATA interrupt number */
9037908f 1264 irq = irq_of_parse_and_map(np, 0);
62936009
RS		 1265 if (irq == NO_IRQ) {
1266 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1267 err = -ENODEV;
1268 goto error_out;
1269 }
1270
50b43375
MR		 1271#ifdef CONFIG_SATA_DWC_OLD_DMA
1272 if (!of_find_property(np, "dmas", NULL)) {
1273 err = sata_dwc_dma_init_old(ofdev, hsdev);
1274 if (err)
1275 goto error_out;
1276 }
1277#endif
1278
0f48debd
MR		 1279 hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
1280 if (IS_ERR(hsdev->phy)) {
1281 err = PTR_ERR(hsdev->phy);
1282 hsdev->phy = NULL;
1283 goto error_out;
1284 }
1285
1286 err = phy_init(hsdev->phy);
1287 if (err)
1288 goto error_out;
1289
62936009
RS		 1290 /*
1291 * Now, register with libATA core, this will also initiate the
1292 * device discovery process, invoking our port_start() handler &
1293 * error_handler() to execute a dummy Softreset EH session
1294 */
4aaa7187
AS		 1295 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1296 if (err)
62936009
RS		 1297 dev_err(&ofdev->dev, "failed to activate host");
1298
1299 dev_set_drvdata(&ofdev->dev, host);
1300 return 0;
1301
1302error_out:
0f48debd 1303 phy_exit(hsdev->phy);
04e506b5 1304 iounmap(base);
62936009
RS		 1305 return err;
1306}
1307
60652d07 1308static int sata_dwc_remove(struct platform_device *ofdev)
62936009
RS		 1309{
1310 struct device *dev = &ofdev->dev;
1311 struct ata_host *host = dev_get_drvdata(dev);
1312 struct sata_dwc_device *hsdev = host->private_data;
1313
1314 ata_host_detach(host);
62936009 1315
0f48debd
MR		 1316 phy_exit(hsdev->phy);
1317
50b43375 1318#ifdef CONFIG_SATA_DWC_OLD_DMA
62936009 1319 /* Free SATA DMA resources */
50b43375
MR		 1320 sata_dwc_dma_exit_old(hsdev);
1321#endif
62936009
RS		 1322
1323 iounmap(hsdev->reg_base);
62936009
RS		 1324 dev_dbg(&ofdev->dev, "done\n");
1325 return 0;
1326}
1327
1328static const struct of_device_id sata_dwc_match[] = {
1329 { .compatible = "amcc,sata-460ex", },
1330 {}
1331};
1332MODULE_DEVICE_TABLE(of, sata_dwc_match);
1333
1c48a5c9 1334static struct platform_driver sata_dwc_driver = {
62936009
RS		 1335 .driver = {
1336 .name = DRV_NAME,
62936009
RS		 1337 .of_match_table = sata_dwc_match,
1338 },
1339 .probe = sata_dwc_probe,
1340 .remove = sata_dwc_remove,
1341};
1342
99c8ea3e 1343module_platform_driver(sata_dwc_driver);
62936009
RS		 1344
1345MODULE_LICENSE("GPL");
1346MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
d578514b 1347MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
62936009 1348MODULE_VERSION(DRV_VERSION);