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ata: sata_highbank: remove superfluous cast
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ata / sata_dwc_460ex.c
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62936009
RS		 1/*
2 * drivers/ata/sata_dwc_460ex.c
3 *
4 * Synopsys DesignWare Cores (DWC) SATA host driver
5 *
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
7 *
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
10 *
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifdef CONFIG_SATA_DWC_DEBUG
22#define DEBUG
23#endif
24
25#ifdef CONFIG_SATA_DWC_VDEBUG
26#define VERBOSE_DEBUG
27#define DEBUG_NCQ
28#endif
29
30#include <linux/kernel.h>
31#include <linux/module.h>
62936009 32#include <linux/device.h>
c11eede6
RH		 33#include <linux/of_address.h>
34#include <linux/of_irq.h>
62936009
RS		 35#include <linux/of_platform.h>
36#include <linux/platform_device.h>
37#include <linux/libata.h>
38#include <linux/slab.h>
39#include "libata.h"
40
41#include <scsi/scsi_host.h>
42#include <scsi/scsi_cmnd.h>
43
c211962d
SS		 44/* These two are defined in "libata.h" */
45#undef DRV_NAME
46#undef DRV_VERSION
72d5f2da 47
62936009 48#define DRV_NAME "sata-dwc"
84b47e3b 49#define DRV_VERSION "1.3"
62936009
RS		 50
51/* SATA DMA driver Globals */
52#define DMA_NUM_CHANS 1
53#define DMA_NUM_CHAN_REGS 8
54
55/* SATA DMA Register definitions */
56#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
57
58struct dmareg {
59 u32 low; /* Low bits 0-31 */
60 u32 high; /* High bits 32-63 */
61};
62
63/* DMA Per Channel registers */
64struct dma_chan_regs {
65 struct dmareg sar; /* Source Address */
66 struct dmareg dar; /* Destination address */
67 struct dmareg llp; /* Linked List Pointer */
68 struct dmareg ctl; /* Control */
69 struct dmareg sstat; /* Source Status not implemented in core */
70 struct dmareg dstat; /* Destination Status not implemented in core*/
71 struct dmareg sstatar; /* Source Status Address not impl in core */
72 struct dmareg dstatar; /* Destination Status Address not implemente */
73 struct dmareg cfg; /* Config */
74 struct dmareg sgr; /* Source Gather */
75 struct dmareg dsr; /* Destination Scatter */
76};
77
78/* Generic Interrupt Registers */
79struct dma_interrupt_regs {
80 struct dmareg tfr; /* Transfer Interrupt */
81 struct dmareg block; /* Block Interrupt */
82 struct dmareg srctran; /* Source Transfer Interrupt */
83 struct dmareg dsttran; /* Dest Transfer Interrupt */
84 struct dmareg error; /* Error */
85};
86
87struct ahb_dma_regs {
88 struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
89 struct dma_interrupt_regs interrupt_raw; /* Raw Interrupt */
90 struct dma_interrupt_regs interrupt_status; /* Interrupt Status */
91 struct dma_interrupt_regs interrupt_mask; /* Interrupt Mask */
92 struct dma_interrupt_regs interrupt_clear; /* Interrupt Clear */
93 struct dmareg statusInt; /* Interrupt combined*/
94 struct dmareg rq_srcreg; /* Src Trans Req */
95 struct dmareg rq_dstreg; /* Dst Trans Req */
96 struct dmareg rq_sgl_srcreg; /* Sngl Src Trans Req*/
97 struct dmareg rq_sgl_dstreg; /* Sngl Dst Trans Req*/
98 struct dmareg rq_lst_srcreg; /* Last Src Trans Req*/
99 struct dmareg rq_lst_dstreg; /* Last Dst Trans Req*/
100 struct dmareg dma_cfg; /* DMA Config */
101 struct dmareg dma_chan_en; /* DMA Channel Enable*/
102 struct dmareg dma_id; /* DMA ID */
103 struct dmareg dma_test; /* DMA Test */
104 struct dmareg res1; /* reserved */
105 struct dmareg res2; /* reserved */
106 /*
107 * DMA Comp Params
108 * Param 6 = dma_param[0], Param 5 = dma_param[1],
109 * Param 4 = dma_param[2] ...
110 */
111 struct dmareg dma_params[6];
112};
113
114/* Data structure for linked list item */
115struct lli {
116 u32 sar; /* Source Address */
117 u32 dar; /* Destination address */
118 u32 llp; /* Linked List Pointer */
119 struct dmareg ctl; /* Control */
120 struct dmareg dstat; /* Destination Status */
121};
122
123enum {
124 SATA_DWC_DMAC_LLI_SZ = (sizeof(struct lli)),
125 SATA_DWC_DMAC_LLI_NUM = 256,
126 SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \
127 SATA_DWC_DMAC_LLI_NUM),
128 SATA_DWC_DMAC_TWIDTH_BYTES = 4,
129 SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \
130 SATA_DWC_DMAC_TWIDTH_BYTES),
131};
132
133/* DMA Register Operation Bits */
134enum {
135 DMA_EN = 0x00000001, /* Enable AHB DMA */
136 DMA_CTL_LLP_SRCEN = 0x10000000, /* Blk chain enable Src */
137 DMA_CTL_LLP_DSTEN = 0x08000000, /* Blk chain enable Dst */
138};
139
140#define DMA_CTL_BLK_TS(size) ((size) & 0x000000FFF) /* Blk Transfer size */
141#define DMA_CHANNEL(ch) (0x00000001 << (ch)) /* Select channel */
142 /* Enable channel */
143#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
144 ((0x000000001 << (ch)) << 8))
145 /* Disable channel */
146#define DMA_DISABLE_CHAN(ch) (0x00000000 | ((0x000000001 << (ch)) << 8))
147 /* Transfer Type & Flow Controller */
148#define DMA_CTL_TTFC(type) (((type) & 0x7) << 20)
149#define DMA_CTL_SMS(num) (((num) & 0x3) << 25) /* Src Master Select */
150#define DMA_CTL_DMS(num) (((num) & 0x3) << 23)/* Dst Master Select */
151 /* Src Burst Transaction Length */
152#define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14)
153 /* Dst Burst Transaction Length */
154#define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11)
155 /* Source Transfer Width */
156#define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4)
157 /* Destination Transfer Width */
158#define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1)
159
160/* Assign HW handshaking interface (x) to destination / source peripheral */
161#define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11)
162#define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7)
dc7f71f4 163#define DMA_CFG_HW_CH_PRIOR(int_num) (((int_num) & 0xF) << 5)
62936009
RS		 164#define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
165
166/*
167 * This define is used to set block chaining disabled in the control low
168 * register. It is already in little endian format so it can be &'d dirctly.
169 * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
170 */
171enum {
172 DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7,
173 DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */
174 DMA_CTL_TTFC_M2P_PER = 0x00000003, /* Mem to per, peripheral cntr */
175 DMA_CTL_SINC_INC = 0x00000000, /* Source Address Increment */
176 DMA_CTL_SINC_DEC = 0x00000200,
177 DMA_CTL_SINC_NOCHANGE = 0x00000400,
178 DMA_CTL_DINC_INC = 0x00000000, /* Destination Address Increment */
179 DMA_CTL_DINC_DEC = 0x00000080,
180 DMA_CTL_DINC_NOCHANGE = 0x00000100,
181 DMA_CTL_INT_EN = 0x00000001, /* Interrupt Enable */
182
183/* Channel Configuration Register high bits */
184 DMA_CFG_FCMOD_REQ = 0x00000001, /* Flow Control - request based */
185 DMA_CFG_PROTCTL = (0x00000003 << 2),/* Protection Control */
186
187/* Channel Configuration Register low bits */
188 DMA_CFG_RELD_DST = 0x80000000, /* Reload Dest / Src Addr */
189 DMA_CFG_RELD_SRC = 0x40000000,
190 DMA_CFG_HS_SELSRC = 0x00000800, /* Software handshake Src/ Dest */
191 DMA_CFG_HS_SELDST = 0x00000400,
192 DMA_CFG_FIFOEMPTY = (0x00000001 << 9), /* FIFO Empty bit */
193
194/* Channel Linked List Pointer Register */
195 DMA_LLP_AHBMASTER1 = 0, /* List Master Select */
196 DMA_LLP_AHBMASTER2 = 1,
197
198 SATA_DWC_MAX_PORTS = 1,
199
200 SATA_DWC_SCR_OFFSET = 0x24,
201 SATA_DWC_REG_OFFSET = 0x64,
202};
203
204/* DWC SATA Registers */
205struct sata_dwc_regs {
206 u32 fptagr; /* 1st party DMA tag */
207 u32 fpbor; /* 1st party DMA buffer offset */
208 u32 fptcr; /* 1st party DMA Xfr count */
209 u32 dmacr; /* DMA Control */
210 u32 dbtsr; /* DMA Burst Transac size */
211 u32 intpr; /* Interrupt Pending */
212 u32 intmr; /* Interrupt Mask */
213 u32 errmr; /* Error Mask */
214 u32 llcr; /* Link Layer Control */
215 u32 phycr; /* PHY Control */
216 u32 physr; /* PHY Status */
217 u32 rxbistpd; /* Recvd BIST pattern def register */
218 u32 rxbistpd1; /* Recvd BIST data dword1 */
219 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
220 u32 txbistpd; /* Trans BIST pattern def register */
221 u32 txbistpd1; /* Trans BIST data dword1 */
222 u32 txbistpd2; /* Trans BIST data dword2 */
223 u32 bistcr; /* BIST Control Register */
224 u32 bistfctr; /* BIST FIS Count Register */
225 u32 bistsr; /* BIST Status Register */
226 u32 bistdecr; /* BIST Dword Error count register */
227 u32 res[15]; /* Reserved locations */
228 u32 testr; /* Test Register */
229 u32 versionr; /* Version Register */
230 u32 idr; /* ID Register */
231 u32 unimpl[192]; /* Unimplemented */
232 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
233};
234
235enum {
236 SCR_SCONTROL_DET_ENABLE = 0x00000001,
237 SCR_SSTATUS_DET_PRESENT = 0x00000001,
238 SCR_SERROR_DIAG_X = 0x04000000,
239/* DWC SATA Register Operations */
240 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
241 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
242 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
243 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
244 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
245 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
246 SATA_DWC_INTPR_DMAT = 0x00000001,
247 SATA_DWC_INTPR_NEWFP = 0x00000002,
248 SATA_DWC_INTPR_PMABRT = 0x00000004,
249 SATA_DWC_INTPR_ERR = 0x00000008,
250 SATA_DWC_INTPR_NEWBIST = 0x00000010,
251 SATA_DWC_INTPR_IPF = 0x10000000,
252 SATA_DWC_INTMR_DMATM = 0x00000001,
253 SATA_DWC_INTMR_NEWFPM = 0x00000002,
254 SATA_DWC_INTMR_PMABRTM = 0x00000004,
255 SATA_DWC_INTMR_ERRM = 0x00000008,
256 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
257 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
258 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
259 SATA_DWC_LLCR_RPDEN = 0x00000004,
260/* This is all error bits, zero's are reserved fields. */
261 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
262};
263
264#define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
265#define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
266 SATA_DWC_DMACR_TMOD_TXCHEN)
267#define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
268 SATA_DWC_DMACR_TMOD_TXCHEN)
269#define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
270#define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
271 << 16)
272struct sata_dwc_device {
273 struct device *dev; /* generic device struct */
274 struct ata_probe_ent *pe; /* ptr to probe-ent */
275 struct ata_host *host;
276 u8 *reg_base;
277 struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
278 int irq_dma;
279};
280
281#define SATA_DWC_QCMD_MAX 32
282
283struct sata_dwc_device_port {
284 struct sata_dwc_device *hsdev;
285 int cmd_issued[SATA_DWC_QCMD_MAX];
286 struct lli *llit[SATA_DWC_QCMD_MAX]; /* DMA LLI table */
287 dma_addr_t llit_dma[SATA_DWC_QCMD_MAX];
288 u32 dma_chan[SATA_DWC_QCMD_MAX];
289 int dma_pending[SATA_DWC_QCMD_MAX];
290};
291
292/*
293 * Commonly used DWC SATA driver Macros
294 */
295#define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
296 (host)->private_data)
297#define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
298 (ap)->host->private_data)
299#define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
300 (ap)->private_data)
301#define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
302 (qc)->ap->host->private_data)
303#define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
304 (hsdevp)->hsdev)
305
306enum {
307 SATA_DWC_CMD_ISSUED_NOT = 0,
308 SATA_DWC_CMD_ISSUED_PEND = 1,
309 SATA_DWC_CMD_ISSUED_EXEC = 2,
310 SATA_DWC_CMD_ISSUED_NODATA = 3,
311
312 SATA_DWC_DMA_PENDING_NONE = 0,
313 SATA_DWC_DMA_PENDING_TX = 1,
314 SATA_DWC_DMA_PENDING_RX = 2,
315};
316
317struct sata_dwc_host_priv {
318 void __iomem *scr_addr_sstatus;
319 u32 sata_dwc_sactive_issued ;
320 u32 sata_dwc_sactive_queued ;
321 u32 dma_interrupt_count;
322 struct ahb_dma_regs *sata_dma_regs;
323 struct device *dwc_dev;
dc7f71f4 324 int dma_channel;
62936009
RS		 325};
326struct sata_dwc_host_priv host_pvt;
327/*
328 * Prototypes
329 */
330static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
331static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
332 u32 check_status);
333static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
334static void sata_dwc_port_stop(struct ata_port *ap);
335static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
336static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq);
337static void dma_dwc_exit(struct sata_dwc_device *hsdev);
338static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
339 struct lli *lli, dma_addr_t dma_lli,
340 void __iomem *addr, int dir);
341static void dma_dwc_xfer_start(int dma_ch);
342
84b47e3b
SS		 343static const char *get_prot_descript(u8 protocol)
344{
345 switch ((enum ata_tf_protocols)protocol) {
346 case ATA_PROT_NODATA:
347 return "ATA no data";
348 case ATA_PROT_PIO:
349 return "ATA PIO";
350 case ATA_PROT_DMA:
351 return "ATA DMA";
352 case ATA_PROT_NCQ:
353 return "ATA NCQ";
354 case ATAPI_PROT_NODATA:
355 return "ATAPI no data";
356 case ATAPI_PROT_PIO:
357 return "ATAPI PIO";
358 case ATAPI_PROT_DMA:
359 return "ATAPI DMA";
360 default:
361 return "unknown";
362 }
363}
364
365static const char *get_dma_dir_descript(int dma_dir)
366{
367 switch ((enum dma_data_direction)dma_dir) {
368 case DMA_BIDIRECTIONAL:
369 return "bidirectional";
370 case DMA_TO_DEVICE:
371 return "to device";
372 case DMA_FROM_DEVICE:
373 return "from device";
374 default:
375 return "none";
376 }
377}
378
62936009
RS		 379static void sata_dwc_tf_dump(struct ata_taskfile *tf)
380{
381 dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:"
84b47e3b
SS		 382 "0x%lx device: %x\n", tf->command,
383 get_prot_descript(tf->protocol), tf->flags, tf->device);
62936009
RS		 384 dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x "
385 "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
386 tf->lbam, tf->lbah);
387 dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x "
388 "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
389 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
390 tf->hob_lbah);
391}
392
393/*
394 * Function: get_burst_length_encode
395 * arguments: datalength: length in bytes of data
8618ccd3 396 * returns value to be programmed in register corresponding to data length
62936009
RS		 397 * This value is effectively the log(base 2) of the length
398 */
399static int get_burst_length_encode(int datalength)
400{
401 int items = datalength >> 2; /* div by 4 to get lword count */
402
403 if (items >= 64)
404 return 5;
405
406 if (items >= 32)
407 return 4;
408
409 if (items >= 16)
410 return 3;
411
412 if (items >= 8)
413 return 2;
414
415 if (items >= 4)
416 return 1;
417
418 return 0;
419}
420
421static void clear_chan_interrupts(int c)
422{
423 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low),
424 DMA_CHANNEL(c));
425 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low),
426 DMA_CHANNEL(c));
427 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low),
428 DMA_CHANNEL(c));
429 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low),
430 DMA_CHANNEL(c));
431 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low),
432 DMA_CHANNEL(c));
433}
434
435/*
436 * Function: dma_request_channel
437 * arguments: None
438 * returns channel number if available else -1
439 * This function assigns the next available DMA channel from the list to the
440 * requester
441 */
442static int dma_request_channel(void)
443{
dc7f71f4
TN		 444 /* Check if the channel is not currently in use */
445 if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) &
446 DMA_CHANNEL(host_pvt.dma_channel)))
447 return host_pvt.dma_channel;
448 dev_err(host_pvt.dwc_dev, "%s Channel %d is currently in use\n",
449 __func__, host_pvt.dma_channel);
62936009
RS		 450 return -1;
451}
452
453/*
454 * Function: dma_dwc_interrupt
455 * arguments: irq, dev_id, pt_regs
456 * returns channel number if available else -1
457 * Interrupt Handler for DW AHB SATA DMA
458 */
459static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
460{
461 int chan;
462 u32 tfr_reg, err_reg;
463 unsigned long flags;
464 struct sata_dwc_device *hsdev =
465 (struct sata_dwc_device *)hsdev_instance;
466 struct ata_host *host = (struct ata_host *)hsdev->host;
467 struct ata_port *ap;
468 struct sata_dwc_device_port *hsdevp;
469 u8 tag = 0;
470 unsigned int port = 0;
471
472 spin_lock_irqsave(&host->lock, flags);
473 ap = host->ports[port];
474 hsdevp = HSDEVP_FROM_AP(ap);
475 tag = ap->link.active_tag;
476
477 tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
478 .low));
479 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
480 .low));
481
482 dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
483 tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
484
dc7f71f4
TN		 485 chan = host_pvt.dma_channel;
486 if (chan >= 0) {
62936009
RS		 487 /* Check for end-of-transfer interrupt. */
488 if (tfr_reg & DMA_CHANNEL(chan)) {
489 /*
490 * Each DMA command produces 2 interrupts. Only
491 * complete the command after both interrupts have been
492 * seen. (See sata_dwc_isr())
493 */
494 host_pvt.dma_interrupt_count++;
495 sata_dwc_clear_dmacr(hsdevp, tag);
496
497 if (hsdevp->dma_pending[tag] ==
498 SATA_DWC_DMA_PENDING_NONE) {
499 dev_err(ap->dev, "DMA not pending eot=0x%08x "
500 "err=0x%08x tag=0x%02x pending=%d\n",
501 tfr_reg, err_reg, tag,
502 hsdevp->dma_pending[tag]);
503 }
504
505 if ((host_pvt.dma_interrupt_count % 2) == 0)
506 sata_dwc_dma_xfer_complete(ap, 1);
507
508 /* Clear the interrupt */
509 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
510 .tfr.low),
511 DMA_CHANNEL(chan));
512 }
513
514 /* Check for error interrupt. */
515 if (err_reg & DMA_CHANNEL(chan)) {
516 /* TODO Need error handler ! */
517 dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
518 err_reg);
519
520 /* Clear the interrupt. */
521 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
522 .error.low),
523 DMA_CHANNEL(chan));
524 }
525 }
526 spin_unlock_irqrestore(&host->lock, flags);
527 return IRQ_HANDLED;
528}
529
530/*
531 * Function: dma_request_interrupts
532 * arguments: hsdev
533 * returns status
534 * This function registers ISR for a particular DMA channel interrupt
535 */
536static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
537{
538 int retval = 0;
dc7f71f4 539 int chan = host_pvt.dma_channel;
62936009 540
dc7f71f4 541 if (chan >= 0) {
62936009
RS		 542 /* Unmask error interrupt */
543 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
544 DMA_ENABLE_CHAN(chan));
545
546 /* Unmask end-of-transfer interrupt */
547 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
548 DMA_ENABLE_CHAN(chan));
549 }
550
551 retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
552 if (retval) {
553 dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
554 __func__, irq);
555 return -ENODEV;
556 }
557
558 /* Mark this interrupt as requested */
559 hsdev->irq_dma = irq;
560 return 0;
561}
562
563/*
564 * Function: map_sg_to_lli
565 * The Synopsis driver has a comment proposing that better performance
566 * is possible by only enabling interrupts on the last item in the linked list.
567 * However, it seems that could be a problem if an error happened on one of the
568 * first items. The transfer would halt, but no error interrupt would occur.
569 * Currently this function sets interrupts enabled for each linked list item:
570 * DMA_CTL_INT_EN.
571 */
572static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
573 struct lli *lli, dma_addr_t dma_lli,
574 void __iomem *dmadr_addr, int dir)
575{
576 int i, idx = 0;
577 int fis_len = 0;
578 dma_addr_t next_llp;
579 int bl;
dc7f71f4 580 int sms_val, dms_val;
62936009 581
dc7f71f4
TN		 582 sms_val = 0;
583 dms_val = 1 + host_pvt.dma_channel;
62936009
RS		 584 dev_dbg(host_pvt.dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x"
585 " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
586 (u32)dmadr_addr);
587
588 bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
589
590 for (i = 0; i < num_elems; i++, sg++) {
591 u32 addr, offset;
592 u32 sg_len, len;
593
594 addr = (u32) sg_dma_address(sg);
595 sg_len = sg_dma_len(sg);
596
597 dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
598 "=%d\n", __func__, i, addr, sg_len);
599
600 while (sg_len) {
601 if (idx >= SATA_DWC_DMAC_LLI_NUM) {
602 /* The LLI table is not large enough. */
603 dev_err(host_pvt.dwc_dev, "LLI table overrun "
604 "(idx=%d)\n", idx);
605 break;
606 }
607 len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
608 SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
609
610 offset = addr & 0xffff;
611 if ((offset + sg_len) > 0x10000)
612 len = 0x10000 - offset;
613
614 /*
615 * Make sure a LLI block is not created that will span
616 * 8K max FIS boundary. If the block spans such a FIS
617 * boundary, there is a chance that a DMA burst will
618 * cross that boundary -- this results in an error in
619 * the host controller.
620 */
621 if (fis_len + len > 8192) {
622 dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
623 "%d(0x%x) len=%d(0x%x)\n", fis_len,
624 fis_len, len, len);
625 len = 8192 - fis_len;
626 fis_len = 0;
627 } else {
628 fis_len += len;
629 }
630 if (fis_len == 8192)
631 fis_len = 0;
632
633 /*
634 * Set DMA addresses and lower half of control register
635 * based on direction.
636 */
637 if (dir == DMA_FROM_DEVICE) {
638 lli[idx].dar = cpu_to_le32(addr);
639 lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
640
641 lli[idx].ctl.low = cpu_to_le32(
642 DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
dc7f71f4
TN		 643 DMA_CTL_SMS(sms_val) |
644 DMA_CTL_DMS(dms_val) |
62936009
RS		 645 DMA_CTL_SRC_MSIZE(bl) |
646 DMA_CTL_DST_MSIZE(bl) |
647 DMA_CTL_SINC_NOCHANGE |
648 DMA_CTL_SRC_TRWID(2) |
649 DMA_CTL_DST_TRWID(2) |
650 DMA_CTL_INT_EN |
651 DMA_CTL_LLP_SRCEN |
652 DMA_CTL_LLP_DSTEN);
653 } else { /* DMA_TO_DEVICE */
654 lli[idx].sar = cpu_to_le32(addr);
655 lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
656
657 lli[idx].ctl.low = cpu_to_le32(
658 DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
dc7f71f4
TN		 659 DMA_CTL_SMS(dms_val) |
660 DMA_CTL_DMS(sms_val) |
62936009
RS		 661 DMA_CTL_SRC_MSIZE(bl) |
662 DMA_CTL_DST_MSIZE(bl) |
663 DMA_CTL_DINC_NOCHANGE |
664 DMA_CTL_SRC_TRWID(2) |
665 DMA_CTL_DST_TRWID(2) |
666 DMA_CTL_INT_EN |
667 DMA_CTL_LLP_SRCEN |
668 DMA_CTL_LLP_DSTEN);
669 }
670
671 dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
672 "0x%08x val: 0x%08x\n", __func__,
673 len, DMA_CTL_BLK_TS(len / 4));
674
675 /* Program the LLI CTL high register */
676 lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
677 (len / 4));
678
679 /* Program the next pointer. The next pointer must be
680 * the physical address, not the virtual address.
681 */
682 next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
683 lli)));
684
685 /* The last 2 bits encode the list master select. */
686 next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
687
688 lli[idx].llp = cpu_to_le32(next_llp);
689 idx++;
690 sg_len -= len;
691 addr += len;
692 }
693 }
694
695 /*
696 * The last next ptr has to be zero and the last control low register
697 * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
698 * and destination enable) set back to 0 (disabled.) This is what tells
699 * the core that this is the last item in the linked list.
700 */
701 if (idx) {
702 lli[idx-1].llp = 0x00000000;
703 lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
704
705 /* Flush cache to memory */
706 dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
707 DMA_BIDIRECTIONAL);
708 }
709
710 return idx;
711}
712
713/*
714 * Function: dma_dwc_xfer_start
715 * arguments: Channel number
716 * Return : None
717 * Enables the DMA channel
718 */
719static void dma_dwc_xfer_start(int dma_ch)
720{
721 /* Enable the DMA channel */
722 out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low),
723 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) |
724 DMA_ENABLE_CHAN(dma_ch));
725}
726
727static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
728 struct lli *lli, dma_addr_t dma_lli,
729 void __iomem *addr, int dir)
730{
731 int dma_ch;
732 int num_lli;
733 /* Acquire DMA channel */
734 dma_ch = dma_request_channel();
735 if (dma_ch == -1) {
736 dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
737 __func__);
738 return -EAGAIN;
739 }
740
741 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
742 num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
743
744 dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:"
745 " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems,
746 lli, (u32)dma_lli, addr, num_lli);
747
748 clear_chan_interrupts(dma_ch);
749
750 /* Program the CFG register. */
751 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high),
dc7f71f4 752 DMA_CFG_HW_HS_SRC(dma_ch) | DMA_CFG_HW_HS_DEST(dma_ch) |
62936009 753 DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
dc7f71f4
TN		 754 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low),
755 DMA_CFG_HW_CH_PRIOR(dma_ch));
62936009
RS		 756
757 /* Program the address of the linked list */
758 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low),
759 DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
760
761 /* Program the CTL register with src enable / dst enable */
762 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low),
763 DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
d285e8bf 764 return dma_ch;
62936009
RS		 765}
766
767/*
768 * Function: dma_dwc_exit
769 * arguments: None
770 * returns status
771 * This function exits the SATA DMA driver
772 */
773static void dma_dwc_exit(struct sata_dwc_device *hsdev)
774{
775 dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__);
04e506b5 776 if (host_pvt.sata_dma_regs) {
62936009 777 iounmap(host_pvt.sata_dma_regs);
04e506b5
VK		 778 host_pvt.sata_dma_regs = NULL;
779 }
62936009 780
04e506b5 781 if (hsdev->irq_dma) {
62936009 782 free_irq(hsdev->irq_dma, hsdev);
04e506b5
VK		 783 hsdev->irq_dma = 0;
784 }
62936009
RS		 785}
786
787/*
788 * Function: dma_dwc_init
789 * arguments: hsdev
790 * returns status
791 * This function initializes the SATA DMA driver
792 */
793static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq)
794{
795 int err;
796
797 err = dma_request_interrupts(hsdev, irq);
798 if (err) {
799 dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
800 " %d\n", __func__, err);
801 goto error_out;
802 }
803
804 /* Enabe DMA */
805 out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN);
806
807 dev_notice(host_pvt.dwc_dev, "DMA initialized\n");
808 dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\
809 sata_dma_regs);
810
811 return 0;
812
813error_out:
814 dma_dwc_exit(hsdev);
815
816 return err;
817}
818
819static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
820{
821 if (scr > SCR_NOTIFICATION) {
822 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
823 __func__, scr);
824 return -EINVAL;
825 }
826
827 *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4));
828 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
829 __func__, link->ap->print_id, scr, *val);
830
831 return 0;
832}
833
834static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
835{
836 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
837 __func__, link->ap->print_id, scr, val);
838 if (scr > SCR_NOTIFICATION) {
839 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
840 __func__, scr);
841 return -EINVAL;
842 }
843 out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val);
844
845 return 0;
846}
847
848static u32 core_scr_read(unsigned int scr)
849{
850 return in_le32((void __iomem *)(host_pvt.scr_addr_sstatus) +\
851 (scr * 4));
852}
853
854static void core_scr_write(unsigned int scr, u32 val)
855{
856 out_le32((void __iomem *)(host_pvt.scr_addr_sstatus) + (scr * 4),
857 val);
858}
859
860static void clear_serror(void)
861{
862 u32 val;
863 val = core_scr_read(SCR_ERROR);
864 core_scr_write(SCR_ERROR, val);
865
866}
867
868static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
869{
870 out_le32(&hsdev->sata_dwc_regs->intpr,
871 in_le32(&hsdev->sata_dwc_regs->intpr));
872}
873
874static u32 qcmd_tag_to_mask(u8 tag)
875{
876 return 0x00000001 << (tag & 0x1f);
877}
878
879/* See ahci.c */
880static void sata_dwc_error_intr(struct ata_port *ap,
881 struct sata_dwc_device *hsdev, uint intpr)
882{
883 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
884 struct ata_eh_info *ehi = &ap->link.eh_info;
885 unsigned int err_mask = 0, action = 0;
886 struct ata_queued_cmd *qc;
887 u32 serror;
888 u8 status, tag;
889 u32 err_reg;
890
891 ata_ehi_clear_desc(ehi);
892
893 serror = core_scr_read(SCR_ERROR);
894 status = ap->ops->sff_check_status(ap);
895
896 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\
897 low));
898 tag = ap->link.active_tag;
899
900 dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
901 "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
902 __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
903 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
904
905 /* Clear error register and interrupt bit */
906 clear_serror();
907 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
908
909 /* This is the only error happening now. TODO check for exact error */
910
911 err_mask |= AC_ERR_HOST_BUS;
912 action |= ATA_EH_RESET;
913
914 /* Pass this on to EH */
915 ehi->serror |= serror;
916 ehi->action |= action;
917
918 qc = ata_qc_from_tag(ap, tag);
919 if (qc)
920 qc->err_mask |= err_mask;
921 else
922 ehi->err_mask |= err_mask;
923
924 ata_port_abort(ap);
925}
926
927/*
928 * Function : sata_dwc_isr
929 * arguments : irq, void *dev_instance, struct pt_regs *regs
930 * Return value : irqreturn_t - status of IRQ
931 * This Interrupt handler called via port ops registered function.
932 * .irq_handler = sata_dwc_isr
933 */
934static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
935{
936 struct ata_host *host = (struct ata_host *)dev_instance;
937 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
938 struct ata_port *ap;
939 struct ata_queued_cmd *qc;
940 unsigned long flags;
941 u8 status, tag;
942 int handled, num_processed, port = 0;
943 uint intpr, sactive, sactive2, tag_mask;
944 struct sata_dwc_device_port *hsdevp;
945 host_pvt.sata_dwc_sactive_issued = 0;
946
947 spin_lock_irqsave(&host->lock, flags);
948
949 /* Read the interrupt register */
950 intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
951
952 ap = host->ports[port];
953 hsdevp = HSDEVP_FROM_AP(ap);
954
955 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
956 ap->link.active_tag);
957
958 /* Check for error interrupt */
959 if (intpr & SATA_DWC_INTPR_ERR) {
960 sata_dwc_error_intr(ap, hsdev, intpr);
961 handled = 1;
962 goto DONE;
963 }
964
965 /* Check for DMA SETUP FIS (FP DMA) interrupt */
966 if (intpr & SATA_DWC_INTPR_NEWFP) {
967 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
968
969 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
970 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
971 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
972 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
973
974 host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
975
976 qc = ata_qc_from_tag(ap, tag);
977 /*
978 * Start FP DMA for NCQ command. At this point the tag is the
979 * active tag. It is the tag that matches the command about to
980 * be completed.
981 */
982 qc->ap->link.active_tag = tag;
983 sata_dwc_bmdma_start_by_tag(qc, tag);
984
985 handled = 1;
986 goto DONE;
987 }
988 sactive = core_scr_read(SCR_ACTIVE);
989 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
990
991 /* If no sactive issued and tag_mask is zero then this is not NCQ */
992 if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
993 if (ap->link.active_tag == ATA_TAG_POISON)
994 tag = 0;
995 else
996 tag = ap->link.active_tag;
997 qc = ata_qc_from_tag(ap, tag);
998
999 /* DEV interrupt w/ no active qc? */
1000 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
1001 dev_err(ap->dev, "%s interrupt with no active qc "
1002 "qc=%p\n", __func__, qc);
1003 ap->ops->sff_check_status(ap);
1004 handled = 1;
1005 goto DONE;
1006 }
1007 status = ap->ops->sff_check_status(ap);
1008
1009 qc->ap->link.active_tag = tag;
1010 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1011
1012 if (status & ATA_ERR) {
1013 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
1014 sata_dwc_qc_complete(ap, qc, 1);
1015 handled = 1;
1016 goto DONE;
1017 }
1018
1019 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
84b47e3b 1020 __func__, get_prot_descript(qc->tf.protocol));
62936009
RS		 1021DRVSTILLBUSY:
1022 if (ata_is_dma(qc->tf.protocol)) {
1023 /*
1024 * Each DMA transaction produces 2 interrupts. The DMAC
1025 * transfer complete interrupt and the SATA controller
1026 * operation done interrupt. The command should be
1027 * completed only after both interrupts are seen.
1028 */
1029 host_pvt.dma_interrupt_count++;
1030 if (hsdevp->dma_pending[tag] == \
1031 SATA_DWC_DMA_PENDING_NONE) {
1032 dev_err(ap->dev, "%s: DMA not pending "
1033 "intpr=0x%08x status=0x%08x pending"
1034 "=%d\n", __func__, intpr, status,
1035 hsdevp->dma_pending[tag]);
1036 }
1037
1038 if ((host_pvt.dma_interrupt_count % 2) == 0)
1039 sata_dwc_dma_xfer_complete(ap, 1);
1040 } else if (ata_is_pio(qc->tf.protocol)) {
1041 ata_sff_hsm_move(ap, qc, status, 0);
1042 handled = 1;
1043 goto DONE;
1044 } else {
1045 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1046 goto DRVSTILLBUSY;
1047 }
1048
1049 handled = 1;
1050 goto DONE;
1051 }
1052
1053 /*
1054 * This is a NCQ command. At this point we need to figure out for which
1055 * tags we have gotten a completion interrupt. One interrupt may serve
1056 * as completion for more than one operation when commands are queued
1057 * (NCQ). We need to process each completed command.
1058 */
1059
1060 /* process completed commands */
1061 sactive = core_scr_read(SCR_ACTIVE);
1062 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
1063
1064 if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
1065 tag_mask > 1) {
1066 dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x sactive_issued=0x%08x"
1067 "tag_mask=0x%08x\n", __func__, sactive,
1068 host_pvt.sata_dwc_sactive_issued, tag_mask);
1069 }
1070
1071 if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
1072 (host_pvt.sata_dwc_sactive_issued)) {
1073 dev_warn(ap->dev, "Bad tag mask? sactive=0x%08x "
1074 "(host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask"
1075 "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued,
1076 tag_mask);
1077 }
1078
1079 /* read just to clear ... not bad if currently still busy */
1080 status = ap->ops->sff_check_status(ap);
1081 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
1082
1083 tag = 0;
1084 num_processed = 0;
1085 while (tag_mask) {
1086 num_processed++;
1087 while (!(tag_mask & 0x00000001)) {
1088 tag++;
1089 tag_mask <<= 1;
1090 }
1091
1092 tag_mask &= (~0x00000001);
1093 qc = ata_qc_from_tag(ap, tag);
1094
1095 /* To be picked up by completion functions */
1096 qc->ap->link.active_tag = tag;
1097 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1098
1099 /* Let libata/scsi layers handle error */
1100 if (status & ATA_ERR) {
1101 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
1102 status);
1103 sata_dwc_qc_complete(ap, qc, 1);
1104 handled = 1;
1105 goto DONE;
1106 }
1107
1108 /* Process completed command */
1109 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
84b47e3b 1110 get_prot_descript(qc->tf.protocol));
62936009
RS		 1111 if (ata_is_dma(qc->tf.protocol)) {
1112 host_pvt.dma_interrupt_count++;
1113 if (hsdevp->dma_pending[tag] == \
1114 SATA_DWC_DMA_PENDING_NONE)
1115 dev_warn(ap->dev, "%s: DMA not pending?\n",
1116 __func__);
1117 if ((host_pvt.dma_interrupt_count % 2) == 0)
1118 sata_dwc_dma_xfer_complete(ap, 1);
1119 } else {
1120 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1121 goto STILLBUSY;
1122 }
1123 continue;
1124
1125STILLBUSY:
1126 ap->stats.idle_irq++;
1127 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
1128 ap->print_id);
1129 } /* while tag_mask */
1130
1131 /*
1132 * Check to see if any commands completed while we were processing our
1133 * initial set of completed commands (read status clears interrupts,
1134 * so we might miss a completed command interrupt if one came in while
1135 * we were processing --we read status as part of processing a completed
1136 * command).
1137 */
1138 sactive2 = core_scr_read(SCR_ACTIVE);
1139 if (sactive2 != sactive) {
1140 dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2"
1141 "=0x%x\n", sactive, sactive2);
1142 }
1143 handled = 1;
1144
1145DONE:
1146 spin_unlock_irqrestore(&host->lock, flags);
1147 return IRQ_RETVAL(handled);
1148}
1149
1150static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
1151{
1152 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
1153
1154 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
1155 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1156 SATA_DWC_DMACR_RX_CLEAR(
1157 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1158 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
1159 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1160 SATA_DWC_DMACR_TX_CLEAR(
1161 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1162 } else {
1163 /*
1164 * This should not happen, it indicates the driver is out of
1165 * sync. If it does happen, clear dmacr anyway.
1166 */
1167 dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and"
1168 "TX DMA not pending tag=0x%02x pending=%d"
1169 " dmacr: 0x%08x\n", __func__, tag,
1170 hsdevp->dma_pending[tag],
1171 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1172 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1173 SATA_DWC_DMACR_TXRXCH_CLEAR);
1174 }
1175}
1176
1177static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
1178{
1179 struct ata_queued_cmd *qc;
1180 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1181 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1182 u8 tag = 0;
1183
1184 tag = ap->link.active_tag;
1185 qc = ata_qc_from_tag(ap, tag);
1186 if (!qc) {
1187 dev_err(ap->dev, "failed to get qc");
1188 return;
1189 }
1190
1191#ifdef DEBUG_NCQ
1192 if (tag > 0) {
1193 dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
1194 "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
84b47e3b
SS		 1195 get_dma_dir_descript(qc->dma_dir),
1196 get_prot_descript(qc->tf.protocol),
62936009
RS		 1197 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1198 }
1199#endif
1200
1201 if (ata_is_dma(qc->tf.protocol)) {
1202 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
1203 dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
1204 "pending dmacr: 0x%08x\n", __func__,
1205 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1206 }
1207
1208 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
1209 sata_dwc_qc_complete(ap, qc, check_status);
1210 ap->link.active_tag = ATA_TAG_POISON;
1211 } else {
1212 sata_dwc_qc_complete(ap, qc, check_status);
1213 }
1214}
1215
1216static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
1217 u32 check_status)
1218{
1219 u8 status = 0;
1220 u32 mask = 0x0;
1221 u8 tag = qc->tag;
1222 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1223 host_pvt.sata_dwc_sactive_queued = 0;
1224 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
1225
1226 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
1227 dev_err(ap->dev, "TX DMA PENDING\n");
1228 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
1229 dev_err(ap->dev, "RX DMA PENDING\n");
1230 dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:"
1231 " protocol=%d\n", qc->tf.command, status, ap->print_id,
1232 qc->tf.protocol);
1233
1234 /* clear active bit */
1235 mask = (~(qcmd_tag_to_mask(tag)));
1236 host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
1237 & mask;
1238 host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
1239 & mask;
1240 ata_qc_complete(qc);
1241 return 0;
1242}
1243
1244static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
1245{
1246 /* Enable selective interrupts by setting the interrupt maskregister*/
1247 out_le32(&hsdev->sata_dwc_regs->intmr,
1248 SATA_DWC_INTMR_ERRM |
1249 SATA_DWC_INTMR_NEWFPM |
1250 SATA_DWC_INTMR_PMABRTM |
1251 SATA_DWC_INTMR_DMATM);
1252 /*
1253 * Unmask the error bits that should trigger an error interrupt by
1254 * setting the error mask register.
1255 */
1256 out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
1257
1258 dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
1259 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
1260 in_le32(&hsdev->sata_dwc_regs->errmr));
1261}
1262
1263static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
1264{
1265 port->cmd_addr = (void *)base + 0x00;
1266 port->data_addr = (void *)base + 0x00;
1267
1268 port->error_addr = (void *)base + 0x04;
1269 port->feature_addr = (void *)base + 0x04;
1270
1271 port->nsect_addr = (void *)base + 0x08;
1272
1273 port->lbal_addr = (void *)base + 0x0c;
1274 port->lbam_addr = (void *)base + 0x10;
1275 port->lbah_addr = (void *)base + 0x14;
1276
1277 port->device_addr = (void *)base + 0x18;
1278 port->command_addr = (void *)base + 0x1c;
1279 port->status_addr = (void *)base + 0x1c;
1280
1281 port->altstatus_addr = (void *)base + 0x20;
1282 port->ctl_addr = (void *)base + 0x20;
1283}
1284
1285/*
1286 * Function : sata_dwc_port_start
1287 * arguments : struct ata_ioports *port
1288 * Return value : returns 0 if success, error code otherwise
1289 * This function allocates the scatter gather LLI table for AHB DMA
1290 */
1291static int sata_dwc_port_start(struct ata_port *ap)
1292{
1293 int err = 0;
1294 struct sata_dwc_device *hsdev;
1295 struct sata_dwc_device_port *hsdevp = NULL;
1296 struct device *pdev;
1297 int i;
1298
1299 hsdev = HSDEV_FROM_AP(ap);
1300
1301 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
1302
1303 hsdev->host = ap->host;
1304 pdev = ap->host->dev;
1305 if (!pdev) {
1306 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
1307 err = -ENODEV;
1308 goto CLEANUP;
1309 }
1310
1311 /* Allocate Port Struct */
1312 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
1313 if (!hsdevp) {
1314 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
1315 err = -ENOMEM;
1316 goto CLEANUP;
1317 }
1318 hsdevp->hsdev = hsdev;
1319
1320 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
1321 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
1322
1323 ap->bmdma_prd = 0; /* set these so libata doesn't use them */
1324 ap->bmdma_prd_dma = 0;
1325
1326 /*
1327 * DMA - Assign scatter gather LLI table. We can't use the libata
1328 * version since it's PRD is IDE PCI specific.
1329 */
1330 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1331 hsdevp->llit[i] = dma_alloc_coherent(pdev,
1332 SATA_DWC_DMAC_LLI_TBL_SZ,
1333 &(hsdevp->llit_dma[i]),
1334 GFP_ATOMIC);
1335 if (!hsdevp->llit[i]) {
1336 dev_err(ap->dev, "%s: dma_alloc_coherent failed\n",
1337 __func__);
1338 err = -ENOMEM;
a081da63 1339 goto CLEANUP_ALLOC;
62936009
RS		 1340 }
1341 }
1342
1343 if (ap->port_no == 0) {
1344 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
1345 __func__);
1346 out_le32(&hsdev->sata_dwc_regs->dmacr,
1347 SATA_DWC_DMACR_TXRXCH_CLEAR);
1348
1349 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
1350 __func__);
1351 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1352 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1353 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
1354 }
1355
1356 /* Clear any error bits before libata starts issuing commands */
1357 clear_serror();
1358 ap->private_data = hsdevp;
a081da63
JL		 1359 dev_dbg(ap->dev, "%s: done\n", __func__);
1360 return 0;
62936009 1361
a081da63
JL		 1362CLEANUP_ALLOC:
1363 kfree(hsdevp);
62936009 1364CLEANUP:
a081da63 1365 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
62936009
RS		 1366 return err;
1367}
1368
1369static void sata_dwc_port_stop(struct ata_port *ap)
1370{
1371 int i;
1372 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1373 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1374
1375 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
1376
1377 if (hsdevp && hsdev) {
1378 /* deallocate LLI table */
1379 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1380 dma_free_coherent(ap->host->dev,
1381 SATA_DWC_DMAC_LLI_TBL_SZ,
1382 hsdevp->llit[i], hsdevp->llit_dma[i]);
1383 }
1384
1385 kfree(hsdevp);
1386 }
1387 ap->private_data = NULL;
1388}
1389
1390/*
1391 * Function : sata_dwc_exec_command_by_tag
1392 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
1393 * Return value : None
1394 * This function keeps track of individual command tag ids and calls
1395 * ata_exec_command in libata
1396 */
1397static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
1398 struct ata_taskfile *tf,
1399 u8 tag, u32 cmd_issued)
1400{
1401 unsigned long flags;
1402 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1403
1404 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
c211962d 1405 ata_get_cmd_descript(tf->command), tag);
62936009
RS		 1406
1407 spin_lock_irqsave(&ap->host->lock, flags);
1408 hsdevp->cmd_issued[tag] = cmd_issued;
1409 spin_unlock_irqrestore(&ap->host->lock, flags);
1410 /*
1411 * Clear SError before executing a new command.
1412 * sata_dwc_scr_write and read can not be used here. Clearing the PM
1413 * managed SError register for the disk needs to be done before the
1414 * task file is loaded.
1415 */
1416 clear_serror();
1417 ata_sff_exec_command(ap, tf);
1418}
1419
1420static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1421{
1422 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1423 SATA_DWC_CMD_ISSUED_PEND);
1424}
1425
1426static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1427{
1428 u8 tag = qc->tag;
1429
1430 if (ata_is_ncq(qc->tf.protocol)) {
1431 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1432 __func__, qc->ap->link.sactive, tag);
1433 } else {
1434 tag = 0;
1435 }
1436 sata_dwc_bmdma_setup_by_tag(qc, tag);
1437}
1438
1439static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1440{
1441 int start_dma;
1442 u32 reg, dma_chan;
1443 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1444 struct ata_port *ap = qc->ap;
1445 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1446 int dir = qc->dma_dir;
1447 dma_chan = hsdevp->dma_chan[tag];
1448
1449 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1450 start_dma = 1;
1451 if (dir == DMA_TO_DEVICE)
1452 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1453 else
1454 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1455 } else {
1456 dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
1457 "(tag=%d) DMA NOT started\n", __func__,
1458 hsdevp->cmd_issued[tag], tag);
1459 start_dma = 0;
1460 }
1461
1462 dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
1463 "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
84b47e3b 1464 get_dma_dir_descript(qc->dma_dir), start_dma);
62936009
RS		 1465 sata_dwc_tf_dump(&(qc->tf));
1466
1467 if (start_dma) {
1468 reg = core_scr_read(SCR_ERROR);
1469 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1470 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1471 __func__, reg);
1472 }
1473
1474 if (dir == DMA_TO_DEVICE)
1475 out_le32(&hsdev->sata_dwc_regs->dmacr,
1476 SATA_DWC_DMACR_TXCHEN);
1477 else
1478 out_le32(&hsdev->sata_dwc_regs->dmacr,
1479 SATA_DWC_DMACR_RXCHEN);
1480
1481 /* Enable AHB DMA transfer on the specified channel */
1482 dma_dwc_xfer_start(dma_chan);
1483 }
1484}
1485
1486static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1487{
1488 u8 tag = qc->tag;
1489
1490 if (ata_is_ncq(qc->tf.protocol)) {
1491 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1492 __func__, qc->ap->link.sactive, tag);
1493 } else {
1494 tag = 0;
1495 }
1496 dev_dbg(qc->ap->dev, "%s\n", __func__);
1497 sata_dwc_bmdma_start_by_tag(qc, tag);
1498}
1499
1500/*
1501 * Function : sata_dwc_qc_prep_by_tag
1502 * arguments : ata_queued_cmd *qc, u8 tag
1503 * Return value : None
1504 * qc_prep for a particular queued command based on tag
1505 */
1506static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
1507{
1508 struct scatterlist *sg = qc->sg;
1509 struct ata_port *ap = qc->ap;
d26377b8 1510 int dma_chan;
62936009
RS		 1511 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1512 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
62936009
RS		 1513
1514 dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
84b47e3b 1515 __func__, ap->port_no, get_dma_dir_descript(qc->dma_dir),
62936009
RS		 1516 qc->n_elem);
1517
1518 dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
1519 hsdevp->llit_dma[tag],
1520 (void *__iomem)(&hsdev->sata_dwc_regs->\
1521 dmadr), qc->dma_dir);
1522 if (dma_chan < 0) {
1523 dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
c211962d 1524 __func__, dma_chan);
62936009
RS		 1525 return;
1526 }
1527 hsdevp->dma_chan[tag] = dma_chan;
1528}
1529
1530static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1531{
1532 u32 sactive;
1533 u8 tag = qc->tag;
1534 struct ata_port *ap = qc->ap;
1535
1536#ifdef DEBUG_NCQ
1537 if (qc->tag > 0 || ap->link.sactive > 1)
1538 dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d "
1539 "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1540 __func__, ap->print_id, qc->tf.command,
c211962d 1541 ata_get_cmd_descript(qc->tf.command),
84b47e3b 1542 qc->tag, get_prot_descript(qc->tf.protocol),
62936009
RS		 1543 ap->link.active_tag, ap->link.sactive);
1544#endif
1545
1546 if (!ata_is_ncq(qc->tf.protocol))
1547 tag = 0;
1548 sata_dwc_qc_prep_by_tag(qc, tag);
1549
1550 if (ata_is_ncq(qc->tf.protocol)) {
1551 sactive = core_scr_read(SCR_ACTIVE);
1552 sactive |= (0x00000001 << tag);
1553 core_scr_write(SCR_ACTIVE, sactive);
1554
1555 dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
1556 "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
1557 sactive);
1558
1559 ap->ops->sff_tf_load(ap, &qc->tf);
1560 sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
1561 SATA_DWC_CMD_ISSUED_PEND);
1562 } else {
1563 ata_sff_qc_issue(qc);
1564 }
1565 return 0;
1566}
1567
1568/*
1569 * Function : sata_dwc_qc_prep
1570 * arguments : ata_queued_cmd *qc
1571 * Return value : None
1572 * qc_prep for a particular queued command
1573 */
1574
1575static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1576{
1577 if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1578 return;
1579
1580#ifdef DEBUG_NCQ
1581 if (qc->tag > 0)
1582 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
c211962d 1583 __func__, qc->tag, qc->ap->link.active_tag);
62936009
RS		 1584
1585 return ;
1586#endif
1587}
1588
1589static void sata_dwc_error_handler(struct ata_port *ap)
1590{
62936009
RS		 1591 ata_sff_error_handler(ap);
1592}
1593
3a8b788f
TN		 1594int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1595 unsigned long deadline)
1596{
1597 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1598 int ret;
1599
1600 ret = sata_sff_hardreset(link, class, deadline);
1601
1602 sata_dwc_enable_interrupts(hsdev);
1603
1604 /* Reconfigure the DMA control register */
1605 out_le32(&hsdev->sata_dwc_regs->dmacr,
1606 SATA_DWC_DMACR_TXRXCH_CLEAR);
1607
1608 /* Reconfigure the DMA Burst Transaction Size register */
1609 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1610 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1611 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1612
1613 return ret;
1614}
1615
62936009
RS		 1616/*
1617 * scsi mid-layer and libata interface structures
1618 */
1619static struct scsi_host_template sata_dwc_sht = {
1620 ATA_NCQ_SHT(DRV_NAME),
1621 /*
1622 * test-only: Currently this driver doesn't handle NCQ
1623 * correctly. We enable NCQ but set the queue depth to a
1624 * max of 1. This will get fixed in in a future release.
1625 */
1626 .sg_tablesize = LIBATA_MAX_PRD,
1627 .can_queue = ATA_DEF_QUEUE, /* ATA_MAX_QUEUE */
1628 .dma_boundary = ATA_DMA_BOUNDARY,
1629};
1630
1631static struct ata_port_operations sata_dwc_ops = {
1632 .inherits = &ata_sff_port_ops,
1633
1634 .error_handler = sata_dwc_error_handler,
3a8b788f 1635 .hardreset = sata_dwc_hardreset,
62936009
RS		 1636
1637 .qc_prep = sata_dwc_qc_prep,
1638 .qc_issue = sata_dwc_qc_issue,
1639
1640 .scr_read = sata_dwc_scr_read,
1641 .scr_write = sata_dwc_scr_write,
1642
1643 .port_start = sata_dwc_port_start,
1644 .port_stop = sata_dwc_port_stop,
1645
1646 .bmdma_setup = sata_dwc_bmdma_setup,
1647 .bmdma_start = sata_dwc_bmdma_start,
1648};
1649
1650static const struct ata_port_info sata_dwc_port_info[] = {
1651 {
9cbe056f 1652 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
b83a4c39 1653 .pio_mask = ATA_PIO4,
62936009
RS		 1654 .udma_mask = ATA_UDMA6,
1655 .port_ops = &sata_dwc_ops,
1656 },
1657};
1658
1c48a5c9 1659static int sata_dwc_probe(struct platform_device *ofdev)
62936009
RS		 1660{
1661 struct sata_dwc_device *hsdev;
1662 u32 idr, versionr;
1663 char *ver = (char *)&versionr;
1664 u8 *base = NULL;
1665 int err = 0;
1666 int irq, rc;
1667 struct ata_host *host;
1668 struct ata_port_info pi = sata_dwc_port_info[0];
1669 const struct ata_port_info *ppi[] = { &pi, NULL };
dc7f71f4
TN		 1670 struct device_node *np = ofdev->dev.of_node;
1671 u32 dma_chan;
62936009
RS		 1672
1673 /* Allocate DWC SATA device */
f35119d6 1674 hsdev = kzalloc(sizeof(*hsdev), GFP_KERNEL);
62936009
RS		 1675 if (hsdev == NULL) {
1676 dev_err(&ofdev->dev, "kmalloc failed for hsdev\n");
1677 err = -ENOMEM;
04e506b5 1678 goto error;
62936009 1679 }
62936009 1680
dc7f71f4
TN		 1681 if (of_property_read_u32(np, "dma-channel", &dma_chan)) {
1682 dev_warn(&ofdev->dev, "no dma-channel property set."
1683 " Use channel 0\n");
1684 dma_chan = 0;
1685 }
1686 host_pvt.dma_channel = dma_chan;
1687
62936009
RS		 1688 /* Ioremap SATA registers */
1689 base = of_iomap(ofdev->dev.of_node, 0);
1690 if (!base) {
1691 dev_err(&ofdev->dev, "ioremap failed for SATA register"
1692 " address\n");
1693 err = -ENODEV;
04e506b5 1694 goto error_kmalloc;
62936009
RS		 1695 }
1696 hsdev->reg_base = base;
1697 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1698
1699 /* Synopsys DWC SATA specific Registers */
1700 hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1701
1702 /* Allocate and fill host */
1703 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1704 if (!host) {
1705 dev_err(&ofdev->dev, "ata_host_alloc_pinfo failed\n");
1706 err = -ENOMEM;
04e506b5 1707 goto error_iomap;
62936009
RS		 1708 }
1709
1710 host->private_data = hsdev;
1711
1712 /* Setup port */
1713 host->ports[0]->ioaddr.cmd_addr = base;
1714 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1715 host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
1716 sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1717
1718 /* Read the ID and Version Registers */
1719 idr = in_le32(&hsdev->sata_dwc_regs->idr);
1720 versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1721 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1722 idr, ver[0], ver[1], ver[2]);
1723
1724 /* Get SATA DMA interrupt number */
1725 irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
1726 if (irq == NO_IRQ) {
1727 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1728 err = -ENODEV;
1729 goto error_out;
1730 }
1731
1732 /* Get physical SATA DMA register base address */
1733 host_pvt.sata_dma_regs = of_iomap(ofdev->dev.of_node, 1);
1734 if (!(host_pvt.sata_dma_regs)) {
1735 dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
1736 " address\n");
1737 err = -ENODEV;
1738 goto error_out;
1739 }
1740
1741 /* Save dev for later use in dev_xxx() routines */
1742 host_pvt.dwc_dev = &ofdev->dev;
1743
1744 /* Initialize AHB DMAC */
1745 dma_dwc_init(hsdev, irq);
1746
1747 /* Enable SATA Interrupts */
1748 sata_dwc_enable_interrupts(hsdev);
1749
1750 /* Get SATA interrupt number */
1751 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1752 if (irq == NO_IRQ) {
1753 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1754 err = -ENODEV;
1755 goto error_out;
1756 }
1757
1758 /*
1759 * Now, register with libATA core, this will also initiate the
1760 * device discovery process, invoking our port_start() handler &
1761 * error_handler() to execute a dummy Softreset EH session
1762 */
1763 rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1764
1765 if (rc != 0)
1766 dev_err(&ofdev->dev, "failed to activate host");
1767
1768 dev_set_drvdata(&ofdev->dev, host);
1769 return 0;
1770
1771error_out:
1772 /* Free SATA DMA resources */
1773 dma_dwc_exit(hsdev);
1774
04e506b5
VK		 1775error_iomap:
1776 iounmap(base);
1777error_kmalloc:
1778 kfree(hsdev);
1779error:
62936009
RS		 1780 return err;
1781}
1782
60652d07 1783static int sata_dwc_remove(struct platform_device *ofdev)
62936009
RS		 1784{
1785 struct device *dev = &ofdev->dev;
1786 struct ata_host *host = dev_get_drvdata(dev);
1787 struct sata_dwc_device *hsdev = host->private_data;
1788
1789 ata_host_detach(host);
1790 dev_set_drvdata(dev, NULL);
1791
1792 /* Free SATA DMA resources */
1793 dma_dwc_exit(hsdev);
1794
1795 iounmap(hsdev->reg_base);
1796 kfree(hsdev);
1797 kfree(host);
1798 dev_dbg(&ofdev->dev, "done\n");
1799 return 0;
1800}
1801
1802static const struct of_device_id sata_dwc_match[] = {
1803 { .compatible = "amcc,sata-460ex", },
1804 {}
1805};
1806MODULE_DEVICE_TABLE(of, sata_dwc_match);
1807
1c48a5c9 1808static struct platform_driver sata_dwc_driver = {
62936009
RS		 1809 .driver = {
1810 .name = DRV_NAME,
1811 .owner = THIS_MODULE,
1812 .of_match_table = sata_dwc_match,
1813 },
1814 .probe = sata_dwc_probe,
1815 .remove = sata_dwc_remove,
1816};
1817
99c8ea3e 1818module_platform_driver(sata_dwc_driver);
62936009
RS		 1819
1820MODULE_LICENSE("GPL");
1821MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1822MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
1823MODULE_VERSION(DRV_VERSION);