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sata_dwc_460ex: move to generic DMA driver
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ata / sata_dwc_460ex.c
CommitLineData
62936009
RS		 1/*
2 * drivers/ata/sata_dwc_460ex.c
3 *
4 * Synopsys DesignWare Cores (DWC) SATA host driver
5 *
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
7 *
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
10 *
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifdef CONFIG_SATA_DWC_DEBUG
22#define DEBUG
23#endif
24
25#ifdef CONFIG_SATA_DWC_VDEBUG
26#define VERBOSE_DEBUG
27#define DEBUG_NCQ
28#endif
29
30#include <linux/kernel.h>
31#include <linux/module.h>
62936009 32#include <linux/device.h>
c11eede6
RH		 33#include <linux/of_address.h>
34#include <linux/of_irq.h>
62936009
RS		 35#include <linux/of_platform.h>
36#include <linux/platform_device.h>
37#include <linux/libata.h>
38#include <linux/slab.h>
8b344485 39
62936009
RS		 40#include "libata.h"
41
42#include <scsi/scsi_host.h>
43#include <scsi/scsi_cmnd.h>
44
8b344485
AS		 45/* Supported DMA engine drivers */
46#include <linux/platform_data/dma-dw.h>
47#include <linux/dma/dw.h>
48
c211962d
SS		 49/* These two are defined in "libata.h" */
50#undef DRV_NAME
51#undef DRV_VERSION
72d5f2da 52
62936009 53#define DRV_NAME "sata-dwc"
84b47e3b 54#define DRV_VERSION "1.3"
62936009 55
84683a7e
AS		 56#ifndef out_le32
57#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (void __iomem *)(a))
58#endif
59
60#ifndef in_le32
61#define in_le32(a) __le32_to_cpu(__raw_readl((void __iomem *)(a)))
62#endif
63
64#ifndef NO_IRQ
65#define NO_IRQ 0
66#endif
67
62936009
RS		 68#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
69
62936009 70enum {
62936009
RS		 71 SATA_DWC_MAX_PORTS = 1,
72
73 SATA_DWC_SCR_OFFSET = 0x24,
74 SATA_DWC_REG_OFFSET = 0x64,
75};
76
77/* DWC SATA Registers */
78struct sata_dwc_regs {
79 u32 fptagr; /* 1st party DMA tag */
80 u32 fpbor; /* 1st party DMA buffer offset */
81 u32 fptcr; /* 1st party DMA Xfr count */
82 u32 dmacr; /* DMA Control */
83 u32 dbtsr; /* DMA Burst Transac size */
84 u32 intpr; /* Interrupt Pending */
85 u32 intmr; /* Interrupt Mask */
86 u32 errmr; /* Error Mask */
87 u32 llcr; /* Link Layer Control */
88 u32 phycr; /* PHY Control */
89 u32 physr; /* PHY Status */
90 u32 rxbistpd; /* Recvd BIST pattern def register */
91 u32 rxbistpd1; /* Recvd BIST data dword1 */
92 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
93 u32 txbistpd; /* Trans BIST pattern def register */
94 u32 txbistpd1; /* Trans BIST data dword1 */
95 u32 txbistpd2; /* Trans BIST data dword2 */
96 u32 bistcr; /* BIST Control Register */
97 u32 bistfctr; /* BIST FIS Count Register */
98 u32 bistsr; /* BIST Status Register */
99 u32 bistdecr; /* BIST Dword Error count register */
100 u32 res[15]; /* Reserved locations */
101 u32 testr; /* Test Register */
102 u32 versionr; /* Version Register */
103 u32 idr; /* ID Register */
104 u32 unimpl[192]; /* Unimplemented */
105 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
106};
107
108enum {
109 SCR_SCONTROL_DET_ENABLE = 0x00000001,
110 SCR_SSTATUS_DET_PRESENT = 0x00000001,
111 SCR_SERROR_DIAG_X = 0x04000000,
112/* DWC SATA Register Operations */
113 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
114 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
115 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
116 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
117 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
118 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
119 SATA_DWC_INTPR_DMAT = 0x00000001,
120 SATA_DWC_INTPR_NEWFP = 0x00000002,
121 SATA_DWC_INTPR_PMABRT = 0x00000004,
122 SATA_DWC_INTPR_ERR = 0x00000008,
123 SATA_DWC_INTPR_NEWBIST = 0x00000010,
124 SATA_DWC_INTPR_IPF = 0x10000000,
125 SATA_DWC_INTMR_DMATM = 0x00000001,
126 SATA_DWC_INTMR_NEWFPM = 0x00000002,
127 SATA_DWC_INTMR_PMABRTM = 0x00000004,
128 SATA_DWC_INTMR_ERRM = 0x00000008,
129 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
130 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
131 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
132 SATA_DWC_LLCR_RPDEN = 0x00000004,
133/* This is all error bits, zero's are reserved fields. */
134 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
135};
136
137#define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
138#define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
139 SATA_DWC_DMACR_TMOD_TXCHEN)
140#define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
141 SATA_DWC_DMACR_TMOD_TXCHEN)
142#define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
143#define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
144 << 16)
145struct sata_dwc_device {
146 struct device *dev; /* generic device struct */
147 struct ata_probe_ent *pe; /* ptr to probe-ent */
148 struct ata_host *host;
d7c256e8 149 u8 __iomem *reg_base;
62936009 150 struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
8b344485 151 struct dw_dma_chip *dma;
62936009
RS		 152};
153
154#define SATA_DWC_QCMD_MAX 32
155
156struct sata_dwc_device_port {
157 struct sata_dwc_device *hsdev;
158 int cmd_issued[SATA_DWC_QCMD_MAX];
62936009 159 int dma_pending[SATA_DWC_QCMD_MAX];
8b344485
AS		 160
161 /* DMA info */
162 struct dw_dma_slave *dws;
163 struct dma_chan *chan;
164 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
165 u32 dma_interrupt_count;
62936009
RS		 166};
167
168/*
169 * Commonly used DWC SATA driver Macros
170 */
171#define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
172 (host)->private_data)
173#define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
174 (ap)->host->private_data)
175#define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
176 (ap)->private_data)
177#define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
178 (qc)->ap->host->private_data)
179#define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
180 (hsdevp)->hsdev)
181
182enum {
183 SATA_DWC_CMD_ISSUED_NOT = 0,
184 SATA_DWC_CMD_ISSUED_PEND = 1,
185 SATA_DWC_CMD_ISSUED_EXEC = 2,
186 SATA_DWC_CMD_ISSUED_NODATA = 3,
187
188 SATA_DWC_DMA_PENDING_NONE = 0,
189 SATA_DWC_DMA_PENDING_TX = 1,
190 SATA_DWC_DMA_PENDING_RX = 2,
191};
192
193struct sata_dwc_host_priv {
194 void __iomem *scr_addr_sstatus;
195 u32 sata_dwc_sactive_issued ;
196 u32 sata_dwc_sactive_queued ;
62936009
RS		 197 struct device *dwc_dev;
198};
d7c256e8
AS		 199
200static struct sata_dwc_host_priv host_pvt;
201
8b344485
AS		 202static struct dw_dma_slave sata_dwc_dma_dws = {
203 .src_id = 0,
204 .dst_id = 0,
205 .src_master = 0,
206 .dst_master = 1,
207};
208
62936009
RS		 209/*
210 * Prototypes
211 */
212static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
213static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
214 u32 check_status);
215static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
216static void sata_dwc_port_stop(struct ata_port *ap);
217static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
62936009 218
84b47e3b
SS		 219static const char *get_prot_descript(u8 protocol)
220{
221 switch ((enum ata_tf_protocols)protocol) {
222 case ATA_PROT_NODATA:
223 return "ATA no data";
224 case ATA_PROT_PIO:
225 return "ATA PIO";
226 case ATA_PROT_DMA:
227 return "ATA DMA";
228 case ATA_PROT_NCQ:
229 return "ATA NCQ";
230 case ATAPI_PROT_NODATA:
231 return "ATAPI no data";
232 case ATAPI_PROT_PIO:
233 return "ATAPI PIO";
234 case ATAPI_PROT_DMA:
235 return "ATAPI DMA";
236 default:
237 return "unknown";
238 }
239}
240
241static const char *get_dma_dir_descript(int dma_dir)
242{
243 switch ((enum dma_data_direction)dma_dir) {
244 case DMA_BIDIRECTIONAL:
245 return "bidirectional";
246 case DMA_TO_DEVICE:
247 return "to device";
248 case DMA_FROM_DEVICE:
249 return "from device";
250 default:
251 return "none";
252 }
253}
254
62936009
RS		 255static void sata_dwc_tf_dump(struct ata_taskfile *tf)
256{
d578514b
AS		 257 dev_vdbg(host_pvt.dwc_dev,
258 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
259 tf->command, get_prot_descript(tf->protocol), tf->flags,
260 tf->device);
261 dev_vdbg(host_pvt.dwc_dev,
262 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
263 tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
264 dev_vdbg(host_pvt.dwc_dev,
265 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
62936009
RS		 266 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
267 tf->hob_lbah);
268}
269
8b344485 270static void dma_dwc_xfer_done(void *hsdev_instance)
62936009 271{
62936009 272 unsigned long flags;
d5185d65 273 struct sata_dwc_device *hsdev = hsdev_instance;
62936009
RS		 274 struct ata_host *host = (struct ata_host *)hsdev->host;
275 struct ata_port *ap;
276 struct sata_dwc_device_port *hsdevp;
277 u8 tag = 0;
278 unsigned int port = 0;
279
280 spin_lock_irqsave(&host->lock, flags);
281 ap = host->ports[port];
282 hsdevp = HSDEVP_FROM_AP(ap);
283 tag = ap->link.active_tag;
284
62936009 285 /*
8b344485
AS		 286 * Each DMA command produces 2 interrupts. Only
287 * complete the command after both interrupts have been
288 * seen. (See sata_dwc_isr())
62936009 289 */
8b344485
AS		 290 hsdevp->dma_interrupt_count++;
291 sata_dwc_clear_dmacr(hsdevp, tag);
62936009 292
8b344485
AS		 293 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
294 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
295 tag, hsdevp->dma_pending[tag]);
62936009
RS		 296 }
297
8b344485
AS		 298 if ((hsdevp->dma_interrupt_count % 2) == 0)
299 sata_dwc_dma_xfer_complete(ap, 1);
62936009 300
8b344485 301 spin_unlock_irqrestore(&host->lock, flags);
62936009
RS		 302}
303
8b344485 304static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
62936009 305{
8b344485
AS		 306 struct ata_port *ap = qc->ap;
307 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
308 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
309 dma_addr_t addr = (dma_addr_t)&hsdev->sata_dwc_regs->dmadr;
310 struct dma_slave_config sconf;
311 struct dma_async_tx_descriptor *desc;
312
313 if (qc->dma_dir == DMA_DEV_TO_MEM) {
314 sconf.src_addr = addr;
315 sconf.device_fc = true;
316 } else { /* DMA_MEM_TO_DEV */
317 sconf.dst_addr = addr;
318 sconf.device_fc = false;
62936009
RS		 319 }
320
8b344485
AS		 321 sconf.direction = qc->dma_dir;
322 sconf.src_maxburst = AHB_DMA_BRST_DFLT;
323 sconf.dst_maxburst = AHB_DMA_BRST_DFLT;
324 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
325 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
62936009 326
8b344485 327 dmaengine_slave_config(hsdevp->chan, &sconf);
62936009 328
8b344485
AS		 329 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
330 desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
331 qc->dma_dir,
332 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
62936009 333
8b344485
AS		 334 if (!desc)
335 return NULL;
62936009 336
8b344485
AS		 337 desc->callback = dma_dwc_xfer_done;
338 desc->callback_param = hsdev;
62936009 339
8b344485
AS		 340 dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d addr: %pad\n",
341 __func__, qc->sg, qc->n_elem, &addr);
62936009 342
8b344485 343 return desc;
62936009
RS		 344}
345
346static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
347{
348 if (scr > SCR_NOTIFICATION) {
349 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
350 __func__, scr);
351 return -EINVAL;
352 }
353
d7c256e8 354 *val = in_le32(link->ap->ioaddr.scr_addr + (scr * 4));
62936009
RS		 355 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
356 __func__, link->ap->print_id, scr, *val);
357
358 return 0;
359}
360
361static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
362{
363 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
364 __func__, link->ap->print_id, scr, val);
365 if (scr > SCR_NOTIFICATION) {
366 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
367 __func__, scr);
368 return -EINVAL;
369 }
d7c256e8 370 out_le32(link->ap->ioaddr.scr_addr + (scr * 4), val);
62936009
RS		 371
372 return 0;
373}
374
375static u32 core_scr_read(unsigned int scr)
376{
d7c256e8 377 return in_le32(host_pvt.scr_addr_sstatus + (scr * 4));
62936009
RS		 378}
379
380static void core_scr_write(unsigned int scr, u32 val)
381{
d7c256e8 382 out_le32(host_pvt.scr_addr_sstatus + (scr * 4), val);
62936009
RS		 383}
384
385static void clear_serror(void)
386{
387 u32 val;
388 val = core_scr_read(SCR_ERROR);
389 core_scr_write(SCR_ERROR, val);
62936009
RS		 390}
391
392static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
393{
394 out_le32(&hsdev->sata_dwc_regs->intpr,
395 in_le32(&hsdev->sata_dwc_regs->intpr));
396}
397
398static u32 qcmd_tag_to_mask(u8 tag)
399{
400 return 0x00000001 << (tag & 0x1f);
401}
402
403/* See ahci.c */
404static void sata_dwc_error_intr(struct ata_port *ap,
405 struct sata_dwc_device *hsdev, uint intpr)
406{
407 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
408 struct ata_eh_info *ehi = &ap->link.eh_info;
409 unsigned int err_mask = 0, action = 0;
410 struct ata_queued_cmd *qc;
411 u32 serror;
412 u8 status, tag;
62936009
RS		 413
414 ata_ehi_clear_desc(ehi);
415
416 serror = core_scr_read(SCR_ERROR);
417 status = ap->ops->sff_check_status(ap);
418
62936009
RS		 419 tag = ap->link.active_tag;
420
8b344485
AS		 421 dev_err(ap->dev,
422 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
423 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
424 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
62936009
RS		 425
426 /* Clear error register and interrupt bit */
427 clear_serror();
428 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
429
430 /* This is the only error happening now. TODO check for exact error */
431
432 err_mask |= AC_ERR_HOST_BUS;
433 action |= ATA_EH_RESET;
434
435 /* Pass this on to EH */
436 ehi->serror |= serror;
437 ehi->action |= action;
438
439 qc = ata_qc_from_tag(ap, tag);
440 if (qc)
441 qc->err_mask |= err_mask;
442 else
443 ehi->err_mask |= err_mask;
444
445 ata_port_abort(ap);
446}
447
448/*
449 * Function : sata_dwc_isr
450 * arguments : irq, void *dev_instance, struct pt_regs *regs
451 * Return value : irqreturn_t - status of IRQ
452 * This Interrupt handler called via port ops registered function.
453 * .irq_handler = sata_dwc_isr
454 */
455static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
456{
457 struct ata_host *host = (struct ata_host *)dev_instance;
458 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
459 struct ata_port *ap;
460 struct ata_queued_cmd *qc;
461 unsigned long flags;
462 u8 status, tag;
463 int handled, num_processed, port = 0;
464 uint intpr, sactive, sactive2, tag_mask;
465 struct sata_dwc_device_port *hsdevp;
466 host_pvt.sata_dwc_sactive_issued = 0;
467
468 spin_lock_irqsave(&host->lock, flags);
469
470 /* Read the interrupt register */
471 intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
472
473 ap = host->ports[port];
474 hsdevp = HSDEVP_FROM_AP(ap);
475
476 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
477 ap->link.active_tag);
478
479 /* Check for error interrupt */
480 if (intpr & SATA_DWC_INTPR_ERR) {
481 sata_dwc_error_intr(ap, hsdev, intpr);
482 handled = 1;
483 goto DONE;
484 }
485
486 /* Check for DMA SETUP FIS (FP DMA) interrupt */
487 if (intpr & SATA_DWC_INTPR_NEWFP) {
488 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
489
490 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
491 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
492 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
493 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
494
495 host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
496
497 qc = ata_qc_from_tag(ap, tag);
498 /*
499 * Start FP DMA for NCQ command. At this point the tag is the
500 * active tag. It is the tag that matches the command about to
501 * be completed.
502 */
503 qc->ap->link.active_tag = tag;
504 sata_dwc_bmdma_start_by_tag(qc, tag);
505
506 handled = 1;
507 goto DONE;
508 }
509 sactive = core_scr_read(SCR_ACTIVE);
510 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
511
512 /* If no sactive issued and tag_mask is zero then this is not NCQ */
513 if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
514 if (ap->link.active_tag == ATA_TAG_POISON)
515 tag = 0;
516 else
517 tag = ap->link.active_tag;
518 qc = ata_qc_from_tag(ap, tag);
519
520 /* DEV interrupt w/ no active qc? */
521 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
d578514b
AS		 522 dev_err(ap->dev,
523 "%s interrupt with no active qc qc=%p\n",
524 __func__, qc);
62936009
RS		 525 ap->ops->sff_check_status(ap);
526 handled = 1;
527 goto DONE;
528 }
529 status = ap->ops->sff_check_status(ap);
530
531 qc->ap->link.active_tag = tag;
532 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
533
534 if (status & ATA_ERR) {
535 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
536 sata_dwc_qc_complete(ap, qc, 1);
537 handled = 1;
538 goto DONE;
539 }
540
541 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
84b47e3b 542 __func__, get_prot_descript(qc->tf.protocol));
62936009
RS		 543DRVSTILLBUSY:
544 if (ata_is_dma(qc->tf.protocol)) {
545 /*
546 * Each DMA transaction produces 2 interrupts. The DMAC
547 * transfer complete interrupt and the SATA controller
548 * operation done interrupt. The command should be
549 * completed only after both interrupts are seen.
550 */
8b344485 551 hsdevp->dma_interrupt_count++;
62936009
RS		 552 if (hsdevp->dma_pending[tag] == \
553 SATA_DWC_DMA_PENDING_NONE) {
d578514b
AS		 554 dev_err(ap->dev,
555 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
556 __func__, intpr, status,
62936009
RS		 557 hsdevp->dma_pending[tag]);
558 }
559
8b344485 560 if ((hsdevp->dma_interrupt_count % 2) == 0)
62936009
RS		 561 sata_dwc_dma_xfer_complete(ap, 1);
562 } else if (ata_is_pio(qc->tf.protocol)) {
563 ata_sff_hsm_move(ap, qc, status, 0);
564 handled = 1;
565 goto DONE;
566 } else {
567 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
568 goto DRVSTILLBUSY;
569 }
570
571 handled = 1;
572 goto DONE;
573 }
574
575 /*
576 * This is a NCQ command. At this point we need to figure out for which
577 * tags we have gotten a completion interrupt. One interrupt may serve
578 * as completion for more than one operation when commands are queued
579 * (NCQ). We need to process each completed command.
580 */
581
582 /* process completed commands */
583 sactive = core_scr_read(SCR_ACTIVE);
584 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
585
586 if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
587 tag_mask > 1) {
d578514b
AS		 588 dev_dbg(ap->dev,
589 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
590 __func__, sactive, host_pvt.sata_dwc_sactive_issued,
591 tag_mask);
62936009
RS		 592 }
593
594 if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
595 (host_pvt.sata_dwc_sactive_issued)) {
d578514b
AS		 596 dev_warn(ap->dev,
597 "Bad tag mask? sactive=0x%08x (host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask=0x%08x\n",
598 sactive, host_pvt.sata_dwc_sactive_issued, tag_mask);
62936009
RS		 599 }
600
601 /* read just to clear ... not bad if currently still busy */
602 status = ap->ops->sff_check_status(ap);
603 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
604
605 tag = 0;
606 num_processed = 0;
607 while (tag_mask) {
608 num_processed++;
609 while (!(tag_mask & 0x00000001)) {
610 tag++;
611 tag_mask <<= 1;
612 }
613
614 tag_mask &= (~0x00000001);
615 qc = ata_qc_from_tag(ap, tag);
616
617 /* To be picked up by completion functions */
618 qc->ap->link.active_tag = tag;
619 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
620
621 /* Let libata/scsi layers handle error */
622 if (status & ATA_ERR) {
623 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
624 status);
625 sata_dwc_qc_complete(ap, qc, 1);
626 handled = 1;
627 goto DONE;
628 }
629
630 /* Process completed command */
631 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
84b47e3b 632 get_prot_descript(qc->tf.protocol));
62936009 633 if (ata_is_dma(qc->tf.protocol)) {
8b344485 634 hsdevp->dma_interrupt_count++;
62936009
RS		 635 if (hsdevp->dma_pending[tag] == \
636 SATA_DWC_DMA_PENDING_NONE)
637 dev_warn(ap->dev, "%s: DMA not pending?\n",
638 __func__);
8b344485 639 if ((hsdevp->dma_interrupt_count % 2) == 0)
62936009
RS		 640 sata_dwc_dma_xfer_complete(ap, 1);
641 } else {
642 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
643 goto STILLBUSY;
644 }
645 continue;
646
647STILLBUSY:
648 ap->stats.idle_irq++;
649 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
650 ap->print_id);
651 } /* while tag_mask */
652
653 /*
654 * Check to see if any commands completed while we were processing our
655 * initial set of completed commands (read status clears interrupts,
656 * so we might miss a completed command interrupt if one came in while
657 * we were processing --we read status as part of processing a completed
658 * command).
659 */
660 sactive2 = core_scr_read(SCR_ACTIVE);
661 if (sactive2 != sactive) {
d578514b
AS		 662 dev_dbg(ap->dev,
663 "More completed - sactive=0x%x sactive2=0x%x\n",
664 sactive, sactive2);
62936009
RS		 665 }
666 handled = 1;
667
668DONE:
669 spin_unlock_irqrestore(&host->lock, flags);
670 return IRQ_RETVAL(handled);
671}
672
673static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
674{
675 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
676
677 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
678 out_le32(&(hsdev->sata_dwc_regs->dmacr),
679 SATA_DWC_DMACR_RX_CLEAR(
680 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
681 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
682 out_le32(&(hsdev->sata_dwc_regs->dmacr),
683 SATA_DWC_DMACR_TX_CLEAR(
684 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
685 } else {
686 /*
687 * This should not happen, it indicates the driver is out of
688 * sync. If it does happen, clear dmacr anyway.
689 */
d578514b
AS		 690 dev_err(host_pvt.dwc_dev,
691 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
692 __func__, tag, hsdevp->dma_pending[tag],
693 in_le32(&hsdev->sata_dwc_regs->dmacr));
62936009
RS		 694 out_le32(&(hsdev->sata_dwc_regs->dmacr),
695 SATA_DWC_DMACR_TXRXCH_CLEAR);
696 }
697}
698
699static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
700{
701 struct ata_queued_cmd *qc;
702 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
703 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
704 u8 tag = 0;
705
706 tag = ap->link.active_tag;
707 qc = ata_qc_from_tag(ap, tag);
708 if (!qc) {
709 dev_err(ap->dev, "failed to get qc");
710 return;
711 }
712
713#ifdef DEBUG_NCQ
714 if (tag > 0) {
d578514b
AS		 715 dev_info(ap->dev,
716 "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
717 __func__, qc->tag, qc->tf.command,
84b47e3b
SS		 718 get_dma_dir_descript(qc->dma_dir),
719 get_prot_descript(qc->tf.protocol),
62936009
RS		 720 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
721 }
722#endif
723
724 if (ata_is_dma(qc->tf.protocol)) {
725 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
d578514b
AS		 726 dev_err(ap->dev,
727 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
728 __func__,
62936009
RS		 729 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
730 }
731
732 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
733 sata_dwc_qc_complete(ap, qc, check_status);
734 ap->link.active_tag = ATA_TAG_POISON;
735 } else {
736 sata_dwc_qc_complete(ap, qc, check_status);
737 }
738}
739
740static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
741 u32 check_status)
742{
743 u8 status = 0;
744 u32 mask = 0x0;
745 u8 tag = qc->tag;
746 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
747 host_pvt.sata_dwc_sactive_queued = 0;
748 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
749
750 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
751 dev_err(ap->dev, "TX DMA PENDING\n");
752 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
753 dev_err(ap->dev, "RX DMA PENDING\n");
d578514b
AS		 754 dev_dbg(ap->dev,
755 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
756 qc->tf.command, status, ap->print_id, qc->tf.protocol);
62936009
RS		 757
758 /* clear active bit */
759 mask = (~(qcmd_tag_to_mask(tag)));
760 host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
761 & mask;
762 host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
763 & mask;
764 ata_qc_complete(qc);
765 return 0;
766}
767
768static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
769{
770 /* Enable selective interrupts by setting the interrupt maskregister*/
771 out_le32(&hsdev->sata_dwc_regs->intmr,
772 SATA_DWC_INTMR_ERRM |
773 SATA_DWC_INTMR_NEWFPM |
774 SATA_DWC_INTMR_PMABRTM |
775 SATA_DWC_INTMR_DMATM);
776 /*
777 * Unmask the error bits that should trigger an error interrupt by
778 * setting the error mask register.
779 */
780 out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
781
782 dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
783 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
784 in_le32(&hsdev->sata_dwc_regs->errmr));
785}
786
8b344485
AS		 787static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
788{
789 struct sata_dwc_device_port *hsdevp = param;
790 struct dw_dma_slave *dws = hsdevp->dws;
791
792 if (dws->dma_dev != chan->device->dev)
793 return false;
794
795 chan->private = dws;
796 return true;
797}
798
62936009
RS		 799static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
800{
d7c256e8
AS		 801 port->cmd_addr = (void __iomem *)base + 0x00;
802 port->data_addr = (void __iomem *)base + 0x00;
62936009 803
d7c256e8
AS		 804 port->error_addr = (void __iomem *)base + 0x04;
805 port->feature_addr = (void __iomem *)base + 0x04;
62936009 806
d7c256e8 807 port->nsect_addr = (void __iomem *)base + 0x08;
62936009 808
d7c256e8
AS		 809 port->lbal_addr = (void __iomem *)base + 0x0c;
810 port->lbam_addr = (void __iomem *)base + 0x10;
811 port->lbah_addr = (void __iomem *)base + 0x14;
62936009 812
d7c256e8
AS		 813 port->device_addr = (void __iomem *)base + 0x18;
814 port->command_addr = (void __iomem *)base + 0x1c;
815 port->status_addr = (void __iomem *)base + 0x1c;
62936009 816
d7c256e8
AS		 817 port->altstatus_addr = (void __iomem *)base + 0x20;
818 port->ctl_addr = (void __iomem *)base + 0x20;
62936009
RS		 819}
820
821/*
822 * Function : sata_dwc_port_start
823 * arguments : struct ata_ioports *port
824 * Return value : returns 0 if success, error code otherwise
825 * This function allocates the scatter gather LLI table for AHB DMA
826 */
827static int sata_dwc_port_start(struct ata_port *ap)
828{
829 int err = 0;
830 struct sata_dwc_device *hsdev;
831 struct sata_dwc_device_port *hsdevp = NULL;
832 struct device *pdev;
8b344485 833 dma_cap_mask_t mask;
62936009
RS		 834 int i;
835
836 hsdev = HSDEV_FROM_AP(ap);
837
838 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
839
840 hsdev->host = ap->host;
841 pdev = ap->host->dev;
842 if (!pdev) {
843 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
844 err = -ENODEV;
845 goto CLEANUP;
846 }
847
848 /* Allocate Port Struct */
849 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
850 if (!hsdevp) {
851 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
852 err = -ENOMEM;
853 goto CLEANUP;
854 }
855 hsdevp->hsdev = hsdev;
856
8b344485
AS		 857 hsdevp->dws = &sata_dwc_dma_dws;
858 hsdevp->dws->dma_dev = host_pvt.dwc_dev;
859
860 dma_cap_zero(mask);
861 dma_cap_set(DMA_SLAVE, mask);
862
863 /* Acquire DMA channel */
864 hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
865 if (!hsdevp->chan) {
866 dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
867 __func__);
868 err = -EAGAIN;
869 goto CLEANUP_ALLOC;
870 }
871
62936009
RS		 872 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
873 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
874
d7c256e8 875 ap->bmdma_prd = NULL; /* set these so libata doesn't use them */
62936009
RS		 876 ap->bmdma_prd_dma = 0;
877
62936009
RS		 878 if (ap->port_no == 0) {
879 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
880 __func__);
881 out_le32(&hsdev->sata_dwc_regs->dmacr,
882 SATA_DWC_DMACR_TXRXCH_CLEAR);
883
884 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
885 __func__);
886 out_le32(&hsdev->sata_dwc_regs->dbtsr,
887 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
888 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
889 }
890
891 /* Clear any error bits before libata starts issuing commands */
892 clear_serror();
893 ap->private_data = hsdevp;
a081da63
JL		 894 dev_dbg(ap->dev, "%s: done\n", __func__);
895 return 0;
62936009 896
a081da63
JL		 897CLEANUP_ALLOC:
898 kfree(hsdevp);
62936009 899CLEANUP:
a081da63 900 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
62936009
RS		 901 return err;
902}
903
904static void sata_dwc_port_stop(struct ata_port *ap)
905{
62936009
RS		 906 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
907
908 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
909
8b344485
AS		 910 dmaengine_terminate_all(hsdevp->chan);
911 dma_release_channel(hsdevp->chan);
62936009 912
8b344485 913 kfree(hsdevp);
62936009
RS		 914 ap->private_data = NULL;
915}
916
917/*
918 * Function : sata_dwc_exec_command_by_tag
919 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
920 * Return value : None
921 * This function keeps track of individual command tag ids and calls
922 * ata_exec_command in libata
923 */
924static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
925 struct ata_taskfile *tf,
926 u8 tag, u32 cmd_issued)
927{
928 unsigned long flags;
929 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
930
931 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
c211962d 932 ata_get_cmd_descript(tf->command), tag);
62936009
RS		 933
934 spin_lock_irqsave(&ap->host->lock, flags);
935 hsdevp->cmd_issued[tag] = cmd_issued;
936 spin_unlock_irqrestore(&ap->host->lock, flags);
937 /*
938 * Clear SError before executing a new command.
939 * sata_dwc_scr_write and read can not be used here. Clearing the PM
940 * managed SError register for the disk needs to be done before the
941 * task file is loaded.
942 */
943 clear_serror();
944 ata_sff_exec_command(ap, tf);
945}
946
947static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
948{
949 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
950 SATA_DWC_CMD_ISSUED_PEND);
951}
952
953static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
954{
955 u8 tag = qc->tag;
956
957 if (ata_is_ncq(qc->tf.protocol)) {
958 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
959 __func__, qc->ap->link.sactive, tag);
960 } else {
961 tag = 0;
962 }
963 sata_dwc_bmdma_setup_by_tag(qc, tag);
964}
965
966static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
967{
968 int start_dma;
8b344485 969 u32 reg;
62936009
RS		 970 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
971 struct ata_port *ap = qc->ap;
972 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
8b344485 973 struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
62936009 974 int dir = qc->dma_dir;
62936009
RS		 975
976 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
977 start_dma = 1;
978 if (dir == DMA_TO_DEVICE)
979 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
980 else
981 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
982 } else {
d578514b
AS		 983 dev_err(ap->dev,
984 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
985 __func__, hsdevp->cmd_issued[tag], tag);
62936009
RS		 986 start_dma = 0;
987 }
988
d578514b
AS		 989 dev_dbg(ap->dev,
990 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
991 __func__, qc, tag, qc->tf.command,
84b47e3b 992 get_dma_dir_descript(qc->dma_dir), start_dma);
62936009
RS		 993 sata_dwc_tf_dump(&(qc->tf));
994
995 if (start_dma) {
996 reg = core_scr_read(SCR_ERROR);
997 if (reg & SATA_DWC_SERROR_ERR_BITS) {
998 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
999 __func__, reg);
1000 }
1001
1002 if (dir == DMA_TO_DEVICE)
1003 out_le32(&hsdev->sata_dwc_regs->dmacr,
1004 SATA_DWC_DMACR_TXCHEN);
1005 else
1006 out_le32(&hsdev->sata_dwc_regs->dmacr,
1007 SATA_DWC_DMACR_RXCHEN);
1008
1009 /* Enable AHB DMA transfer on the specified channel */
8b344485
AS		 1010 dmaengine_submit(desc);
1011 dma_async_issue_pending(hsdevp->chan);
62936009
RS		 1012 }
1013}
1014
1015static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1016{
1017 u8 tag = qc->tag;
1018
1019 if (ata_is_ncq(qc->tf.protocol)) {
1020 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1021 __func__, qc->ap->link.sactive, tag);
1022 } else {
1023 tag = 0;
1024 }
1025 dev_dbg(qc->ap->dev, "%s\n", __func__);
1026 sata_dwc_bmdma_start_by_tag(qc, tag);
1027}
1028
1029/*
1030 * Function : sata_dwc_qc_prep_by_tag
1031 * arguments : ata_queued_cmd *qc, u8 tag
1032 * Return value : None
1033 * qc_prep for a particular queued command based on tag
1034 */
1035static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
1036{
8b344485 1037 struct dma_async_tx_descriptor *desc;
62936009 1038 struct ata_port *ap = qc->ap;
62936009 1039 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
62936009
RS		 1040
1041 dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
84b47e3b 1042 __func__, ap->port_no, get_dma_dir_descript(qc->dma_dir),
62936009
RS		 1043 qc->n_elem);
1044
8b344485
AS		 1045 desc = dma_dwc_xfer_setup(qc);
1046 if (!desc) {
1047 dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns NULL\n",
1048 __func__);
62936009
RS		 1049 return;
1050 }
8b344485 1051 hsdevp->desc[tag] = desc;
62936009
RS		 1052}
1053
1054static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1055{
1056 u32 sactive;
1057 u8 tag = qc->tag;
1058 struct ata_port *ap = qc->ap;
1059
1060#ifdef DEBUG_NCQ
1061 if (qc->tag > 0 || ap->link.sactive > 1)
d578514b
AS		 1062 dev_info(ap->dev,
1063 "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
62936009 1064 __func__, ap->print_id, qc->tf.command,
c211962d 1065 ata_get_cmd_descript(qc->tf.command),
84b47e3b 1066 qc->tag, get_prot_descript(qc->tf.protocol),
62936009
RS		 1067 ap->link.active_tag, ap->link.sactive);
1068#endif
1069
1070 if (!ata_is_ncq(qc->tf.protocol))
1071 tag = 0;
1072 sata_dwc_qc_prep_by_tag(qc, tag);
1073
1074 if (ata_is_ncq(qc->tf.protocol)) {
1075 sactive = core_scr_read(SCR_ACTIVE);
1076 sactive |= (0x00000001 << tag);
1077 core_scr_write(SCR_ACTIVE, sactive);
1078
d578514b
AS		 1079 dev_dbg(qc->ap->dev,
1080 "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1081 __func__, tag, qc->ap->link.sactive, sactive);
62936009
RS		 1082
1083 ap->ops->sff_tf_load(ap, &qc->tf);
1084 sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
1085 SATA_DWC_CMD_ISSUED_PEND);
1086 } else {
1087 ata_sff_qc_issue(qc);
1088 }
1089 return 0;
1090}
1091
1092/*
1093 * Function : sata_dwc_qc_prep
1094 * arguments : ata_queued_cmd *qc
1095 * Return value : None
1096 * qc_prep for a particular queued command
1097 */
1098
1099static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1100{
1101 if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1102 return;
1103
1104#ifdef DEBUG_NCQ
1105 if (qc->tag > 0)
1106 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
c211962d 1107 __func__, qc->tag, qc->ap->link.active_tag);
62936009
RS		 1108
1109 return ;
1110#endif
1111}
1112
1113static void sata_dwc_error_handler(struct ata_port *ap)
1114{
62936009
RS		 1115 ata_sff_error_handler(ap);
1116}
1117
d7c256e8
AS		 1118static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1119 unsigned long deadline)
3a8b788f
TN		 1120{
1121 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1122 int ret;
1123
1124 ret = sata_sff_hardreset(link, class, deadline);
1125
1126 sata_dwc_enable_interrupts(hsdev);
1127
1128 /* Reconfigure the DMA control register */
1129 out_le32(&hsdev->sata_dwc_regs->dmacr,
1130 SATA_DWC_DMACR_TXRXCH_CLEAR);
1131
1132 /* Reconfigure the DMA Burst Transaction Size register */
1133 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1134 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1135 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1136
1137 return ret;
1138}
1139
62936009
RS		 1140/*
1141 * scsi mid-layer and libata interface structures
1142 */
1143static struct scsi_host_template sata_dwc_sht = {
1144 ATA_NCQ_SHT(DRV_NAME),
1145 /*
1146 * test-only: Currently this driver doesn't handle NCQ
1147 * correctly. We enable NCQ but set the queue depth to a
1148 * max of 1. This will get fixed in in a future release.
1149 */
1150 .sg_tablesize = LIBATA_MAX_PRD,
d7c256e8 1151 /* .can_queue = ATA_MAX_QUEUE, */
62936009
RS		 1152 .dma_boundary = ATA_DMA_BOUNDARY,
1153};
1154
1155static struct ata_port_operations sata_dwc_ops = {
1156 .inherits = &ata_sff_port_ops,
1157
1158 .error_handler = sata_dwc_error_handler,
3a8b788f 1159 .hardreset = sata_dwc_hardreset,
62936009
RS		 1160
1161 .qc_prep = sata_dwc_qc_prep,
1162 .qc_issue = sata_dwc_qc_issue,
1163
1164 .scr_read = sata_dwc_scr_read,
1165 .scr_write = sata_dwc_scr_write,
1166
1167 .port_start = sata_dwc_port_start,
1168 .port_stop = sata_dwc_port_stop,
1169
1170 .bmdma_setup = sata_dwc_bmdma_setup,
1171 .bmdma_start = sata_dwc_bmdma_start,
1172};
1173
1174static const struct ata_port_info sata_dwc_port_info[] = {
1175 {
9cbe056f 1176 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
b83a4c39 1177 .pio_mask = ATA_PIO4,
62936009
RS		 1178 .udma_mask = ATA_UDMA6,
1179 .port_ops = &sata_dwc_ops,
1180 },
1181};
1182
1c48a5c9 1183static int sata_dwc_probe(struct platform_device *ofdev)
62936009
RS		 1184{
1185 struct sata_dwc_device *hsdev;
1186 u32 idr, versionr;
1187 char *ver = (char *)&versionr;
d7c256e8 1188 u8 __iomem *base;
62936009 1189 int err = 0;
4aaa7187 1190 int irq;
62936009
RS		 1191 struct ata_host *host;
1192 struct ata_port_info pi = sata_dwc_port_info[0];
1193 const struct ata_port_info *ppi[] = { &pi, NULL };
dc7f71f4 1194 struct device_node *np = ofdev->dev.of_node;
62936009
RS		 1195
1196 /* Allocate DWC SATA device */
d537fc0c
AS		 1197 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1198 hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
1199 if (!host || !hsdev)
c592b74f 1200 return -ENOMEM;
62936009 1201
d537fc0c
AS		 1202 host->private_data = hsdev;
1203
62936009 1204 /* Ioremap SATA registers */
9037908f 1205 base = of_iomap(np, 0);
62936009 1206 if (!base) {
d578514b
AS		 1207 dev_err(&ofdev->dev,
1208 "ioremap failed for SATA register address\n");
d537fc0c 1209 return -ENODEV;
62936009
RS		 1210 }
1211 hsdev->reg_base = base;
1212 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1213
1214 /* Synopsys DWC SATA specific Registers */
1215 hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1216
62936009
RS		 1217 /* Setup port */
1218 host->ports[0]->ioaddr.cmd_addr = base;
1219 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1220 host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
1221 sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1222
1223 /* Read the ID and Version Registers */
1224 idr = in_le32(&hsdev->sata_dwc_regs->idr);
1225 versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1226 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1227 idr, ver[0], ver[1], ver[2]);
1228
1229 /* Get SATA DMA interrupt number */
8b344485
AS		 1230 hsdev->dma->irq = irq_of_parse_and_map(np, 1);
1231 if (hsdev->dma->irq == NO_IRQ) {
62936009
RS		 1232 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1233 err = -ENODEV;
4aaa7187 1234 goto error_iomap;
62936009
RS		 1235 }
1236
1237 /* Get physical SATA DMA register base address */
8b344485
AS		 1238 hsdev->dma->regs = of_iomap(np, 1);
1239 if (!hsdev->dma->regs) {
d578514b
AS		 1240 dev_err(&ofdev->dev,
1241 "ioremap failed for AHBDMA register address\n");
62936009 1242 err = -ENODEV;
4aaa7187 1243 goto error_iomap;
62936009
RS		 1244 }
1245
1246 /* Save dev for later use in dev_xxx() routines */
1247 host_pvt.dwc_dev = &ofdev->dev;
1248
8b344485
AS		 1249 hsdev->dma->dev = &ofdev->dev;
1250
62936009 1251 /* Initialize AHB DMAC */
8b344485 1252 err = dw_dma_probe(hsdev->dma, NULL);
4aaa7187
AS		 1253 if (err)
1254 goto error_dma_iomap;
62936009
RS		 1255
1256 /* Enable SATA Interrupts */
1257 sata_dwc_enable_interrupts(hsdev);
1258
1259 /* Get SATA interrupt number */
9037908f 1260 irq = irq_of_parse_and_map(np, 0);
62936009
RS		 1261 if (irq == NO_IRQ) {
1262 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1263 err = -ENODEV;
1264 goto error_out;
1265 }
1266
1267 /*
1268 * Now, register with libATA core, this will also initiate the
1269 * device discovery process, invoking our port_start() handler &
1270 * error_handler() to execute a dummy Softreset EH session
1271 */
4aaa7187
AS		 1272 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1273 if (err)
62936009
RS		 1274 dev_err(&ofdev->dev, "failed to activate host");
1275
1276 dev_set_drvdata(&ofdev->dev, host);
1277 return 0;
1278
1279error_out:
1280 /* Free SATA DMA resources */
8b344485 1281 dw_dma_remove(hsdev->dma);
4aaa7187 1282error_dma_iomap:
8b344485 1283 iounmap(hsdev->dma->regs);
04e506b5
VK		 1284error_iomap:
1285 iounmap(base);
62936009
RS		 1286 return err;
1287}
1288
60652d07 1289static int sata_dwc_remove(struct platform_device *ofdev)
62936009
RS		 1290{
1291 struct device *dev = &ofdev->dev;
1292 struct ata_host *host = dev_get_drvdata(dev);
1293 struct sata_dwc_device *hsdev = host->private_data;
1294
1295 ata_host_detach(host);
62936009
RS		 1296
1297 /* Free SATA DMA resources */
8b344485 1298 dw_dma_remove(hsdev->dma);
62936009 1299
8b344485 1300 iounmap(hsdev->dma->regs);
62936009 1301 iounmap(hsdev->reg_base);
62936009
RS		 1302 dev_dbg(&ofdev->dev, "done\n");
1303 return 0;
1304}
1305
1306static const struct of_device_id sata_dwc_match[] = {
1307 { .compatible = "amcc,sata-460ex", },
1308 {}
1309};
1310MODULE_DEVICE_TABLE(of, sata_dwc_match);
1311
1c48a5c9 1312static struct platform_driver sata_dwc_driver = {
62936009
RS		 1313 .driver = {
1314 .name = DRV_NAME,
62936009
RS		 1315 .of_match_table = sata_dwc_match,
1316 },
1317 .probe = sata_dwc_probe,
1318 .remove = sata_dwc_remove,
1319};
1320
99c8ea3e 1321module_platform_driver(sata_dwc_driver);
62936009
RS		 1322
1323MODULE_LICENSE("GPL");
1324MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
d578514b 1325MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
62936009 1326MODULE_VERSION(DRV_VERSION);