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libata: reimplement reset sequencing
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ata / pata_sis.c
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669a5db4
JG		 1/*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Based upon linux/drivers/ide/pci/sis5513.c
7 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
9 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
10 * SiS Taiwan : for direct support and hardware.
11 * Daniela Engert : for initial ATA100 advices and numerous others.
12 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
13 * for checking code correctness, providing patches.
14 * Original tests and design on the SiS620 chipset.
15 * ATA100 tests and design on the SiS735 chipset.
16 * ATA16/33 support from specs
17 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
18 *
19 *
20 * TODO
21 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
22 * More Testing
23 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34#include <linux/ata.h>
4bb64fb9 35#include "sis.h"
669a5db4
JG		 36
37#define DRV_NAME "pata_sis"
2e413f51 38#define DRV_VERSION "0.5.1"
669a5db4
JG		 39
40struct sis_chipset {
41 u16 device; /* PCI host ID */
42 struct ata_port_info *info; /* Info block */
43 /* Probably add family, cable detect type etc here to clean
44 up code later */
45};
46
7dcbc1f2
JJ		 47struct sis_laptop {
48 u16 device;
49 u16 subvendor;
50 u16 subdevice;
51};
52
53static const struct sis_laptop sis_laptop[] = {
54 /* devid, subvendor, subdev */
55 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
56 /* end marker */
57 { 0, }
58};
59
60static int sis_short_ata40(struct pci_dev *dev)
61{
62 const struct sis_laptop *lap = &sis_laptop[0];
63
64 while (lap->device) {
65 if (lap->device == dev->device &&
66 lap->subvendor == dev->subsystem_vendor &&
67 lap->subdevice == dev->subsystem_device)
68 return 1;
69 lap++;
70 }
71
72 return 0;
73}
74
669a5db4
JG		 75/**
76 * sis_port_base - return PCI configuration base for dev
77 * @adev: device
78 *
79 * Returns the base of the PCI configuration registers for this port
80 * number.
81 */
82
83static int sis_port_base(struct ata_device *adev)
84{
85 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno);
86}
87
88/**
2e413f51 89 * sis_133_cable_detect - check for 40/80 pin
669a5db4 90 * @ap: Port
d4b2bab4 91 * @deadline: deadline jiffies for the operation
669a5db4
JG		 92 *
93 * Perform cable detection for the later UDMA133 capable
94 * SiS chipset.
95 */
96
2e413f51 97static int sis_133_cable_detect(struct ata_port *ap)
669a5db4 98{
669a5db4
JG		 99 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
100 u16 tmp;
101
669a5db4
JG		 102 /* The top bit of this register is the cable detect bit */
103 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
7dcbc1f2 104 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
2e413f51
AC		 105 return ATA_CBL_PATA40;
106 return ATA_CBL_PATA80;
669a5db4
JG		 107}
108
109/**
2e413f51 110 * sis_66_cable_detect - check for 40/80 pin
669a5db4 111 * @ap: Port
d4b2bab4 112 * @deadline: deadline jiffies for the operation
669a5db4
JG		 113 *
114 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
115 * SiS IDE controllers.
116 */
117
2e413f51 118static int sis_66_cable_detect(struct ata_port *ap)
669a5db4 119{
669a5db4
JG		 120 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
121 u8 tmp;
122
669a5db4
JG		 123 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
124 pci_read_config_byte(pdev, 0x48, &tmp);
125 tmp >>= ap->port_no;
7dcbc1f2 126 if ((tmp & 0x10) && !sis_short_ata40(pdev))
2e413f51
AC		 127 return ATA_CBL_PATA40;
128 return ATA_CBL_PATA80;
669a5db4
JG		 129}
130
669a5db4
JG		 131
132/**
2e413f51 133 * sis_pre_reset - probe begin
669a5db4 134 * @ap: ATA port
d4b2bab4 135 * @deadline: deadline jiffies for the operation
669a5db4
JG		 136 *
137 * Set up cable type and use generic probe init
138 */
139
d4b2bab4 140static int sis_old_pre_reset(struct ata_port *ap, unsigned long deadline)
669a5db4
JG		 141{
142 static const struct pci_bits sis_enable_bits[] = {
143 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
144 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
145 };
85cd7251 146
669a5db4
JG		 147 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
148
2e413f51
AC		 149 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
150 return -ENOENT;
d4b2bab4
TH		 151
152 return ata_std_prereset(ap, deadline);
669a5db4
JG		 153}
154
155
156/**
2e413f51 157 * sis_error_handler - Probe specified port on PATA host controller
669a5db4
JG		 158 * @ap: Port to probe
159 *
160 * LOCKING:
161 * None (inherited from caller).
162 */
163
2e413f51 164static void sis_error_handler(struct ata_port *ap)
669a5db4 165{
2e413f51 166 ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
669a5db4
JG		 167}
168
169/**
170 * sis_set_fifo - Set RWP fifo bits for this device
171 * @ap: Port
172 * @adev: Device
173 *
174 * SIS chipsets implement prefetch/postwrite bits for each device
175 * on both channels. This functionality is not ATAPI compatible and
176 * must be configured according to the class of device present
177 */
178
179static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
180{
181 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
182 u8 fifoctrl;
183 u8 mask = 0x11;
184
185 mask <<= (2 * ap->port_no);
186 mask <<= adev->devno;
187
188 /* This holds various bits including the FIFO control */
189 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
190 fifoctrl &= ~mask;
191
192 /* Enable for ATA (disk) only */
193 if (adev->class == ATA_DEV_ATA)
194 fifoctrl |= mask;
195 pci_write_config_byte(pdev, 0x4B, fifoctrl);
196}
197
198/**
199 * sis_old_set_piomode - Initialize host controller PATA PIO timings
200 * @ap: Port whose timings we are configuring
201 * @adev: Device we are configuring for.
202 *
203 * Set PIO mode for device, in host controller PCI config space. This
204 * function handles PIO set up for all chips that are pre ATA100 and
205 * also early ATA100 devices.
206 *
207 * LOCKING:
208 * None (inherited from caller).
209 */
210
211static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
212{
213 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
214 int port = sis_port_base(adev);
215 u8 t1, t2;
216 int speed = adev->pio_mode - XFER_PIO_0;
217
218 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
219 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
220
221 sis_set_fifo(ap, adev);
222
223 pci_read_config_byte(pdev, port, &t1);
224 pci_read_config_byte(pdev, port + 1, &t2);
225
226 t1 &= ~0x0F; /* Clear active/recovery timings */
227 t2 &= ~0x07;
228
229 t1 |= active[speed];
230 t2 |= recovery[speed];
231
232 pci_write_config_byte(pdev, port, t1);
233 pci_write_config_byte(pdev, port + 1, t2);
234}
235
236/**
237 * sis_100_set_pioode - Initialize host controller PATA PIO timings
238 * @ap: Port whose timings we are configuring
239 * @adev: Device we are configuring for.
240 *
241 * Set PIO mode for device, in host controller PCI config space. This
242 * function handles PIO set up for ATA100 devices and early ATA133.
243 *
244 * LOCKING:
245 * None (inherited from caller).
246 */
247
248static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
249{
250 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
251 int port = sis_port_base(adev);
252 int speed = adev->pio_mode - XFER_PIO_0;
253
254 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
255
256 sis_set_fifo(ap, adev);
257
258 pci_write_config_byte(pdev, port, actrec[speed]);
259}
260
261/**
262 * sis_133_set_pioode - Initialize host controller PATA PIO timings
263 * @ap: Port whose timings we are configuring
264 * @adev: Device we are configuring for.
265 *
266 * Set PIO mode for device, in host controller PCI config space. This
267 * function handles PIO set up for the later ATA133 devices.
268 *
269 * LOCKING:
270 * None (inherited from caller).
271 */
272
273static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
274{
275 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
276 int port = 0x40;
277 u32 t1;
278 u32 reg54;
279 int speed = adev->pio_mode - XFER_PIO_0;
280
281 const u32 timing133[] = {
282 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
283 0x0C266000,
284 0x04263000,
285 0x0C0A3000,
286 0x05093000
287 };
288 const u32 timing100[] = {
289 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
290 0x091C4000,
291 0x031C2000,
292 0x09072000,
293 0x04062000
294 };
295
296 sis_set_fifo(ap, adev);
297
298 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
299 pci_read_config_dword(pdev, 0x54, &reg54);
300 if (reg54 & 0x40000000)
301 port = 0x70;
302 port += 8 * ap->port_no + 4 * adev->devno;
303
304 pci_read_config_dword(pdev, port, &t1);
305 t1 &= 0xC0C00FFF; /* Mask out timing */
306
307 if (t1 & 0x08) /* 100 or 133 ? */
308 t1 |= timing133[speed];
309 else
310 t1 |= timing100[speed];
311 pci_write_config_byte(pdev, port, t1);
312}
313
314/**
315 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
316 * @ap: Port whose timings we are configuring
317 * @adev: Device to program
318 *
319 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
320 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
321 * the old ide/pci driver.
322 *
323 * LOCKING:
324 * None (inherited from caller).
325 */
326
327static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
328{
329 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
330 int speed = adev->dma_mode - XFER_MW_DMA_0;
331 int drive_pci = sis_port_base(adev);
332 u16 timing;
333
334 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
335 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
336
337 pci_read_config_word(pdev, drive_pci, &timing);
338
339 if (adev->dma_mode < XFER_UDMA_0) {
340 /* bits 3-0 hold recovery timing bits 8-10 active timing and
341 the higer bits are dependant on the device */
342 timing &= ~ 0x870F;
343 timing |= mwdma_bits[speed];
344 pci_write_config_word(pdev, drive_pci, timing);
345 } else {
346 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
347 speed = adev->dma_mode - XFER_UDMA_0;
348 timing &= ~0x6000;
349 timing |= udma_bits[speed];
350 }
351}
352
353/**
354 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
355 * @ap: Port whose timings we are configuring
356 * @adev: Device to program
357 *
358 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
359 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
360 * the old ide/pci driver.
361 *
362 * LOCKING:
363 * None (inherited from caller).
364 */
365
366static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
367{
368 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
369 int speed = adev->dma_mode - XFER_MW_DMA_0;
370 int drive_pci = sis_port_base(adev);
371 u16 timing;
372
373 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
374 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000};
375
376 pci_read_config_word(pdev, drive_pci, &timing);
377
378 if (adev->dma_mode < XFER_UDMA_0) {
379 /* bits 3-0 hold recovery timing bits 8-10 active timing and
380 the higer bits are dependant on the device, bit 15 udma */
381 timing &= ~ 0x870F;
382 timing |= mwdma_bits[speed];
383 } else {
384 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
385 speed = adev->dma_mode - XFER_UDMA_0;
386 timing &= ~0x6000;
387 timing |= udma_bits[speed];
388 }
389 pci_write_config_word(pdev, drive_pci, timing);
390}
391
392/**
393 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
394 * @ap: Port whose timings we are configuring
395 * @adev: Device to program
396 *
397 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
398 * Handles UDMA66 and early UDMA100 devices.
399 *
400 * LOCKING:
401 * None (inherited from caller).
402 */
403
404static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
405{
406 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
407 int speed = adev->dma_mode - XFER_MW_DMA_0;
408 int drive_pci = sis_port_base(adev);
409 u16 timing;
410
411 const u16 udma_bits[] = { 0x8B00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
412
413 pci_read_config_word(pdev, drive_pci, &timing);
414
415 if (adev->dma_mode < XFER_UDMA_0) {
416 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
417 } else {
418 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
419 speed = adev->dma_mode - XFER_UDMA_0;
420 timing &= ~0x0F00;
421 timing |= udma_bits[speed];
422 }
423 pci_write_config_word(pdev, drive_pci, timing);
424}
425
426/**
427 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
428 * @ap: Port whose timings we are configuring
429 * @adev: Device to program
430 *
431 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
432 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
433 * the old ide/pci driver.
434 *
435 * LOCKING:
436 * None (inherited from caller).
437 */
438
439static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
440{
441 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
442 int speed = adev->dma_mode - XFER_MW_DMA_0;
443 int drive_pci = sis_port_base(adev);
444 u16 timing;
445
2e413f51 446 static const u16 udma_bits[] = { 0x8F00, 0x8A00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
669a5db4
JG		 447
448 pci_read_config_word(pdev, drive_pci, &timing);
449
450 if (adev->dma_mode < XFER_UDMA_0) {
451 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
452 } else {
453 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
454 speed = adev->dma_mode - XFER_UDMA_0;
455 timing &= ~0x0F00;
456 timing |= udma_bits[speed];
457 }
458 pci_write_config_word(pdev, drive_pci, timing);
459}
460
461/**
462 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
463 * @ap: Port whose timings we are configuring
464 * @adev: Device to program
465 *
466 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
467 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
468 * the old ide/pci driver.
469 *
470 * LOCKING:
471 * None (inherited from caller).
472 */
473
474static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
475{
476 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
477 int speed = adev->dma_mode - XFER_MW_DMA_0;
478 int port = 0x40;
479 u32 t1;
480 u32 reg54;
481
482 /* bits 4- cycle time 8 - cvs time */
2e413f51
AC		 483 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
484 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
669a5db4
JG		 485
486 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
487 pci_read_config_dword(pdev, 0x54, &reg54);
488 if (reg54 & 0x40000000)
489 port = 0x70;
490 port += (8 * ap->port_no) + (4 * adev->devno);
491
492 pci_read_config_dword(pdev, port, &t1);
493
494 if (adev->dma_mode < XFER_UDMA_0) {
495 t1 &= ~0x00000004;
496 /* FIXME: need data sheet to add MWDMA here. Also lacking on
497 ide/pci driver */
498 } else {
499 speed = adev->dma_mode - XFER_UDMA_0;
500 /* if & 8 no UDMA133 - need info for ... */
501 t1 &= ~0x00000FF0;
502 t1 |= 0x00000004;
503 if (t1 & 0x08)
504 t1 |= timing_u133[speed];
505 else
506 t1 |= timing_u100[speed];
507 }
508 pci_write_config_dword(pdev, port, t1);
509}
510
511static struct scsi_host_template sis_sht = {
512 .module = THIS_MODULE,
513 .name = DRV_NAME,
514 .ioctl = ata_scsi_ioctl,
515 .queuecommand = ata_scsi_queuecmd,
516 .can_queue = ATA_DEF_QUEUE,
517 .this_id = ATA_SHT_THIS_ID,
518 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 519 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
520 .emulated = ATA_SHT_EMULATED,
521 .use_clustering = ATA_SHT_USE_CLUSTERING,
522 .proc_name = DRV_NAME,
523 .dma_boundary = ATA_DMA_BOUNDARY,
524 .slave_configure = ata_scsi_slave_config,
afdfe899 525 .slave_destroy = ata_scsi_slave_destroy,
669a5db4 526 .bios_param = ata_std_bios_param,
438ac6d5 527#ifdef CONFIG_PM
62d64ae0
AC		 528 .resume = ata_scsi_device_resume,
529 .suspend = ata_scsi_device_suspend,
438ac6d5 530#endif
669a5db4
JG		 531};
532
533static const struct ata_port_operations sis_133_ops = {
534 .port_disable = ata_port_disable,
535 .set_piomode = sis_133_set_piomode,
536 .set_dmamode = sis_133_set_dmamode,
537 .mode_filter = ata_pci_default_filter,
538
539 .tf_load = ata_tf_load,
540 .tf_read = ata_tf_read,
541 .check_status = ata_check_status,
542 .exec_command = ata_exec_command,
543 .dev_select = ata_std_dev_select,
544
545 .freeze = ata_bmdma_freeze,
546 .thaw = ata_bmdma_thaw,
2e413f51 547 .error_handler = sis_error_handler,
669a5db4 548 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2e413f51 549 .cable_detect = sis_133_cable_detect,
669a5db4
JG		 550
551 .bmdma_setup = ata_bmdma_setup,
552 .bmdma_start = ata_bmdma_start,
553 .bmdma_stop = ata_bmdma_stop,
554 .bmdma_status = ata_bmdma_status,
555 .qc_prep = ata_qc_prep,
556 .qc_issue = ata_qc_issue_prot,
0d5ff566 557 .data_xfer = ata_data_xfer,
669a5db4 558
669a5db4
JG		 559 .irq_handler = ata_interrupt,
560 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 561 .irq_on = ata_irq_on,
562 .irq_ack = ata_irq_ack,
669a5db4
JG		 563
564 .port_start = ata_port_start,
669a5db4
JG		 565};
566
567static const struct ata_port_operations sis_133_early_ops = {
568 .port_disable = ata_port_disable,
569 .set_piomode = sis_100_set_piomode,
570 .set_dmamode = sis_133_early_set_dmamode,
571 .mode_filter = ata_pci_default_filter,
572
573 .tf_load = ata_tf_load,
574 .tf_read = ata_tf_read,
575 .check_status = ata_check_status,
576 .exec_command = ata_exec_command,
577 .dev_select = ata_std_dev_select,
578
579 .freeze = ata_bmdma_freeze,
580 .thaw = ata_bmdma_thaw,
2e413f51 581 .error_handler = sis_error_handler,
669a5db4 582 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2e413f51 583 .cable_detect = sis_66_cable_detect,
85cd7251 584
669a5db4
JG		 585 .bmdma_setup = ata_bmdma_setup,
586 .bmdma_start = ata_bmdma_start,
587 .bmdma_stop = ata_bmdma_stop,
588 .bmdma_status = ata_bmdma_status,
589 .qc_prep = ata_qc_prep,
590 .qc_issue = ata_qc_issue_prot,
0d5ff566 591 .data_xfer = ata_data_xfer,
669a5db4 592
669a5db4
JG		 593 .irq_handler = ata_interrupt,
594 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 595 .irq_on = ata_irq_on,
596 .irq_ack = ata_irq_ack,
669a5db4
JG		 597
598 .port_start = ata_port_start,
669a5db4
JG		 599};
600
601static const struct ata_port_operations sis_100_ops = {
602 .port_disable = ata_port_disable,
603 .set_piomode = sis_100_set_piomode,
604 .set_dmamode = sis_100_set_dmamode,
605 .mode_filter = ata_pci_default_filter,
606
607 .tf_load = ata_tf_load,
608 .tf_read = ata_tf_read,
609 .check_status = ata_check_status,
610 .exec_command = ata_exec_command,
611 .dev_select = ata_std_dev_select,
612
613 .freeze = ata_bmdma_freeze,
614 .thaw = ata_bmdma_thaw,
2e413f51 615 .error_handler = sis_error_handler,
669a5db4 616 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2e413f51 617 .cable_detect = sis_66_cable_detect,
669a5db4
JG		 618
619 .bmdma_setup = ata_bmdma_setup,
620 .bmdma_start = ata_bmdma_start,
621 .bmdma_stop = ata_bmdma_stop,
622 .bmdma_status = ata_bmdma_status,
623 .qc_prep = ata_qc_prep,
624 .qc_issue = ata_qc_issue_prot,
0d5ff566 625 .data_xfer = ata_data_xfer,
669a5db4 626
669a5db4
JG		 627 .irq_handler = ata_interrupt,
628 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 629 .irq_on = ata_irq_on,
630 .irq_ack = ata_irq_ack,
669a5db4
JG		 631
632 .port_start = ata_port_start,
669a5db4
JG		 633};
634
635static const struct ata_port_operations sis_66_ops = {
636 .port_disable = ata_port_disable,
637 .set_piomode = sis_old_set_piomode,
638 .set_dmamode = sis_66_set_dmamode,
639 .mode_filter = ata_pci_default_filter,
640
641 .tf_load = ata_tf_load,
642 .tf_read = ata_tf_read,
643 .check_status = ata_check_status,
644 .exec_command = ata_exec_command,
645 .dev_select = ata_std_dev_select,
2e413f51 646 .cable_detect = sis_66_cable_detect,
669a5db4
JG		 647
648 .freeze = ata_bmdma_freeze,
649 .thaw = ata_bmdma_thaw,
2e413f51 650 .error_handler = sis_error_handler,
669a5db4
JG		 651 .post_internal_cmd = ata_bmdma_post_internal_cmd,
652
653 .bmdma_setup = ata_bmdma_setup,
654 .bmdma_start = ata_bmdma_start,
655 .bmdma_stop = ata_bmdma_stop,
656 .bmdma_status = ata_bmdma_status,
657 .qc_prep = ata_qc_prep,
658 .qc_issue = ata_qc_issue_prot,
0d5ff566 659 .data_xfer = ata_data_xfer,
669a5db4 660
669a5db4
JG		 661 .irq_handler = ata_interrupt,
662 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 663 .irq_on = ata_irq_on,
664 .irq_ack = ata_irq_ack,
669a5db4
JG		 665
666 .port_start = ata_port_start,
669a5db4
JG		 667};
668
669static const struct ata_port_operations sis_old_ops = {
670 .port_disable = ata_port_disable,
671 .set_piomode = sis_old_set_piomode,
672 .set_dmamode = sis_old_set_dmamode,
673 .mode_filter = ata_pci_default_filter,
674
675 .tf_load = ata_tf_load,
676 .tf_read = ata_tf_read,
677 .check_status = ata_check_status,
678 .exec_command = ata_exec_command,
679 .dev_select = ata_std_dev_select,
680
681 .freeze = ata_bmdma_freeze,
682 .thaw = ata_bmdma_thaw,
2e413f51 683 .error_handler = sis_error_handler,
669a5db4 684 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2e413f51 685 .cable_detect = ata_cable_40wire,
669a5db4
JG		 686
687 .bmdma_setup = ata_bmdma_setup,
688 .bmdma_start = ata_bmdma_start,
689 .bmdma_stop = ata_bmdma_stop,
690 .bmdma_status = ata_bmdma_status,
691 .qc_prep = ata_qc_prep,
692 .qc_issue = ata_qc_issue_prot,
0d5ff566 693 .data_xfer = ata_data_xfer,
669a5db4 694
669a5db4
JG		 695 .irq_handler = ata_interrupt,
696 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 697 .irq_on = ata_irq_on,
698 .irq_ack = ata_irq_ack,
669a5db4
JG		 699
700 .port_start = ata_port_start,
669a5db4
JG		 701};
702
703static struct ata_port_info sis_info = {
704 .sht = &sis_sht,
705 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
706 .pio_mask = 0x1f, /* pio0-4 */
707 .mwdma_mask = 0x07,
708 .udma_mask = 0,
709 .port_ops = &sis_old_ops,
710};
711static struct ata_port_info sis_info33 = {
712 .sht = &sis_sht,
713 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
714 .pio_mask = 0x1f, /* pio0-4 */
715 .mwdma_mask = 0x07,
716 .udma_mask = ATA_UDMA2, /* UDMA 33 */
717 .port_ops = &sis_old_ops,
718};
719static struct ata_port_info sis_info66 = {
720 .sht = &sis_sht,
721 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
722 .pio_mask = 0x1f, /* pio0-4 */
723 .udma_mask = ATA_UDMA4, /* UDMA 66 */
724 .port_ops = &sis_66_ops,
725};
726static struct ata_port_info sis_info100 = {
727 .sht = &sis_sht,
728 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
729 .pio_mask = 0x1f, /* pio0-4 */
730 .udma_mask = ATA_UDMA5,
731 .port_ops = &sis_100_ops,
732};
733static struct ata_port_info sis_info100_early = {
734 .sht = &sis_sht,
735 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
736 .udma_mask = ATA_UDMA5,
737 .pio_mask = 0x1f, /* pio0-4 */
738 .port_ops = &sis_66_ops,
739};
77a527ea 740struct ata_port_info sis_info133 = {
669a5db4
JG		 741 .sht = &sis_sht,
742 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
743 .pio_mask = 0x1f, /* pio0-4 */
744 .udma_mask = ATA_UDMA6,
745 .port_ops = &sis_133_ops,
746};
747static struct ata_port_info sis_info133_early = {
748 .sht = &sis_sht,
749 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
750 .pio_mask = 0x1f, /* pio0-4 */
751 .udma_mask = ATA_UDMA6,
752 .port_ops = &sis_133_early_ops,
753};
754
9b14dec5
AC		 755/* Privately shared with the SiS180 SATA driver, not for use elsewhere */
756EXPORT_SYMBOL_GPL(sis_info133);
669a5db4
JG		 757
758static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
759{
760 u16 regw;
761 u8 reg;
762
763 if (sis->info == &sis_info133) {
764 pci_read_config_word(pdev, 0x50, &regw);
765 if (regw & 0x08)
766 pci_write_config_word(pdev, 0x50, regw & ~0x08);
767 pci_read_config_word(pdev, 0x52, &regw);
768 if (regw & 0x08)
769 pci_write_config_word(pdev, 0x52, regw & ~0x08);
770 return;
771 }
772
773 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
774 /* Fix up latency */
775 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
776 /* Set compatibility bit */
777 pci_read_config_byte(pdev, 0x49, &reg);
778 if (!(reg & 0x01))
779 pci_write_config_byte(pdev, 0x49, reg | 0x01);
780 return;
781 }
782
783 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
784 /* Fix up latency */
785 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
786 /* Set compatibility bit */
787 pci_read_config_byte(pdev, 0x52, &reg);
788 if (!(reg & 0x04))
789 pci_write_config_byte(pdev, 0x52, reg | 0x04);
790 return;
791 }
792
793 if (sis->info == &sis_info33) {
794 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
795 if (( reg & 0x0F ) != 0x00)
796 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
797 /* Fall through to ATA16 fixup below */
798 }
799
800 if (sis->info == &sis_info || sis->info == &sis_info33) {
801 /* force per drive recovery and active timings
802 needed on ATA_33 and below chips */
803 pci_read_config_byte(pdev, 0x52, &reg);
804 if (!(reg & 0x08))
805 pci_write_config_byte(pdev, 0x52, reg|0x08);
806 return;
807 }
808
809 BUG();
810}
811
812/**
813 * sis_init_one - Register SiS ATA PCI device with kernel services
814 * @pdev: PCI device to register
815 * @ent: Entry in sis_pci_tbl matching with @pdev
816 *
817 * Called from kernel PCI layer. We probe for combined mode (sigh),
818 * and then hand over control to libata, for it to do the rest.
819 *
820 * LOCKING:
821 * Inherited from PCI layer (may sleep).
822 *
823 * RETURNS:
824 * Zero on success, or -ERRNO value.
825 */
826
827static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
828{
829 static int printed_version;
830 static struct ata_port_info *port_info[2];
831 struct ata_port_info *port;
832 struct pci_dev *host = NULL;
833 struct sis_chipset *chipset = NULL;
f3769e9d 834 struct sis_chipset *sets;
669a5db4
JG		 835
836 static struct sis_chipset sis_chipsets[] = {
f20b16ff 837
af323a2f
AC		 838 { 0x0968, &sis_info133 },
839 { 0x0966, &sis_info133 },
840 { 0x0965, &sis_info133 },
669a5db4
JG		 841 { 0x0745, &sis_info100 },
842 { 0x0735, &sis_info100 },
843 { 0x0733, &sis_info100 },
844 { 0x0635, &sis_info100 },
845 { 0x0633, &sis_info100 },
846
847 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
848 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
849
850 { 0x0640, &sis_info66 },
851 { 0x0630, &sis_info66 },
852 { 0x0620, &sis_info66 },
853 { 0x0540, &sis_info66 },
854 { 0x0530, &sis_info66 },
855
856 { 0x5600, &sis_info33 },
857 { 0x5598, &sis_info33 },
858 { 0x5597, &sis_info33 },
859 { 0x5591, &sis_info33 },
860 { 0x5582, &sis_info33 },
861 { 0x5581, &sis_info33 },
862
863 { 0x5596, &sis_info },
864 { 0x5571, &sis_info },
865 { 0x5517, &sis_info },
866 { 0x5511, &sis_info },
867
868 {0}
869 };
870 static struct sis_chipset sis133_early = {
871 0x0, &sis_info133_early
872 };
873 static struct sis_chipset sis133 = {
874 0x0, &sis_info133
875 };
876 static struct sis_chipset sis100_early = {
877 0x0, &sis_info100_early
878 };
879 static struct sis_chipset sis100 = {
880 0x0, &sis_info100
881 };
882
883 if (!printed_version++)
884 dev_printk(KERN_DEBUG, &pdev->dev,
885 "version " DRV_VERSION "\n");
886
887 /* We have to find the bridge first */
888
f3769e9d
AC		 889 for (sets = &sis_chipsets[0]; sets->device; sets++) {
890 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
669a5db4 891 if (host != NULL) {
f3769e9d
AC		 892 chipset = sets; /* Match found */
893 if (sets->device == 0x630) { /* SIS630 */
669a5db4
JG		 894 u8 host_rev;
895 pci_read_config_byte(host, PCI_REVISION_ID, &host_rev);
896 if (host_rev >= 0x30) /* 630 ET */
897 chipset = &sis100_early;
898 }
899 break;
900 }
901 }
902
903 /* Look for concealed bridges */
f3769e9d 904 if (chipset == NULL) {
669a5db4
JG		 905 /* Second check */
906 u32 idemisc;
907 u16 trueid;
908
909 /* Disable ID masking and register remapping then
910 see what the real ID is */
911
912 pci_read_config_dword(pdev, 0x54, &idemisc);
913 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
914 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
915 pci_write_config_dword(pdev, 0x54, idemisc);
916
917 switch(trueid) {
918 case 0x5518: /* SIS 962/963 */
919 chipset = &sis133;
920 if ((idemisc & 0x40000000) == 0) {
921 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
922 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
923 }
924 break;
925 case 0x0180: /* SIS 965/965L */
926 chipset = &sis133;
927 break;
928 case 0x1180: /* SIS 966/966L */
929 chipset = &sis133;
930 break;
931 }
932 }
933
934 /* Further check */
935 if (chipset == NULL) {
936 struct pci_dev *lpc_bridge;
937 u16 trueid;
938 u8 prefctl;
939 u8 idecfg;
940 u8 sbrev;
941
942 /* Try the second unmasking technique */
943 pci_read_config_byte(pdev, 0x4a, &idecfg);
944 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
945 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
946 pci_write_config_byte(pdev, 0x4a, idecfg);
947
948 switch(trueid) {
949 case 0x5517:
950 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
951 if (lpc_bridge == NULL)
952 break;
953 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
954 pci_read_config_byte(pdev, 0x49, &prefctl);
955 pci_dev_put(lpc_bridge);
956
957 if (sbrev == 0x10 && (prefctl & 0x80)) {
958 chipset = &sis133_early;
959 break;
960 }
961 chipset = &sis100;
962 break;
963 }
964 }
965 pci_dev_put(host);
966
967 /* No chipset info, no support */
968 if (chipset == NULL)
969 return -ENODEV;
970
971 port = chipset->info;
972 port->private_data = chipset;
973
974 sis_fixup(pdev, chipset);
975
976 port_info[0] = port_info[1] = port;
977 return ata_pci_init_one(pdev, port_info, 2);
978}
979
980static const struct pci_device_id sis_pci_tbl[] = {
2d2744fc
JG		 981 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
982 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
983
669a5db4
JG		 984 { }
985};
986
987static struct pci_driver sis_pci_driver = {
988 .name = DRV_NAME,
989 .id_table = sis_pci_tbl,
990 .probe = sis_init_one,
991 .remove = ata_pci_remove_one,
438ac6d5 992#ifdef CONFIG_PM
62d64ae0
AC		 993 .suspend = ata_pci_device_suspend,
994 .resume = ata_pci_device_resume,
438ac6d5 995#endif
669a5db4
JG		 996};
997
998static int __init sis_init(void)
999{
1000 return pci_register_driver(&sis_pci_driver);
1001}
1002
1003static void __exit sis_exit(void)
1004{
1005 pci_unregister_driver(&sis_pci_driver);
1006}
1007
669a5db4
JG		 1008module_init(sis_init);
1009module_exit(sis_exit);
1010
1011MODULE_AUTHOR("Alan Cox");
1012MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1013MODULE_LICENSE("GPL");
1014MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1015MODULE_VERSION(DRV_VERSION);
1016