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pata_platform: fix devres conversion
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ata / pata_sis.c
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669a5db4
JG		 1/*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Based upon linux/drivers/ide/pci/sis5513.c
7 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
9 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
10 * SiS Taiwan : for direct support and hardware.
11 * Daniela Engert : for initial ATA100 advices and numerous others.
12 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
13 * for checking code correctness, providing patches.
14 * Original tests and design on the SiS620 chipset.
15 * ATA100 tests and design on the SiS735 chipset.
16 * ATA16/33 support from specs
17 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
18 *
19 *
20 * TODO
21 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
22 * More Testing
23 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34#include <linux/ata.h>
77a527ea 35#include "libata.h"
669a5db4 36
fda0efc5 37#undef DRV_NAME /* already defined in libata.h, for libata-core */
669a5db4 38#define DRV_NAME "pata_sis"
62d64ae0 39#define DRV_VERSION "0.4.5"
669a5db4
JG		 40
41struct sis_chipset {
42 u16 device; /* PCI host ID */
43 struct ata_port_info *info; /* Info block */
44 /* Probably add family, cable detect type etc here to clean
45 up code later */
46};
47
7dcbc1f2
JJ		 48struct sis_laptop {
49 u16 device;
50 u16 subvendor;
51 u16 subdevice;
52};
53
54static const struct sis_laptop sis_laptop[] = {
55 /* devid, subvendor, subdev */
56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
57 /* end marker */
58 { 0, }
59};
60
61static int sis_short_ata40(struct pci_dev *dev)
62{
63 const struct sis_laptop *lap = &sis_laptop[0];
64
65 while (lap->device) {
66 if (lap->device == dev->device &&
67 lap->subvendor == dev->subsystem_vendor &&
68 lap->subdevice == dev->subsystem_device)
69 return 1;
70 lap++;
71 }
72
73 return 0;
74}
75
669a5db4
JG		 76/**
77 * sis_port_base - return PCI configuration base for dev
78 * @adev: device
79 *
80 * Returns the base of the PCI configuration registers for this port
81 * number.
82 */
83
84static int sis_port_base(struct ata_device *adev)
85{
86 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno);
87}
88
89/**
90 * sis_133_pre_reset - check for 40/80 pin
91 * @ap: Port
92 *
93 * Perform cable detection for the later UDMA133 capable
94 * SiS chipset.
95 */
96
97static int sis_133_pre_reset(struct ata_port *ap)
98{
99 static const struct pci_bits sis_enable_bits[] = {
100 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
101 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
102 };
85cd7251 103
669a5db4
JG		 104 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
105 u16 tmp;
106
c961922b
AC		 107 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
108 return -ENOENT;
109
669a5db4
JG		 110 /* The top bit of this register is the cable detect bit */
111 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
7dcbc1f2 112 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
669a5db4
JG		 113 ap->cbl = ATA_CBL_PATA40;
114 else
115 ap->cbl = ATA_CBL_PATA80;
116
117 return ata_std_prereset(ap);
118}
119
120/**
121 * sis_error_handler - Probe specified port on PATA host controller
122 * @ap: Port to probe
123 *
124 * LOCKING:
125 * None (inherited from caller).
126 */
127
128static void sis_133_error_handler(struct ata_port *ap)
129{
130 ata_bmdma_drive_eh(ap, sis_133_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
131}
132
133
134/**
135 * sis_66_pre_reset - check for 40/80 pin
136 * @ap: Port
137 *
138 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
139 * SiS IDE controllers.
140 */
141
142static int sis_66_pre_reset(struct ata_port *ap)
143{
144 static const struct pci_bits sis_enable_bits[] = {
145 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
146 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
147 };
148
149 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
150 u8 tmp;
151
152 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
153 ata_port_disable(ap);
154 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
155 return 0;
156 }
157 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
158 pci_read_config_byte(pdev, 0x48, &tmp);
159 tmp >>= ap->port_no;
7dcbc1f2 160 if ((tmp & 0x10) && !sis_short_ata40(pdev))
669a5db4
JG		 161 ap->cbl = ATA_CBL_PATA40;
162 else
163 ap->cbl = ATA_CBL_PATA80;
164
165 return ata_std_prereset(ap);
166}
167
168/**
169 * sis_66_error_handler - Probe specified port on PATA host controller
170 * @ap: Port to probe
171 * @classes:
172 *
173 * LOCKING:
174 * None (inherited from caller).
175 */
176
177static void sis_66_error_handler(struct ata_port *ap)
178{
179 ata_bmdma_drive_eh(ap, sis_66_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
180}
181
182/**
183 * sis_old_pre_reset - probe begin
184 * @ap: ATA port
185 *
186 * Set up cable type and use generic probe init
187 */
188
189static int sis_old_pre_reset(struct ata_port *ap)
190{
191 static const struct pci_bits sis_enable_bits[] = {
192 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
193 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
194 };
85cd7251 195
669a5db4
JG		 196 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
197
198 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) {
199 ata_port_disable(ap);
200 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
201 return 0;
202 }
203 ap->cbl = ATA_CBL_PATA40;
204 return ata_std_prereset(ap);
205}
206
207
208/**
209 * sis_old_error_handler - Probe specified port on PATA host controller
210 * @ap: Port to probe
211 *
212 * LOCKING:
213 * None (inherited from caller).
214 */
215
216static void sis_old_error_handler(struct ata_port *ap)
217{
218 ata_bmdma_drive_eh(ap, sis_old_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
219}
220
221/**
222 * sis_set_fifo - Set RWP fifo bits for this device
223 * @ap: Port
224 * @adev: Device
225 *
226 * SIS chipsets implement prefetch/postwrite bits for each device
227 * on both channels. This functionality is not ATAPI compatible and
228 * must be configured according to the class of device present
229 */
230
231static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
232{
233 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
234 u8 fifoctrl;
235 u8 mask = 0x11;
236
237 mask <<= (2 * ap->port_no);
238 mask <<= adev->devno;
239
240 /* This holds various bits including the FIFO control */
241 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
242 fifoctrl &= ~mask;
243
244 /* Enable for ATA (disk) only */
245 if (adev->class == ATA_DEV_ATA)
246 fifoctrl |= mask;
247 pci_write_config_byte(pdev, 0x4B, fifoctrl);
248}
249
250/**
251 * sis_old_set_piomode - Initialize host controller PATA PIO timings
252 * @ap: Port whose timings we are configuring
253 * @adev: Device we are configuring for.
254 *
255 * Set PIO mode for device, in host controller PCI config space. This
256 * function handles PIO set up for all chips that are pre ATA100 and
257 * also early ATA100 devices.
258 *
259 * LOCKING:
260 * None (inherited from caller).
261 */
262
263static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
264{
265 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
266 int port = sis_port_base(adev);
267 u8 t1, t2;
268 int speed = adev->pio_mode - XFER_PIO_0;
269
270 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
271 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
272
273 sis_set_fifo(ap, adev);
274
275 pci_read_config_byte(pdev, port, &t1);
276 pci_read_config_byte(pdev, port + 1, &t2);
277
278 t1 &= ~0x0F; /* Clear active/recovery timings */
279 t2 &= ~0x07;
280
281 t1 |= active[speed];
282 t2 |= recovery[speed];
283
284 pci_write_config_byte(pdev, port, t1);
285 pci_write_config_byte(pdev, port + 1, t2);
286}
287
288/**
289 * sis_100_set_pioode - Initialize host controller PATA PIO timings
290 * @ap: Port whose timings we are configuring
291 * @adev: Device we are configuring for.
292 *
293 * Set PIO mode for device, in host controller PCI config space. This
294 * function handles PIO set up for ATA100 devices and early ATA133.
295 *
296 * LOCKING:
297 * None (inherited from caller).
298 */
299
300static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
301{
302 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
303 int port = sis_port_base(adev);
304 int speed = adev->pio_mode - XFER_PIO_0;
305
306 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
307
308 sis_set_fifo(ap, adev);
309
310 pci_write_config_byte(pdev, port, actrec[speed]);
311}
312
313/**
314 * sis_133_set_pioode - Initialize host controller PATA PIO timings
315 * @ap: Port whose timings we are configuring
316 * @adev: Device we are configuring for.
317 *
318 * Set PIO mode for device, in host controller PCI config space. This
319 * function handles PIO set up for the later ATA133 devices.
320 *
321 * LOCKING:
322 * None (inherited from caller).
323 */
324
325static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
326{
327 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
328 int port = 0x40;
329 u32 t1;
330 u32 reg54;
331 int speed = adev->pio_mode - XFER_PIO_0;
332
333 const u32 timing133[] = {
334 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
335 0x0C266000,
336 0x04263000,
337 0x0C0A3000,
338 0x05093000
339 };
340 const u32 timing100[] = {
341 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
342 0x091C4000,
343 0x031C2000,
344 0x09072000,
345 0x04062000
346 };
347
348 sis_set_fifo(ap, adev);
349
350 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
351 pci_read_config_dword(pdev, 0x54, &reg54);
352 if (reg54 & 0x40000000)
353 port = 0x70;
354 port += 8 * ap->port_no + 4 * adev->devno;
355
356 pci_read_config_dword(pdev, port, &t1);
357 t1 &= 0xC0C00FFF; /* Mask out timing */
358
359 if (t1 & 0x08) /* 100 or 133 ? */
360 t1 |= timing133[speed];
361 else
362 t1 |= timing100[speed];
363 pci_write_config_byte(pdev, port, t1);
364}
365
366/**
367 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
368 * @ap: Port whose timings we are configuring
369 * @adev: Device to program
370 *
371 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
372 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
373 * the old ide/pci driver.
374 *
375 * LOCKING:
376 * None (inherited from caller).
377 */
378
379static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
380{
381 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
382 int speed = adev->dma_mode - XFER_MW_DMA_0;
383 int drive_pci = sis_port_base(adev);
384 u16 timing;
385
386 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
387 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
388
389 pci_read_config_word(pdev, drive_pci, &timing);
390
391 if (adev->dma_mode < XFER_UDMA_0) {
392 /* bits 3-0 hold recovery timing bits 8-10 active timing and
393 the higer bits are dependant on the device */
394 timing &= ~ 0x870F;
395 timing |= mwdma_bits[speed];
396 pci_write_config_word(pdev, drive_pci, timing);
397 } else {
398 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
399 speed = adev->dma_mode - XFER_UDMA_0;
400 timing &= ~0x6000;
401 timing |= udma_bits[speed];
402 }
403}
404
405/**
406 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
407 * @ap: Port whose timings we are configuring
408 * @adev: Device to program
409 *
410 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
411 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
412 * the old ide/pci driver.
413 *
414 * LOCKING:
415 * None (inherited from caller).
416 */
417
418static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
419{
420 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
421 int speed = adev->dma_mode - XFER_MW_DMA_0;
422 int drive_pci = sis_port_base(adev);
423 u16 timing;
424
425 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
426 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000};
427
428 pci_read_config_word(pdev, drive_pci, &timing);
429
430 if (adev->dma_mode < XFER_UDMA_0) {
431 /* bits 3-0 hold recovery timing bits 8-10 active timing and
432 the higer bits are dependant on the device, bit 15 udma */
433 timing &= ~ 0x870F;
434 timing |= mwdma_bits[speed];
435 } else {
436 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
437 speed = adev->dma_mode - XFER_UDMA_0;
438 timing &= ~0x6000;
439 timing |= udma_bits[speed];
440 }
441 pci_write_config_word(pdev, drive_pci, timing);
442}
443
444/**
445 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
446 * @ap: Port whose timings we are configuring
447 * @adev: Device to program
448 *
449 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
450 * Handles UDMA66 and early UDMA100 devices.
451 *
452 * LOCKING:
453 * None (inherited from caller).
454 */
455
456static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
457{
458 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
459 int speed = adev->dma_mode - XFER_MW_DMA_0;
460 int drive_pci = sis_port_base(adev);
461 u16 timing;
462
463 const u16 udma_bits[] = { 0x8B00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
464
465 pci_read_config_word(pdev, drive_pci, &timing);
466
467 if (adev->dma_mode < XFER_UDMA_0) {
468 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
469 } else {
470 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
471 speed = adev->dma_mode - XFER_UDMA_0;
472 timing &= ~0x0F00;
473 timing |= udma_bits[speed];
474 }
475 pci_write_config_word(pdev, drive_pci, timing);
476}
477
478/**
479 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
480 * @ap: Port whose timings we are configuring
481 * @adev: Device to program
482 *
483 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
484 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
485 * the old ide/pci driver.
486 *
487 * LOCKING:
488 * None (inherited from caller).
489 */
490
491static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
492{
493 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
494 int speed = adev->dma_mode - XFER_MW_DMA_0;
495 int drive_pci = sis_port_base(adev);
496 u16 timing;
497
498 const u16 udma_bits[] = { 0x8F00, 0x8A00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
499
500 pci_read_config_word(pdev, drive_pci, &timing);
501
502 if (adev->dma_mode < XFER_UDMA_0) {
503 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
504 } else {
505 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
506 speed = adev->dma_mode - XFER_UDMA_0;
507 timing &= ~0x0F00;
508 timing |= udma_bits[speed];
509 }
510 pci_write_config_word(pdev, drive_pci, timing);
511}
512
513/**
514 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
515 * @ap: Port whose timings we are configuring
516 * @adev: Device to program
517 *
518 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
519 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
520 * the old ide/pci driver.
521 *
522 * LOCKING:
523 * None (inherited from caller).
524 */
525
526static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
527{
528 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
529 int speed = adev->dma_mode - XFER_MW_DMA_0;
530 int port = 0x40;
531 u32 t1;
532 u32 reg54;
533
534 /* bits 4- cycle time 8 - cvs time */
535 const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
536 const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
537
538 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
539 pci_read_config_dword(pdev, 0x54, &reg54);
540 if (reg54 & 0x40000000)
541 port = 0x70;
542 port += (8 * ap->port_no) + (4 * adev->devno);
543
544 pci_read_config_dword(pdev, port, &t1);
545
546 if (adev->dma_mode < XFER_UDMA_0) {
547 t1 &= ~0x00000004;
548 /* FIXME: need data sheet to add MWDMA here. Also lacking on
549 ide/pci driver */
550 } else {
551 speed = adev->dma_mode - XFER_UDMA_0;
552 /* if & 8 no UDMA133 - need info for ... */
553 t1 &= ~0x00000FF0;
554 t1 |= 0x00000004;
555 if (t1 & 0x08)
556 t1 |= timing_u133[speed];
557 else
558 t1 |= timing_u100[speed];
559 }
560 pci_write_config_dword(pdev, port, t1);
561}
562
563static struct scsi_host_template sis_sht = {
564 .module = THIS_MODULE,
565 .name = DRV_NAME,
566 .ioctl = ata_scsi_ioctl,
567 .queuecommand = ata_scsi_queuecmd,
568 .can_queue = ATA_DEF_QUEUE,
569 .this_id = ATA_SHT_THIS_ID,
570 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 571 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
572 .emulated = ATA_SHT_EMULATED,
573 .use_clustering = ATA_SHT_USE_CLUSTERING,
574 .proc_name = DRV_NAME,
575 .dma_boundary = ATA_DMA_BOUNDARY,
576 .slave_configure = ata_scsi_slave_config,
afdfe899 577 .slave_destroy = ata_scsi_slave_destroy,
669a5db4 578 .bios_param = ata_std_bios_param,
62d64ae0
AC		 579 .resume = ata_scsi_device_resume,
580 .suspend = ata_scsi_device_suspend,
669a5db4
JG		 581};
582
583static const struct ata_port_operations sis_133_ops = {
584 .port_disable = ata_port_disable,
585 .set_piomode = sis_133_set_piomode,
586 .set_dmamode = sis_133_set_dmamode,
587 .mode_filter = ata_pci_default_filter,
588
589 .tf_load = ata_tf_load,
590 .tf_read = ata_tf_read,
591 .check_status = ata_check_status,
592 .exec_command = ata_exec_command,
593 .dev_select = ata_std_dev_select,
594
595 .freeze = ata_bmdma_freeze,
596 .thaw = ata_bmdma_thaw,
597 .error_handler = sis_133_error_handler,
598 .post_internal_cmd = ata_bmdma_post_internal_cmd,
599
600 .bmdma_setup = ata_bmdma_setup,
601 .bmdma_start = ata_bmdma_start,
602 .bmdma_stop = ata_bmdma_stop,
603 .bmdma_status = ata_bmdma_status,
604 .qc_prep = ata_qc_prep,
605 .qc_issue = ata_qc_issue_prot,
606 .data_xfer = ata_pio_data_xfer,
607
669a5db4
JG		 608 .irq_handler = ata_interrupt,
609 .irq_clear = ata_bmdma_irq_clear,
610
611 .port_start = ata_port_start,
669a5db4
JG		 612};
613
614static const struct ata_port_operations sis_133_early_ops = {
615 .port_disable = ata_port_disable,
616 .set_piomode = sis_100_set_piomode,
617 .set_dmamode = sis_133_early_set_dmamode,
618 .mode_filter = ata_pci_default_filter,
619
620 .tf_load = ata_tf_load,
621 .tf_read = ata_tf_read,
622 .check_status = ata_check_status,
623 .exec_command = ata_exec_command,
624 .dev_select = ata_std_dev_select,
625
626 .freeze = ata_bmdma_freeze,
627 .thaw = ata_bmdma_thaw,
628 .error_handler = sis_66_error_handler,
629 .post_internal_cmd = ata_bmdma_post_internal_cmd,
85cd7251 630
669a5db4
JG		 631 .bmdma_setup = ata_bmdma_setup,
632 .bmdma_start = ata_bmdma_start,
633 .bmdma_stop = ata_bmdma_stop,
634 .bmdma_status = ata_bmdma_status,
635 .qc_prep = ata_qc_prep,
636 .qc_issue = ata_qc_issue_prot,
637 .data_xfer = ata_pio_data_xfer,
638
669a5db4
JG		 639 .irq_handler = ata_interrupt,
640 .irq_clear = ata_bmdma_irq_clear,
641
642 .port_start = ata_port_start,
669a5db4
JG		 643};
644
645static const struct ata_port_operations sis_100_ops = {
646 .port_disable = ata_port_disable,
647 .set_piomode = sis_100_set_piomode,
648 .set_dmamode = sis_100_set_dmamode,
649 .mode_filter = ata_pci_default_filter,
650
651 .tf_load = ata_tf_load,
652 .tf_read = ata_tf_read,
653 .check_status = ata_check_status,
654 .exec_command = ata_exec_command,
655 .dev_select = ata_std_dev_select,
656
657 .freeze = ata_bmdma_freeze,
658 .thaw = ata_bmdma_thaw,
659 .error_handler = sis_66_error_handler,
660 .post_internal_cmd = ata_bmdma_post_internal_cmd,
85cd7251 661
669a5db4
JG		 662
663 .bmdma_setup = ata_bmdma_setup,
664 .bmdma_start = ata_bmdma_start,
665 .bmdma_stop = ata_bmdma_stop,
666 .bmdma_status = ata_bmdma_status,
667 .qc_prep = ata_qc_prep,
668 .qc_issue = ata_qc_issue_prot,
669 .data_xfer = ata_pio_data_xfer,
670
669a5db4
JG		 671 .irq_handler = ata_interrupt,
672 .irq_clear = ata_bmdma_irq_clear,
673
674 .port_start = ata_port_start,
669a5db4
JG		 675};
676
677static const struct ata_port_operations sis_66_ops = {
678 .port_disable = ata_port_disable,
679 .set_piomode = sis_old_set_piomode,
680 .set_dmamode = sis_66_set_dmamode,
681 .mode_filter = ata_pci_default_filter,
682
683 .tf_load = ata_tf_load,
684 .tf_read = ata_tf_read,
685 .check_status = ata_check_status,
686 .exec_command = ata_exec_command,
687 .dev_select = ata_std_dev_select,
688
689 .freeze = ata_bmdma_freeze,
690 .thaw = ata_bmdma_thaw,
691 .error_handler = sis_66_error_handler,
692 .post_internal_cmd = ata_bmdma_post_internal_cmd,
693
694 .bmdma_setup = ata_bmdma_setup,
695 .bmdma_start = ata_bmdma_start,
696 .bmdma_stop = ata_bmdma_stop,
697 .bmdma_status = ata_bmdma_status,
698 .qc_prep = ata_qc_prep,
699 .qc_issue = ata_qc_issue_prot,
700 .data_xfer = ata_pio_data_xfer,
701
669a5db4
JG		 702 .irq_handler = ata_interrupt,
703 .irq_clear = ata_bmdma_irq_clear,
704
705 .port_start = ata_port_start,
669a5db4
JG		 706};
707
708static const struct ata_port_operations sis_old_ops = {
709 .port_disable = ata_port_disable,
710 .set_piomode = sis_old_set_piomode,
711 .set_dmamode = sis_old_set_dmamode,
712 .mode_filter = ata_pci_default_filter,
713
714 .tf_load = ata_tf_load,
715 .tf_read = ata_tf_read,
716 .check_status = ata_check_status,
717 .exec_command = ata_exec_command,
718 .dev_select = ata_std_dev_select,
719
720 .freeze = ata_bmdma_freeze,
721 .thaw = ata_bmdma_thaw,
722 .error_handler = sis_old_error_handler,
723 .post_internal_cmd = ata_bmdma_post_internal_cmd,
724
725 .bmdma_setup = ata_bmdma_setup,
726 .bmdma_start = ata_bmdma_start,
727 .bmdma_stop = ata_bmdma_stop,
728 .bmdma_status = ata_bmdma_status,
729 .qc_prep = ata_qc_prep,
730 .qc_issue = ata_qc_issue_prot,
731 .data_xfer = ata_pio_data_xfer,
732
669a5db4
JG		 733 .irq_handler = ata_interrupt,
734 .irq_clear = ata_bmdma_irq_clear,
735
736 .port_start = ata_port_start,
669a5db4
JG		 737};
738
739static struct ata_port_info sis_info = {
740 .sht = &sis_sht,
741 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
742 .pio_mask = 0x1f, /* pio0-4 */
743 .mwdma_mask = 0x07,
744 .udma_mask = 0,
745 .port_ops = &sis_old_ops,
746};
747static struct ata_port_info sis_info33 = {
748 .sht = &sis_sht,
749 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
750 .pio_mask = 0x1f, /* pio0-4 */
751 .mwdma_mask = 0x07,
752 .udma_mask = ATA_UDMA2, /* UDMA 33 */
753 .port_ops = &sis_old_ops,
754};
755static struct ata_port_info sis_info66 = {
756 .sht = &sis_sht,
757 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
758 .pio_mask = 0x1f, /* pio0-4 */
759 .udma_mask = ATA_UDMA4, /* UDMA 66 */
760 .port_ops = &sis_66_ops,
761};
762static struct ata_port_info sis_info100 = {
763 .sht = &sis_sht,
764 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
765 .pio_mask = 0x1f, /* pio0-4 */
766 .udma_mask = ATA_UDMA5,
767 .port_ops = &sis_100_ops,
768};
769static struct ata_port_info sis_info100_early = {
770 .sht = &sis_sht,
771 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
772 .udma_mask = ATA_UDMA5,
773 .pio_mask = 0x1f, /* pio0-4 */
774 .port_ops = &sis_66_ops,
775};
77a527ea 776struct ata_port_info sis_info133 = {
669a5db4
JG		 777 .sht = &sis_sht,
778 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
779 .pio_mask = 0x1f, /* pio0-4 */
780 .udma_mask = ATA_UDMA6,
781 .port_ops = &sis_133_ops,
782};
783static struct ata_port_info sis_info133_early = {
784 .sht = &sis_sht,
785 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
786 .pio_mask = 0x1f, /* pio0-4 */
787 .udma_mask = ATA_UDMA6,
788 .port_ops = &sis_133_early_ops,
789};
790
9b14dec5
AC		 791/* Privately shared with the SiS180 SATA driver, not for use elsewhere */
792EXPORT_SYMBOL_GPL(sis_info133);
669a5db4
JG		 793
794static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
795{
796 u16 regw;
797 u8 reg;
798
799 if (sis->info == &sis_info133) {
800 pci_read_config_word(pdev, 0x50, &regw);
801 if (regw & 0x08)
802 pci_write_config_word(pdev, 0x50, regw & ~0x08);
803 pci_read_config_word(pdev, 0x52, &regw);
804 if (regw & 0x08)
805 pci_write_config_word(pdev, 0x52, regw & ~0x08);
806 return;
807 }
808
809 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
810 /* Fix up latency */
811 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
812 /* Set compatibility bit */
813 pci_read_config_byte(pdev, 0x49, &reg);
814 if (!(reg & 0x01))
815 pci_write_config_byte(pdev, 0x49, reg | 0x01);
816 return;
817 }
818
819 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
820 /* Fix up latency */
821 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
822 /* Set compatibility bit */
823 pci_read_config_byte(pdev, 0x52, &reg);
824 if (!(reg & 0x04))
825 pci_write_config_byte(pdev, 0x52, reg | 0x04);
826 return;
827 }
828
829 if (sis->info == &sis_info33) {
830 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
831 if (( reg & 0x0F ) != 0x00)
832 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
833 /* Fall through to ATA16 fixup below */
834 }
835
836 if (sis->info == &sis_info || sis->info == &sis_info33) {
837 /* force per drive recovery and active timings
838 needed on ATA_33 and below chips */
839 pci_read_config_byte(pdev, 0x52, &reg);
840 if (!(reg & 0x08))
841 pci_write_config_byte(pdev, 0x52, reg|0x08);
842 return;
843 }
844
845 BUG();
846}
847
848/**
849 * sis_init_one - Register SiS ATA PCI device with kernel services
850 * @pdev: PCI device to register
851 * @ent: Entry in sis_pci_tbl matching with @pdev
852 *
853 * Called from kernel PCI layer. We probe for combined mode (sigh),
854 * and then hand over control to libata, for it to do the rest.
855 *
856 * LOCKING:
857 * Inherited from PCI layer (may sleep).
858 *
859 * RETURNS:
860 * Zero on success, or -ERRNO value.
861 */
862
863static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
864{
865 static int printed_version;
866 static struct ata_port_info *port_info[2];
867 struct ata_port_info *port;
868 struct pci_dev *host = NULL;
869 struct sis_chipset *chipset = NULL;
870
871 static struct sis_chipset sis_chipsets[] = {
f20b16ff 872
af323a2f
AC		 873 { 0x0968, &sis_info133 },
874 { 0x0966, &sis_info133 },
875 { 0x0965, &sis_info133 },
669a5db4
JG		 876 { 0x0745, &sis_info100 },
877 { 0x0735, &sis_info100 },
878 { 0x0733, &sis_info100 },
879 { 0x0635, &sis_info100 },
880 { 0x0633, &sis_info100 },
881
882 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
883 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
884
885 { 0x0640, &sis_info66 },
886 { 0x0630, &sis_info66 },
887 { 0x0620, &sis_info66 },
888 { 0x0540, &sis_info66 },
889 { 0x0530, &sis_info66 },
890
891 { 0x5600, &sis_info33 },
892 { 0x5598, &sis_info33 },
893 { 0x5597, &sis_info33 },
894 { 0x5591, &sis_info33 },
895 { 0x5582, &sis_info33 },
896 { 0x5581, &sis_info33 },
897
898 { 0x5596, &sis_info },
899 { 0x5571, &sis_info },
900 { 0x5517, &sis_info },
901 { 0x5511, &sis_info },
902
903 {0}
904 };
905 static struct sis_chipset sis133_early = {
906 0x0, &sis_info133_early
907 };
908 static struct sis_chipset sis133 = {
909 0x0, &sis_info133
910 };
911 static struct sis_chipset sis100_early = {
912 0x0, &sis_info100_early
913 };
914 static struct sis_chipset sis100 = {
915 0x0, &sis_info100
916 };
917
918 if (!printed_version++)
919 dev_printk(KERN_DEBUG, &pdev->dev,
920 "version " DRV_VERSION "\n");
921
922 /* We have to find the bridge first */
923
924 for (chipset = &sis_chipsets[0]; chipset->device; chipset++) {
925 host = pci_get_device(PCI_VENDOR_ID_SI, chipset->device, NULL);
926 if (host != NULL) {
927 if (chipset->device == 0x630) { /* SIS630 */
928 u8 host_rev;
929 pci_read_config_byte(host, PCI_REVISION_ID, &host_rev);
930 if (host_rev >= 0x30) /* 630 ET */
931 chipset = &sis100_early;
932 }
933 break;
934 }
935 }
936
937 /* Look for concealed bridges */
938 if (host == NULL) {
939 /* Second check */
940 u32 idemisc;
941 u16 trueid;
942
943 /* Disable ID masking and register remapping then
944 see what the real ID is */
945
946 pci_read_config_dword(pdev, 0x54, &idemisc);
947 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
948 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
949 pci_write_config_dword(pdev, 0x54, idemisc);
950
951 switch(trueid) {
952 case 0x5518: /* SIS 962/963 */
953 chipset = &sis133;
954 if ((idemisc & 0x40000000) == 0) {
955 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
956 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
957 }
958 break;
959 case 0x0180: /* SIS 965/965L */
960 chipset = &sis133;
961 break;
962 case 0x1180: /* SIS 966/966L */
963 chipset = &sis133;
964 break;
965 }
966 }
967
968 /* Further check */
969 if (chipset == NULL) {
970 struct pci_dev *lpc_bridge;
971 u16 trueid;
972 u8 prefctl;
973 u8 idecfg;
974 u8 sbrev;
975
976 /* Try the second unmasking technique */
977 pci_read_config_byte(pdev, 0x4a, &idecfg);
978 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
979 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
980 pci_write_config_byte(pdev, 0x4a, idecfg);
981
982 switch(trueid) {
983 case 0x5517:
984 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
985 if (lpc_bridge == NULL)
986 break;
987 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
988 pci_read_config_byte(pdev, 0x49, &prefctl);
989 pci_dev_put(lpc_bridge);
990
991 if (sbrev == 0x10 && (prefctl & 0x80)) {
992 chipset = &sis133_early;
993 break;
994 }
995 chipset = &sis100;
996 break;
997 }
998 }
999 pci_dev_put(host);
1000
1001 /* No chipset info, no support */
1002 if (chipset == NULL)
1003 return -ENODEV;
1004
1005 port = chipset->info;
1006 port->private_data = chipset;
1007
1008 sis_fixup(pdev, chipset);
1009
1010 port_info[0] = port_info[1] = port;
1011 return ata_pci_init_one(pdev, port_info, 2);
1012}
1013
1014static const struct pci_device_id sis_pci_tbl[] = {
2d2744fc
JG		 1015 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
1016 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
1017
669a5db4
JG		 1018 { }
1019};
1020
1021static struct pci_driver sis_pci_driver = {
1022 .name = DRV_NAME,
1023 .id_table = sis_pci_tbl,
1024 .probe = sis_init_one,
1025 .remove = ata_pci_remove_one,
62d64ae0
AC		 1026 .suspend = ata_pci_device_suspend,
1027 .resume = ata_pci_device_resume,
669a5db4
JG		 1028};
1029
1030static int __init sis_init(void)
1031{
1032 return pci_register_driver(&sis_pci_driver);
1033}
1034
1035static void __exit sis_exit(void)
1036{
1037 pci_unregister_driver(&sis_pci_driver);
1038}
1039
669a5db4
JG		 1040module_init(sis_init);
1041module_exit(sis_exit);
1042
1043MODULE_AUTHOR("Alan Cox");
1044MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1045MODULE_LICENSE("GPL");
1046MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1047MODULE_VERSION(DRV_VERSION);
1048