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libata: implement and use ata_port_desc() to report port configuration
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_scc.c
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a619f981
AI		 1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
12 *
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
15 *
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/device.h>
42#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44
45#define DRV_NAME "pata_scc"
2a3103ce 46#define DRV_VERSION "0.3"
a619f981
AI		 47
48#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
49
50/* PCI BARs */
51#define SCC_CTRL_BAR 0
52#define SCC_BMID_BAR 1
53
54/* offset of CTRL registers */
55#define SCC_CTL_PIOSHT 0x000
56#define SCC_CTL_PIOCT 0x004
57#define SCC_CTL_MDMACT 0x008
58#define SCC_CTL_MCRCST 0x00C
59#define SCC_CTL_SDMACT 0x010
60#define SCC_CTL_SCRCST 0x014
61#define SCC_CTL_UDENVT 0x018
62#define SCC_CTL_TDVHSEL 0x020
63#define SCC_CTL_MODEREG 0x024
64#define SCC_CTL_ECMODE 0xF00
65#define SCC_CTL_MAEA0 0xF50
66#define SCC_CTL_MAEC0 0xF54
67#define SCC_CTL_CCKCTRL 0xFF0
68
69/* offset of BMID registers */
70#define SCC_DMA_CMD 0x000
71#define SCC_DMA_STATUS 0x004
72#define SCC_DMA_TABLE_OFS 0x008
73#define SCC_DMA_INTMASK 0x010
74#define SCC_DMA_INTST 0x014
75#define SCC_DMA_PTERADD 0x018
76#define SCC_REG_CMD_ADDR 0x020
77#define SCC_REG_DATA 0x000
78#define SCC_REG_ERR 0x004
79#define SCC_REG_FEATURE 0x004
80#define SCC_REG_NSECT 0x008
81#define SCC_REG_LBAL 0x00C
82#define SCC_REG_LBAM 0x010
83#define SCC_REG_LBAH 0x014
84#define SCC_REG_DEVICE 0x018
85#define SCC_REG_STATUS 0x01C
86#define SCC_REG_CMD 0x01C
87#define SCC_REG_ALTSTATUS 0x020
88
89/* register value */
90#define TDVHSEL_MASTER 0x00000001
91#define TDVHSEL_SLAVE 0x00000004
92
93#define MODE_JCUSFEN 0x00000080
94
95#define ECMODE_VALUE 0x01
96
97#define CCKCTRL_ATARESET 0x00040000
98#define CCKCTRL_BUFCNT 0x00020000
99#define CCKCTRL_CRST 0x00010000
100#define CCKCTRL_OCLKEN 0x00000100
101#define CCKCTRL_ATACLKOEN 0x00000002
102#define CCKCTRL_LCLKEN 0x00000001
103
104#define QCHCD_IOS_SS 0x00000001
105
106#define QCHSD_STPDIAG 0x00020000
107
108#define INTMASK_MSK 0xD1000012
109#define INTSTS_SERROR 0x80000000
110#define INTSTS_PRERR 0x40000000
111#define INTSTS_RERR 0x10000000
112#define INTSTS_ICERR 0x01000000
113#define INTSTS_BMSINT 0x00000010
114#define INTSTS_BMHE 0x00000008
115#define INTSTS_IOIRQS 0x00000004
116#define INTSTS_INTRQ 0x00000002
117#define INTSTS_ACTEINT 0x00000001
118
119
120/* PIO transfer mode table */
121/* JCHST */
122static const unsigned long JCHSTtbl[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
125};
126
127/* JCHHT */
128static const unsigned long JCHHTtbl[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
131};
132
133/* JCHCT */
134static const unsigned long JCHCTtbl[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
137};
138
139/* DMA transfer mode table */
140/* JCHDCTM/JCHDCTS */
141static const unsigned long JCHDCTxtbl[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
144};
145
146/* JCSTWTM/JCSTWTS */
147static const unsigned long JCSTWTxtbl[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
150};
151
152/* JCTSS */
153static const unsigned long JCTSStbl[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
156};
157
158/* JCENVT */
159static const unsigned long JCENVTtbl[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
162};
163
164/* JCACTSELS/JCACTSELM */
165static const unsigned long JCACTSELtbl[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
168};
169
170static const struct pci_device_id scc_pci_tbl[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 { } /* terminate list */
174};
175
176/**
177 * scc_set_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
179 * @adev: um
180 *
181 * Set PIO mode for device.
182 *
183 * LOCKING:
184 * None (inherited from caller).
185 */
186
187static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
188{
189 unsigned int pio = adev->pio_mode - XFER_PIO_0;
190 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
191 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
192 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
193 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
194 unsigned long reg;
195 int offset;
196
197 reg = in_be32(cckctrl_port);
198 if (reg & CCKCTRL_ATACLKOEN)
199 offset = 1; /* 133MHz */
200 else
201 offset = 0; /* 100MHz */
202
203 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
204 out_be32(piosht_port, reg);
205 reg = JCHCTtbl[offset][pio];
206 out_be32(pioct_port, reg);
207}
208
209/**
210 * scc_set_dmamode - Initialize host controller PATA DMA timings
211 * @ap: Port whose timings we are configuring
212 * @adev: um
213 * @udma: udma mode, 0 - 6
214 *
215 * Set UDMA mode for device.
216 *
217 * LOCKING:
218 * None (inherited from caller).
219 */
220
221static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
222{
223 unsigned int udma = adev->dma_mode;
224 unsigned int is_slave = (adev->devno != 0);
225 u8 speed = udma;
226 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
227 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
228 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
229 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
230 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
231 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
232 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
233 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
234 int offset, idx;
235
a84471fe 236 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
a619f981
AI		 237 offset = 1; /* 133MHz */
238 else
239 offset = 0; /* 100MHz */
240
241 if (speed >= XFER_UDMA_0)
242 idx = speed - XFER_UDMA_0;
243 else
244 return;
245
246 if (is_slave) {
247 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
248 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
249 out_be32(tdvhsel_port,
250 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
251 } else {
252 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
253 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
254 out_be32(tdvhsel_port,
255 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
256 }
257 out_be32(udenvt_port,
258 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
259}
260
dcd03447
AI		 261unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
262{
263 /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
264 if (adev->class == ATA_DEV_ATAPI &&
265 (mask & (0xE0 << ATA_SHIFT_UDMA))) {
266 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
267 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
268 }
269 return ata_pci_default_filter(adev, mask);
270}
271
a619f981
AI		 272/**
273 * scc_tf_load - send taskfile registers to host controller
274 * @ap: Port to which output is sent
275 * @tf: ATA taskfile register set
276 *
277 * Note: Original code is ata_tf_load().
278 */
279
280static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
281{
282 struct ata_ioports *ioaddr = &ap->ioaddr;
283 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
284
285 if (tf->ctl != ap->last_ctl) {
286 out_be32(ioaddr->ctl_addr, tf->ctl);
287 ap->last_ctl = tf->ctl;
288 ata_wait_idle(ap);
289 }
290
291 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
292 out_be32(ioaddr->feature_addr, tf->hob_feature);
293 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
294 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
295 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
296 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
297 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
298 tf->hob_feature,
299 tf->hob_nsect,
300 tf->hob_lbal,
301 tf->hob_lbam,
302 tf->hob_lbah);
303 }
304
305 if (is_addr) {
306 out_be32(ioaddr->feature_addr, tf->feature);
307 out_be32(ioaddr->nsect_addr, tf->nsect);
308 out_be32(ioaddr->lbal_addr, tf->lbal);
309 out_be32(ioaddr->lbam_addr, tf->lbam);
310 out_be32(ioaddr->lbah_addr, tf->lbah);
311 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
312 tf->feature,
313 tf->nsect,
314 tf->lbal,
315 tf->lbam,
316 tf->lbah);
317 }
318
319 if (tf->flags & ATA_TFLAG_DEVICE) {
320 out_be32(ioaddr->device_addr, tf->device);
321 VPRINTK("device 0x%X\n", tf->device);
322 }
323
324 ata_wait_idle(ap);
325}
326
327/**
328 * scc_check_status - Read device status reg & clear interrupt
329 * @ap: port where the device is
330 *
331 * Note: Original code is ata_check_status().
332 */
333
334static u8 scc_check_status (struct ata_port *ap)
335{
336 return in_be32(ap->ioaddr.status_addr);
337}
338
339/**
340 * scc_tf_read - input device's ATA taskfile shadow registers
341 * @ap: Port from which input is read
342 * @tf: ATA taskfile register set for storing input
343 *
344 * Note: Original code is ata_tf_read().
345 */
346
347static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
348{
349 struct ata_ioports *ioaddr = &ap->ioaddr;
350
351 tf->command = scc_check_status(ap);
352 tf->feature = in_be32(ioaddr->error_addr);
353 tf->nsect = in_be32(ioaddr->nsect_addr);
354 tf->lbal = in_be32(ioaddr->lbal_addr);
355 tf->lbam = in_be32(ioaddr->lbam_addr);
356 tf->lbah = in_be32(ioaddr->lbah_addr);
357 tf->device = in_be32(ioaddr->device_addr);
358
359 if (tf->flags & ATA_TFLAG_LBA48) {
360 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
361 tf->hob_feature = in_be32(ioaddr->error_addr);
362 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
363 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
364 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
365 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
fe36cb53
PV		 366 out_be32(ioaddr->ctl_addr, tf->ctl);
367 ap->last_ctl = tf->ctl;
a619f981
AI		 368 }
369}
370
371/**
372 * scc_exec_command - issue ATA command to host controller
373 * @ap: port to which command is being issued
374 * @tf: ATA taskfile register set
375 *
376 * Note: Original code is ata_exec_command().
377 */
378
379static void scc_exec_command (struct ata_port *ap,
380 const struct ata_taskfile *tf)
381{
878d4fed 382 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
a619f981
AI		 383
384 out_be32(ap->ioaddr.command_addr, tf->command);
385 ata_pause(ap);
386}
387
388/**
389 * scc_check_altstatus - Read device alternate status reg
390 * @ap: port where the device is
391 */
392
393static u8 scc_check_altstatus (struct ata_port *ap)
394{
395 return in_be32(ap->ioaddr.altstatus_addr);
396}
397
398/**
399 * scc_std_dev_select - Select device 0/1 on ATA bus
400 * @ap: ATA channel to manipulate
401 * @device: ATA device (numbered from zero) to select
402 *
403 * Note: Original code is ata_std_dev_select().
404 */
405
406static void scc_std_dev_select (struct ata_port *ap, unsigned int device)
407{
408 u8 tmp;
409
410 if (device == 0)
411 tmp = ATA_DEVICE_OBS;
412 else
413 tmp = ATA_DEVICE_OBS | ATA_DEV1;
414
415 out_be32(ap->ioaddr.device_addr, tmp);
416 ata_pause(ap);
417}
418
419/**
420 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
421 * @qc: Info associated with this ATA transaction.
422 *
423 * Note: Original code is ata_bmdma_setup().
424 */
425
426static void scc_bmdma_setup (struct ata_queued_cmd *qc)
427{
428 struct ata_port *ap = qc->ap;
429 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
430 u8 dmactl;
431 void __iomem *mmio = ap->ioaddr.bmdma_addr;
432
433 /* load PRD table addr */
434 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->prd_dma);
435
436 /* specify data direction, triple-check start bit is clear */
437 dmactl = in_be32(mmio + SCC_DMA_CMD);
438 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
439 if (!rw)
440 dmactl |= ATA_DMA_WR;
441 out_be32(mmio + SCC_DMA_CMD, dmactl);
442
443 /* issue r/w command */
444 ap->ops->exec_command(ap, &qc->tf);
445}
446
447/**
448 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
449 * @qc: Info associated with this ATA transaction.
450 *
451 * Note: Original code is ata_bmdma_start().
452 */
453
454static void scc_bmdma_start (struct ata_queued_cmd *qc)
455{
456 struct ata_port *ap = qc->ap;
457 u8 dmactl;
458 void __iomem *mmio = ap->ioaddr.bmdma_addr;
459
460 /* start host DMA transaction */
461 dmactl = in_be32(mmio + SCC_DMA_CMD);
462 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
463}
464
465/**
466 * scc_devchk - PATA device presence detection
467 * @ap: ATA channel to examine
468 * @device: Device to examine (starting at zero)
469 *
470 * Note: Original code is ata_devchk().
471 */
472
473static unsigned int scc_devchk (struct ata_port *ap,
474 unsigned int device)
475{
476 struct ata_ioports *ioaddr = &ap->ioaddr;
477 u8 nsect, lbal;
478
479 ap->ops->dev_select(ap, device);
480
481 out_be32(ioaddr->nsect_addr, 0x55);
482 out_be32(ioaddr->lbal_addr, 0xaa);
483
484 out_be32(ioaddr->nsect_addr, 0xaa);
485 out_be32(ioaddr->lbal_addr, 0x55);
486
487 out_be32(ioaddr->nsect_addr, 0x55);
488 out_be32(ioaddr->lbal_addr, 0xaa);
489
490 nsect = in_be32(ioaddr->nsect_addr);
491 lbal = in_be32(ioaddr->lbal_addr);
492
493 if ((nsect == 0x55) && (lbal == 0xaa))
494 return 1; /* we found a device */
495
496 return 0; /* nothing found */
497}
498
499/**
500 * scc_bus_post_reset - PATA device post reset
501 *
502 * Note: Original code is ata_bus_post_reset().
503 */
504
7e068376
TB		 505static int scc_bus_post_reset(struct ata_port *ap, unsigned int devmask,
506 unsigned long deadline)
a619f981
AI		 507{
508 struct ata_ioports *ioaddr = &ap->ioaddr;
509 unsigned int dev0 = devmask & (1 << 0);
510 unsigned int dev1 = devmask & (1 << 1);
7e068376 511 int rc;
a619f981
AI		 512
513 /* if device 0 was found in ata_devchk, wait for its
514 * BSY bit to clear
515 */
7e068376
TB		 516 if (dev0) {
517 rc = ata_wait_ready(ap, deadline);
518 if (rc && rc != -ENODEV)
519 return rc;
520 }
a619f981
AI		 521
522 /* if device 1 was found in ata_devchk, wait for
523 * register access, then wait for BSY to clear
524 */
a619f981
AI		 525 while (dev1) {
526 u8 nsect, lbal;
527
528 ap->ops->dev_select(ap, 1);
529 nsect = in_be32(ioaddr->nsect_addr);
530 lbal = in_be32(ioaddr->lbal_addr);
531 if ((nsect == 1) && (lbal == 1))
532 break;
7e068376
TB		 533 if (time_after(jiffies, deadline))
534 return -EBUSY;
a619f981
AI		 535 msleep(50); /* give drive a breather */
536 }
7e068376
TB		 537 if (dev1) {
538 rc = ata_wait_ready(ap, deadline);
539 if (rc && rc != -ENODEV)
540 return rc;
541 }
a619f981
AI		 542
543 /* is all this really necessary? */
544 ap->ops->dev_select(ap, 0);
545 if (dev1)
546 ap->ops->dev_select(ap, 1);
547 if (dev0)
548 ap->ops->dev_select(ap, 0);
7e068376
TB		 549
550 return 0;
a619f981
AI		 551}
552
553/**
554 * scc_bus_softreset - PATA device software reset
555 *
556 * Note: Original code is ata_bus_softreset().
557 */
558
7e068376
TB		 559static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
560 unsigned long deadline)
a619f981
AI		 561{
562 struct ata_ioports *ioaddr = &ap->ioaddr;
563
878d4fed 564 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
a619f981
AI		 565
566 /* software reset. causes dev0 to be selected */
567 out_be32(ioaddr->ctl_addr, ap->ctl);
568 udelay(20);
569 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
570 udelay(20);
571 out_be32(ioaddr->ctl_addr, ap->ctl);
572
573 /* spec mandates ">= 2ms" before checking status.
574 * We wait 150ms, because that was the magic delay used for
575 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
576 * between when the ATA command register is written, and then
577 * status is checked. Because waiting for "a while" before
578 * checking status is fine, post SRST, we perform this magic
579 * delay here as well.
580 *
581 * Old drivers/ide uses the 2mS rule and then waits for ready
582 */
583 msleep(150);
584
585 /* Before we perform post reset processing we want to see if
586 * the bus shows 0xFF because the odd clown forgets the D7
587 * pulldown resistor.
588 */
589 if (scc_check_status(ap) == 0xFF)
590 return 0;
591
7e068376 592 scc_bus_post_reset(ap, devmask, deadline);
a619f981
AI		 593
594 return 0;
595}
596
597/**
598 * scc_std_softreset - reset host port via ATA SRST
599 * @ap: port to reset
600 * @classes: resulting classes of attached devices
7e068376 601 * @deadline: deadline jiffies for the operation
a619f981
AI		 602 *
603 * Note: Original code is ata_std_softreset().
604 */
605
7e068376
TB		 606static int scc_std_softreset (struct ata_port *ap, unsigned int *classes,
607 unsigned long deadline)
a619f981
AI		 608{
609 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
610 unsigned int devmask = 0, err_mask;
611 u8 err;
612
613 DPRINTK("ENTER\n");
614
936fd732 615 if (ata_link_offline(&ap->link)) {
a619f981
AI		 616 classes[0] = ATA_DEV_NONE;
617 goto out;
618 }
619
620 /* determine if device 0/1 are present */
621 if (scc_devchk(ap, 0))
622 devmask |= (1 << 0);
623 if (slave_possible && scc_devchk(ap, 1))
624 devmask |= (1 << 1);
625
626 /* select device 0 again */
627 ap->ops->dev_select(ap, 0);
628
629 /* issue bus reset */
630 DPRINTK("about to softreset, devmask=%x\n", devmask);
7e068376 631 err_mask = scc_bus_softreset(ap, devmask, deadline);
a619f981
AI		 632 if (err_mask) {
633 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
634 err_mask);
635 return -EIO;
636 }
637
638 /* determine by signature whether we have ATA or ATAPI devices */
639 classes[0] = ata_dev_try_classify(ap, 0, &err);
640 if (slave_possible && err != 0x81)
641 classes[1] = ata_dev_try_classify(ap, 1, &err);
642
643 out:
644 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
645 return 0;
646}
647
648/**
649 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
650 * @qc: Command we are ending DMA for
651 */
652
653static void scc_bmdma_stop (struct ata_queued_cmd *qc)
654{
655 struct ata_port *ap = qc->ap;
656 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
657 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
658 u32 reg;
659
660 while (1) {
661 reg = in_be32(bmid_base + SCC_DMA_INTST);
662
663 if (reg & INTSTS_SERROR) {
664 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
665 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
666 out_be32(bmid_base + SCC_DMA_CMD,
667 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
668 continue;
669 }
670
671 if (reg & INTSTS_PRERR) {
672 u32 maea0, maec0;
673 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
674 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
675 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
676 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
677 out_be32(bmid_base + SCC_DMA_CMD,
678 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
679 continue;
680 }
681
682 if (reg & INTSTS_RERR) {
683 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
684 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
685 out_be32(bmid_base + SCC_DMA_CMD,
686 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
687 continue;
688 }
689
690 if (reg & INTSTS_ICERR) {
691 out_be32(bmid_base + SCC_DMA_CMD,
692 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
693 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
694 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
695 continue;
696 }
697
698 if (reg & INTSTS_BMSINT) {
699 unsigned int classes;
7e068376 700 unsigned long deadline = jiffies + ATA_TMOUT_BOOT;
a619f981
AI		 701 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
702 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
703 /* TBD: SW reset */
7e068376 704 scc_std_softreset(ap, &classes, deadline);
a619f981
AI		 705 continue;
706 }
707
708 if (reg & INTSTS_BMHE) {
709 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
710 continue;
711 }
712
713 if (reg & INTSTS_ACTEINT) {
714 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
715 continue;
716 }
717
718 if (reg & INTSTS_IOIRQS) {
719 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
720 continue;
721 }
722 break;
723 }
724
725 /* clear start/stop bit */
726 out_be32(bmid_base + SCC_DMA_CMD,
727 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
728
729 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
730 ata_altstatus(ap); /* dummy read */
731}
732
733/**
734 * scc_bmdma_status - Read PCI IDE BMDMA status
735 * @ap: Port associated with this ATA transaction.
736 */
737
738static u8 scc_bmdma_status (struct ata_port *ap)
739{
a619f981 740 void __iomem *mmio = ap->ioaddr.bmdma_addr;
fae57d34
AI		 741 u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
742 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
743 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
744 static int retry = 0;
745
746 /* return if IOS_SS is cleared */
747 if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
748 return host_stat;
749
750 /* errata A252,A308 workaround: Step4 */
dcd03447 751 if ((ata_altstatus(ap) & ATA_ERR) && (int_status & INTSTS_INTRQ))
fae57d34
AI		 752 return (host_stat | ATA_DMA_INTR);
753
754 /* errata A308 workaround Step5 */
755 if (int_status & INTSTS_IOIRQS) {
756 host_stat |= ATA_DMA_INTR;
757
758 /* We don't check ATAPI DMA because it is limited to UDMA4 */
759 if ((qc->tf.protocol == ATA_PROT_DMA &&
760 qc->dev->xfer_mode > XFER_UDMA_4)) {
761 if (!(int_status & INTSTS_ACTEINT)) {
dcd03447
AI		 762 printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
763 ap->print_id);
fae57d34
AI		 764 host_stat |= ATA_DMA_ERR;
765 if (retry++)
dcd03447 766 ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
fae57d34
AI		 767 } else
768 retry = 0;
769 }
a619f981
AI		 770 }
771
772 return host_stat;
773}
774
775/**
776 * scc_data_xfer - Transfer data by PIO
777 * @adev: device for this I/O
778 * @buf: data buffer
779 * @buflen: buffer length
780 * @write_data: read/write
781 *
782 * Note: Original code is ata_data_xfer().
783 */
784
785static void scc_data_xfer (struct ata_device *adev, unsigned char *buf,
786 unsigned int buflen, int write_data)
787{
9af5c9c9 788 struct ata_port *ap = adev->link->ap;
a619f981
AI		 789 unsigned int words = buflen >> 1;
790 unsigned int i;
791 u16 *buf16 = (u16 *) buf;
792 void __iomem *mmio = ap->ioaddr.data_addr;
793
794 /* Transfer multiple of 2 bytes */
795 if (write_data) {
796 for (i = 0; i < words; i++)
797 out_be32(mmio, cpu_to_le16(buf16[i]));
798 } else {
799 for (i = 0; i < words; i++)
800 buf16[i] = le16_to_cpu(in_be32(mmio));
801 }
802
803 /* Transfer trailing 1 byte, if any. */
804 if (unlikely(buflen & 0x01)) {
805 u16 align_buf[1] = { 0 };
806 unsigned char *trailing_buf = buf + buflen - 1;
807
808 if (write_data) {
809 memcpy(align_buf, trailing_buf, 1);
810 out_be32(mmio, cpu_to_le16(align_buf[0]));
811 } else {
812 align_buf[0] = le16_to_cpu(in_be32(mmio));
813 memcpy(trailing_buf, align_buf, 1);
814 }
815 }
816}
817
818/**
819 * scc_irq_on - Enable interrupts on a port.
820 * @ap: Port on which interrupts are enabled.
821 *
822 * Note: Original code is ata_irq_on().
823 */
824
825static u8 scc_irq_on (struct ata_port *ap)
826{
827 struct ata_ioports *ioaddr = &ap->ioaddr;
828 u8 tmp;
829
830 ap->ctl &= ~ATA_NIEN;
831 ap->last_ctl = ap->ctl;
832
833 out_be32(ioaddr->ctl_addr, ap->ctl);
834 tmp = ata_wait_idle(ap);
835
836 ap->ops->irq_clear(ap);
837
838 return tmp;
839}
840
a619f981
AI		 841/**
842 * scc_bmdma_freeze - Freeze BMDMA controller port
843 * @ap: port to freeze
844 *
845 * Note: Original code is ata_bmdma_freeze().
846 */
847
848static void scc_bmdma_freeze (struct ata_port *ap)
849{
850 struct ata_ioports *ioaddr = &ap->ioaddr;
851
852 ap->ctl |= ATA_NIEN;
853 ap->last_ctl = ap->ctl;
854
855 out_be32(ioaddr->ctl_addr, ap->ctl);
856
857 /* Under certain circumstances, some controllers raise IRQ on
858 * ATA_NIEN manipulation. Also, many controllers fail to mask
859 * previously pending IRQ on ATA_NIEN assertion. Clear it.
860 */
861 ata_chk_status(ap);
862
863 ap->ops->irq_clear(ap);
864}
865
866/**
867 * scc_pata_prereset - prepare for reset
868 * @ap: ATA port to be reset
7e068376 869 * @deadline: deadline jiffies for the operation
a619f981
AI		 870 */
871
7e068376 872static int scc_pata_prereset(struct ata_port *ap, unsigned long deadline)
a619f981
AI		 873{
874 ap->cbl = ATA_CBL_PATA80;
d1c68fa6 875 return ata_std_prereset(ap, deadline);
a619f981
AI		 876}
877
878/**
879 * scc_std_postreset - standard postreset callback
880 * @ap: the target ata_port
881 * @classes: classes of attached devices
882 *
883 * Note: Original code is ata_std_postreset().
884 */
885
886static void scc_std_postreset (struct ata_port *ap, unsigned int *classes)
887{
888 DPRINTK("ENTER\n");
889
a619f981
AI		 890 /* is double-select really necessary? */
891 if (classes[0] != ATA_DEV_NONE)
892 ap->ops->dev_select(ap, 1);
893 if (classes[1] != ATA_DEV_NONE)
894 ap->ops->dev_select(ap, 0);
895
896 /* bail out if no device is present */
897 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
898 DPRINTK("EXIT, no device\n");
899 return;
900 }
901
902 /* set up device control */
903 if (ap->ioaddr.ctl_addr)
904 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
905
906 DPRINTK("EXIT\n");
907}
908
909/**
910 * scc_error_handler - Stock error handler for BMDMA controller
911 * @ap: port to handle error for
912 */
913
914static void scc_error_handler (struct ata_port *ap)
915{
916 ata_bmdma_drive_eh(ap, scc_pata_prereset, scc_std_softreset, NULL,
917 scc_std_postreset);
918}
919
920/**
921 * scc_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
922 * @ap: Port associated with this ATA transaction.
923 *
924 * Note: Original code is ata_bmdma_irq_clear().
925 */
926
927static void scc_bmdma_irq_clear (struct ata_port *ap)
928{
929 void __iomem *mmio = ap->ioaddr.bmdma_addr;
930
931 if (!mmio)
932 return;
933
934 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
935}
936
937/**
938 * scc_port_start - Set port up for dma.
939 * @ap: Port to initialize
940 *
941 * Allocate space for PRD table using ata_port_start().
942 * Set PRD table address for PTERADD. (PRD Transfer End Read)
943 */
944
945static int scc_port_start (struct ata_port *ap)
946{
947 void __iomem *mmio = ap->ioaddr.bmdma_addr;
948 int rc;
949
950 rc = ata_port_start(ap);
951 if (rc)
952 return rc;
953
954 out_be32(mmio + SCC_DMA_PTERADD, ap->prd_dma);
955 return 0;
956}
957
958/**
959 * scc_port_stop - Undo scc_port_start()
960 * @ap: Port to shut down
961 *
962 * Reset PTERADD.
963 */
964
965static void scc_port_stop (struct ata_port *ap)
966{
967 void __iomem *mmio = ap->ioaddr.bmdma_addr;
968
969 out_be32(mmio + SCC_DMA_PTERADD, 0);
970}
971
972static struct scsi_host_template scc_sht = {
973 .module = THIS_MODULE,
974 .name = DRV_NAME,
975 .ioctl = ata_scsi_ioctl,
976 .queuecommand = ata_scsi_queuecmd,
977 .can_queue = ATA_DEF_QUEUE,
978 .this_id = ATA_SHT_THIS_ID,
979 .sg_tablesize = LIBATA_MAX_PRD,
980 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
981 .emulated = ATA_SHT_EMULATED,
982 .use_clustering = ATA_SHT_USE_CLUSTERING,
983 .proc_name = DRV_NAME,
984 .dma_boundary = ATA_DMA_BOUNDARY,
985 .slave_configure = ata_scsi_slave_config,
986 .slave_destroy = ata_scsi_slave_destroy,
987 .bios_param = ata_std_bios_param,
a619f981
AI		 988};
989
990static const struct ata_port_operations scc_pata_ops = {
a619f981
AI		 991 .set_piomode = scc_set_piomode,
992 .set_dmamode = scc_set_dmamode,
dcd03447 993 .mode_filter = scc_mode_filter,
a619f981
AI		 994
995 .tf_load = scc_tf_load,
996 .tf_read = scc_tf_read,
997 .exec_command = scc_exec_command,
998 .check_status = scc_check_status,
999 .check_altstatus = scc_check_altstatus,
1000 .dev_select = scc_std_dev_select,
1001
1002 .bmdma_setup = scc_bmdma_setup,
1003 .bmdma_start = scc_bmdma_start,
1004 .bmdma_stop = scc_bmdma_stop,
1005 .bmdma_status = scc_bmdma_status,
1006 .data_xfer = scc_data_xfer,
1007
1008 .qc_prep = ata_qc_prep,
1009 .qc_issue = ata_qc_issue_prot,
1010
1011 .freeze = scc_bmdma_freeze,
1012 .error_handler = scc_error_handler,
1013 .post_internal_cmd = scc_bmdma_stop,
1014
a619f981
AI		 1015 .irq_clear = scc_bmdma_irq_clear,
1016 .irq_on = scc_irq_on,
a619f981
AI		 1017
1018 .port_start = scc_port_start,
1019 .port_stop = scc_port_stop,
1020};
1021
1022static struct ata_port_info scc_port_info[] = {
1023 {
a619f981
AI		 1024 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY,
1025 .pio_mask = 0x1f, /* pio0-4 */
1026 .mwdma_mask = 0x00,
1027 .udma_mask = ATA_UDMA6,
1028 .port_ops = &scc_pata_ops,
1029 },
1030};
1031
1032/**
1033 * scc_reset_controller - initialize SCC PATA controller.
1034 */
1035
5d728824 1036static int scc_reset_controller(struct ata_host *host)
a619f981 1037{
5d728824
TH		 1038 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
1039 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
a619f981
AI		 1040 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
1041 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
1042 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
1043 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
1044 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
1045 u32 reg = 0;
1046
1047 out_be32(cckctrl_port, reg);
1048 reg |= CCKCTRL_ATACLKOEN;
1049 out_be32(cckctrl_port, reg);
1050 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
1051 out_be32(cckctrl_port, reg);
1052 reg |= CCKCTRL_CRST;
1053 out_be32(cckctrl_port, reg);
1054
1055 for (;;) {
1056 reg = in_be32(cckctrl_port);
1057 if (reg & CCKCTRL_CRST)
1058 break;
1059 udelay(5000);
1060 }
1061
1062 reg |= CCKCTRL_ATARESET;
1063 out_be32(cckctrl_port, reg);
1064 out_be32(ecmode_port, ECMODE_VALUE);
1065 out_be32(mode_port, MODE_JCUSFEN);
1066 out_be32(intmask_port, INTMASK_MSK);
1067
1068 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
1069 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
1070 return -EIO;
1071 }
1072
1073 return 0;
1074}
1075
1076/**
1077 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1078 * @ioaddr: IO address structure to be initialized
1079 * @base: base address of BMID region
1080 */
1081
1082static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1083{
1084 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1085 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1086 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1087 ioaddr->bmdma_addr = base;
1088 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1089 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1090 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1091 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1092 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1093 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1094 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1095 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1096 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1097 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1098}
1099
5d728824 1100static int scc_host_init(struct ata_host *host)
a619f981 1101{
5d728824 1102 struct pci_dev *pdev = to_pci_dev(host->dev);
a619f981
AI		 1103 int rc;
1104
5d728824 1105 rc = scc_reset_controller(host);
a619f981
AI		 1106 if (rc)
1107 return rc;
1108
a619f981
AI		 1109 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1110 if (rc)
1111 return rc;
1112 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1113 if (rc)
1114 return rc;
1115
5d728824 1116 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
a619f981
AI		 1117
1118 pci_set_master(pdev);
1119
1120 return 0;
1121}
1122
1123/**
1124 * scc_init_one - Register SCC PATA device with kernel services
1125 * @pdev: PCI device to register
1126 * @ent: Entry in scc_pci_tbl matching with @pdev
1127 *
1128 * LOCKING:
1129 * Inherited from PCI layer (may sleep).
1130 *
1131 * RETURNS:
1132 * Zero on success, or -ERRNO value.
1133 */
1134
1135static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1136{
1137 static int printed_version;
1138 unsigned int board_idx = (unsigned int) ent->driver_data;
5d728824 1139 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
0397bad5 1140 struct ata_host *host;
a619f981
AI		 1141 int rc;
1142
1143 if (!printed_version++)
1144 dev_printk(KERN_DEBUG, &pdev->dev,
1145 "version " DRV_VERSION "\n");
1146
0397bad5 1147 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
5d728824
TH		 1148 if (!host)
1149 return -ENOMEM;
1150
a619f981
AI		 1151 rc = pcim_enable_device(pdev);
1152 if (rc)
1153 return rc;
1154
1155 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1156 if (rc == -EBUSY)
1157 pcim_pin_device(pdev);
1158 if (rc)
1159 return rc;
5d728824 1160 host->iomap = pcim_iomap_table(pdev);
a619f981 1161
cbcdd875
TH		 1162 ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
1163 ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
1164
5d728824 1165 rc = scc_host_init(host);
a619f981
AI		 1166 if (rc)
1167 return rc;
1168
5d728824
TH		 1169 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
1170 &scc_sht);
a619f981
AI		 1171}
1172
1173static struct pci_driver scc_pci_driver = {
1174 .name = DRV_NAME,
1175 .id_table = scc_pci_tbl,
1176 .probe = scc_init_one,
1177 .remove = ata_pci_remove_one,
1178#ifdef CONFIG_PM
1179 .suspend = ata_pci_device_suspend,
1180 .resume = ata_pci_device_resume,
1181#endif
1182};
1183
1184static int __init scc_init (void)
1185{
1186 int rc;
1187
1188 DPRINTK("pci_register_driver\n");
1189 rc = pci_register_driver(&scc_pci_driver);
1190 if (rc)
1191 return rc;
1192
1193 DPRINTK("done\n");
1194 return 0;
1195}
1196
1197static void __exit scc_exit (void)
1198{
1199 pci_unregister_driver(&scc_pci_driver);
1200}
1201
1202module_init(scc_init);
1203module_exit(scc_exit);
1204
1205MODULE_AUTHOR("Toshiba corp");
1206MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1207MODULE_LICENSE("GPL");
1208MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1209MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)