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155bf48f AK |
1 | /* |
2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * PATA driver for Samsung SoCs. | |
6 | * Supports CF Interface in True IDE mode. Currently only PIO mode has been | |
7 | * implemented; UDMA support has to be added. | |
8 | * | |
9 | * Based on: | |
10 | * PATA driver for AT91SAM9260 Static Memory Controller | |
11 | * PATA driver for Toshiba SCC controller | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License version 2 | |
15 | * as published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/libata.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | ||
436d42c6 | 26 | #include <linux/platform_data/ata-samsung_cf.h> |
155bf48f AK |
27 | |
28 | #define DRV_NAME "pata_samsung_cf" | |
29 | #define DRV_VERSION "0.1" | |
30 | ||
15e5318c SK |
31 | #define S3C_CFATA_REG(x) (x) |
32 | #define S3C_CFATA_MUX S3C_CFATA_REG(0x0) | |
33 | #define S3C_ATA_CTRL S3C_CFATA_REG(0x0) | |
15e5318c | 34 | #define S3C_ATA_CMD S3C_CFATA_REG(0x8) |
15e5318c SK |
35 | #define S3C_ATA_IRQ S3C_CFATA_REG(0x10) |
36 | #define S3C_ATA_IRQ_MSK S3C_CFATA_REG(0x14) | |
37 | #define S3C_ATA_CFG S3C_CFATA_REG(0x18) | |
38 | ||
15e5318c | 39 | #define S3C_ATA_PIO_TIME S3C_CFATA_REG(0x2c) |
15e5318c SK |
40 | #define S3C_ATA_PIO_DTR S3C_CFATA_REG(0x54) |
41 | #define S3C_ATA_PIO_FED S3C_CFATA_REG(0x58) | |
42 | #define S3C_ATA_PIO_SCR S3C_CFATA_REG(0x5c) | |
43 | #define S3C_ATA_PIO_LLR S3C_CFATA_REG(0x60) | |
44 | #define S3C_ATA_PIO_LMR S3C_CFATA_REG(0x64) | |
45 | #define S3C_ATA_PIO_LHR S3C_CFATA_REG(0x68) | |
46 | #define S3C_ATA_PIO_DVR S3C_CFATA_REG(0x6c) | |
47 | #define S3C_ATA_PIO_CSD S3C_CFATA_REG(0x70) | |
48 | #define S3C_ATA_PIO_DAD S3C_CFATA_REG(0x74) | |
15e5318c SK |
49 | #define S3C_ATA_PIO_RDATA S3C_CFATA_REG(0x7c) |
50 | ||
51 | #define S3C_CFATA_MUX_TRUEIDE 0x01 | |
52 | #define S3C_ATA_CFG_SWAP 0x40 | |
53 | #define S3C_ATA_CFG_IORDYEN 0x02 | |
54 | ||
155bf48f AK |
55 | enum s3c_cpu_type { |
56 | TYPE_S3C64XX, | |
57 | TYPE_S5PC100, | |
58 | TYPE_S5PV210, | |
59 | }; | |
60 | ||
61 | /* | |
62 | * struct s3c_ide_info - S3C PATA instance. | |
63 | * @clk: The clock resource for this controller. | |
64 | * @ide_addr: The area mapped for the hardware registers. | |
65 | * @sfr_addr: The area mapped for the special function registers. | |
66 | * @irq: The IRQ number we are using. | |
67 | * @cpu_type: The exact type of this controller. | |
68 | * @fifo_status_reg: The ATA_FIFO_STATUS register offset. | |
69 | */ | |
70 | struct s3c_ide_info { | |
71 | struct clk *clk; | |
72 | void __iomem *ide_addr; | |
73 | void __iomem *sfr_addr; | |
74 | unsigned int irq; | |
75 | enum s3c_cpu_type cpu_type; | |
76 | unsigned int fifo_status_reg; | |
77 | }; | |
78 | ||
79 | static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode) | |
80 | { | |
81 | u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG); | |
82 | reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP); | |
83 | writel(reg, s3c_ide_regbase + S3C_ATA_CFG); | |
84 | } | |
85 | ||
86 | static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase) | |
87 | { | |
88 | /* Select true-ide as the internal operating mode */ | |
89 | writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE, | |
90 | s3c_ide_sfrbase + S3C_CFATA_MUX); | |
91 | } | |
92 | ||
93 | static unsigned long | |
94 | pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata) | |
95 | { | |
96 | int t1 = ata->setup; | |
97 | int t2 = ata->act8b; | |
98 | int t2i = ata->rec8b; | |
99 | ulong piotime; | |
100 | ||
101 | piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf); | |
102 | ||
103 | return piotime; | |
104 | } | |
105 | ||
106 | static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
107 | { | |
108 | struct s3c_ide_info *info = ap->host->private_data; | |
109 | struct ata_timing timing; | |
110 | int cycle_time; | |
111 | ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG); | |
112 | ulong piotime; | |
113 | ||
114 | /* Enables IORDY if mode requires it */ | |
115 | if (ata_pio_need_iordy(adev)) | |
116 | ata_cfg |= S3C_ATA_CFG_IORDYEN; | |
117 | else | |
118 | ata_cfg &= ~S3C_ATA_CFG_IORDYEN; | |
119 | ||
120 | cycle_time = (int)(1000000000UL / clk_get_rate(info->clk)); | |
121 | ||
122 | ata_timing_compute(adev, adev->pio_mode, &timing, | |
123 | cycle_time * 1000, 0); | |
124 | ||
125 | piotime = pata_s3c_setup_timing(info, &timing); | |
126 | ||
127 | writel(ata_cfg, info->ide_addr + S3C_ATA_CFG); | |
128 | writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME); | |
129 | } | |
130 | ||
131 | /* | |
132 | * Waits until the IDE controller is able to perform next read/write | |
133 | * operation to the disk. Needed for 64XX series boards only. | |
134 | */ | |
135 | static int wait_for_host_ready(struct s3c_ide_info *info) | |
136 | { | |
137 | ulong timeout; | |
138 | void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg; | |
139 | ||
140 | /* wait for maximum of 20 msec */ | |
141 | timeout = jiffies + msecs_to_jiffies(20); | |
142 | while (time_before(jiffies, timeout)) { | |
143 | if ((readl(fifo_reg) >> 28) == 0) | |
144 | return 0; | |
145 | } | |
146 | return -EBUSY; | |
147 | } | |
148 | ||
149 | /* | |
150 | * Writes to one of the task file registers. | |
151 | */ | |
152 | static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg) | |
153 | { | |
154 | struct s3c_ide_info *info = host->private_data; | |
155 | ||
156 | wait_for_host_ready(info); | |
157 | writeb(addr, reg); | |
158 | } | |
159 | ||
160 | /* | |
161 | * Reads from one of the task file registers. | |
162 | */ | |
163 | static u8 ata_inb(struct ata_host *host, void __iomem *reg) | |
164 | { | |
165 | struct s3c_ide_info *info = host->private_data; | |
166 | u8 temp; | |
167 | ||
168 | wait_for_host_ready(info); | |
169 | (void) readb(reg); | |
170 | wait_for_host_ready(info); | |
171 | temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA); | |
172 | return temp; | |
173 | } | |
174 | ||
175 | /* | |
176 | * pata_s3c_tf_load - send taskfile registers to host controller | |
177 | */ | |
178 | static void pata_s3c_tf_load(struct ata_port *ap, | |
179 | const struct ata_taskfile *tf) | |
180 | { | |
181 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
182 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
183 | ||
184 | if (tf->ctl != ap->last_ctl) { | |
185 | ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr); | |
186 | ap->last_ctl = tf->ctl; | |
187 | ata_wait_idle(ap); | |
188 | } | |
189 | ||
190 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
191 | ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr); | |
192 | ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr); | |
193 | ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr); | |
194 | ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr); | |
195 | ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr); | |
196 | } | |
197 | ||
198 | if (is_addr) { | |
199 | ata_outb(ap->host, tf->feature, ioaddr->feature_addr); | |
200 | ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr); | |
201 | ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr); | |
202 | ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr); | |
203 | ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr); | |
204 | } | |
205 | ||
206 | if (tf->flags & ATA_TFLAG_DEVICE) | |
207 | ata_outb(ap->host, tf->device, ioaddr->device_addr); | |
208 | ||
209 | ata_wait_idle(ap); | |
210 | } | |
211 | ||
212 | /* | |
213 | * pata_s3c_tf_read - input device's ATA taskfile shadow registers | |
214 | */ | |
215 | static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
216 | { | |
217 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
218 | ||
219 | tf->feature = ata_inb(ap->host, ioaddr->error_addr); | |
220 | tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr); | |
221 | tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr); | |
222 | tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr); | |
223 | tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr); | |
224 | tf->device = ata_inb(ap->host, ioaddr->device_addr); | |
225 | ||
226 | if (tf->flags & ATA_TFLAG_LBA48) { | |
227 | ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
228 | tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr); | |
229 | tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr); | |
230 | tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr); | |
231 | tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr); | |
232 | tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr); | |
233 | ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr); | |
234 | ap->last_ctl = tf->ctl; | |
235 | } | |
236 | } | |
237 | ||
238 | /* | |
239 | * pata_s3c_exec_command - issue ATA command to host controller | |
240 | */ | |
241 | static void pata_s3c_exec_command(struct ata_port *ap, | |
242 | const struct ata_taskfile *tf) | |
243 | { | |
244 | ata_outb(ap->host, tf->command, ap->ioaddr.command_addr); | |
245 | ata_sff_pause(ap); | |
246 | } | |
247 | ||
248 | /* | |
249 | * pata_s3c_check_status - Read device status register | |
250 | */ | |
251 | static u8 pata_s3c_check_status(struct ata_port *ap) | |
252 | { | |
253 | return ata_inb(ap->host, ap->ioaddr.status_addr); | |
254 | } | |
255 | ||
256 | /* | |
257 | * pata_s3c_check_altstatus - Read alternate device status register | |
258 | */ | |
259 | static u8 pata_s3c_check_altstatus(struct ata_port *ap) | |
260 | { | |
261 | return ata_inb(ap->host, ap->ioaddr.altstatus_addr); | |
262 | } | |
263 | ||
264 | /* | |
265 | * pata_s3c_data_xfer - Transfer data by PIO | |
266 | */ | |
3d70a363 JH |
267 | static unsigned int pata_s3c_data_xfer(struct ata_device *dev, |
268 | unsigned char *buf, unsigned int buflen, int rw) | |
155bf48f AK |
269 | { |
270 | struct ata_port *ap = dev->link->ap; | |
271 | struct s3c_ide_info *info = ap->host->private_data; | |
272 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
273 | unsigned int words = buflen >> 1, i; | |
274 | u16 *data_ptr = (u16 *)buf; | |
275 | ||
276 | /* Requires wait same as in ata_inb/ata_outb */ | |
277 | if (rw == READ) | |
278 | for (i = 0; i < words; i++, data_ptr++) { | |
279 | wait_for_host_ready(info); | |
280 | (void) readw(data_addr); | |
281 | wait_for_host_ready(info); | |
282 | *data_ptr = readw(info->ide_addr | |
283 | + S3C_ATA_PIO_RDATA); | |
284 | } | |
285 | else | |
286 | for (i = 0; i < words; i++, data_ptr++) { | |
287 | wait_for_host_ready(info); | |
288 | writew(*data_ptr, data_addr); | |
289 | } | |
290 | ||
291 | if (buflen & 0x01) | |
292 | dev_err(ap->dev, "unexpected trailing data\n"); | |
293 | ||
294 | return words << 1; | |
295 | } | |
296 | ||
297 | /* | |
298 | * pata_s3c_dev_select - Select device on ATA bus | |
299 | */ | |
300 | static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device) | |
301 | { | |
302 | u8 tmp = ATA_DEVICE_OBS; | |
303 | ||
304 | if (device != 0) | |
305 | tmp |= ATA_DEV1; | |
306 | ||
307 | ata_outb(ap->host, tmp, ap->ioaddr.device_addr); | |
308 | ata_sff_pause(ap); | |
309 | } | |
310 | ||
311 | /* | |
312 | * pata_s3c_devchk - PATA device presence detection | |
313 | */ | |
314 | static unsigned int pata_s3c_devchk(struct ata_port *ap, | |
315 | unsigned int device) | |
316 | { | |
317 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
318 | u8 nsect, lbal; | |
319 | ||
320 | pata_s3c_dev_select(ap, device); | |
321 | ||
322 | ata_outb(ap->host, 0x55, ioaddr->nsect_addr); | |
323 | ata_outb(ap->host, 0xaa, ioaddr->lbal_addr); | |
324 | ||
325 | ata_outb(ap->host, 0xaa, ioaddr->nsect_addr); | |
326 | ata_outb(ap->host, 0x55, ioaddr->lbal_addr); | |
327 | ||
328 | ata_outb(ap->host, 0x55, ioaddr->nsect_addr); | |
329 | ata_outb(ap->host, 0xaa, ioaddr->lbal_addr); | |
330 | ||
331 | nsect = ata_inb(ap->host, ioaddr->nsect_addr); | |
332 | lbal = ata_inb(ap->host, ioaddr->lbal_addr); | |
333 | ||
334 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
335 | return 1; /* we found a device */ | |
336 | ||
337 | return 0; /* nothing found */ | |
338 | } | |
339 | ||
340 | /* | |
341 | * pata_s3c_wait_after_reset - wait for devices to become ready after reset | |
342 | */ | |
343 | static int pata_s3c_wait_after_reset(struct ata_link *link, | |
344 | unsigned long deadline) | |
345 | { | |
346 | int rc; | |
347 | ||
97750ceb | 348 | ata_msleep(link->ap, ATA_WAIT_AFTER_RESET); |
155bf48f AK |
349 | |
350 | /* always check readiness of the master device */ | |
351 | rc = ata_sff_wait_ready(link, deadline); | |
352 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
353 | * and TF status is 0xff, bail out on it too. | |
354 | */ | |
355 | if (rc) | |
356 | return rc; | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | /* | |
362 | * pata_s3c_bus_softreset - PATA device software reset | |
363 | */ | |
364 | static unsigned int pata_s3c_bus_softreset(struct ata_port *ap, | |
365 | unsigned long deadline) | |
366 | { | |
367 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
368 | ||
369 | /* software reset. causes dev0 to be selected */ | |
370 | ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr); | |
371 | udelay(20); | |
372 | ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
373 | udelay(20); | |
374 | ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr); | |
375 | ap->last_ctl = ap->ctl; | |
376 | ||
377 | return pata_s3c_wait_after_reset(&ap->link, deadline); | |
378 | } | |
379 | ||
380 | /* | |
381 | * pata_s3c_softreset - reset host port via ATA SRST | |
382 | */ | |
383 | static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes, | |
384 | unsigned long deadline) | |
385 | { | |
386 | struct ata_port *ap = link->ap; | |
387 | unsigned int devmask = 0; | |
388 | int rc; | |
389 | u8 err; | |
390 | ||
391 | /* determine if device 0 is present */ | |
392 | if (pata_s3c_devchk(ap, 0)) | |
393 | devmask |= (1 << 0); | |
394 | ||
395 | /* select device 0 again */ | |
396 | pata_s3c_dev_select(ap, 0); | |
397 | ||
398 | /* issue bus reset */ | |
399 | rc = pata_s3c_bus_softreset(ap, deadline); | |
400 | /* if link is occupied, -ENODEV too is an error */ | |
401 | if (rc && rc != -ENODEV) { | |
a9a79dfe | 402 | ata_link_err(link, "SRST failed (errno=%d)\n", rc); |
155bf48f AK |
403 | return rc; |
404 | } | |
405 | ||
406 | /* determine by signature whether we have ATA or ATAPI devices */ | |
407 | classes[0] = ata_sff_dev_classify(&ap->link.device[0], | |
408 | devmask & (1 << 0), &err); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | /* | |
414 | * pata_s3c_set_devctl - Write device control register | |
415 | */ | |
416 | static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl) | |
417 | { | |
418 | ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr); | |
419 | } | |
420 | ||
421 | static struct scsi_host_template pata_s3c_sht = { | |
422 | ATA_PIO_SHT(DRV_NAME), | |
423 | }; | |
424 | ||
425 | static struct ata_port_operations pata_s3c_port_ops = { | |
426 | .inherits = &ata_sff_port_ops, | |
427 | .sff_check_status = pata_s3c_check_status, | |
428 | .sff_check_altstatus = pata_s3c_check_altstatus, | |
429 | .sff_tf_load = pata_s3c_tf_load, | |
430 | .sff_tf_read = pata_s3c_tf_read, | |
431 | .sff_data_xfer = pata_s3c_data_xfer, | |
432 | .sff_exec_command = pata_s3c_exec_command, | |
433 | .sff_dev_select = pata_s3c_dev_select, | |
434 | .sff_set_devctl = pata_s3c_set_devctl, | |
435 | .softreset = pata_s3c_softreset, | |
436 | .set_piomode = pata_s3c_set_piomode, | |
437 | }; | |
438 | ||
439 | static struct ata_port_operations pata_s5p_port_ops = { | |
440 | .inherits = &ata_sff_port_ops, | |
441 | .set_piomode = pata_s3c_set_piomode, | |
442 | }; | |
443 | ||
3d70a363 | 444 | static void pata_s3c_enable(void __iomem *s3c_ide_regbase, bool state) |
155bf48f AK |
445 | { |
446 | u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL); | |
447 | temp = state ? (temp | 1) : (temp & ~1); | |
448 | writel(temp, s3c_ide_regbase + S3C_ATA_CTRL); | |
449 | } | |
450 | ||
451 | static irqreturn_t pata_s3c_irq(int irq, void *dev_instance) | |
452 | { | |
453 | struct ata_host *host = dev_instance; | |
454 | struct s3c_ide_info *info = host->private_data; | |
455 | u32 reg; | |
456 | ||
457 | reg = readl(info->ide_addr + S3C_ATA_IRQ); | |
458 | writel(reg, info->ide_addr + S3C_ATA_IRQ); | |
459 | ||
460 | return ata_sff_interrupt(irq, dev_instance); | |
461 | } | |
462 | ||
463 | static void pata_s3c_hwinit(struct s3c_ide_info *info, | |
464 | struct s3c_ide_platdata *pdata) | |
465 | { | |
466 | switch (info->cpu_type) { | |
467 | case TYPE_S3C64XX: | |
468 | /* Configure as big endian */ | |
469 | pata_s3c_cfg_mode(info->sfr_addr); | |
470 | pata_s3c_set_endian(info->ide_addr, 1); | |
471 | pata_s3c_enable(info->ide_addr, true); | |
472 | msleep(100); | |
473 | ||
474 | /* Remove IRQ Status */ | |
475 | writel(0x1f, info->ide_addr + S3C_ATA_IRQ); | |
476 | writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK); | |
477 | break; | |
478 | ||
479 | case TYPE_S5PC100: | |
480 | pata_s3c_cfg_mode(info->sfr_addr); | |
481 | /* FALLTHROUGH */ | |
482 | ||
483 | case TYPE_S5PV210: | |
484 | /* Configure as little endian */ | |
485 | pata_s3c_set_endian(info->ide_addr, 0); | |
486 | pata_s3c_enable(info->ide_addr, true); | |
487 | msleep(100); | |
488 | ||
489 | /* Remove IRQ Status */ | |
490 | writel(0x3f, info->ide_addr + S3C_ATA_IRQ); | |
491 | writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK); | |
492 | break; | |
493 | ||
494 | default: | |
495 | BUG(); | |
496 | } | |
497 | } | |
498 | ||
499 | static int __init pata_s3c_probe(struct platform_device *pdev) | |
500 | { | |
61b8c345 | 501 | struct s3c_ide_platdata *pdata = dev_get_platdata(&pdev->dev); |
155bf48f AK |
502 | struct device *dev = &pdev->dev; |
503 | struct s3c_ide_info *info; | |
504 | struct resource *res; | |
505 | struct ata_port *ap; | |
506 | struct ata_host *host; | |
507 | enum s3c_cpu_type cpu_type; | |
508 | int ret; | |
509 | ||
510 | cpu_type = platform_get_device_id(pdev)->driver_data; | |
511 | ||
512 | info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); | |
513 | if (!info) { | |
514 | dev_err(dev, "failed to allocate memory for device data\n"); | |
515 | return -ENOMEM; | |
516 | } | |
517 | ||
518 | info->irq = platform_get_irq(pdev, 0); | |
519 | ||
520 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
155bf48f | 521 | |
3e692a94 JH |
522 | info->ide_addr = devm_ioremap_resource(dev, res); |
523 | if (IS_ERR(info->ide_addr)) | |
524 | return PTR_ERR(info->ide_addr); | |
155bf48f | 525 | |
25effc36 | 526 | info->clk = devm_clk_get(&pdev->dev, "cfcon"); |
155bf48f AK |
527 | if (IS_ERR(info->clk)) { |
528 | dev_err(dev, "failed to get access to cf controller clock\n"); | |
529 | ret = PTR_ERR(info->clk); | |
530 | info->clk = NULL; | |
531 | return ret; | |
532 | } | |
533 | ||
534 | clk_enable(info->clk); | |
535 | ||
536 | /* init ata host */ | |
537 | host = ata_host_alloc(dev, 1); | |
538 | if (!host) { | |
539 | dev_err(dev, "failed to allocate ide host\n"); | |
540 | ret = -ENOMEM; | |
541 | goto stop_clk; | |
542 | } | |
543 | ||
544 | ap = host->ports[0]; | |
155bf48f AK |
545 | ap->pio_mask = ATA_PIO4; |
546 | ||
547 | if (cpu_type == TYPE_S3C64XX) { | |
548 | ap->ops = &pata_s3c_port_ops; | |
549 | info->sfr_addr = info->ide_addr + 0x1800; | |
550 | info->ide_addr += 0x1900; | |
551 | info->fifo_status_reg = 0x94; | |
552 | } else if (cpu_type == TYPE_S5PC100) { | |
553 | ap->ops = &pata_s5p_port_ops; | |
554 | info->sfr_addr = info->ide_addr + 0x1800; | |
555 | info->ide_addr += 0x1900; | |
556 | info->fifo_status_reg = 0x84; | |
557 | } else { | |
558 | ap->ops = &pata_s5p_port_ops; | |
559 | info->fifo_status_reg = 0x84; | |
560 | } | |
561 | ||
562 | info->cpu_type = cpu_type; | |
563 | ||
564 | if (info->irq <= 0) { | |
565 | ap->flags |= ATA_FLAG_PIO_POLLING; | |
566 | info->irq = 0; | |
567 | ata_port_desc(ap, "no IRQ, using PIO polling\n"); | |
568 | } | |
569 | ||
570 | ap->ioaddr.cmd_addr = info->ide_addr + S3C_ATA_CMD; | |
571 | ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR; | |
572 | ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED; | |
573 | ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED; | |
574 | ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR; | |
575 | ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR; | |
576 | ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR; | |
577 | ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR; | |
578 | ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR; | |
579 | ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD; | |
580 | ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD; | |
581 | ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD; | |
582 | ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD; | |
583 | ||
584 | ata_port_desc(ap, "mmio cmd 0x%llx ", | |
585 | (unsigned long long)res->start); | |
586 | ||
587 | host->private_data = info; | |
588 | ||
589 | if (pdata && pdata->setup_gpio) | |
590 | pdata->setup_gpio(); | |
591 | ||
592 | /* Set endianness and enable the interface */ | |
593 | pata_s3c_hwinit(info, pdata); | |
594 | ||
595 | platform_set_drvdata(pdev, host); | |
596 | ||
597 | return ata_host_activate(host, info->irq, | |
598 | info->irq ? pata_s3c_irq : NULL, | |
599 | 0, &pata_s3c_sht); | |
600 | ||
601 | stop_clk: | |
602 | clk_disable(info->clk); | |
155bf48f AK |
603 | return ret; |
604 | } | |
605 | ||
606 | static int __exit pata_s3c_remove(struct platform_device *pdev) | |
607 | { | |
608 | struct ata_host *host = platform_get_drvdata(pdev); | |
609 | struct s3c_ide_info *info = host->private_data; | |
610 | ||
611 | ata_host_detach(host); | |
612 | ||
613 | clk_disable(info->clk); | |
155bf48f AK |
614 | |
615 | return 0; | |
616 | } | |
617 | ||
58eb8cd5 | 618 | #ifdef CONFIG_PM_SLEEP |
155bf48f AK |
619 | static int pata_s3c_suspend(struct device *dev) |
620 | { | |
621 | struct platform_device *pdev = to_platform_device(dev); | |
622 | struct ata_host *host = platform_get_drvdata(pdev); | |
623 | ||
624 | return ata_host_suspend(host, PMSG_SUSPEND); | |
625 | } | |
626 | ||
627 | static int pata_s3c_resume(struct device *dev) | |
628 | { | |
629 | struct platform_device *pdev = to_platform_device(dev); | |
630 | struct ata_host *host = platform_get_drvdata(pdev); | |
61b8c345 | 631 | struct s3c_ide_platdata *pdata = dev_get_platdata(&pdev->dev); |
155bf48f AK |
632 | struct s3c_ide_info *info = host->private_data; |
633 | ||
634 | pata_s3c_hwinit(info, pdata); | |
635 | ata_host_resume(host); | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
640 | static const struct dev_pm_ops pata_s3c_pm_ops = { | |
641 | .suspend = pata_s3c_suspend, | |
642 | .resume = pata_s3c_resume, | |
643 | }; | |
644 | #endif | |
645 | ||
646 | /* driver device registration */ | |
647 | static struct platform_device_id pata_s3c_driver_ids[] = { | |
648 | { | |
649 | .name = "s3c64xx-pata", | |
650 | .driver_data = TYPE_S3C64XX, | |
651 | }, { | |
652 | .name = "s5pc100-pata", | |
653 | .driver_data = TYPE_S5PC100, | |
654 | }, { | |
655 | .name = "s5pv210-pata", | |
656 | .driver_data = TYPE_S5PV210, | |
657 | }, | |
658 | { } | |
659 | }; | |
660 | ||
661 | MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids); | |
662 | ||
663 | static struct platform_driver pata_s3c_driver = { | |
664 | .remove = __exit_p(pata_s3c_remove), | |
665 | .id_table = pata_s3c_driver_ids, | |
666 | .driver = { | |
667 | .name = DRV_NAME, | |
668 | .owner = THIS_MODULE, | |
58eb8cd5 | 669 | #ifdef CONFIG_PM_SLEEP |
155bf48f AK |
670 | .pm = &pata_s3c_pm_ops, |
671 | #endif | |
672 | }, | |
673 | }; | |
674 | ||
b186affe | 675 | module_platform_driver_probe(pata_s3c_driver, pata_s3c_probe); |
155bf48f AK |
676 | |
677 | MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>"); | |
678 | MODULE_DESCRIPTION("low-level driver for Samsung PATA controller"); | |
679 | MODULE_LICENSE("GPL"); | |
680 | MODULE_VERSION(DRV_VERSION); |