[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_pdc202xx_old.c

/*
 * pata_pdc202xx_old.c 	- Promise PDC202xx PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
 *			  (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
 *
 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
 *
 * First cut with LBA48/ATAPI
 *
 * TODO:
 *	Channel interlock/reset on both required ?
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_pdc202xx_old"
#define DRV_VERSION "0.4.3"

static int pdc2026x_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 cis;

	pci_read_config_word(pdev, 0x50, &cis);
	if (cis & (1 << (10 + ap->port_no)))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void pdc202xx_exec_command(struct ata_port *ap,
				  const struct ata_taskfile *tf)
{
	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);

	iowrite8(tf->command, ap->ioaddr.command_addr);
	ndelay(400);
}

/**
 *	pdc202xx_configure_piomode	-	set chip PIO timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@pio: PIO mode
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	so a configure_dmamode call will undo any work we do here and vice
 *	versa
 */

static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
	static u16 pio_timing[5] = {
		0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	};
	u8 r_ap, r_bp;

	pci_read_config_byte(pdev, port, &r_ap);
	pci_read_config_byte(pdev, port + 1, &r_bp);
	r_ap &= ~0x3F;	/* Preserve ERRDY_EN, SYNC_IN */
	r_bp &= ~0x1F;
	r_ap |= (pio_timing[pio] >> 8);
	r_bp |= (pio_timing[pio] & 0xFF);

	if (ata_pio_need_iordy(adev))
		r_ap |= 0x20;	/* IORDY enable */
	if (adev->class == ATA_DEV_ATA)
		r_ap |= 0x10;	/* FIFO enable */
	pci_write_config_byte(pdev, port, r_ap);
	pci_write_config_byte(pdev, port + 1, r_bp);
}

/**
 *	pdc202xx_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	but we want to set the PIO timing by default.
 */

static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	pdc202xx_configure_dmamode	-	set DMA mode in chip
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Load DMA cycle times into the chip ready for a DMA transfer
 *	to occur.
 */

static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
	static u8 udma_timing[6][2] = {
		{ 0x60, 0x03 },	/* 33 Mhz Clock */
		{ 0x40, 0x02 },
		{ 0x20, 0x01 },
		{ 0x40, 0x02 },	/* 66 Mhz Clock */
		{ 0x20, 0x01 },
		{ 0x20, 0x01 }
	};
	static u8 mdma_timing[3][2] = {
		{ 0xe0, 0x0f },
		{ 0x60, 0x04 },
		{ 0x60, 0x03 },
	};
	u8 r_bp, r_cp;

	pci_read_config_byte(pdev, port + 1, &r_bp);
	pci_read_config_byte(pdev, port + 2, &r_cp);

	r_bp &= ~0xE0;
	r_cp &= ~0x0F;

	if (adev->dma_mode >= XFER_UDMA_0) {
		int speed = adev->dma_mode - XFER_UDMA_0;
		r_bp |= udma_timing[speed][0];
		r_cp |= udma_timing[speed][1];

	} else {
		int speed = adev->dma_mode - XFER_MW_DMA_0;
		r_bp |= mdma_timing[speed][0];
		r_cp |= mdma_timing[speed][1];
	}
	pci_write_config_byte(pdev, port + 1, r_bp);
	pci_write_config_byte(pdev, port + 2, r_cp);

}

/**
 *	pdc2026x_bmdma_start		-	DMA engine begin
 *	@qc: ATA command
 *
 *	In UDMA3 or higher we have to clock switch for the duration of the
 *	DMA transfer sequence.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;
	int sel66 = ap->port_no ? 0x08: 0x02;

	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	u32 len;

	/* Check we keep host level locking here */
	if (adev->dma_mode > XFER_UDMA_2)
		iowrite8(ioread8(clock) | sel66, clock);
	else
		iowrite8(ioread8(clock) & ~sel66, clock);

	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
	   and move to qc_issue ? */
	pdc202xx_set_dmamode(ap, qc->dev);

	/* Cases the state machine will not complete correctly without help */
	if ((tf->flags & ATA_TFLAG_LBA48) ||  tf->protocol == ATAPI_PROT_DMA) {
		len = qc->nbytes / 2;

		if (tf->flags & ATA_TFLAG_WRITE)
			len |= 0x06000000;
		else
			len |= 0x05000000;

		iowrite32(len, atapi_reg);
	}

	/* Activate DMA */
	ata_bmdma_start(qc);
}

/**
 *	pdc2026x_bmdma_end		-	DMA engine stop
 *	@qc: ATA command
 *
 *	After a DMA completes we need to put the clock back to 33MHz for
 *	PIO timings.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;

	int sel66 = ap->port_no ? 0x08: 0x02;
	/* The clock bits are in the same register for both channels */
	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	/* Cases the state machine will not complete correctly */
	if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
		iowrite32(0, atapi_reg);
		iowrite8(ioread8(clock) & ~sel66, clock);
	}
	/* Flip back to 33Mhz for PIO */
	if (adev->dma_mode > XFER_UDMA_2)
		iowrite8(ioread8(clock) & ~sel66, clock);
	ata_bmdma_stop(qc);
	pdc202xx_set_piomode(ap, adev);
}

/**
 *	pdc2026x_dev_config	-	device setup hook
 *	@adev: newly found device
 *
 *	Perform chip specific early setup. We need to lock the transfer
 *	sizes to 8bit to avoid making the state engine on the 2026x cards
 *	barf.
 */

static void pdc2026x_dev_config(struct ata_device *adev)
{
	adev->max_sectors = 256;
}

static int pdc2026x_port_start(struct ata_port *ap)
{
	void __iomem *bmdma = ap->ioaddr.bmdma_addr;
	if (bmdma) {
		/* Enable burst mode */
		u8 burst = ioread8(bmdma + 0x1f);
		iowrite8(burst | 0x01, bmdma + 0x1f);
	}
	return ata_bmdma_port_start(ap);
}

/**
 *	pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
 *	@qc: Metadata associated with taskfile to check
 *
 *	Just say no - not supported on older Promise.
 *
 *	LOCKING:
 *	None (inherited from caller).
 *
 *	RETURNS: 0 when ATAPI DMA can be used
 *		 1 otherwise
 */

static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
{
	return 1;
}

static struct scsi_host_template pdc202xx_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations pdc2024x_port_ops = {
	.inherits		= &ata_bmdma_port_ops,

	.cable_detect		= ata_cable_40wire,
	.set_piomode		= pdc202xx_set_piomode,
	.set_dmamode		= pdc202xx_set_dmamode,

	.sff_exec_command	= pdc202xx_exec_command,
};

static struct ata_port_operations pdc2026x_port_ops = {
	.inherits		= &pdc2024x_port_ops,

	.check_atapi_dma	= pdc2026x_check_atapi_dma,
	.bmdma_start		= pdc2026x_bmdma_start,
	.bmdma_stop		= pdc2026x_bmdma_stop,

	.cable_detect		= pdc2026x_cable_detect,
	.dev_config		= pdc2026x_dev_config,

	.port_start		= pdc2026x_port_start,

	.sff_exec_command	= pdc202xx_exec_command,
};

static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[3] = {
		{
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA2,
			.port_ops = &pdc2024x_port_ops
		},
		{
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA4,
			.port_ops = &pdc2026x_port_ops
		},
		{
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA5,
			.port_ops = &pdc2026x_port_ops
		}

	};
	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };

	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;
		/* Don't grab anything behind a Promise I2O RAID */
		if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
			if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
				return -ENODEV;
			if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
				return -ENODEV;
		}
	}
	return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
}

static const struct pci_device_id pdc202xx[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },

	{ },
};

static struct pci_driver pdc202xx_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= pdc202xx,
	.probe 		= pdc202xx_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init pdc202xx_init(void)
{
	return pci_register_driver(&pdc202xx_pci_driver);
}

static void __exit pdc202xx_exit(void)
{
	pci_unregister_driver(&pdc202xx_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pdc202xx);
MODULE_VERSION(DRV_VERSION);

module_init(pdc202xx_init);
module_exit(pdc202xx_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
ab771630	4	* Alan Cox <alan@lxorguk.ukuu.org.uk>
a75032e8	5	* (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
	8	*
	9	* First cut with LBA48/ATAPI
	10	*
	11	* TODO:
06b74dd2	12	* Channel interlock/reset on both required ?
669a5db4	13	*/
85cd7251	14
669a5db4 JG	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/blkdev.h>
	20	#include <linux/delay.h>
	21	#include <scsi/scsi_host.h>
	22	#include <linux/libata.h>
	23
	24	#define DRV_NAME "pata_pdc202xx_old"
06b74dd2	25	#define DRV_VERSION "0.4.3"
669a5db4	26
a0fcdc02	27	static int pdc2026x_cable_detect(struct ata_port *ap)
669a5db4 JG	28	{
	29	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	30	u16 cis;
85cd7251	31
669a5db4 JG	32	pci_read_config_word(pdev, 0x50, &cis);
669a5db4 JG	33	if (cis & (1 << (10 + ap->port_no)))
a0ac38f1 AC	34	return ATA_CBL_PATA40;
a0ac38f1 AC	35	return ATA_CBL_PATA80;
669a5db4 JG	36	}
669a5db4 JG	37
750e519d	38	static void pdc202xx_exec_command(struct ata_port *ap,
a75032e8 BZ	39	const struct ata_taskfile *tf)
	40	{
	41	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
	42
	43	iowrite8(tf->command, ap->ioaddr.command_addr);
	44	ndelay(400);
	45	}
	46
669a5db4	47	/**
ada406c8	48	* pdc202xx_configure_piomode - set chip PIO timing
669a5db4 JG	49	* @ap: ATA interface
	50	* @adev: ATA device
	51	* @pio: PIO mode
	52	*
	53	* Called to do the PIO mode setup. Our timing registers are shared
	54	* so a configure_dmamode call will undo any work we do here and vice
	55	* versa
	56	*/
85cd7251	57
ada406c8	58	static void pdc202xx_configure_piomode(struct ata_port ap, struct ata_device adev, int pio)
669a5db4 JG	59	{
669a5db4 JG	60	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63ed7101	61	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
669a5db4 JG	62	static u16 pio_timing[5] = {
	63	0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	64	};
	65	u8 r_ap, r_bp;
	66
	67	pci_read_config_byte(pdev, port, &r_ap);
	68	pci_read_config_byte(pdev, port + 1, &r_bp);
	69	r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
63ed7101	70	r_bp &= ~0x1F;
669a5db4 JG	71	r_ap \|= (pio_timing[pio] >> 8);
669a5db4 JG	72	r_bp \|= (pio_timing[pio] & 0xFF);
85cd7251	73
669a5db4 JG	74	if (ata_pio_need_iordy(adev))
	75	r_ap \|= 0x20; /* IORDY enable */
	76	if (adev->class == ATA_DEV_ATA)
	77	r_ap \|= 0x10; /* FIFO enable */
	78	pci_write_config_byte(pdev, port, r_ap);
	79	pci_write_config_byte(pdev, port + 1, r_bp);
	80	}
	81
	82	/**
ada406c8	83	* pdc202xx_set_piomode - set initial PIO mode data
669a5db4 JG	84	* @ap: ATA interface
	85	* @adev: ATA device
	86	*
	87	* Called to do the PIO mode setup. Our timing registers are shared
	88	* but we want to set the PIO timing by default.
	89	*/
85cd7251	90
ada406c8	91	static void pdc202xx_set_piomode(struct ata_port ap, struct ata_device adev)
669a5db4	92	{
ada406c8	93	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
669a5db4 JG	94	}
	95
	96	/**
ada406c8	97	* pdc202xx_configure_dmamode - set DMA mode in chip
669a5db4 JG	98	* @ap: ATA interface
	99	* @adev: ATA device
	100	*
	101	* Load DMA cycle times into the chip ready for a DMA transfer
	102	* to occur.
	103	*/
85cd7251	104
ada406c8	105	static void pdc202xx_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	106	{
669a5db4 JG	107	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63ed7101	108	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
669a5db4 JG	109	static u8 udma_timing[6][2] = {
	110	{ 0x60, 0x03 }, /* 33 Mhz Clock */
	111	{ 0x40, 0x02 },
	112	{ 0x20, 0x01 },
	113	{ 0x40, 0x02 }, /* 66 Mhz Clock */
	114	{ 0x20, 0x01 },
85cd7251	115	{ 0x20, 0x01 }
669a5db4	116	};
63ed7101	117	static u8 mdma_timing[3][2] = {
63ed7101	118	{ 0xe0, 0x0f },
06b74dd2 AC	119	{ 0x60, 0x04 },
06b74dd2 AC	120	{ 0x60, 0x03 },
63ed7101	121	};
669a5db4	122	u8 r_bp, r_cp;
85cd7251	123
669a5db4 JG	124	pci_read_config_byte(pdev, port + 1, &r_bp);
669a5db4 JG	125	pci_read_config_byte(pdev, port + 2, &r_cp);
85cd7251	126
63ed7101	127	r_bp &= ~0xE0;
669a5db4	128	r_cp &= ~0x0F;
85cd7251	129
669a5db4 JG	130	if (adev->dma_mode >= XFER_UDMA_0) {
	131	int speed = adev->dma_mode - XFER_UDMA_0;
	132	r_bp \|= udma_timing[speed][0];
	133	r_cp \|= udma_timing[speed][1];
85cd7251	134
669a5db4 JG	135	} else {
669a5db4 JG	136	int speed = adev->dma_mode - XFER_MW_DMA_0;
63ed7101 BZ	137	r_bp \|= mdma_timing[speed][0];
63ed7101 BZ	138	r_cp \|= mdma_timing[speed][1];
669a5db4 JG	139	}
	140	pci_write_config_byte(pdev, port + 1, r_bp);
	141	pci_write_config_byte(pdev, port + 2, r_cp);
85cd7251	142
669a5db4 JG	143	}
	144
	145	/**
	146	* pdc2026x_bmdma_start - DMA engine begin
	147	* @qc: ATA command
	148	*
	149	* In UDMA3 or higher we have to clock switch for the duration of the
	150	* DMA transfer sequence.
06b74dd2 AC	151	*
	152	* Note: The host lock held by the libata layer protects
	153	* us from two channels both trying to set DMA bits at once
669a5db4	154	*/
85cd7251	155
669a5db4 JG	156	static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
	157	{
	158	struct ata_port *ap = qc->ap;
	159	struct ata_device *adev = qc->dev;
	160	struct ata_taskfile *tf = &qc->tf;
	161	int sel66 = ap->port_no ? 0x08: 0x02;
	162
0d5ff566 TH	163	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	164	void __iomem *clock = master + 0x11;
	165	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	166
669a5db4	167	u32 len;
85cd7251	168
669a5db4	169	/* Check we keep host level locking here */
6ad58b24	170	if (adev->dma_mode > XFER_UDMA_2)
0d5ff566	171	iowrite8(ioread8(clock) \| sel66, clock);
669a5db4	172	else
0d5ff566	173	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	174
85cd7251	175	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
669a5db4	176	and move to qc_issue ? */
ada406c8	177	pdc202xx_set_dmamode(ap, qc->dev);
669a5db4 JG	178
669a5db4 JG	179	/* Cases the state machine will not complete correctly without help */
0dc36888	180	if ((tf->flags & ATA_TFLAG_LBA48) \|\| tf->protocol == ATAPI_PROT_DMA) {
5e518810	181	len = qc->nbytes / 2;
85cd7251	182
669a5db4 JG	183	if (tf->flags & ATA_TFLAG_WRITE)
	184	len \|= 0x06000000;
	185	else
	186	len \|= 0x05000000;
85cd7251	187
0d5ff566	188	iowrite32(len, atapi_reg);
669a5db4	189	}
85cd7251 JG	190
85cd7251 JG	191	/* Activate DMA */
669a5db4 JG	192	ata_bmdma_start(qc);
	193	}
	194
	195	/**
	196	* pdc2026x_bmdma_end - DMA engine stop
	197	* @qc: ATA command
	198	*
	199	* After a DMA completes we need to put the clock back to 33MHz for
	200	* PIO timings.
06b74dd2 AC	201	*
	202	* Note: The host lock held by the libata layer protects
	203	* us from two channels both trying to set DMA bits at once
669a5db4	204	*/
85cd7251	205
669a5db4 JG	206	static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
	207	{
	208	struct ata_port *ap = qc->ap;
	209	struct ata_device *adev = qc->dev;
	210	struct ata_taskfile *tf = &qc->tf;
85cd7251	211
669a5db4 JG	212	int sel66 = ap->port_no ? 0x08: 0x02;
669a5db4 JG	213	/* The clock bits are in the same register for both channels */
0d5ff566 TH	214	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	215	void __iomem *clock = master + 0x11;
	216	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	217
669a5db4	218	/* Cases the state machine will not complete correctly */
0dc36888	219	if (tf->protocol == ATAPI_PROT_DMA \|\| (tf->flags & ATA_TFLAG_LBA48)) {
0d5ff566 TH	220	iowrite32(0, atapi_reg);
0d5ff566 TH	221	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	222	}
669a5db4	223	/* Flip back to 33Mhz for PIO */
6ad58b24	224	if (adev->dma_mode > XFER_UDMA_2)
0d5ff566	225	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	226	ata_bmdma_stop(qc);
36906d9b	227	pdc202xx_set_piomode(ap, adev);
669a5db4 JG	228	}
	229
	230	/**
	231	* pdc2026x_dev_config - device setup hook
669a5db4 JG	232	* @adev: newly found device
	233	*
	234	* Perform chip specific early setup. We need to lock the transfer
	235	* sizes to 8bit to avoid making the state engine on the 2026x cards
	236	* barf.
	237	*/
85cd7251	238
cd0d3bbc	239	static void pdc2026x_dev_config(struct ata_device *adev)
669a5db4 JG	240	{
	241	adev->max_sectors = 256;
	242	}
	243
36906d9b AC	244	static int pdc2026x_port_start(struct ata_port *ap)
	245	{
	246	void __iomem *bmdma = ap->ioaddr.bmdma_addr;
	247	if (bmdma) {
	248	/* Enable burst mode */
	249	u8 burst = ioread8(bmdma + 0x1f);
	250	iowrite8(burst \| 0x01, bmdma + 0x1f);
	251	}
c7087652	252	return ata_bmdma_port_start(ap);
36906d9b AC	253	}
36906d9b AC	254
aa8f2371 AC	255	/**
	256	* pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
	257	* @qc: Metadata associated with taskfile to check
	258	*
	259	* Just say no - not supported on older Promise.
	260	*
	261	* LOCKING:
	262	* None (inherited from caller).
	263	*
	264	* RETURNS: 0 when ATAPI DMA can be used
	265	* 1 otherwise
	266	*/
	267
	268	static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
	269	{
	270	return 1;
	271	}
	272
ada406c8	273	static struct scsi_host_template pdc202xx_sht = {
68d1d07b	274	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	275	};
	276
	277	static struct ata_port_operations pdc2024x_port_ops = {
029cfd6b TH	278	.inherits = &ata_bmdma_port_ops,
	279
	280	.cable_detect = ata_cable_40wire,
	281	.set_piomode = pdc202xx_set_piomode,
	282	.set_dmamode = pdc202xx_set_dmamode,
a75032e8	283
750e519d	284	.sff_exec_command = pdc202xx_exec_command,
85cd7251	285	};
669a5db4 JG	286
669a5db4 JG	287	static struct ata_port_operations pdc2026x_port_ops = {
029cfd6b TH	288	.inherits = &pdc2024x_port_ops,
	289
	290	.check_atapi_dma = pdc2026x_check_atapi_dma,
	291	.bmdma_start = pdc2026x_bmdma_start,
	292	.bmdma_stop = pdc2026x_bmdma_stop,
	293
	294	.cable_detect = pdc2026x_cable_detect,
	295	.dev_config = pdc2026x_dev_config,
	296
	297	.port_start = pdc2026x_port_start,
750e519d BZ	298
750e519d BZ	299	.sff_exec_command = pdc202xx_exec_command,
85cd7251	300	};
669a5db4	301
ada406c8	302	static int pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4	303	{
1626aeb8	304	static const struct ata_port_info info[3] = {
669a5db4	305	{
1d2808fd	306	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	307	.pio_mask = ATA_PIO4,
14bdef98 EIB	308	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	309	.udma_mask = ATA_UDMA2,
669a5db4 JG	310	.port_ops = &pdc2024x_port_ops
85cd7251	311	},
669a5db4	312	{
1d2808fd	313	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	314	.pio_mask = ATA_PIO4,
14bdef98 EIB	315	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	316	.udma_mask = ATA_UDMA4,
	317	.port_ops = &pdc2026x_port_ops
	318	},
	319	{
1d2808fd	320	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	321	.pio_mask = ATA_PIO4,
14bdef98 EIB	322	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	323	.udma_mask = ATA_UDMA5,
	324	.port_ops = &pdc2026x_port_ops
	325	}
85cd7251	326
669a5db4	327	};
1626aeb8	328	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
85cd7251	329
669a5db4 JG	330	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
	331	struct pci_dev *bridge = dev->bus->self;
	332	/* Don't grab anything behind a Promise I2O RAID */
	333	if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
b447916e	334	if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
669a5db4	335	return -ENODEV;
b447916e	336	if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
669a5db4 JG	337	return -ENODEV;
	338	}
	339	}
1c5afdf7	340	return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
669a5db4 JG	341	}
669a5db4 JG	342
ada406c8	343	static const struct pci_device_id pdc202xx[] = {
2d2744fc JG	344	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	345	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	346	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	347	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	348	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	349
	350	{ },
669a5db4 JG	351	};
669a5db4 JG	352
ada406c8	353	static struct pci_driver pdc202xx_pci_driver = {
2d2744fc	354	.name = DRV_NAME,
ada406c8 AC	355	.id_table = pdc202xx,
ada406c8 AC	356	.probe = pdc202xx_init_one,
62d64ae0	357	.remove = ata_pci_remove_one,
438ac6d5	358	#ifdef CONFIG_PM
62d64ae0 AC	359	.suspend = ata_pci_device_suspend,
62d64ae0 AC	360	.resume = ata_pci_device_resume,
438ac6d5	361	#endif
669a5db4 JG	362	};
669a5db4 JG	363
ada406c8	364	static int __init pdc202xx_init(void)
669a5db4	365	{
ada406c8	366	return pci_register_driver(&pdc202xx_pci_driver);
669a5db4 JG	367	}
669a5db4 JG	368
ada406c8	369	static void __exit pdc202xx_exit(void)
669a5db4	370	{
ada406c8	371	pci_unregister_driver(&pdc202xx_pci_driver);
669a5db4 JG	372	}
669a5db4 JG	373
669a5db4 JG	374	MODULE_AUTHOR("Alan Cox");
	375	MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
	376	MODULE_LICENSE("GPL");
ada406c8	377	MODULE_DEVICE_TABLE(pci, pdc202xx);
669a5db4 JG	378	MODULE_VERSION(DRV_VERSION);
669a5db4 JG	379
ada406c8 AC	380	module_init(pdc202xx_init);
ada406c8 AC	381	module_exit(pdc202xx_exit);