[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_opti.c

/*
 * pata_opti.c 	- ATI PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * Based on
 *  linux/drivers/ide/pci/opti621.c		Version 0.7	Sept 10, 2002
 *
 *  Copyright (C) 1996-1998  Linus Torvalds & authors (see below)
 *
 * Authors:
 * Jaromir Koutek <miri@punknet.cz>,
 * Jan Harkes <jaharkes@cwi.nl>,
 * Mark Lord <mlord@pobox.com>
 * Some parts of code are from ali14xx.c and from rz1000.c.
 *
 * Also consulted the FreeBSD prototype driver by Kevin Day to try
 * and resolve some confusions. Further documentation can be found in
 * Ralf Brown's interrupt list
 *
 * If you have other variants of the Opti range (Viper/Vendetta) please
 * try this driver with those PCI idents and report back. For the later
 * chips see the pata_optidma driver
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_opti"
#define DRV_VERSION "0.2.9"

enum {
	READ_REG	= 0,	/* index of Read cycle timing register */
	WRITE_REG 	= 1,	/* index of Write cycle timing register */
	CNTRL_REG 	= 3,	/* index of Control register */
	STRAP_REG 	= 5,	/* index of Strap register */
	MISC_REG 	= 6	/* index of Miscellaneous register */
};

/**
 *	opti_pre_reset		-	probe begin
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Set up cable type and use generic probe init
 */

static int opti_pre_reset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const struct pci_bits opti_enable_bits[] = {
		{ 0x45, 1, 0x80, 0x00 },
		{ 0x40, 1, 0x08, 0x00 }
	};

	if (!pci_test_config_bits(pdev, &opti_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_std_prereset(link, deadline);
}

/**
 *	opti_probe_reset		-	probe reset
 *	@ap: ATA port
 *
 *	Perform the ATA probe and bus reset sequence plus specific handling
 *	for this hardware. The Opti needs little handling - we have no UDMA66
 *	capability that needs cable detection. All we must do is check the port
 *	is enabled.
 */

static void opti_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, opti_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	opti_write_reg		-	control register setup
 *	@ap: ATA port
 *	@value: value
 *	@reg: control register number
 *
 *	The Opti uses magic 'trapdoor' register accesses to do configuration
 *	rather than using PCI space as other controllers do. The double inw
 *	on the error register activates configuration mode. We can then write
 *	the control register
 */

static void opti_write_reg(struct ata_port *ap, u8 val, int reg)
{
	void __iomem *regio = ap->ioaddr.cmd_addr;

	/* These 3 unlock the control register access */
	ioread16(regio + 1);
	ioread16(regio + 1);
	iowrite8(3, regio + 2);

	/* Do the I/O */
	iowrite8(val, regio + reg);

	/* Relock */
	iowrite8(0x83, regio + 2);
}

/**
 *	opti_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Timing numbers are taken from
 *	the FreeBSD driver then pre computed to keep the code clean. There
 *	are two tables depending on the hardware clock speed.
 */

static void opti_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct ata_device *pair = ata_dev_pair(adev);
	int clock;
	int pio = adev->pio_mode - XFER_PIO_0;
	void __iomem *regio = ap->ioaddr.cmd_addr;
	u8 addr;

	/* Address table precomputed with prefetch off and a DCLK of 2 */
	static const u8 addr_timing[2][5] = {
		{ 0x30, 0x20, 0x20, 0x10, 0x10 },
		{ 0x20, 0x20, 0x10, 0x10, 0x10 }
	};
	static const u8 data_rec_timing[2][5] = {
		{ 0x6B, 0x56, 0x42, 0x32, 0x31 },
		{ 0x58, 0x44, 0x32, 0x22, 0x21 }
	};

	iowrite8(0xff, regio + 5);
	clock = ioread16(regio + 5) & 1;

	/*
 	 *	As with many controllers the address setup time is shared
 	 *	and must suit both devices if present.
	 */

	addr = addr_timing[clock][pio];
	if (pair) {
		/* Hardware constraint */
		u8 pair_addr = addr_timing[clock][pair->pio_mode - XFER_PIO_0];
		if (pair_addr > addr)
			addr = pair_addr;
	}

	/* Commence primary programming sequence */
	opti_write_reg(ap, adev->devno, MISC_REG);
	opti_write_reg(ap, data_rec_timing[clock][pio], READ_REG);
	opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG);
	opti_write_reg(ap, addr, MISC_REG);

	/* Programming sequence complete, override strapping */
	opti_write_reg(ap, 0x85, CNTRL_REG);
}

static struct scsi_host_template opti_sht = {
	ATA_PIO_SHT(DRV_NAME),
};

static struct ata_port_operations opti_port_ops = {
	.inherits	= &ata_sff_port_ops,
	.cable_detect	= ata_cable_40wire,
	.set_piomode	= opti_set_piomode,
	.error_handler	= opti_error_handler,
};

static int opti_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.port_ops = &opti_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, NULL };
	static int printed_version;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");

	return ata_pci_init_one(dev, ppi, &opti_sht, NULL);
}

static const struct pci_device_id opti[] = {
	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },

	{ },
};

static struct pci_driver opti_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= opti,
	.probe 		= opti_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init opti_init(void)
{
	return pci_register_driver(&opti_pci_driver);
}

static void __exit opti_exit(void)
{
	pci_unregister_driver(&opti_pci_driver);
}


MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Opti 621/621X");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, opti);
MODULE_VERSION(DRV_VERSION);

module_init(opti_init);
module_exit(opti_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_opti.c - ATI PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Based on
	7	* linux/drivers/ide/pci/opti621.c Version 0.7 Sept 10, 2002
	8	*
	9	* Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
	10	*
	11	* Authors:
	12	* Jaromir Koutek <miri@punknet.cz>,
	13	* Jan Harkes <jaharkes@cwi.nl>,
	14	* Mark Lord <mlord@pobox.com>
	15	* Some parts of code are from ali14xx.c and from rz1000.c.
	16	*
	17	* Also consulted the FreeBSD prototype driver by Kevin Day to try
	18	* and resolve some confusions. Further documentation can be found in
	19	* Ralf Brown's interrupt list
	20	*
	21	* If you have other variants of the Opti range (Viper/Vendetta) please
	22	* try this driver with those PCI idents and report back. For the later
	23	* chips see the pata_optidma driver
	24	*
	25	*/
	26
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
	29	#include <linux/pci.h>
	30	#include <linux/init.h>
	31	#include <linux/blkdev.h>
	32	#include <linux/delay.h>
	33	#include <scsi/scsi_host.h>
	34	#include <linux/libata.h>
	35
	36	#define DRV_NAME "pata_opti"
a0fcdc02	37	#define DRV_VERSION "0.2.9"
669a5db4 JG	38
	39	enum {
	40	READ_REG = 0, /* index of Read cycle timing register */
	41	WRITE_REG = 1, /* index of Write cycle timing register */
	42	CNTRL_REG = 3, /* index of Control register */
	43	STRAP_REG = 5, /* index of Strap register */
	44	MISC_REG = 6 /* index of Miscellaneous register */
	45	};
	46
	47	/**
	48	* opti_pre_reset - probe begin
cc0680a5	49	* @link: ATA link
d4b2bab4	50	* @deadline: deadline jiffies for the operation
669a5db4 JG	51	*
	52	* Set up cable type and use generic probe init
	53	*/
	54
cc0680a5	55	static int opti_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	56	{
cc0680a5	57	struct ata_port *ap = link->ap;
669a5db4 JG	58	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	59	static const struct pci_bits opti_enable_bits[] = {
	60	{ 0x45, 1, 0x80, 0x00 },
	61	{ 0x40, 1, 0x08, 0x00 }
	62	};
	63
c961922b AC	64	if (!pci_test_config_bits(pdev, &opti_enable_bits[ap->port_no]))
c961922b AC	65	return -ENOENT;
d4b2bab4	66
cc0680a5	67	return ata_std_prereset(link, deadline);
669a5db4 JG	68	}
	69
	70	/**
	71	* opti_probe_reset - probe reset
	72	* @ap: ATA port
	73	*
	74	* Perform the ATA probe and bus reset sequence plus specific handling
	75	* for this hardware. The Opti needs little handling - we have no UDMA66
	76	* capability that needs cable detection. All we must do is check the port
	77	* is enabled.
	78	*/
	79
	80	static void opti_error_handler(struct ata_port *ap)
	81	{
	82	ata_bmdma_drive_eh(ap, opti_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	83	}
	84
	85	/**
	86	* opti_write_reg - control register setup
	87	* @ap: ATA port
	88	* @value: value
	89	* @reg: control register number
	90	*
	91	* The Opti uses magic 'trapdoor' register accesses to do configuration
	92	* rather than using PCI space as other controllers do. The double inw
	93	* on the error register activates configuration mode. We can then write
	94	* the control register
	95	*/
	96
	97	static void opti_write_reg(struct ata_port *ap, u8 val, int reg)
	98	{
0d5ff566	99	void __iomem *regio = ap->ioaddr.cmd_addr;
669a5db4 JG	100
669a5db4 JG	101	/* These 3 unlock the control register access */
0d5ff566 TH	102	ioread16(regio + 1);
	103	ioread16(regio + 1);
	104	iowrite8(3, regio + 2);
669a5db4 JG	105
669a5db4 JG	106	/* Do the I/O */
0d5ff566	107	iowrite8(val, regio + reg);
669a5db4 JG	108
669a5db4 JG	109	/* Relock */
0d5ff566	110	iowrite8(0x83, regio + 2);
669a5db4 JG	111	}
669a5db4 JG	112
669a5db4 JG	113	/**
	114	* opti_set_piomode - set initial PIO mode data
	115	* @ap: ATA interface
	116	* @adev: ATA device
	117	*
	118	* Called to do the PIO mode setup. Timing numbers are taken from
	119	* the FreeBSD driver then pre computed to keep the code clean. There
	120	* are two tables depending on the hardware clock speed.
	121	*/
	122
	123	static void opti_set_piomode(struct ata_port ap, struct ata_device adev)
	124	{
	125	struct ata_device *pair = ata_dev_pair(adev);
	126	int clock;
	127	int pio = adev->pio_mode - XFER_PIO_0;
0d5ff566	128	void __iomem *regio = ap->ioaddr.cmd_addr;
669a5db4 JG	129	u8 addr;
	130
	131	/* Address table precomputed with prefetch off and a DCLK of 2 */
	132	static const u8 addr_timing[2][5] = {
	133	{ 0x30, 0x20, 0x20, 0x10, 0x10 },
	134	{ 0x20, 0x20, 0x10, 0x10, 0x10 }
	135	};
	136	static const u8 data_rec_timing[2][5] = {
	137	{ 0x6B, 0x56, 0x42, 0x32, 0x31 },
	138	{ 0x58, 0x44, 0x32, 0x22, 0x21 }
	139	};
	140
0d5ff566 TH	141	iowrite8(0xff, regio + 5);
0d5ff566 TH	142	clock = ioread16(regio + 5) & 1;
669a5db4 JG	143
	144	/*
	145	* As with many controllers the address setup time is shared
	146	* and must suit both devices if present.
	147	*/
	148
	149	addr = addr_timing[clock][pio];
	150	if (pair) {
	151	/* Hardware constraint */
	152	u8 pair_addr = addr_timing[clock][pair->pio_mode - XFER_PIO_0];
	153	if (pair_addr > addr)
	154	addr = pair_addr;
	155	}
	156
	157	/* Commence primary programming sequence */
	158	opti_write_reg(ap, adev->devno, MISC_REG);
	159	opti_write_reg(ap, data_rec_timing[clock][pio], READ_REG);
	160	opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG);
	161	opti_write_reg(ap, addr, MISC_REG);
	162
	163	/* Programming sequence complete, override strapping */
	164	opti_write_reg(ap, 0x85, CNTRL_REG);
	165	}
	166
	167	static struct scsi_host_template opti_sht = {
68d1d07b	168	ATA_PIO_SHT(DRV_NAME),
669a5db4 JG	169	};
	170
	171	static struct ata_port_operations opti_port_ops = {
029cfd6b TH	172	.inherits = &ata_sff_port_ops,
029cfd6b TH	173	.cable_detect = ata_cable_40wire,
669a5db4	174	.set_piomode = opti_set_piomode,
669a5db4	175	.error_handler = opti_error_handler,
669a5db4 JG	176	};
	177
	178	static int opti_init_one(struct pci_dev dev, const struct pci_device_id id)
	179	{
1626aeb8	180	static const struct ata_port_info info = {
1d2808fd	181	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	182	.pio_mask = 0x1f,
	183	.port_ops = &opti_port_ops
	184	};
1626aeb8	185	const struct ata_port_info *ppi[] = { &info, NULL };
669a5db4 JG	186	static int printed_version;
	187
	188	if (!printed_version++)
	189	dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
	190
887125e3	191	return ata_pci_init_one(dev, ppi, &opti_sht, NULL);
669a5db4 JG	192	}
	193
	194	static const struct pci_device_id opti[] = {
2d2744fc JG	195	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
	196	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
	197
	198	{ },
669a5db4 JG	199	};
	200
	201	static struct pci_driver opti_pci_driver = {
2d2744fc	202	.name = DRV_NAME,
669a5db4 JG	203	.id_table = opti,
669a5db4 JG	204	.probe = opti_init_one,
30ced0f0	205	.remove = ata_pci_remove_one,
438ac6d5	206	#ifdef CONFIG_PM
30ced0f0 AC	207	.suspend = ata_pci_device_suspend,
30ced0f0 AC	208	.resume = ata_pci_device_resume,
438ac6d5	209	#endif
669a5db4 JG	210	};
	211
	212	static int __init opti_init(void)
	213	{
	214	return pci_register_driver(&opti_pci_driver);
	215	}
	216
669a5db4 JG	217	static void __exit opti_exit(void)
	218	{
	219	pci_unregister_driver(&opti_pci_driver);
	220	}
	221
	222
	223	MODULE_AUTHOR("Alan Cox");
	224	MODULE_DESCRIPTION("low-level driver for Opti 621/621X");
	225	MODULE_LICENSE("GPL");
	226	MODULE_DEVICE_TABLE(pci, opti);
	227	MODULE_VERSION(DRV_VERSION);
	228
	229	module_init(opti_init);
	230	module_exit(opti_exit);