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669a5db4 JG |
1 | /* |
2 | * pata_opti.c - ATI PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * Based on | |
7 | * linux/drivers/ide/pci/opti621.c Version 0.7 Sept 10, 2002 | |
8 | * | |
9 | * Copyright (C) 1996-1998 Linus Torvalds & authors (see below) | |
10 | * | |
11 | * Authors: | |
12 | * Jaromir Koutek <miri@punknet.cz>, | |
13 | * Jan Harkes <jaharkes@cwi.nl>, | |
14 | * Mark Lord <mlord@pobox.com> | |
15 | * Some parts of code are from ali14xx.c and from rz1000.c. | |
16 | * | |
17 | * Also consulted the FreeBSD prototype driver by Kevin Day to try | |
18 | * and resolve some confusions. Further documentation can be found in | |
19 | * Ralf Brown's interrupt list | |
20 | * | |
21 | * If you have other variants of the Opti range (Viper/Vendetta) please | |
22 | * try this driver with those PCI idents and report back. For the later | |
23 | * chips see the pata_optidma driver | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/blkdev.h> | |
32 | #include <linux/delay.h> | |
33 | #include <scsi/scsi_host.h> | |
34 | #include <linux/libata.h> | |
35 | ||
36 | #define DRV_NAME "pata_opti" | |
c961922b | 37 | #define DRV_VERSION "0.2.5" |
669a5db4 JG |
38 | |
39 | enum { | |
40 | READ_REG = 0, /* index of Read cycle timing register */ | |
41 | WRITE_REG = 1, /* index of Write cycle timing register */ | |
42 | CNTRL_REG = 3, /* index of Control register */ | |
43 | STRAP_REG = 5, /* index of Strap register */ | |
44 | MISC_REG = 6 /* index of Miscellaneous register */ | |
45 | }; | |
46 | ||
47 | /** | |
48 | * opti_pre_reset - probe begin | |
49 | * @ap: ATA port | |
50 | * | |
51 | * Set up cable type and use generic probe init | |
52 | */ | |
53 | ||
54 | static int opti_pre_reset(struct ata_port *ap) | |
55 | { | |
56 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
57 | static const struct pci_bits opti_enable_bits[] = { | |
58 | { 0x45, 1, 0x80, 0x00 }, | |
59 | { 0x40, 1, 0x08, 0x00 } | |
60 | }; | |
61 | ||
c961922b AC |
62 | if (!pci_test_config_bits(pdev, &opti_enable_bits[ap->port_no])) |
63 | return -ENOENT; | |
64 | ||
669a5db4 JG |
65 | ap->cbl = ATA_CBL_PATA40; |
66 | return ata_std_prereset(ap); | |
67 | } | |
68 | ||
69 | /** | |
70 | * opti_probe_reset - probe reset | |
71 | * @ap: ATA port | |
72 | * | |
73 | * Perform the ATA probe and bus reset sequence plus specific handling | |
74 | * for this hardware. The Opti needs little handling - we have no UDMA66 | |
75 | * capability that needs cable detection. All we must do is check the port | |
76 | * is enabled. | |
77 | */ | |
78 | ||
79 | static void opti_error_handler(struct ata_port *ap) | |
80 | { | |
81 | ata_bmdma_drive_eh(ap, opti_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
82 | } | |
83 | ||
84 | /** | |
85 | * opti_write_reg - control register setup | |
86 | * @ap: ATA port | |
87 | * @value: value | |
88 | * @reg: control register number | |
89 | * | |
90 | * The Opti uses magic 'trapdoor' register accesses to do configuration | |
91 | * rather than using PCI space as other controllers do. The double inw | |
92 | * on the error register activates configuration mode. We can then write | |
93 | * the control register | |
94 | */ | |
95 | ||
96 | static void opti_write_reg(struct ata_port *ap, u8 val, int reg) | |
97 | { | |
98 | unsigned long regio = ap->ioaddr.cmd_addr; | |
99 | ||
100 | /* These 3 unlock the control register access */ | |
101 | inw(regio + 1); | |
102 | inw(regio + 1); | |
103 | outb(3, regio + 2); | |
104 | ||
105 | /* Do the I/O */ | |
106 | outb(val, regio + reg); | |
107 | ||
108 | /* Relock */ | |
109 | outb(0x83, regio + 2); | |
110 | } | |
111 | ||
112 | #if 0 | |
113 | /** | |
114 | * opti_read_reg - control register read | |
115 | * @ap: ATA port | |
116 | * @reg: control register number | |
117 | * | |
118 | * The Opti uses magic 'trapdoor' register accesses to do configuration | |
119 | * rather than using PCI space as other controllers do. The double inw | |
120 | * on the error register activates configuration mode. We can then read | |
121 | * the control register | |
122 | */ | |
123 | ||
124 | static u8 opti_read_reg(struct ata_port *ap, int reg) | |
125 | { | |
126 | unsigned long regio = ap->ioaddr.cmd_addr; | |
127 | u8 ret; | |
128 | inw(regio + 1); | |
129 | inw(regio + 1); | |
130 | outb(3, regio + 2); | |
131 | ret = inb(regio + reg); | |
132 | outb(0x83, regio + 2); | |
133 | } | |
134 | #endif | |
135 | ||
136 | /** | |
137 | * opti_set_piomode - set initial PIO mode data | |
138 | * @ap: ATA interface | |
139 | * @adev: ATA device | |
140 | * | |
141 | * Called to do the PIO mode setup. Timing numbers are taken from | |
142 | * the FreeBSD driver then pre computed to keep the code clean. There | |
143 | * are two tables depending on the hardware clock speed. | |
144 | */ | |
145 | ||
146 | static void opti_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
147 | { | |
148 | struct ata_device *pair = ata_dev_pair(adev); | |
149 | int clock; | |
150 | int pio = adev->pio_mode - XFER_PIO_0; | |
151 | unsigned long regio = ap->ioaddr.cmd_addr; | |
152 | u8 addr; | |
153 | ||
154 | /* Address table precomputed with prefetch off and a DCLK of 2 */ | |
155 | static const u8 addr_timing[2][5] = { | |
156 | { 0x30, 0x20, 0x20, 0x10, 0x10 }, | |
157 | { 0x20, 0x20, 0x10, 0x10, 0x10 } | |
158 | }; | |
159 | static const u8 data_rec_timing[2][5] = { | |
160 | { 0x6B, 0x56, 0x42, 0x32, 0x31 }, | |
161 | { 0x58, 0x44, 0x32, 0x22, 0x21 } | |
162 | }; | |
163 | ||
164 | outb(0xff, regio + 5); | |
165 | clock = inw(regio + 5) & 1; | |
166 | ||
167 | /* | |
168 | * As with many controllers the address setup time is shared | |
169 | * and must suit both devices if present. | |
170 | */ | |
171 | ||
172 | addr = addr_timing[clock][pio]; | |
173 | if (pair) { | |
174 | /* Hardware constraint */ | |
175 | u8 pair_addr = addr_timing[clock][pair->pio_mode - XFER_PIO_0]; | |
176 | if (pair_addr > addr) | |
177 | addr = pair_addr; | |
178 | } | |
179 | ||
180 | /* Commence primary programming sequence */ | |
181 | opti_write_reg(ap, adev->devno, MISC_REG); | |
182 | opti_write_reg(ap, data_rec_timing[clock][pio], READ_REG); | |
183 | opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG); | |
184 | opti_write_reg(ap, addr, MISC_REG); | |
185 | ||
186 | /* Programming sequence complete, override strapping */ | |
187 | opti_write_reg(ap, 0x85, CNTRL_REG); | |
188 | } | |
189 | ||
190 | static struct scsi_host_template opti_sht = { | |
191 | .module = THIS_MODULE, | |
192 | .name = DRV_NAME, | |
193 | .ioctl = ata_scsi_ioctl, | |
194 | .queuecommand = ata_scsi_queuecmd, | |
195 | .can_queue = ATA_DEF_QUEUE, | |
196 | .this_id = ATA_SHT_THIS_ID, | |
197 | .sg_tablesize = LIBATA_MAX_PRD, | |
198 | .max_sectors = ATA_MAX_SECTORS, | |
199 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
200 | .emulated = ATA_SHT_EMULATED, | |
201 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
202 | .proc_name = DRV_NAME, | |
203 | .dma_boundary = ATA_DMA_BOUNDARY, | |
204 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 205 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
206 | .bios_param = ata_std_bios_param, |
207 | }; | |
208 | ||
209 | static struct ata_port_operations opti_port_ops = { | |
210 | .port_disable = ata_port_disable, | |
211 | .set_piomode = opti_set_piomode, | |
212 | /* .set_dmamode = opti_set_dmamode, */ | |
213 | .tf_load = ata_tf_load, | |
214 | .tf_read = ata_tf_read, | |
215 | .check_status = ata_check_status, | |
216 | .exec_command = ata_exec_command, | |
217 | .dev_select = ata_std_dev_select, | |
218 | ||
219 | .freeze = ata_bmdma_freeze, | |
220 | .thaw = ata_bmdma_thaw, | |
221 | .error_handler = opti_error_handler, | |
222 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
223 | ||
224 | .bmdma_setup = ata_bmdma_setup, | |
225 | .bmdma_start = ata_bmdma_start, | |
226 | .bmdma_stop = ata_bmdma_stop, | |
227 | .bmdma_status = ata_bmdma_status, | |
228 | ||
229 | .qc_prep = ata_qc_prep, | |
230 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 231 | |
669a5db4 JG |
232 | .data_xfer = ata_pio_data_xfer, |
233 | ||
234 | .irq_handler = ata_interrupt, | |
235 | .irq_clear = ata_bmdma_irq_clear, | |
236 | ||
237 | .port_start = ata_port_start, | |
238 | .port_stop = ata_port_stop, | |
239 | .host_stop = ata_host_stop | |
240 | }; | |
241 | ||
242 | static int opti_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
243 | { | |
244 | static struct ata_port_info info = { | |
245 | .sht = &opti_sht, | |
246 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
247 | .pio_mask = 0x1f, | |
248 | .port_ops = &opti_port_ops | |
249 | }; | |
250 | static struct ata_port_info *port_info[2] = { &info, &info }; | |
251 | static int printed_version; | |
252 | ||
253 | if (!printed_version++) | |
254 | dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n"); | |
255 | ||
256 | return ata_pci_init_one(dev, port_info, 2); | |
257 | } | |
258 | ||
259 | static const struct pci_device_id opti[] = { | |
2d2744fc JG |
260 | { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 }, |
261 | { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 }, | |
262 | ||
263 | { }, | |
669a5db4 JG |
264 | }; |
265 | ||
266 | static struct pci_driver opti_pci_driver = { | |
2d2744fc | 267 | .name = DRV_NAME, |
669a5db4 JG |
268 | .id_table = opti, |
269 | .probe = opti_init_one, | |
270 | .remove = ata_pci_remove_one | |
271 | }; | |
272 | ||
273 | static int __init opti_init(void) | |
274 | { | |
275 | return pci_register_driver(&opti_pci_driver); | |
276 | } | |
277 | ||
669a5db4 JG |
278 | static void __exit opti_exit(void) |
279 | { | |
280 | pci_unregister_driver(&opti_pci_driver); | |
281 | } | |
282 | ||
283 | ||
284 | MODULE_AUTHOR("Alan Cox"); | |
285 | MODULE_DESCRIPTION("low-level driver for Opti 621/621X"); | |
286 | MODULE_LICENSE("GPL"); | |
287 | MODULE_DEVICE_TABLE(pci, opti); | |
288 | MODULE_VERSION(DRV_VERSION); | |
289 | ||
290 | module_init(opti_init); | |
291 | module_exit(opti_exit); |