[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_hpt366.c

/*
 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
 *
 * This driver is heavily based upon:
 *
 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
 *
 *
 * TODO
 *	Look into engine reset on timeout errors. Should not be required.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt366"
#define DRV_VERSION	"0.6.11"

struct hpt_clock {
	u8	xfer_mode;
	u32	timing;
};

/* key for bus clock timings
 * bit
 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 *        register access.
 * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 *        register access.
 * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
 * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
 * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
 *        register access.
 * 28     UDMA enable.
 * 29     DMA  enable.
 * 30     PIO_MST enable. If set, the chip is in bus master mode during
 *        PIO xfer.
 * 31     FIFO enable.
 */

static const struct hpt_clock hpt366_40[] = {
	{	XFER_UDMA_4,	0x900fd943	},
	{	XFER_UDMA_3,	0x900ad943	},
	{	XFER_UDMA_2,	0x900bd943	},
	{	XFER_UDMA_1,	0x9008d943	},
	{	XFER_UDMA_0,	0x9008d943	},

	{	XFER_MW_DMA_2,	0xa008d943	},
	{	XFER_MW_DMA_1,	0xa010d955	},
	{	XFER_MW_DMA_0,	0xa010d9fc	},

	{	XFER_PIO_4,	0xc008d963	},
	{	XFER_PIO_3,	0xc010d974	},
	{	XFER_PIO_2,	0xc010d997	},
	{	XFER_PIO_1,	0xc010d9c7	},
	{	XFER_PIO_0,	0xc018d9d9	},
	{	0,		0x0120d9d9	}
};

static const struct hpt_clock hpt366_33[] = {
	{	XFER_UDMA_4,	0x90c9a731	},
	{	XFER_UDMA_3,	0x90cfa731	},
	{	XFER_UDMA_2,	0x90caa731	},
	{	XFER_UDMA_1,	0x90cba731	},
	{	XFER_UDMA_0,	0x90c8a731	},

	{	XFER_MW_DMA_2,	0xa0c8a731	},
	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
	{	XFER_MW_DMA_0,	0xa0c8a797	},

	{	XFER_PIO_4,	0xc0c8a731	},
	{	XFER_PIO_3,	0xc0c8a742	},
	{	XFER_PIO_2,	0xc0d0a753	},
	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
	{	0,		0x0120a7a7	}
};

static const struct hpt_clock hpt366_25[] = {
	{	XFER_UDMA_4,	0x90c98521	},
	{	XFER_UDMA_3,	0x90cf8521	},
	{	XFER_UDMA_2,	0x90cf8521	},
	{	XFER_UDMA_1,	0x90cb8521	},
	{	XFER_UDMA_0,	0x90cb8521	},

	{	XFER_MW_DMA_2,	0xa0ca8521	},
	{	XFER_MW_DMA_1,	0xa0ca8532	},
	{	XFER_MW_DMA_0,	0xa0ca8575	},

	{	XFER_PIO_4,	0xc0ca8521	},
	{	XFER_PIO_3,	0xc0ca8532	},
	{	XFER_PIO_2,	0xc0ca8542	},
	{	XFER_PIO_1,	0xc0d08572	},
	{	XFER_PIO_0,	0xc0d08585	},
	{	0,		0x01208585	}
};

/**
 *	hpt36x_find_mode	-	find the hpt36x timing
 *	@ap: ATA port
 *	@speed: transfer mode
 *
 *	Return the 32bit register programming information for this channel
 *	that matches the speed provided.
 */

static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
{
	struct hpt_clock *clocks = ap->host->private_data;

	while (clocks->xfer_mode) {
		if (clocks->xfer_mode == speed)
			return clocks->timing;
		clocks++;
	}
	BUG();
	return 0xffffffffU;	/* silence compiler warning */
}

static const char * const bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
	"Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
	"Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
	"Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
	"Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
	"Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

static const char * const bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char * const bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
			       const char * const list[])
{
	unsigned char model_num[ATA_ID_PROD_LEN + 1];
	int i = 0;

	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	while (list[i] != NULL) {
		if (!strcmp(list[i], model_num)) {
			pr_warn("%s is not supported for %s\n",
				modestr, list[i]);
			return 1;
		}
		i++;
	}
	return 0;
}

/**
 *	hpt366_filter	-	mode selection filter
 *	@adev: ATA device
 *
 *	Block UDMA on devices that cause trouble with this controller.
 */

static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA) {
		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
			mask &= ~ATA_MASK_UDMA;
		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
	} else if (adev->class == ATA_DEV_ATAPI)
		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);

	return mask;
}

static int hpt36x_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 ata66;

	/*
	 * Each channel of pata_hpt366 occupies separate PCI function
	 * as the primary channel and bit1 indicates the cable type.
	 */
	pci_read_config_byte(pdev, 0x5A, &ata66);
	if (ata66 & 2)
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
			    u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 addr = 0x40 + 4 * adev->devno;
	u32 mask, reg, t;

	/* determine timing mask and find matching clock entry */
	if (mode < XFER_MW_DMA_0)
		mask = 0xc1f8ffff;
	else if (mode < XFER_UDMA_0)
		mask = 0x303800ff;
	else
		mask = 0x30070000;

	t = hpt36x_find_mode(ap, mode);

	/*
	 * Combine new mode bits with old config bits and disable
	 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	 * problems handling I/O errors later.
	 */
	pci_read_config_dword(pdev, addr, &reg);
	reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
	pci_write_config_dword(pdev, addr, reg);
}

/**
 *	hpt366_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Perform PIO mode setup.
 */

static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->pio_mode);
}

/**
 *	hpt366_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 */

static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->dma_mode);
}

static struct scsi_host_template hpt36x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

/*
 *	Configuration for HPT366/68
 */

static struct ata_port_operations hpt366_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= hpt36x_cable_detect,
	.mode_filter	= hpt366_filter,
	.set_piomode	= hpt366_set_piomode,
	.set_dmamode	= hpt366_set_dmamode,
};

/**
 *	hpt36x_init_chipset	-	common chip setup
 *	@dev: PCI device
 *
 *	Perform the chip setup work that must be done at both init and
 *	resume time
 */

static void hpt36x_init_chipset(struct pci_dev *dev)
{
	u8 drive_fast;

	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);

	pci_read_config_byte(dev, 0x51, &drive_fast);
	if (drive_fast & 0x80)
		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
}

/**
 *	hpt36x_init_one		-	Initialise an HPT366/368
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Initialise an HPT36x device. There are some interesting complications
 *	here. Firstly the chip may report 366 and be one of several variants.
 *	Secondly all the timings depend on the clock for the chip which we must
 *	detect and look up
 *
 *	This is the known chip mappings. It may be missing a couple of later
 *	releases.
 *
 *	Chip version		PCI		Rev	Notes
 *	HPT366			4 (HPT366)	0	UDMA66
 *	HPT366			4 (HPT366)	1	UDMA66
 *	HPT368			4 (HPT366)	2	UDMA66
 *	HPT37x/30x		4 (HPT366)	3+	Other driver
 *
 */

static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_hpt366 = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA4,
		.port_ops = &hpt366_port_ops
	};
	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };

	void *hpriv = NULL;
	u32 reg1;
	int rc;

	rc = pcim_enable_device(dev);
	if (rc)
		return rc;

	/* May be a later chip in disguise. Check */
	/* Newer chips are not in the HPT36x driver. Ignore them */
	if (dev->revision > 2)
		return -ENODEV;

	hpt36x_init_chipset(dev);

	pci_read_config_dword(dev, 0x40,  &reg1);

	/* PCI clocking determines the ATA timing values to use */
	/* info_hpt366 is safe against re-entry so we can scribble on it */
	switch ((reg1 & 0x700) >> 8) {
	case 9:
		hpriv = &hpt366_40;
		break;
	case 5:
		hpriv = &hpt366_25;
		break;
	default:
		hpriv = &hpt366_33;
		break;
	}
	/* Now kick off ATA set up */
	return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
}

#ifdef CONFIG_PM
static int hpt36x_reinit_one(struct pci_dev *dev)
{
	struct ata_host *host = dev_get_drvdata(&dev->dev);
	int rc;

	rc = ata_pci_device_do_resume(dev);
	if (rc)
		return rc;
	hpt36x_init_chipset(dev);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id hpt36x[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
	{ },
};

static struct pci_driver hpt36x_pci_driver = {
	.name		= DRV_NAME,
	.id_table	= hpt36x,
	.probe		= hpt36x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= hpt36x_reinit_one,
#endif
};

module_pci_driver(hpt36x_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt36x);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
	3	*
	4	* This driver is heavily based upon:
	5	*
	6	* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
	7	*
	8	* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
	9	* Portions Copyright (C) 2001 Sun Microsystems, Inc.
	10	* Portions Copyright (C) 2003 Red Hat Inc
	11	*
	12	*
	13	* TODO
d817898c	14	* Look into engine reset on timeout errors. Should not be required.
669a5db4 JG	15	*/
669a5db4 JG	16
8d7b1c70	17	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
669a5db4 JG	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
	22	#include <linux/init.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/delay.h>
	25	#include <scsi/scsi_host.h>
	26	#include <linux/libata.h>
	27
	28	#define DRV_NAME "pata_hpt366"
8d7b1c70	29	#define DRV_VERSION "0.6.11"
669a5db4 JG	30
669a5db4 JG	31	struct hpt_clock {
6ecb6f25	32	u8 xfer_mode;
669a5db4 JG	33	u32 timing;
	34	};
	35
	36	/* key for bus clock timings
	37	* bit
82beb5d8 SS	38	* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
	39	* cycles = value + 1
	40	* 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
	41	* cycles = value + 1
	42	* 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
669a5db4	43	* register access.
82beb5d8	44	* 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file
669a5db4	45	* register access.
82beb5d8 SS	46	* 16:18 udma_cycle_time. Clock cycles for UDMA xfer?
	47	* 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
	48	* 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
669a5db4	49	* register access.
82beb5d8 SS	50	* 28 UDMA enable.
	51	* 29 DMA enable.
	52	* 30 PIO_MST enable. If set, the chip is in bus master mode during
	53	* PIO xfer.
669a5db4 JG	54	* 31 FIFO enable.
	55	*/
	56
	57	static const struct hpt_clock hpt366_40[] = {
	58	{ XFER_UDMA_4, 0x900fd943 },
	59	{ XFER_UDMA_3, 0x900ad943 },
	60	{ XFER_UDMA_2, 0x900bd943 },
	61	{ XFER_UDMA_1, 0x9008d943 },
	62	{ XFER_UDMA_0, 0x9008d943 },
	63
	64	{ XFER_MW_DMA_2, 0xa008d943 },
	65	{ XFER_MW_DMA_1, 0xa010d955 },
	66	{ XFER_MW_DMA_0, 0xa010d9fc },
	67
	68	{ XFER_PIO_4, 0xc008d963 },
	69	{ XFER_PIO_3, 0xc010d974 },
	70	{ XFER_PIO_2, 0xc010d997 },
	71	{ XFER_PIO_1, 0xc010d9c7 },
	72	{ XFER_PIO_0, 0xc018d9d9 },
	73	{ 0, 0x0120d9d9 }
	74	};
	75
	76	static const struct hpt_clock hpt366_33[] = {
	77	{ XFER_UDMA_4, 0x90c9a731 },
	78	{ XFER_UDMA_3, 0x90cfa731 },
	79	{ XFER_UDMA_2, 0x90caa731 },
	80	{ XFER_UDMA_1, 0x90cba731 },
	81	{ XFER_UDMA_0, 0x90c8a731 },
	82
	83	{ XFER_MW_DMA_2, 0xa0c8a731 },
	84	{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
	85	{ XFER_MW_DMA_0, 0xa0c8a797 },
	86
	87	{ XFER_PIO_4, 0xc0c8a731 },
	88	{ XFER_PIO_3, 0xc0c8a742 },
	89	{ XFER_PIO_2, 0xc0d0a753 },
	90	{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
	91	{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
	92	{ 0, 0x0120a7a7 }
	93	};
	94
	95	static const struct hpt_clock hpt366_25[] = {
	96	{ XFER_UDMA_4, 0x90c98521 },
	97	{ XFER_UDMA_3, 0x90cf8521 },
	98	{ XFER_UDMA_2, 0x90cf8521 },
	99	{ XFER_UDMA_1, 0x90cb8521 },
	100	{ XFER_UDMA_0, 0x90cb8521 },
	101
	102	{ XFER_MW_DMA_2, 0xa0ca8521 },
	103	{ XFER_MW_DMA_1, 0xa0ca8532 },
	104	{ XFER_MW_DMA_0, 0xa0ca8575 },
	105
	106	{ XFER_PIO_4, 0xc0ca8521 },
	107	{ XFER_PIO_3, 0xc0ca8532 },
	108	{ XFER_PIO_2, 0xc0ca8542 },
	109	{ XFER_PIO_1, 0xc0d08572 },
	110	{ XFER_PIO_0, 0xc0d08585 },
	111	{ 0, 0x01208585 }
	112	};
	113
dc5e44ec BZ	114	/**
	115	* hpt36x_find_mode - find the hpt36x timing
	116	* @ap: ATA port
	117	* @speed: transfer mode
	118	*
	119	* Return the 32bit register programming information for this channel
	120	* that matches the speed provided.
	121	*/
	122
	123	static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
	124	{
	125	struct hpt_clock *clocks = ap->host->private_data;
	126
	127	while (clocks->xfer_mode) {
	128	if (clocks->xfer_mode == speed)
	129	return clocks->timing;
	130	clocks++;
	131	}
	132	BUG();
	133	return 0xffffffffU; /* silence compiler warning */
	134	}
	135
28cd4b6b SS	136	static const char * const bad_ata33[] = {
	137	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
	138	"Maxtor 90845U3", "Maxtor 90650U2",
	139	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
	140	"Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	141	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
	142	"Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
669a5db4 JG	143	"Maxtor 90510D4",
669a5db4 JG	144	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
28cd4b6b SS	145	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
	146	"Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	147	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
	148	"Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
669a5db4 JG	149	NULL
	150	};
	151
28cd4b6b	152	static const char * const bad_ata66_4[] = {
669a5db4 JG	153	"IBM-DTLA-307075",
	154	"IBM-DTLA-307060",
	155	"IBM-DTLA-307045",
	156	"IBM-DTLA-307030",
	157	"IBM-DTLA-307020",
	158	"IBM-DTLA-307015",
	159	"IBM-DTLA-305040",
	160	"IBM-DTLA-305030",
	161	"IBM-DTLA-305020",
	162	"IC35L010AVER07-0",
	163	"IC35L020AVER07-0",
	164	"IC35L030AVER07-0",
	165	"IC35L040AVER07-0",
	166	"IC35L060AVER07-0",
	167	"WDC AC310200R",
	168	NULL
	169	};
	170
28cd4b6b	171	static const char * const bad_ata66_3[] = {
669a5db4 JG	172	"WDC AC310200R",
	173	NULL
	174	};
	175
28cd4b6b SS	176	static int hpt_dma_blacklisted(const struct ata_device dev, char modestr,
28cd4b6b SS	177	const char * const list[])
669a5db4	178	{
8bfa79fc	179	unsigned char model_num[ATA_ID_PROD_LEN + 1];
669a5db4 JG	180	int i = 0;
669a5db4 JG	181
8bfa79fc	182	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
669a5db4	183
8bfa79fc TH	184	while (list[i] != NULL) {
8bfa79fc TH	185	if (!strcmp(list[i], model_num)) {
8d7b1c70 JP	186	pr_warn("%s is not supported for %s\n",
8d7b1c70 JP	187	modestr, list[i]);
669a5db4 JG	188	return 1;
	189	}
	190	i++;
	191	}
	192	return 0;
	193	}
	194
	195	/**
	196	* hpt366_filter - mode selection filter
669a5db4 JG	197	* @adev: ATA device
	198	*
	199	* Block UDMA on devices that cause trouble with this controller.
	200	*/
85cd7251	201
a76b62ca	202	static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	203	{
	204	if (adev->class == ATA_DEV_ATA) {
	205	if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
	206	mask &= ~ATA_MASK_UDMA;
	207	if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
6ddd6861	208	mask &= ~(0xF8 << ATA_SHIFT_UDMA);
669a5db4	209	if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
6ddd6861	210	mask &= ~(0xF0 << ATA_SHIFT_UDMA);
3ee89f17 TH	211	} else if (adev->class == ATA_DEV_ATAPI)
	212	mask &= ~(ATA_MASK_MWDMA \| ATA_MASK_UDMA);
	213
c7087652	214	return mask;
669a5db4 JG	215	}
669a5db4 JG	216
fecfda5d AC	217	static int hpt36x_cable_detect(struct ata_port *ap)
fecfda5d AC	218	{
fecfda5d	219	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
bab5b32a	220	u8 ata66;
fecfda5d	221
bab5b32a TH	222	/*
	223	* Each channel of pata_hpt366 occupies separate PCI function
	224	* as the primary channel and bit1 indicates the cable type.
	225	*/
fecfda5d	226	pci_read_config_byte(pdev, 0x5A, &ata66);
bab5b32a	227	if (ata66 & 2)
fecfda5d AC	228	return ATA_CBL_PATA40;
	229	return ATA_CBL_PATA80;
	230	}
	231
6ecb6f25 TH	232	static void hpt366_set_mode(struct ata_port ap, struct ata_device adev,
6ecb6f25 TH	233	u8 mode)
669a5db4 JG	234	{
669a5db4 JG	235	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
859faa87	236	u32 addr = 0x40 + 4 * adev->devno;
dc5e44ec	237	u32 mask, reg, t;
85cd7251	238
6ecb6f25 TH	239	/* determine timing mask and find matching clock entry */
	240	if (mode < XFER_MW_DMA_0)
	241	mask = 0xc1f8ffff;
	242	else if (mode < XFER_UDMA_0)
	243	mask = 0x303800ff;
	244	else
	245	mask = 0x30070000;
	246
dc5e44ec	247	t = hpt36x_find_mode(ap, mode);
6ecb6f25 TH	248
	249	/*
	250	* Combine new mode bits with old config bits and disable
	251	* on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	252	* problems handling I/O errors later.
	253	*/
859faa87	254	pci_read_config_dword(pdev, addr, &reg);
dc5e44ec	255	reg = ((reg & ~mask) \| (t & mask)) & ~0xc0000000;
859faa87	256	pci_write_config_dword(pdev, addr, reg);
6ecb6f25 TH	257	}
	258
	259	/**
	260	* hpt366_set_piomode - PIO setup
	261	* @ap: ATA interface
	262	* @adev: device on the interface
	263	*
	264	* Perform PIO mode setup.
	265	*/
	266
	267	static void hpt366_set_piomode(struct ata_port ap, struct ata_device adev)
	268	{
	269	hpt366_set_mode(ap, adev, adev->pio_mode);
669a5db4 JG	270	}
	271
	272	/**
	273	* hpt366_set_dmamode - DMA timing setup
	274	* @ap: ATA interface
	275	* @adev: Device being configured
	276	*
	277	* Set up the channel for MWDMA or UDMA modes. Much the same as with
	278	* PIO, load the mode number and then set MWDMA or UDMA flag.
	279	*/
85cd7251	280
669a5db4 JG	281	static void hpt366_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	282	{
6ecb6f25	283	hpt366_set_mode(ap, adev, adev->dma_mode);
669a5db4 JG	284	}
	285
	286	static struct scsi_host_template hpt36x_sht = {
68d1d07b	287	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	288	};
	289
	290	/*
	291	* Configuration for HPT366/68
	292	*/
85cd7251	293
669a5db4	294	static struct ata_port_operations hpt366_port_ops = {
029cfd6b TH	295	.inherits = &ata_bmdma_port_ops,
	296	.cable_detect = hpt36x_cable_detect,
	297	.mode_filter = hpt366_filter,
669a5db4 JG	298	.set_piomode = hpt366_set_piomode,
669a5db4 JG	299	.set_dmamode = hpt366_set_dmamode,
85cd7251	300	};
669a5db4	301
aa54ab1e AC	302	/**
	303	* hpt36x_init_chipset - common chip setup
	304	* @dev: PCI device
	305	*
	306	* Perform the chip setup work that must be done at both init and
	307	* resume time
	308	*/
	309
	310	static void hpt36x_init_chipset(struct pci_dev *dev)
	311	{
	312	u8 drive_fast;
28cd4b6b	313
aa54ab1e AC	314	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	315	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	316	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	317	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
	318
	319	pci_read_config_byte(dev, 0x51, &drive_fast);
	320	if (drive_fast & 0x80)
	321	pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
	322	}
	323
669a5db4 JG	324	/**
	325	* hpt36x_init_one - Initialise an HPT366/368
	326	* @dev: PCI device
	327	* @id: Entry in match table
	328	*
	329	* Initialise an HPT36x device. There are some interesting complications
	330	* here. Firstly the chip may report 366 and be one of several variants.
	331	* Secondly all the timings depend on the clock for the chip which we must
	332	* detect and look up
	333	*
	334	* This is the known chip mappings. It may be missing a couple of later
	335	* releases.
	336	*
	337	* Chip version PCI Rev Notes
	338	* HPT366 4 (HPT366) 0 UDMA66
	339	* HPT366 4 (HPT366) 1 UDMA66
	340	* HPT368 4 (HPT366) 2 UDMA66
	341	* HPT37x/30x 4 (HPT366) 3+ Other driver
	342	*
	343	*/
85cd7251	344
669a5db4 JG	345	static int hpt36x_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	346	{
1626aeb8	347	static const struct ata_port_info info_hpt366 = {
1d2808fd	348	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	349	.pio_mask = ATA_PIO4,
14bdef98 EIB	350	.mwdma_mask = ATA_MWDMA2,
bf6263a8	351	.udma_mask = ATA_UDMA4,
669a5db4 JG	352	.port_ops = &hpt366_port_ops
669a5db4 JG	353	};
887125e3	354	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
669a5db4	355
887125e3	356	void *hpriv = NULL;
669a5db4	357	u32 reg1;
f08048e9 TH	358	int rc;
	359
	360	rc = pcim_enable_device(dev);
	361	if (rc)
	362	return rc;
669a5db4	363
669a5db4 JG	364	/* May be a later chip in disguise. Check */
669a5db4 JG	365	/* Newer chips are not in the HPT36x driver. Ignore them */
89d3b360 SS	366	if (dev->revision > 2)
89d3b360 SS	367	return -ENODEV;
669a5db4	368
aa54ab1e	369	hpt36x_init_chipset(dev);
669a5db4 JG	370
669a5db4 JG	371	pci_read_config_dword(dev, 0x40, &reg1);
85cd7251	372
669a5db4 JG	373	/* PCI clocking determines the ATA timing values to use */
669a5db4 JG	374	/* info_hpt366 is safe against re-entry so we can scribble on it */
28cd4b6b SS	375	switch ((reg1 & 0x700) >> 8) {
	376	case 9:
	377	hpriv = &hpt366_40;
	378	break;
	379	case 5:
	380	hpriv = &hpt366_25;
	381	break;
	382	default:
	383	hpriv = &hpt366_33;
	384	break;
669a5db4 JG	385	}
669a5db4 JG	386	/* Now kick off ATA set up */
1c5afdf7	387	return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
669a5db4 JG	388	}
669a5db4 JG	389
438ac6d5	390	#ifdef CONFIG_PM
aa54ab1e AC	391	static int hpt36x_reinit_one(struct pci_dev *dev)
aa54ab1e AC	392	{
f08048e9 TH	393	struct ata_host *host = dev_get_drvdata(&dev->dev);
	394	int rc;
	395
	396	rc = ata_pci_device_do_resume(dev);
	397	if (rc)
	398	return rc;
aa54ab1e	399	hpt36x_init_chipset(dev);
f08048e9 TH	400	ata_host_resume(host);
f08048e9 TH	401	return 0;
aa54ab1e	402	}
438ac6d5	403	#endif
aa54ab1e	404
2d2744fc JG	405	static const struct pci_device_id hpt36x[] = {
2d2744fc JG	406	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
2d2744fc	407	{ },
669a5db4 JG	408	};
	409
	410	static struct pci_driver hpt36x_pci_driver = {
28cd4b6b	411	.name = DRV_NAME,
669a5db4	412	.id_table = hpt36x,
28cd4b6b	413	.probe = hpt36x_init_one,
aa54ab1e	414	.remove = ata_pci_remove_one,
438ac6d5	415	#ifdef CONFIG_PM
aa54ab1e AC	416	.suspend = ata_pci_device_suspend,
aa54ab1e AC	417	.resume = hpt36x_reinit_one,
438ac6d5	418	#endif
669a5db4 JG	419	};
669a5db4 JG	420
2fc75da0	421	module_pci_driver(hpt36x_pci_driver);
669a5db4	422
669a5db4 JG	423	MODULE_AUTHOR("Alan Cox");
	424	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
	425	MODULE_LICENSE("GPL");
	426	MODULE_DEVICE_TABLE(pci, hpt36x);
	427	MODULE_VERSION(DRV_VERSION);