[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_cs5535.c

/*
 * pata-cs5535.c 	- CS5535 PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
 * made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de
 * and Alexander Kiausch <alex.kiausch@t-online.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * Loosely based on the piix & svwks drivers.
 *
 * Documentation:
 *	Available from AMD web site.
 * TODO
 *	Review errata to see if serializing is neccessary
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <asm/msr.h>

#define DRV_NAME	"cs5535"
#define DRV_VERSION	"0.2.11"

/*
 *	The Geode (Aka Athlon GX now) uses an internal MSR based
 *	bus system for control. Demented but there you go.
 */

#define MSR_ATAC_BASE    	0x51300000
#define ATAC_GLD_MSR_CAP 	(MSR_ATAC_BASE+0)
#define ATAC_GLD_MSR_CONFIG    (MSR_ATAC_BASE+0x01)
#define ATAC_GLD_MSR_SMI       (MSR_ATAC_BASE+0x02)
#define ATAC_GLD_MSR_ERROR     (MSR_ATAC_BASE+0x03)
#define ATAC_GLD_MSR_PM        (MSR_ATAC_BASE+0x04)
#define ATAC_GLD_MSR_DIAG      (MSR_ATAC_BASE+0x05)
#define ATAC_IO_BAR            (MSR_ATAC_BASE+0x08)
#define ATAC_RESET             (MSR_ATAC_BASE+0x10)
#define ATAC_CH0D0_PIO         (MSR_ATAC_BASE+0x20)
#define ATAC_CH0D0_DMA         (MSR_ATAC_BASE+0x21)
#define ATAC_CH0D1_PIO         (MSR_ATAC_BASE+0x22)
#define ATAC_CH0D1_DMA         (MSR_ATAC_BASE+0x23)
#define ATAC_PCI_ABRTERR       (MSR_ATAC_BASE+0x24)

#define ATAC_BM0_CMD_PRIM      0x00
#define ATAC_BM0_STS_PRIM      0x02
#define ATAC_BM0_PRD           0x04

#define CS5535_CABLE_DETECT    0x48

#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL)==0x00009172 )

/**
 *	cs5535_cable_detect	-	detect cable type
 *	@ap: Port to detect on
 *	@deadline: deadline jiffies for the operation
 *
 *	Perform cable detection for ATA66 capable cable. Return a libata
 *	cable type.
 */

static int cs5535_cable_detect(struct ata_port *ap)
{
	u8 cable;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
	if (cable & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

/**
 *	cs5535_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Set our PIO requirements. The CS5535 is pretty clean about all this
 */

static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const u16 pio_timings[5] = {
		0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
	};
	static const u16 pio_cmd_timings[5] = {
		0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
	};
	u32 reg, dummy;
	struct ata_device *pair = ata_dev_pair(adev);

	int mode = adev->pio_mode - XFER_PIO_0;
	int cmdmode = mode;

	/* Command timing has to be for the lowest of the pair of devices */
	if (pair) {
		int pairmode = pair->pio_mode - XFER_PIO_0;
		cmdmode = min(mode, pairmode);
		/* Write the other drive timing register if it changed */
		if (cmdmode < pairmode)
			wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
				pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode], 0);
	}
	/* Write the drive timing register */
	wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
		pio_cmd_timings[cmdmode] << 16 | pio_timings[mode], 0);

	/* Set the PIO "format 1" bit in the DMA timing register */
	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
}

/**
 *	cs5535_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 */

static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u32 udma_timings[5] = {
		0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
	};
	static const u32 mwdma_timings[3] = {
		0x7F0FFFF3, 0x7F035352, 0x7F024241
	};
	u32 reg, dummy;
	int mode = adev->dma_mode;

	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	reg &= 0x80000000UL;
	if (mode >= XFER_UDMA_0)
		reg |= udma_timings[mode - XFER_UDMA_0];
	else
		reg |= mwdma_timings[mode - XFER_MW_DMA_0];
	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
}

static struct scsi_host_template cs5535_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations cs5535_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= cs5535_set_piomode,
	.set_dmamode	= cs5535_set_dmamode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= cs5535_cable_detect,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

/**
 *	cs5535_init_one		-	Initialise a CS5530
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Install a driver for the newly found CS5530 companion chip. Most of
 *	this is just housekeeping. We have to set the chip up correctly and
 *	turn off various bits of emulation magic.
 */

static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.sht = &cs5535_sht,
		.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x1f,
		.port_ops = &cs5535_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };

	u32 timings, dummy;

	/* Check the BIOS set the initial timing clock. If not set the
	   timings for PIO0 */
	rdmsr(ATAC_CH0D0_PIO, timings, dummy);
	if (CS5535_BAD_PIO(timings))
		wrmsr(ATAC_CH0D0_PIO, 0xF7F4F7F4UL, 0);
	rdmsr(ATAC_CH0D1_PIO, timings, dummy);
	if (CS5535_BAD_PIO(timings))
		wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0);
	return ata_pci_init_one(dev, ppi);
}

static const struct pci_device_id cs5535[] = {
	{ PCI_VDEVICE(NS, 0x002D), },

	{ },
};

static struct pci_driver cs5535_pci_driver = {
	.name		= DRV_NAME,
	.id_table	= cs5535,
	.probe 		= cs5535_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init cs5535_init(void)
{
	return pci_register_driver(&cs5535_pci_driver);
}

static void __exit cs5535_exit(void)
{
	pci_unregister_driver(&cs5535_pci_driver);
}

MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
MODULE_DESCRIPTION("low-level driver for the NS/AMD 5530");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cs5535);
MODULE_VERSION(DRV_VERSION);

module_init(cs5535_init);
module_exit(cs5535_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata-cs5535.c - CS5535 PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
	7	* made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de
	8	* and Alexander Kiausch <alex.kiausch@t-online.de>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* Loosely based on the piix & svwks drivers.
	24	*
	25	* Documentation:
	26	* Available from AMD web site.
	27	* TODO
	28	* Review errata to see if serializing is neccessary
	29	*/
	30
	31	#include <linux/kernel.h>
	32	#include <linux/module.h>
	33	#include <linux/pci.h>
	34	#include <linux/init.h>
	35	#include <linux/blkdev.h>
	36	#include <linux/delay.h>
	37	#include <scsi/scsi_host.h>
	38	#include <linux/libata.h>
	39	#include <asm/msr.h>
	40
	41	#define DRV_NAME "cs5535"
30ced0f0	42	#define DRV_VERSION "0.2.11"
669a5db4 JG	43
	44	/*
	45	* The Geode (Aka Athlon GX now) uses an internal MSR based
	46	* bus system for control. Demented but there you go.
	47	*/
	48
	49	#define MSR_ATAC_BASE 0x51300000
	50	#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
	51	#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
	52	#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
	53	#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
	54	#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
	55	#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
	56	#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
	57	#define ATAC_RESET (MSR_ATAC_BASE+0x10)
	58	#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
	59	#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
	60	#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
	61	#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
	62	#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
	63
	64	#define ATAC_BM0_CMD_PRIM 0x00
	65	#define ATAC_BM0_STS_PRIM 0x02
	66	#define ATAC_BM0_PRD 0x04
	67
	68	#define CS5535_CABLE_DETECT 0x48
	69
	70	#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL)==0x00009172 )
	71
	72	/**
eb4a2c7f	73	* cs5535_cable_detect - detect cable type
669a5db4	74	* @ap: Port to detect on
d4b2bab4	75	* @deadline: deadline jiffies for the operation
669a5db4 JG	76	*
	77	* Perform cable detection for ATA66 capable cable. Return a libata
	78	* cable type.
	79	*/
	80
eb4a2c7f	81	static int cs5535_cable_detect(struct ata_port *ap)
669a5db4 JG	82	{
	83	u8 cable;
	84	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	85
	86	pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
	87	if (cable & 1)
eb4a2c7f	88	return ATA_CBL_PATA80;
669a5db4	89	else
eb4a2c7f	90	return ATA_CBL_PATA40;
669a5db4 JG	91	}
	92
	93	/**
	94	* cs5535_set_piomode - PIO setup
	95	* @ap: ATA interface
	96	* @adev: device on the interface
	97	*
	98	* Set our PIO requirements. The CS5535 is pretty clean about all this
	99	*/
	100
	101	static void cs5535_set_piomode(struct ata_port ap, struct ata_device adev)
	102	{
	103	static const u16 pio_timings[5] = {
	104	0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
	105	};
	106	static const u16 pio_cmd_timings[5] = {
	107	0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
	108	};
	109	u32 reg, dummy;
	110	struct ata_device *pair = ata_dev_pair(adev);
	111
	112	int mode = adev->pio_mode - XFER_PIO_0;
	113	int cmdmode = mode;
	114
	115	/* Command timing has to be for the lowest of the pair of devices */
	116	if (pair) {
	117	int pairmode = pair->pio_mode - XFER_PIO_0;
	118	cmdmode = min(mode, pairmode);
	119	/* Write the other drive timing register if it changed */
	120	if (cmdmode < pairmode)
	121	wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
	122	pio_cmd_timings[cmdmode] << 16 \| pio_timings[pairmode], 0);
	123	}
	124	/* Write the drive timing register */
	125	wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
	126	pio_cmd_timings[cmdmode] << 16 \| pio_timings[mode], 0);
	127
	128	/* Set the PIO "format 1" bit in the DMA timing register */
	129	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	130	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg \| 0x80000000UL, 0);
	131	}
	132
	133	/**
	134	* cs5535_set_dmamode - DMA timing setup
	135	* @ap: ATA interface
	136	* @adev: Device being configured
	137	*
	138	*/
	139
	140	static void cs5535_set_dmamode(struct ata_port ap, struct ata_device adev)
	141	{
	142	static const u32 udma_timings[5] = {
	143	0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
	144	};
	145	static const u32 mwdma_timings[3] = {
	146	0x7F0FFFF3, 0x7F035352, 0x7F024241
	147	};
	148	u32 reg, dummy;
	149	int mode = adev->dma_mode;
	150
	151	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	152	reg &= 0x80000000UL;
	153	if (mode >= XFER_UDMA_0)
	154	reg \|= udma_timings[mode - XFER_UDMA_0];
155	else
156	reg \|= mwdma_timings[mode - XFER_MW_DMA_0];
157	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
158	}
159
160	static struct scsi_host_template cs5535_sht = {
161	.module = THIS_MODULE,
162	.name = DRV_NAME,
163	.ioctl = ata_scsi_ioctl,
164	.queuecommand = ata_scsi_queuecmd,
165	.can_queue = ATA_DEF_QUEUE,
166	.this_id = ATA_SHT_THIS_ID,
167	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	168	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	169	.emulated = ATA_SHT_EMULATED,
	170	.use_clustering = ATA_SHT_USE_CLUSTERING,
	171	.proc_name = DRV_NAME,
	172	.dma_boundary = ATA_DMA_BOUNDARY,
	173	.slave_configure = ata_scsi_slave_config,
afdfe899	174	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	175	.bios_param = ata_std_bios_param,
	176	};
	177
	178	static struct ata_port_operations cs5535_port_ops = {
	179	.port_disable = ata_port_disable,
	180	.set_piomode = cs5535_set_piomode,
	181	.set_dmamode = cs5535_set_dmamode,
	182	.mode_filter = ata_pci_default_filter,
	183
	184	.tf_load = ata_tf_load,
	185	.tf_read = ata_tf_read,
	186	.check_status = ata_check_status,
	187	.exec_command = ata_exec_command,
	188	.dev_select = ata_std_dev_select,
	189
	190	.freeze = ata_bmdma_freeze,
	191	.thaw = ata_bmdma_thaw,
eb4a2c7f	192	.error_handler = ata_bmdma_error_handler,
669a5db4	193	.post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f	194	.cable_detect = cs5535_cable_detect,
669a5db4 JG	195
	196	.bmdma_setup = ata_bmdma_setup,
	197	.bmdma_start = ata_bmdma_start,
	198	.bmdma_stop = ata_bmdma_stop,
	199	.bmdma_status = ata_bmdma_status,
	200
	201	.qc_prep = ata_qc_prep,
	202	.qc_issue = ata_qc_issue_prot,
bda30288	203
0d5ff566	204	.data_xfer = ata_data_xfer,
669a5db4 JG	205
	206	.irq_handler = ata_interrupt,
	207	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	208	.irq_on = ata_irq_on,
246ce3b6 AI	209	.irq_ack = ata_irq_ack,
669a5db4 JG	210
669a5db4 JG	211	.port_start = ata_port_start,
669a5db4 JG	212	};
	213
	214	/**
	215	* cs5535_init_one - Initialise a CS5530
	216	* @dev: PCI device
	217	* @id: Entry in match table
	218	*
	219	* Install a driver for the newly found CS5530 companion chip. Most of
	220	* this is just housekeeping. We have to set the chip up correctly and
	221	* turn off various bits of emulation magic.
	222	*/
	223
	224	static int cs5535_init_one(struct pci_dev dev, const struct pci_device_id id)
	225	{
1626aeb8	226	static const struct ata_port_info info = {
669a5db4 JG	227	.sht = &cs5535_sht,
	228	.flags = ATA_FLAG_SLAVE_POSS\|ATA_FLAG_SRST,
	229	.pio_mask = 0x1f,
	230	.mwdma_mask = 0x07,
	231	.udma_mask = 0x1f,
	232	.port_ops = &cs5535_port_ops
	233	};
1626aeb8	234	const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
669a5db4 JG	235
	236	u32 timings, dummy;
	237
	238	/* Check the BIOS set the initial timing clock. If not set the
	239	timings for PIO0 */
	240	rdmsr(ATAC_CH0D0_PIO, timings, dummy);
	241	if (CS5535_BAD_PIO(timings))
	242	wrmsr(ATAC_CH0D0_PIO, 0xF7F4F7F4UL, 0);
	243	rdmsr(ATAC_CH0D1_PIO, timings, dummy);
	244	if (CS5535_BAD_PIO(timings))
	245	wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0);
1626aeb8	246	return ata_pci_init_one(dev, ppi);
669a5db4 JG	247	}
669a5db4 JG	248
2d2744fc JG	249	static const struct pci_device_id cs5535[] = {
	250	{ PCI_VDEVICE(NS, 0x002D), },
	251
	252	{ },
669a5db4 JG	253	};
	254
	255	static struct pci_driver cs5535_pci_driver = {
	256	.name = DRV_NAME,
	257	.id_table = cs5535,
	258	.probe = cs5535_init_one,
3ac551a6	259	.remove = ata_pci_remove_one,
438ac6d5	260	#ifdef CONFIG_PM
30ced0f0 AC	261	.suspend = ata_pci_device_suspend,
30ced0f0 AC	262	.resume = ata_pci_device_resume,
438ac6d5	263	#endif
669a5db4 JG	264	};
	265
	266	static int __init cs5535_init(void)
	267	{
	268	return pci_register_driver(&cs5535_pci_driver);
	269	}
	270
669a5db4 JG	271	static void __exit cs5535_exit(void)
	272	{
	273	pci_unregister_driver(&cs5535_pci_driver);
	274	}
	275
669a5db4 JG	276	MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
	277	MODULE_DESCRIPTION("low-level driver for the NS/AMD 5530");
	278	MODULE_LICENSE("GPL");
	279	MODULE_DEVICE_TABLE(pci, cs5535);
	280	MODULE_VERSION(DRV_VERSION);
	281
	282	module_init(cs5535_init);
	283	module_exit(cs5535_exit);