[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_cs5530.c

/*
 * pata-cs5530.c 	- CS5530 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * based upon cs5530.c by Mark Lord.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * Loosely based on the piix & svwks drivers.
 *
 * Documentation:
 *	Available from AMD web site.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/dmi.h>

#define DRV_NAME	"pata_cs5530"
#define DRV_VERSION	"0.7.2"

static void __iomem *cs5530_port_base(struct ata_port *ap)
{
	unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;

	return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no);
}

/**
 *	cs5530_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Set our PIO requirements. This is fairly simple on the CS5530
 *	chips.
 */

static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const unsigned int cs5530_pio_timings[2][5] = {
		{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
		{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	};
	void __iomem *base = cs5530_port_base(ap);
	u32 tuning;
	int format;

	/* Find out which table to use */
	tuning = ioread32(base + 0x04);
	format = (tuning & 0x80000000UL) ? 1 : 0;

	/* Now load the right timing register */
	if (adev->devno)
		base += 0x08;

	iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
}

/**
 *	cs5530_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	We cannot mix MWDMA and UDMA without reloading timings each switch
 *	master to slave. We track the last DMA setup in order to minimise
 *	reloads.
 */

static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	void __iomem *base = cs5530_port_base(ap);
	u32 tuning, timing = 0;
	u8 reg;

	/* Find out which table to use */
	tuning = ioread32(base + 0x04);

	switch(adev->dma_mode) {
		case XFER_UDMA_0:
			timing  = 0x00921250;break;
		case XFER_UDMA_1:
			timing  = 0x00911140;break;
		case XFER_UDMA_2:
			timing  = 0x00911030;break;
		case XFER_MW_DMA_0:
			timing  = 0x00077771;break;
		case XFER_MW_DMA_1:
			timing  = 0x00012121;break;
		case XFER_MW_DMA_2:
			timing  = 0x00002020;break;
		default:
			BUG();
	}
	/* Merge in the PIO format bit */
	timing |= (tuning & 0x80000000UL);
	if (adev->devno == 0) /* Master */
		iowrite32(timing, base + 0x04);
	else {
		if (timing & 0x00100000)
			tuning |= 0x00100000;	/* UDMA for both */
		else
			tuning &= ~0x00100000;	/* MWDMA for both */
		iowrite32(tuning, base + 0x04);
		iowrite32(timing, base + 0x0C);
	}

	/* Set the DMA capable bit in the BMDMA area */
	reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
	reg |= (1 << (5 + adev->devno));
	iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);

	/* Remember the last DMA setup we did */

	ap->private_data = adev;
}

/**
 *	cs5530_qc_issue_prot	-	command issue
 *	@qc: command pending
 *
 *	Called when the libata layer is about to issue a command. We wrap
 *	this interface so that we can load the correct ATA timings if
 *	neccessary.  Specifically we have a problem that there is only
 *	one MWDMA/UDMA bit.
 */

static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_device *prev = ap->private_data;

	/* See if the DMA settings could be wrong */
	if (adev->dma_mode != 0 && adev != prev && prev != NULL) {
		/* Maybe, but do the channels match MWDMA/UDMA ? */
		if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) ||
		    (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0))
		    	/* Switch the mode bits */
		    	cs5530_set_dmamode(ap, adev);
	}

	return ata_qc_issue_prot(qc);
}

static struct scsi_host_template cs5530_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations cs5530_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= cs5530_set_piomode,
	.set_dmamode	= cs5530_set_dmamode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= ata_cable_40wire,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= cs5530_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static struct dmi_system_id palmax_dmi_table[] = {
	{
		.ident = "Palmax PD1100",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
			DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
		},
	},
	{ }
};

static int cs5530_is_palmax(void)
{
	if (dmi_check_system(palmax_dmi_table)) {
		printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
		return 1;
	}
	return 0;
}


/**
 *	cs5530_init_chip	-	Chipset init
 *
 *	Perform the chip initialisation work that is shared between both
 *	setup and resume paths
 */

static int cs5530_init_chip(void)
{
	struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL;

	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
		switch (dev->device) {
			case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
				master_0 = pci_dev_get(dev);
				break;
			case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
				cs5530_0 = pci_dev_get(dev);
				break;
		}
	}
	if (!master_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
		goto fail_put;
	}
	if (!cs5530_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
		goto fail_put;
	}

	pci_set_master(cs5530_0);
	pci_set_mwi(cs5530_0);

	/*
	 * Set PCI CacheLineSize to 16-bytes:
	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	 *
	 * Note: This value is constant because the 5530 is only a Geode companion
	 */

	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);

	/*
	 * Disable trapping of UDMA register accesses (Win98 hack):
	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	 */

	pci_write_config_word(cs5530_0, 0xd0, 0x5006);

	/*
	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	 * The other settings are what is necessary to get the register
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x40, 0x1e);

	/*
	 * Set max PCI burst size (16-bytes seems to work best):
	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)
	 *	all others: clear bit-1 at 0x41, and do:
	 *	  128bytes: OR 0x00 at 0x41
	 *	  256bytes: OR 0x04 at 0x41
	 *	  512bytes: OR 0x08 at 0x41
	 *	 1024bytes: OR 0x0c at 0x41
	 */

	pci_write_config_byte(master_0, 0x41, 0x14);

	/*
	 * These settings are necessary to get the chip
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x42, 0x00);
	pci_write_config_byte(master_0, 0x43, 0xc1);

	pci_dev_put(master_0);
	pci_dev_put(cs5530_0);
	return 0;
fail_put:
	if (master_0)
		pci_dev_put(master_0);
	if (cs5530_0)
		pci_dev_put(cs5530_0);
	return -ENODEV;
}

/**
 *	cs5530_init_one		-	Initialise a CS5530
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Install a driver for the newly found CS5530 companion chip. Most of
 *	this is just housekeeping. We have to set the chip up correctly and
 *	turn off various bits of emulation magic.
 */

static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.sht = &cs5530_sht,
		.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x07,
		.port_ops = &cs5530_port_ops
	};
	/* The docking connector doesn't do UDMA, and it seems not MWDMA */
	static const struct ata_port_info info_palmax_secondary = {
		.sht = &cs5530_sht,
		.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.port_ops = &cs5530_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, NULL };

	/* Chip initialisation */
	if (cs5530_init_chip())
		return -ENODEV;

	if (cs5530_is_palmax())
		ppi[1] = &info_palmax_secondary;

	/* Now kick off ATA set up */
	return ata_pci_init_one(pdev, ppi);
}

#ifdef CONFIG_PM
static int cs5530_reinit_one(struct pci_dev *pdev)
{
	/* If we fail on resume we are doomed */
	if (cs5530_init_chip())
		BUG();
	return ata_pci_device_resume(pdev);
}
#endif /* CONFIG_PM */

static const struct pci_device_id cs5530[] = {
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },

	{ },
};

static struct pci_driver cs5530_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cs5530,
	.probe 		= cs5530_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= cs5530_reinit_one,
#endif
};

static int __init cs5530_init(void)
{
	return pci_register_driver(&cs5530_pci_driver);
}

static void __exit cs5530_exit(void)
{
	pci_unregister_driver(&cs5530_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cs5530);
MODULE_VERSION(DRV_VERSION);

module_init(cs5530_init);
module_exit(cs5530_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata-cs5530.c - CS5530 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* based upon cs5530.c by Mark Lord.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*
	21	* Loosely based on the piix & svwks drivers.
	22	*
	23	* Documentation:
	24	* Available from AMD web site.
	25	*/
	26
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
	29	#include <linux/pci.h>
	30	#include <linux/init.h>
	31	#include <linux/blkdev.h>
	32	#include <linux/delay.h>
	33	#include <scsi/scsi_host.h>
	34	#include <linux/libata.h>
	35	#include <linux/dmi.h>
	36
	37	#define DRV_NAME "pata_cs5530"
cb48cab7	38	#define DRV_VERSION "0.7.2"
669a5db4	39
0d5ff566 TH	40	static void __iomem cs5530_port_base(struct ata_port ap)
	41	{
	42	unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;
	43
	44	return (void __iomem )((bmdma & ~0x0F) + 0x20 + 0x10 ap->port_no);
	45	}
	46
669a5db4 JG	47	/**
	48	* cs5530_set_piomode - PIO setup
	49	* @ap: ATA interface
	50	* @adev: device on the interface
	51	*
	52	* Set our PIO requirements. This is fairly simple on the CS5530
	53	* chips.
	54	*/
	55
	56	static void cs5530_set_piomode(struct ata_port ap, struct ata_device adev)
	57	{
	58	static const unsigned int cs5530_pio_timings[2][5] = {
	59	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	60	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	61	};
0d5ff566	62	void __iomem *base = cs5530_port_base(ap);
669a5db4 JG	63	u32 tuning;
	64	int format;
	65
	66	/* Find out which table to use */
0d5ff566	67	tuning = ioread32(base + 0x04);
669a5db4 JG	68	format = (tuning & 0x80000000UL) ? 1 : 0;
	69
	70	/* Now load the right timing register */
	71	if (adev->devno)
	72	base += 0x08;
	73
0d5ff566	74	iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
669a5db4 JG	75	}
	76
	77	/**
	78	* cs5530_set_dmamode - DMA timing setup
	79	* @ap: ATA interface
	80	* @adev: Device being configured
	81	*
	82	* We cannot mix MWDMA and UDMA without reloading timings each switch
	83	* master to slave. We track the last DMA setup in order to minimise
	84	* reloads.
	85	*/
	86
	87	static void cs5530_set_dmamode(struct ata_port ap, struct ata_device adev)
	88	{
0d5ff566	89	void __iomem *base = cs5530_port_base(ap);
669a5db4 JG	90	u32 tuning, timing = 0;
	91	u8 reg;
	92
	93	/* Find out which table to use */
0d5ff566	94	tuning = ioread32(base + 0x04);
669a5db4 JG	95
	96	switch(adev->dma_mode) {
	97	case XFER_UDMA_0:
	98	timing = 0x00921250;break;
	99	case XFER_UDMA_1:
	100	timing = 0x00911140;break;
	101	case XFER_UDMA_2:
	102	timing = 0x00911030;break;
	103	case XFER_MW_DMA_0:
	104	timing = 0x00077771;break;
	105	case XFER_MW_DMA_1:
	106	timing = 0x00012121;break;
	107	case XFER_MW_DMA_2:
	108	timing = 0x00002020;break;
	109	default:
	110	BUG();
	111	}
	112	/* Merge in the PIO format bit */
	113	timing \|= (tuning & 0x80000000UL);
	114	if (adev->devno == 0) /* Master */
0d5ff566	115	iowrite32(timing, base + 0x04);
669a5db4 JG	116	else {
	117	if (timing & 0x00100000)
	118	tuning \|= 0x00100000; /* UDMA for both */
	119	else
	120	tuning &= ~0x00100000; /* MWDMA for both */
0d5ff566 TH	121	iowrite32(tuning, base + 0x04);
0d5ff566 TH	122	iowrite32(timing, base + 0x0C);
669a5db4 JG	123	}
	124
	125	/* Set the DMA capable bit in the BMDMA area */
0d5ff566	126	reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
669a5db4	127	reg \|= (1 << (5 + adev->devno));
0d5ff566	128	iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
669a5db4 JG	129
	130	/* Remember the last DMA setup we did */
	131
	132	ap->private_data = adev;
	133	}
	134
	135	/**
	136	* cs5530_qc_issue_prot - command issue
	137	* @qc: command pending
	138	*
	139	* Called when the libata layer is about to issue a command. We wrap
	140	* this interface so that we can load the correct ATA timings if
	141	* neccessary. Specifically we have a problem that there is only
	142	* one MWDMA/UDMA bit.
	143	*/
	144
	145	static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc)
	146	{
	147	struct ata_port *ap = qc->ap;
	148	struct ata_device *adev = qc->dev;
	149	struct ata_device *prev = ap->private_data;
	150
	151	/* See if the DMA settings could be wrong */
	152	if (adev->dma_mode != 0 && adev != prev && prev != NULL) {
	153	/* Maybe, but do the channels match MWDMA/UDMA ? */
	154	if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) \|\|
	155	(adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0))
	156	/* Switch the mode bits */
	157	cs5530_set_dmamode(ap, adev);
	158	}
	159
	160	return ata_qc_issue_prot(qc);
	161	}
	162
669a5db4 JG	163	static struct scsi_host_template cs5530_sht = {
	164	.module = THIS_MODULE,
	165	.name = DRV_NAME,
	166	.ioctl = ata_scsi_ioctl,
	167	.queuecommand = ata_scsi_queuecmd,
	168	.can_queue = ATA_DEF_QUEUE,
	169	.this_id = ATA_SHT_THIS_ID,
	170	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	171	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	172	.emulated = ATA_SHT_EMULATED,
	173	.use_clustering = ATA_SHT_USE_CLUSTERING,
	174	.proc_name = DRV_NAME,
	175	.dma_boundary = ATA_DMA_BOUNDARY,
	176	.slave_configure = ata_scsi_slave_config,
afdfe899	177	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	178	.bios_param = ata_std_bios_param,
	179	};
	180
	181	static struct ata_port_operations cs5530_port_ops = {
	182	.port_disable = ata_port_disable,
	183	.set_piomode = cs5530_set_piomode,
	184	.set_dmamode = cs5530_set_dmamode,
	185	.mode_filter = ata_pci_default_filter,
	186
	187	.tf_load = ata_tf_load,
	188	.tf_read = ata_tf_read,
	189	.check_status = ata_check_status,
	190	.exec_command = ata_exec_command,
	191	.dev_select = ata_std_dev_select,
	192
	193	.bmdma_setup = ata_bmdma_setup,
	194	.bmdma_start = ata_bmdma_start,
	195	.bmdma_stop = ata_bmdma_stop,
	196	.bmdma_status = ata_bmdma_status,
	197
	198	.freeze = ata_bmdma_freeze,
	199	.thaw = ata_bmdma_thaw,
a73984a0	200	.error_handler = ata_bmdma_error_handler,
669a5db4	201	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	202	.cable_detect = ata_cable_40wire,
669a5db4 JG	203
	204	.qc_prep = ata_qc_prep,
	205	.qc_issue = cs5530_qc_issue_prot,
bda30288	206
0d5ff566	207	.data_xfer = ata_data_xfer,
669a5db4 JG	208
	209	.irq_handler = ata_interrupt,
	210	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	211	.irq_on = ata_irq_on,
246ce3b6 AI	212	.irq_ack = ata_irq_ack,
669a5db4 JG	213
669a5db4 JG	214	.port_start = ata_port_start,
669a5db4 JG	215	};
	216
	217	static struct dmi_system_id palmax_dmi_table[] = {
	218	{
	219	.ident = "Palmax PD1100",
	220	.matches = {
	221	DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
	222	DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
	223	},
	224	},
	225	{ }
	226	};
	227
	228	static int cs5530_is_palmax(void)
	229	{
	230	if (dmi_check_system(palmax_dmi_table)) {
	231	printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
	232	return 1;
	233	}
	234	return 0;
	235	}
	236
f7e37ba8	237
669a5db4	238	/**
f7e37ba8	239	* cs5530_init_chip - Chipset init
669a5db4	240	*
f7e37ba8 AC	241	* Perform the chip initialisation work that is shared between both
f7e37ba8 AC	242	* setup and resume paths
669a5db4	243	*/
f20b16ff	244
f7e37ba8	245	static int cs5530_init_chip(void)
669a5db4	246	{
f7e37ba8	247	struct pci_dev master_0 = NULL, cs5530_0 = NULL, *dev = NULL;
669a5db4	248
669a5db4 JG	249	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
	250	switch (dev->device) {
	251	case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
	252	master_0 = pci_dev_get(dev);
	253	break;
	254	case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
	255	cs5530_0 = pci_dev_get(dev);
	256	break;
	257	}
	258	}
	259	if (!master_0) {
	260	printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
	261	goto fail_put;
	262	}
	263	if (!cs5530_0) {
	264	printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
	265	goto fail_put;
	266	}
	267
	268	pci_set_master(cs5530_0);
f7e37ba8	269	pci_set_mwi(cs5530_0);
669a5db4 JG	270
	271	/*
	272	* Set PCI CacheLineSize to 16-bytes:
	273	* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	274	*
	275	* Note: This value is constant because the 5530 is only a Geode companion
	276	*/
	277
	278	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
	279
	280	/*
	281	* Disable trapping of UDMA register accesses (Win98 hack):
	282	* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	283	*/
	284
	285	pci_write_config_word(cs5530_0, 0xd0, 0x5006);
	286
	287	/*
	288	* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	289	* The other settings are what is necessary to get the register
	290	* into a sane state for IDE DMA operation.
	291	*/
	292
	293	pci_write_config_byte(master_0, 0x40, 0x1e);
	294
	295	/*
	296	* Set max PCI burst size (16-bytes seems to work best):
	297	* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
	298	* all others: clear bit-1 at 0x41, and do:
	299	* 128bytes: OR 0x00 at 0x41
	300	* 256bytes: OR 0x04 at 0x41
	301	* 512bytes: OR 0x08 at 0x41
	302	* 1024bytes: OR 0x0c at 0x41
	303	*/
	304
	305	pci_write_config_byte(master_0, 0x41, 0x14);
	306
	307	/*
	308	* These settings are necessary to get the chip
	309	* into a sane state for IDE DMA operation.
	310	*/
	311
	312	pci_write_config_byte(master_0, 0x42, 0x00);
	313	pci_write_config_byte(master_0, 0x43, 0xc1);
	314
	315	pci_dev_put(master_0);
	316	pci_dev_put(cs5530_0);
f7e37ba8	317	return 0;
669a5db4 JG	318	fail_put:
	319	if (master_0)
	320	pci_dev_put(master_0);
	321	if (cs5530_0)
	322	pci_dev_put(cs5530_0);
	323	return -ENODEV;
	324	}
	325
f7e37ba8 AC	326	/**
	327	* cs5530_init_one - Initialise a CS5530
	328	* @dev: PCI device
	329	* @id: Entry in match table
	330	*
	331	* Install a driver for the newly found CS5530 companion chip. Most of
	332	* this is just housekeeping. We have to set the chip up correctly and
	333	* turn off various bits of emulation magic.
	334	*/
	335
	336	static int cs5530_init_one(struct pci_dev pdev, const struct pci_device_id id)
	337	{
1626aeb8	338	static const struct ata_port_info info = {
f7e37ba8 AC	339	.sht = &cs5530_sht,
	340	.flags = ATA_FLAG_SLAVE_POSS\|ATA_FLAG_SRST,
	341	.pio_mask = 0x1f,
	342	.mwdma_mask = 0x07,
	343	.udma_mask = 0x07,
	344	.port_ops = &cs5530_port_ops
	345	};
	346	/* The docking connector doesn't do UDMA, and it seems not MWDMA */
1626aeb8	347	static const struct ata_port_info info_palmax_secondary = {
f7e37ba8 AC	348	.sht = &cs5530_sht,
	349	.flags = ATA_FLAG_SLAVE_POSS\|ATA_FLAG_SRST,
	350	.pio_mask = 0x1f,
	351	.port_ops = &cs5530_port_ops
	352	};
1626aeb8	353	const struct ata_port_info *ppi[] = { &info, NULL };
f20b16ff	354
f7e37ba8 AC	355	/* Chip initialisation */
	356	if (cs5530_init_chip())
	357	return -ENODEV;
f20b16ff	358
f7e37ba8	359	if (cs5530_is_palmax())
1626aeb8	360	ppi[1] = &info_palmax_secondary;
f7e37ba8 AC	361
f7e37ba8 AC	362	/* Now kick off ATA set up */
1626aeb8	363	return ata_pci_init_one(pdev, ppi);
f7e37ba8 AC	364	}
f7e37ba8 AC	365
438ac6d5	366	#ifdef CONFIG_PM
f7e37ba8 AC	367	static int cs5530_reinit_one(struct pci_dev *pdev)
	368	{
	369	/* If we fail on resume we are doomed */
0153260a AM	370	if (cs5530_init_chip())
0153260a AM	371	BUG();
f7e37ba8 AC	372	return ata_pci_device_resume(pdev);
f7e37ba8 AC	373	}
438ac6d5	374	#endif /* CONFIG_PM */
f20b16ff	375
2d2744fc JG	376	static const struct pci_device_id cs5530[] = {
	377	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
	378
	379	{ },
669a5db4 JG	380	};
	381
	382	static struct pci_driver cs5530_pci_driver = {
2d2744fc	383	.name = DRV_NAME,
669a5db4 JG	384	.id_table = cs5530,
669a5db4 JG	385	.probe = cs5530_init_one,
f7e37ba8	386	.remove = ata_pci_remove_one,
438ac6d5	387	#ifdef CONFIG_PM
f7e37ba8 AC	388	.suspend = ata_pci_device_suspend,
f7e37ba8 AC	389	.resume = cs5530_reinit_one,
438ac6d5	390	#endif
669a5db4 JG	391	};
	392
	393	static int __init cs5530_init(void)
	394	{
	395	return pci_register_driver(&cs5530_pci_driver);
	396	}
	397
669a5db4 JG	398	static void __exit cs5530_exit(void)
	399	{
	400	pci_unregister_driver(&cs5530_pci_driver);
	401	}
	402
669a5db4 JG	403	MODULE_AUTHOR("Alan Cox");
	404	MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
	405	MODULE_LICENSE("GPL");
	406	MODULE_DEVICE_TABLE(pci, cs5530);
	407	MODULE_VERSION(DRV_VERSION);
	408
	409	module_init(cs5530_init);
	410	module_exit(cs5530_exit);