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669a5db4 JG |
1 | /* |
2 | * pata-cs5530.c - CS5530 PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * based upon cs5530.c by Mark Lord. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | * | |
21 | * Loosely based on the piix & svwks drivers. | |
22 | * | |
23 | * Documentation: | |
24 | * Available from AMD web site. | |
25 | */ | |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/blkdev.h> | |
32 | #include <linux/delay.h> | |
33 | #include <scsi/scsi_host.h> | |
34 | #include <linux/libata.h> | |
35 | #include <linux/dmi.h> | |
36 | ||
37 | #define DRV_NAME "pata_cs5530" | |
2a3103ce | 38 | #define DRV_VERSION "0.7.4" |
669a5db4 | 39 | |
0d5ff566 TH |
40 | static void __iomem *cs5530_port_base(struct ata_port *ap) |
41 | { | |
42 | unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr; | |
43 | ||
44 | return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no); | |
45 | } | |
46 | ||
669a5db4 JG |
47 | /** |
48 | * cs5530_set_piomode - PIO setup | |
49 | * @ap: ATA interface | |
50 | * @adev: device on the interface | |
51 | * | |
52 | * Set our PIO requirements. This is fairly simple on the CS5530 | |
53 | * chips. | |
54 | */ | |
55 | ||
56 | static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
57 | { | |
58 | static const unsigned int cs5530_pio_timings[2][5] = { | |
59 | {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, | |
60 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010} | |
61 | }; | |
0d5ff566 | 62 | void __iomem *base = cs5530_port_base(ap); |
669a5db4 JG |
63 | u32 tuning; |
64 | int format; | |
65 | ||
66 | /* Find out which table to use */ | |
0d5ff566 | 67 | tuning = ioread32(base + 0x04); |
669a5db4 JG |
68 | format = (tuning & 0x80000000UL) ? 1 : 0; |
69 | ||
70 | /* Now load the right timing register */ | |
71 | if (adev->devno) | |
72 | base += 0x08; | |
73 | ||
0d5ff566 | 74 | iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); |
669a5db4 JG |
75 | } |
76 | ||
77 | /** | |
78 | * cs5530_set_dmamode - DMA timing setup | |
79 | * @ap: ATA interface | |
80 | * @adev: Device being configured | |
81 | * | |
82 | * We cannot mix MWDMA and UDMA without reloading timings each switch | |
83 | * master to slave. We track the last DMA setup in order to minimise | |
84 | * reloads. | |
85 | */ | |
86 | ||
87 | static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
88 | { | |
0d5ff566 | 89 | void __iomem *base = cs5530_port_base(ap); |
669a5db4 JG |
90 | u32 tuning, timing = 0; |
91 | u8 reg; | |
92 | ||
93 | /* Find out which table to use */ | |
0d5ff566 | 94 | tuning = ioread32(base + 0x04); |
669a5db4 JG |
95 | |
96 | switch(adev->dma_mode) { | |
97 | case XFER_UDMA_0: | |
98 | timing = 0x00921250;break; | |
99 | case XFER_UDMA_1: | |
100 | timing = 0x00911140;break; | |
101 | case XFER_UDMA_2: | |
102 | timing = 0x00911030;break; | |
103 | case XFER_MW_DMA_0: | |
104 | timing = 0x00077771;break; | |
105 | case XFER_MW_DMA_1: | |
106 | timing = 0x00012121;break; | |
107 | case XFER_MW_DMA_2: | |
108 | timing = 0x00002020;break; | |
109 | default: | |
110 | BUG(); | |
111 | } | |
112 | /* Merge in the PIO format bit */ | |
113 | timing |= (tuning & 0x80000000UL); | |
114 | if (adev->devno == 0) /* Master */ | |
0d5ff566 | 115 | iowrite32(timing, base + 0x04); |
669a5db4 JG |
116 | else { |
117 | if (timing & 0x00100000) | |
118 | tuning |= 0x00100000; /* UDMA for both */ | |
119 | else | |
120 | tuning &= ~0x00100000; /* MWDMA for both */ | |
0d5ff566 TH |
121 | iowrite32(tuning, base + 0x04); |
122 | iowrite32(timing, base + 0x0C); | |
669a5db4 JG |
123 | } |
124 | ||
125 | /* Set the DMA capable bit in the BMDMA area */ | |
0d5ff566 | 126 | reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
669a5db4 | 127 | reg |= (1 << (5 + adev->devno)); |
0d5ff566 | 128 | iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
669a5db4 JG |
129 | |
130 | /* Remember the last DMA setup we did */ | |
131 | ||
132 | ap->private_data = adev; | |
133 | } | |
134 | ||
135 | /** | |
136 | * cs5530_qc_issue_prot - command issue | |
137 | * @qc: command pending | |
138 | * | |
139 | * Called when the libata layer is about to issue a command. We wrap | |
140 | * this interface so that we can load the correct ATA timings if | |
3a4fa0a2 | 141 | * necessary. Specifically we have a problem that there is only |
669a5db4 JG |
142 | * one MWDMA/UDMA bit. |
143 | */ | |
144 | ||
145 | static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc) | |
146 | { | |
147 | struct ata_port *ap = qc->ap; | |
148 | struct ata_device *adev = qc->dev; | |
149 | struct ata_device *prev = ap->private_data; | |
150 | ||
151 | /* See if the DMA settings could be wrong */ | |
152 | if (adev->dma_mode != 0 && adev != prev && prev != NULL) { | |
153 | /* Maybe, but do the channels match MWDMA/UDMA ? */ | |
154 | if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) || | |
155 | (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0)) | |
156 | /* Switch the mode bits */ | |
157 | cs5530_set_dmamode(ap, adev); | |
158 | } | |
159 | ||
160 | return ata_qc_issue_prot(qc); | |
161 | } | |
162 | ||
669a5db4 | 163 | static struct scsi_host_template cs5530_sht = { |
68d1d07b TH |
164 | ATA_BMDMA_SHT(DRV_NAME), |
165 | .sg_tablesize = LIBATA_DUMB_MAX_PRD, | |
669a5db4 JG |
166 | }; |
167 | ||
168 | static struct ata_port_operations cs5530_port_ops = { | |
029cfd6b | 169 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 170 | |
d26fc955 | 171 | .qc_prep = ata_dumb_qc_prep, |
669a5db4 | 172 | .qc_issue = cs5530_qc_issue_prot, |
bda30288 | 173 | |
029cfd6b TH |
174 | .cable_detect = ata_cable_40wire, |
175 | .set_piomode = cs5530_set_piomode, | |
176 | .set_dmamode = cs5530_set_dmamode, | |
669a5db4 JG |
177 | }; |
178 | ||
1855256c | 179 | static const struct dmi_system_id palmax_dmi_table[] = { |
669a5db4 JG |
180 | { |
181 | .ident = "Palmax PD1100", | |
182 | .matches = { | |
183 | DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"), | |
184 | DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"), | |
185 | }, | |
186 | }, | |
187 | { } | |
188 | }; | |
189 | ||
190 | static int cs5530_is_palmax(void) | |
191 | { | |
192 | if (dmi_check_system(palmax_dmi_table)) { | |
193 | printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n"); | |
194 | return 1; | |
195 | } | |
196 | return 0; | |
197 | } | |
198 | ||
f7e37ba8 | 199 | |
669a5db4 | 200 | /** |
f7e37ba8 | 201 | * cs5530_init_chip - Chipset init |
669a5db4 | 202 | * |
f7e37ba8 AC |
203 | * Perform the chip initialisation work that is shared between both |
204 | * setup and resume paths | |
669a5db4 | 205 | */ |
f20b16ff | 206 | |
f7e37ba8 | 207 | static int cs5530_init_chip(void) |
669a5db4 | 208 | { |
f7e37ba8 | 209 | struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL; |
669a5db4 | 210 | |
669a5db4 JG |
211 | while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) { |
212 | switch (dev->device) { | |
213 | case PCI_DEVICE_ID_CYRIX_PCI_MASTER: | |
214 | master_0 = pci_dev_get(dev); | |
215 | break; | |
216 | case PCI_DEVICE_ID_CYRIX_5530_LEGACY: | |
217 | cs5530_0 = pci_dev_get(dev); | |
218 | break; | |
219 | } | |
220 | } | |
221 | if (!master_0) { | |
222 | printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n"); | |
223 | goto fail_put; | |
224 | } | |
225 | if (!cs5530_0) { | |
226 | printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n"); | |
227 | goto fail_put; | |
228 | } | |
229 | ||
230 | pci_set_master(cs5530_0); | |
694625c0 | 231 | pci_try_set_mwi(cs5530_0); |
669a5db4 JG |
232 | |
233 | /* | |
234 | * Set PCI CacheLineSize to 16-bytes: | |
235 | * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530 | |
236 | * | |
237 | * Note: This value is constant because the 5530 is only a Geode companion | |
238 | */ | |
239 | ||
240 | pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04); | |
241 | ||
242 | /* | |
243 | * Disable trapping of UDMA register accesses (Win98 hack): | |
244 | * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530 | |
245 | */ | |
246 | ||
247 | pci_write_config_word(cs5530_0, 0xd0, 0x5006); | |
248 | ||
249 | /* | |
250 | * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus: | |
251 | * The other settings are what is necessary to get the register | |
252 | * into a sane state for IDE DMA operation. | |
253 | */ | |
254 | ||
255 | pci_write_config_byte(master_0, 0x40, 0x1e); | |
256 | ||
257 | /* | |
258 | * Set max PCI burst size (16-bytes seems to work best): | |
259 | * 16bytes: set bit-1 at 0x41 (reg value of 0x16) | |
260 | * all others: clear bit-1 at 0x41, and do: | |
261 | * 128bytes: OR 0x00 at 0x41 | |
262 | * 256bytes: OR 0x04 at 0x41 | |
263 | * 512bytes: OR 0x08 at 0x41 | |
264 | * 1024bytes: OR 0x0c at 0x41 | |
265 | */ | |
266 | ||
267 | pci_write_config_byte(master_0, 0x41, 0x14); | |
268 | ||
269 | /* | |
270 | * These settings are necessary to get the chip | |
271 | * into a sane state for IDE DMA operation. | |
272 | */ | |
273 | ||
274 | pci_write_config_byte(master_0, 0x42, 0x00); | |
275 | pci_write_config_byte(master_0, 0x43, 0xc1); | |
276 | ||
277 | pci_dev_put(master_0); | |
278 | pci_dev_put(cs5530_0); | |
f7e37ba8 | 279 | return 0; |
669a5db4 JG |
280 | fail_put: |
281 | if (master_0) | |
282 | pci_dev_put(master_0); | |
283 | if (cs5530_0) | |
284 | pci_dev_put(cs5530_0); | |
285 | return -ENODEV; | |
286 | } | |
287 | ||
f7e37ba8 AC |
288 | /** |
289 | * cs5530_init_one - Initialise a CS5530 | |
290 | * @dev: PCI device | |
291 | * @id: Entry in match table | |
292 | * | |
293 | * Install a driver for the newly found CS5530 companion chip. Most of | |
294 | * this is just housekeeping. We have to set the chip up correctly and | |
295 | * turn off various bits of emulation magic. | |
296 | */ | |
297 | ||
298 | static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |
299 | { | |
1626aeb8 | 300 | static const struct ata_port_info info = { |
f7e37ba8 | 301 | .sht = &cs5530_sht, |
1d2808fd | 302 | .flags = ATA_FLAG_SLAVE_POSS, |
f7e37ba8 AC |
303 | .pio_mask = 0x1f, |
304 | .mwdma_mask = 0x07, | |
305 | .udma_mask = 0x07, | |
306 | .port_ops = &cs5530_port_ops | |
307 | }; | |
308 | /* The docking connector doesn't do UDMA, and it seems not MWDMA */ | |
1626aeb8 | 309 | static const struct ata_port_info info_palmax_secondary = { |
f7e37ba8 | 310 | .sht = &cs5530_sht, |
1d2808fd | 311 | .flags = ATA_FLAG_SLAVE_POSS, |
f7e37ba8 AC |
312 | .pio_mask = 0x1f, |
313 | .port_ops = &cs5530_port_ops | |
314 | }; | |
1626aeb8 | 315 | const struct ata_port_info *ppi[] = { &info, NULL }; |
f08048e9 TH |
316 | int rc; |
317 | ||
318 | rc = pcim_enable_device(pdev); | |
319 | if (rc) | |
320 | return rc; | |
f20b16ff | 321 | |
f7e37ba8 AC |
322 | /* Chip initialisation */ |
323 | if (cs5530_init_chip()) | |
324 | return -ENODEV; | |
f20b16ff | 325 | |
f7e37ba8 | 326 | if (cs5530_is_palmax()) |
1626aeb8 | 327 | ppi[1] = &info_palmax_secondary; |
f7e37ba8 AC |
328 | |
329 | /* Now kick off ATA set up */ | |
1626aeb8 | 330 | return ata_pci_init_one(pdev, ppi); |
f7e37ba8 AC |
331 | } |
332 | ||
438ac6d5 | 333 | #ifdef CONFIG_PM |
f7e37ba8 AC |
334 | static int cs5530_reinit_one(struct pci_dev *pdev) |
335 | { | |
f08048e9 TH |
336 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
337 | int rc; | |
338 | ||
339 | rc = ata_pci_device_do_resume(pdev); | |
340 | if (rc) | |
341 | return rc; | |
342 | ||
f7e37ba8 | 343 | /* If we fail on resume we are doomed */ |
0153260a | 344 | if (cs5530_init_chip()) |
f08048e9 TH |
345 | return -EIO; |
346 | ||
347 | ata_host_resume(host); | |
348 | return 0; | |
f7e37ba8 | 349 | } |
438ac6d5 | 350 | #endif /* CONFIG_PM */ |
f20b16ff | 351 | |
2d2744fc JG |
352 | static const struct pci_device_id cs5530[] = { |
353 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), }, | |
354 | ||
355 | { }, | |
669a5db4 JG |
356 | }; |
357 | ||
358 | static struct pci_driver cs5530_pci_driver = { | |
2d2744fc | 359 | .name = DRV_NAME, |
669a5db4 JG |
360 | .id_table = cs5530, |
361 | .probe = cs5530_init_one, | |
f7e37ba8 | 362 | .remove = ata_pci_remove_one, |
438ac6d5 | 363 | #ifdef CONFIG_PM |
f7e37ba8 AC |
364 | .suspend = ata_pci_device_suspend, |
365 | .resume = cs5530_reinit_one, | |
438ac6d5 | 366 | #endif |
669a5db4 JG |
367 | }; |
368 | ||
369 | static int __init cs5530_init(void) | |
370 | { | |
371 | return pci_register_driver(&cs5530_pci_driver); | |
372 | } | |
373 | ||
669a5db4 JG |
374 | static void __exit cs5530_exit(void) |
375 | { | |
376 | pci_unregister_driver(&cs5530_pci_driver); | |
377 | } | |
378 | ||
669a5db4 JG |
379 | MODULE_AUTHOR("Alan Cox"); |
380 | MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530"); | |
381 | MODULE_LICENSE("GPL"); | |
382 | MODULE_DEVICE_TABLE(pci, cs5530); | |
383 | MODULE_VERSION(DRV_VERSION); | |
384 | ||
385 | module_init(cs5530_init); | |
386 | module_exit(cs5530_exit); |