Commit | Line | Data |
---|---|---|
669a5db4 | 1 | /* |
fb9f8905 | 2 | * pata_cmd64x.c - CMD64x PATA for new ATA layer |
669a5db4 JG |
3 | * (C) 2005 Red Hat Inc |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * Based upon | |
7 | * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 | |
8 | * | |
9 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. | |
10 | * Note, this driver is not used at all on other systems because | |
11 | * there the "BIOS" has done all of the following already. | |
12 | * Due to massive hardware bugs, UltraDMA is only supported | |
13 | * on the 646U2 and not on the 646U. | |
14 | * | |
15 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
16 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) | |
17 | * | |
18 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
19 | * | |
20 | * TODO | |
21 | * Testing work | |
22 | */ | |
85cd7251 | 23 | |
669a5db4 JG |
24 | #include <linux/kernel.h> |
25 | #include <linux/module.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/blkdev.h> | |
29 | #include <linux/delay.h> | |
30 | #include <scsi/scsi_host.h> | |
31 | #include <linux/libata.h> | |
32 | ||
33 | #define DRV_NAME "pata_cmd64x" | |
05d1efff | 34 | #define DRV_VERSION "0.2.5" |
669a5db4 JG |
35 | |
36 | /* | |
37 | * CMD64x specific registers definition. | |
38 | */ | |
85cd7251 | 39 | |
669a5db4 JG |
40 | enum { |
41 | CFR = 0x50, | |
42 | CFR_INTR_CH0 = 0x02, | |
43 | CNTRL = 0x51, | |
44 | CNTRL_DIS_RA0 = 0x40, | |
45 | CNTRL_DIS_RA1 = 0x80, | |
46 | CNTRL_ENA_2ND = 0x08, | |
47 | CMDTIM = 0x52, | |
48 | ARTTIM0 = 0x53, | |
49 | DRWTIM0 = 0x54, | |
50 | ARTTIM1 = 0x55, | |
51 | DRWTIM1 = 0x56, | |
52 | ARTTIM23 = 0x57, | |
53 | ARTTIM23_DIS_RA2 = 0x04, | |
54 | ARTTIM23_DIS_RA3 = 0x08, | |
55 | ARTTIM23_INTR_CH1 = 0x10, | |
56 | ARTTIM2 = 0x57, | |
57 | ARTTIM3 = 0x57, | |
58 | DRWTIM23 = 0x58, | |
59 | DRWTIM2 = 0x58, | |
60 | BRST = 0x59, | |
61 | DRWTIM3 = 0x5b, | |
62 | BMIDECR0 = 0x70, | |
63 | MRDMODE = 0x71, | |
64 | MRDMODE_INTR_CH0 = 0x04, | |
65 | MRDMODE_INTR_CH1 = 0x08, | |
66 | MRDMODE_BLK_CH0 = 0x10, | |
67 | MRDMODE_BLK_CH1 = 0x20, | |
68 | BMIDESR0 = 0x72, | |
69 | UDIDETCR0 = 0x73, | |
70 | DTPR0 = 0x74, | |
71 | BMIDECR1 = 0x78, | |
72 | BMIDECSR = 0x79, | |
73 | BMIDESR1 = 0x7A, | |
74 | UDIDETCR1 = 0x7B, | |
75 | DTPR1 = 0x7C | |
76 | }; | |
77 | ||
a73984a0 | 78 | static int cmd648_cable_detect(struct ata_port *ap) |
669a5db4 JG |
79 | { |
80 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
81 | u8 r; | |
82 | ||
83 | /* Check cable detect bits */ | |
84 | pci_read_config_byte(pdev, BMIDECSR, &r); | |
85 | if (r & (1 << ap->port_no)) | |
a73984a0 JG |
86 | return ATA_CBL_PATA80; |
87 | return ATA_CBL_PATA40; | |
669a5db4 JG |
88 | } |
89 | ||
90 | /** | |
05d1efff | 91 | * cmd64x_set_piomode - set PIO and MWDMA timing |
669a5db4 JG |
92 | * @ap: ATA interface |
93 | * @adev: ATA device | |
05d1efff | 94 | * @mode: mode |
669a5db4 | 95 | * |
05d1efff | 96 | * Called to do the PIO and MWDMA mode setup. |
669a5db4 | 97 | */ |
85cd7251 | 98 | |
05d1efff | 99 | static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode) |
669a5db4 JG |
100 | { |
101 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
102 | struct ata_timing t; | |
103 | const unsigned long T = 1000000 / 33; | |
104 | const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; | |
85cd7251 | 105 | |
669a5db4 | 106 | u8 reg; |
85cd7251 | 107 | |
669a5db4 | 108 | /* Port layout is not logical so use a table */ |
85cd7251 | 109 | const u8 arttim_port[2][2] = { |
669a5db4 JG |
110 | { ARTTIM0, ARTTIM1 }, |
111 | { ARTTIM23, ARTTIM23 } | |
112 | }; | |
113 | const u8 drwtim_port[2][2] = { | |
114 | { DRWTIM0, DRWTIM1 }, | |
115 | { DRWTIM2, DRWTIM3 } | |
116 | }; | |
85cd7251 | 117 | |
669a5db4 JG |
118 | int arttim = arttim_port[ap->port_no][adev->devno]; |
119 | int drwtim = drwtim_port[ap->port_no][adev->devno]; | |
85cd7251 | 120 | |
05d1efff AC |
121 | /* ata_timing_compute is smart and will produce timings for MWDMA |
122 | that don't violate the drives PIO capabilities. */ | |
123 | if (ata_timing_compute(adev, mode, &t, T, 0) < 0) { | |
669a5db4 JG |
124 | printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); |
125 | return; | |
126 | } | |
127 | if (ap->port_no) { | |
128 | /* Slave has shared address setup */ | |
129 | struct ata_device *pair = ata_dev_pair(adev); | |
85cd7251 | 130 | |
669a5db4 JG |
131 | if (pair) { |
132 | struct ata_timing tp; | |
133 | ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); | |
134 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
135 | } | |
136 | } | |
85cd7251 | 137 | |
669a5db4 JG |
138 | printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", |
139 | t.active, t.recover, t.setup); | |
140 | if (t.recover > 16) { | |
141 | t.active += t.recover - 16; | |
142 | t.recover = 16; | |
143 | } | |
144 | if (t.active > 16) | |
145 | t.active = 16; | |
85cd7251 | 146 | |
669a5db4 JG |
147 | /* Now convert the clocks into values we can actually stuff into |
148 | the chip */ | |
85cd7251 | 149 | |
669a5db4 JG |
150 | if (t.recover > 1) |
151 | t.recover--; | |
152 | else | |
153 | t.recover = 15; | |
85cd7251 | 154 | |
669a5db4 JG |
155 | if (t.setup > 4) |
156 | t.setup = 0xC0; | |
157 | else | |
158 | t.setup = setup_data[t.setup]; | |
85cd7251 | 159 | |
669a5db4 | 160 | t.active &= 0x0F; /* 0 = 16 */ |
85cd7251 | 161 | |
669a5db4 JG |
162 | /* Load setup timing */ |
163 | pci_read_config_byte(pdev, arttim, ®); | |
164 | reg &= 0x3F; | |
165 | reg |= t.setup; | |
166 | pci_write_config_byte(pdev, arttim, reg); | |
85cd7251 | 167 | |
669a5db4 | 168 | /* Load active/recovery */ |
85cd7251 | 169 | pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); |
669a5db4 JG |
170 | } |
171 | ||
05d1efff AC |
172 | /** |
173 | * cmd64x_set_piomode - set initial PIO mode data | |
174 | * @ap: ATA interface | |
175 | * @adev: ATA device | |
176 | * | |
177 | * Used when configuring the devices ot set the PIO timings. All the | |
178 | * actual work is done by the PIO/MWDMA setting helper | |
179 | */ | |
180 | ||
181 | static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
182 | { | |
183 | cmd64x_set_timing(ap, adev, adev->pio_mode); | |
184 | } | |
185 | ||
669a5db4 JG |
186 | /** |
187 | * cmd64x_set_dmamode - set initial DMA mode data | |
188 | * @ap: ATA interface | |
189 | * @adev: ATA device | |
190 | * | |
191 | * Called to do the DMA mode setup. | |
192 | */ | |
85cd7251 | 193 | |
669a5db4 JG |
194 | static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
195 | { | |
196 | static const u8 udma_data[] = { | |
6a40da02 | 197 | 0x30, 0x20, 0x10, 0x20, 0x10, 0x00 |
669a5db4 | 198 | }; |
85cd7251 | 199 | |
669a5db4 JG |
200 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
201 | u8 regU, regD; | |
202 | ||
203 | int pciU = UDIDETCR0 + 8 * ap->port_no; | |
204 | int pciD = BMIDESR0 + 8 * ap->port_no; | |
205 | int shift = 2 * adev->devno; | |
85cd7251 | 206 | |
669a5db4 JG |
207 | pci_read_config_byte(pdev, pciD, ®D); |
208 | pci_read_config_byte(pdev, pciU, ®U); | |
209 | ||
6a40da02 AC |
210 | /* DMA bits off */ |
211 | regD &= ~(0x20 << adev->devno); | |
212 | /* DMA control bits */ | |
213 | regU &= ~(0x30 << shift); | |
214 | /* DMA timing bits */ | |
215 | regU &= ~(0x05 << adev->devno); | |
85cd7251 | 216 | |
6a40da02 | 217 | if (adev->dma_mode >= XFER_UDMA_0) { |
24b7ce98 | 218 | /* Merge the timing value */ |
669a5db4 | 219 | regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; |
6a40da02 AC |
220 | /* Merge the control bits */ |
221 | regU |= 1 << adev->devno; /* UDMA on */ | |
222 | if (adev->dma_mode > 2) /* 15nS timing */ | |
223 | regU |= 4 << adev->devno; | |
05d1efff AC |
224 | } else { |
225 | regU &= ~ (1 << adev->devno); /* UDMA off */ | |
226 | cmd64x_set_timing(ap, adev, adev->dma_mode); | |
227 | } | |
669a5db4 JG |
228 | |
229 | regD |= 0x20 << adev->devno; | |
230 | ||
231 | pci_write_config_byte(pdev, pciU, regU); | |
232 | pci_write_config_byte(pdev, pciD, regD); | |
233 | } | |
234 | ||
235 | /** | |
236 | * cmd648_dma_stop - DMA stop callback | |
237 | * @qc: Command in progress | |
238 | * | |
239 | * DMA has completed. | |
240 | */ | |
241 | ||
242 | static void cmd648_bmdma_stop(struct ata_queued_cmd *qc) | |
243 | { | |
244 | struct ata_port *ap = qc->ap; | |
245 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
246 | u8 dma_intr; | |
6a40da02 AC |
247 | int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; |
248 | int dma_reg = ap->port_no ? ARTTIM2 : CFR; | |
85cd7251 | 249 | |
669a5db4 | 250 | ata_bmdma_stop(qc); |
85cd7251 | 251 | |
669a5db4 JG |
252 | pci_read_config_byte(pdev, dma_reg, &dma_intr); |
253 | pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask); | |
254 | } | |
85cd7251 | 255 | |
669a5db4 JG |
256 | /** |
257 | * cmd646r1_dma_stop - DMA stop callback | |
258 | * @qc: Command in progress | |
259 | * | |
260 | * Stub for now while investigating the r1 quirk in the old driver. | |
261 | */ | |
262 | ||
263 | static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc) | |
264 | { | |
265 | ata_bmdma_stop(qc); | |
266 | } | |
85cd7251 | 267 | |
669a5db4 | 268 | static struct scsi_host_template cmd64x_sht = { |
68d1d07b | 269 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
270 | }; |
271 | ||
029cfd6b TH |
272 | static const struct ata_port_operations cmd64x_base_ops = { |
273 | .inherits = &ata_bmdma_port_ops, | |
669a5db4 JG |
274 | .set_piomode = cmd64x_set_piomode, |
275 | .set_dmamode = cmd64x_set_dmamode, | |
85cd7251 | 276 | }; |
669a5db4 | 277 | |
029cfd6b TH |
278 | static struct ata_port_operations cmd64x_port_ops = { |
279 | .inherits = &cmd64x_base_ops, | |
a73984a0 | 280 | .cable_detect = ata_cable_40wire, |
029cfd6b | 281 | }; |
669a5db4 | 282 | |
029cfd6b TH |
283 | static struct ata_port_operations cmd646r1_port_ops = { |
284 | .inherits = &cmd64x_base_ops, | |
669a5db4 | 285 | .bmdma_stop = cmd646r1_bmdma_stop, |
029cfd6b | 286 | .cable_detect = ata_cable_40wire, |
85cd7251 | 287 | }; |
669a5db4 JG |
288 | |
289 | static struct ata_port_operations cmd648_port_ops = { | |
029cfd6b | 290 | .inherits = &cmd64x_base_ops, |
669a5db4 | 291 | .bmdma_stop = cmd648_bmdma_stop, |
029cfd6b | 292 | .cable_detect = cmd648_cable_detect, |
85cd7251 JG |
293 | }; |
294 | ||
669a5db4 JG |
295 | static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
296 | { | |
297 | u32 class_rev; | |
85cd7251 | 298 | |
1626aeb8 | 299 | static const struct ata_port_info cmd_info[6] = { |
669a5db4 JG |
300 | { /* CMD 643 - no UDMA */ |
301 | .sht = &cmd64x_sht, | |
1d2808fd | 302 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
303 | .pio_mask = 0x1f, |
304 | .mwdma_mask = 0x07, | |
305 | .port_ops = &cmd64x_port_ops | |
306 | }, | |
307 | { /* CMD 646 with broken UDMA */ | |
308 | .sht = &cmd64x_sht, | |
1d2808fd | 309 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
310 | .pio_mask = 0x1f, |
311 | .mwdma_mask = 0x07, | |
312 | .port_ops = &cmd64x_port_ops | |
313 | }, | |
314 | { /* CMD 646 with working UDMA */ | |
315 | .sht = &cmd64x_sht, | |
1d2808fd | 316 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
317 | .pio_mask = 0x1f, |
318 | .mwdma_mask = 0x07, | |
dbf0c89c | 319 | .udma_mask = ATA_UDMA2, |
669a5db4 JG |
320 | .port_ops = &cmd64x_port_ops |
321 | }, | |
322 | { /* CMD 646 rev 1 */ | |
323 | .sht = &cmd64x_sht, | |
1d2808fd | 324 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
325 | .pio_mask = 0x1f, |
326 | .mwdma_mask = 0x07, | |
327 | .port_ops = &cmd646r1_port_ops | |
328 | }, | |
329 | { /* CMD 648 */ | |
330 | .sht = &cmd64x_sht, | |
1d2808fd | 331 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
332 | .pio_mask = 0x1f, |
333 | .mwdma_mask = 0x07, | |
dbf0c89c | 334 | .udma_mask = ATA_UDMA4, |
669a5db4 JG |
335 | .port_ops = &cmd648_port_ops |
336 | }, | |
337 | { /* CMD 649 */ | |
338 | .sht = &cmd64x_sht, | |
1d2808fd | 339 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
340 | .pio_mask = 0x1f, |
341 | .mwdma_mask = 0x07, | |
dbf0c89c | 342 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
343 | .port_ops = &cmd648_port_ops |
344 | } | |
345 | }; | |
1626aeb8 | 346 | const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL }; |
669a5db4 | 347 | u8 mrdmode; |
f08048e9 TH |
348 | int rc; |
349 | ||
350 | rc = pcim_enable_device(pdev); | |
351 | if (rc) | |
352 | return rc; | |
85cd7251 | 353 | |
669a5db4 JG |
354 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev); |
355 | class_rev &= 0xFF; | |
85cd7251 | 356 | |
669a5db4 JG |
357 | if (id->driver_data == 0) /* 643 */ |
358 | ata_pci_clear_simplex(pdev); | |
85cd7251 | 359 | |
669a5db4 JG |
360 | if (pdev->device == PCI_DEVICE_ID_CMD_646) { |
361 | /* Does UDMA work ? */ | |
362 | if (class_rev > 4) | |
1626aeb8 | 363 | ppi[0] = &cmd_info[2]; |
669a5db4 JG |
364 | /* Early rev with other problems ? */ |
365 | else if (class_rev == 1) | |
1626aeb8 | 366 | ppi[0] = &cmd_info[3]; |
669a5db4 JG |
367 | } |
368 | ||
369 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); | |
370 | pci_read_config_byte(pdev, MRDMODE, &mrdmode); | |
371 | mrdmode &= ~ 0x30; /* IRQ set up */ | |
372 | mrdmode |= 0x02; /* Memory read line enable */ | |
373 | pci_write_config_byte(pdev, MRDMODE, mrdmode); | |
85cd7251 | 374 | |
669a5db4 | 375 | /* Force PIO 0 here.. */ |
85cd7251 | 376 | |
669a5db4 JG |
377 | /* PPC specific fixup copied from old driver */ |
378 | #ifdef CONFIG_PPC | |
379 | pci_write_config_byte(pdev, UDIDETCR0, 0xF0); | |
380 | #endif | |
85cd7251 | 381 | |
1626aeb8 | 382 | return ata_pci_init_one(pdev, ppi); |
669a5db4 JG |
383 | } |
384 | ||
438ac6d5 | 385 | #ifdef CONFIG_PM |
7f72a379 AC |
386 | static int cmd64x_reinit_one(struct pci_dev *pdev) |
387 | { | |
f08048e9 | 388 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
7f72a379 | 389 | u8 mrdmode; |
f08048e9 TH |
390 | int rc; |
391 | ||
392 | rc = ata_pci_device_do_resume(pdev); | |
393 | if (rc) | |
394 | return rc; | |
395 | ||
7f72a379 AC |
396 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); |
397 | pci_read_config_byte(pdev, MRDMODE, &mrdmode); | |
398 | mrdmode &= ~ 0x30; /* IRQ set up */ | |
399 | mrdmode |= 0x02; /* Memory read line enable */ | |
400 | pci_write_config_byte(pdev, MRDMODE, mrdmode); | |
401 | #ifdef CONFIG_PPC | |
402 | pci_write_config_byte(pdev, UDIDETCR0, 0xF0); | |
403 | #endif | |
f08048e9 TH |
404 | ata_host_resume(host); |
405 | return 0; | |
7f72a379 | 406 | } |
438ac6d5 | 407 | #endif |
7f72a379 | 408 | |
2d2744fc JG |
409 | static const struct pci_device_id cmd64x[] = { |
410 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, | |
411 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, | |
412 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 }, | |
413 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 }, | |
414 | ||
415 | { }, | |
669a5db4 JG |
416 | }; |
417 | ||
418 | static struct pci_driver cmd64x_pci_driver = { | |
2d2744fc | 419 | .name = DRV_NAME, |
669a5db4 JG |
420 | .id_table = cmd64x, |
421 | .probe = cmd64x_init_one, | |
7f72a379 | 422 | .remove = ata_pci_remove_one, |
438ac6d5 | 423 | #ifdef CONFIG_PM |
7f72a379 AC |
424 | .suspend = ata_pci_device_suspend, |
425 | .resume = cmd64x_reinit_one, | |
438ac6d5 | 426 | #endif |
669a5db4 JG |
427 | }; |
428 | ||
429 | static int __init cmd64x_init(void) | |
430 | { | |
431 | return pci_register_driver(&cmd64x_pci_driver); | |
432 | } | |
433 | ||
669a5db4 JG |
434 | static void __exit cmd64x_exit(void) |
435 | { | |
436 | pci_unregister_driver(&cmd64x_pci_driver); | |
437 | } | |
438 | ||
669a5db4 JG |
439 | MODULE_AUTHOR("Alan Cox"); |
440 | MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers"); | |
441 | MODULE_LICENSE("GPL"); | |
442 | MODULE_DEVICE_TABLE(pci, cmd64x); | |
443 | MODULE_VERSION(DRV_VERSION); | |
444 | ||
445 | module_init(cmd64x_init); | |
446 | module_exit(cmd64x_exit); |