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ARM: SPEAr13xx: Pass generic DW DMAC platform data from DT
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_arasan_cf.c
CommitLineData
a480167b
VK		 1/*
2 * drivers/ata/pata_arasan_cf.c
3 *
4 * Arasan Compact Flash host controller source file
5 *
6 * Copyright (C) 2011 ST Microelectronics
10d8935f 7 * Viresh Kumar <viresh.linux@gmail.com>
a480167b
VK		 8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14/*
15 * The Arasan CompactFlash Device Controller IP core has three basic modes of
16 * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card
17 * ATA using true IDE modes. This driver supports only True IDE mode currently.
18 *
19 * Arasan CF Controller shares global irq register with Arasan XD Controller.
20 *
21 * Tested on arch/arm/mach-spear13xx
22 */
23
24#include <linux/ata.h>
25#include <linux/clk.h>
26#include <linux/completion.h>
27#include <linux/delay.h>
28#include <linux/dmaengine.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/libata.h>
33#include <linux/module.h>
26fdaa74 34#include <linux/of.h>
a480167b
VK		 35#include <linux/pata_arasan_cf_data.h>
36#include <linux/platform_device.h>
37#include <linux/pm.h>
38#include <linux/slab.h>
39#include <linux/spinlock.h>
40#include <linux/types.h>
41#include <linux/workqueue.h>
42
43#define DRIVER_NAME "arasan_cf"
44#define TIMEOUT msecs_to_jiffies(3000)
45
46/* Registers */
47/* CompactFlash Interface Status */
48#define CFI_STS 0x000
49 #define STS_CHG (1)
50 #define BIN_AUDIO_OUT (1 << 1)
51 #define CARD_DETECT1 (1 << 2)
52 #define CARD_DETECT2 (1 << 3)
53 #define INP_ACK (1 << 4)
54 #define CARD_READY (1 << 5)
55 #define IO_READY (1 << 6)
56 #define B16_IO_PORT_SEL (1 << 7)
57/* IRQ */
58#define IRQ_STS 0x004
59/* Interrupt Enable */
60#define IRQ_EN 0x008
61 #define CARD_DETECT_IRQ (1)
62 #define STATUS_CHNG_IRQ (1 << 1)
63 #define MEM_MODE_IRQ (1 << 2)
64 #define IO_MODE_IRQ (1 << 3)
65 #define TRUE_IDE_MODE_IRQ (1 << 8)
66 #define PIO_XFER_ERR_IRQ (1 << 9)
67 #define BUF_AVAIL_IRQ (1 << 10)
68 #define XFER_DONE_IRQ (1 << 11)
69 #define IGNORED_IRQS (STATUS_CHNG_IRQ | MEM_MODE_IRQ | IO_MODE_IRQ |\
70 TRUE_IDE_MODE_IRQ)
71 #define TRUE_IDE_IRQS (CARD_DETECT_IRQ | PIO_XFER_ERR_IRQ |\
72 BUF_AVAIL_IRQ | XFER_DONE_IRQ)
73/* Operation Mode */
74#define OP_MODE 0x00C
75 #define CARD_MODE_MASK (0x3)
76 #define MEM_MODE (0x0)
77 #define IO_MODE (0x1)
78 #define TRUE_IDE_MODE (0x2)
79
80 #define CARD_TYPE_MASK (1 << 2)
81 #define CF_CARD (0)
82 #define CF_PLUS_CARD (1 << 2)
83
84 #define CARD_RESET (1 << 3)
85 #define CFHOST_ENB (1 << 4)
86 #define OUTPUTS_TRISTATE (1 << 5)
87 #define ULTRA_DMA_ENB (1 << 8)
88 #define MULTI_WORD_DMA_ENB (1 << 9)
89 #define DRQ_BLOCK_SIZE_MASK (0x3 << 11)
90 #define DRQ_BLOCK_SIZE_512 (0)
91 #define DRQ_BLOCK_SIZE_1024 (1 << 11)
92 #define DRQ_BLOCK_SIZE_2048 (2 << 11)
93 #define DRQ_BLOCK_SIZE_4096 (3 << 11)
94/* CF Interface Clock Configuration */
95#define CLK_CFG 0x010
96 #define CF_IF_CLK_MASK (0XF)
97/* CF Timing Mode Configuration */
98#define TM_CFG 0x014
99 #define MEM_MODE_TIMING_MASK (0x3)
100 #define MEM_MODE_TIMING_250NS (0x0)
101 #define MEM_MODE_TIMING_120NS (0x1)
102 #define MEM_MODE_TIMING_100NS (0x2)
103 #define MEM_MODE_TIMING_80NS (0x3)
104
105 #define IO_MODE_TIMING_MASK (0x3 << 2)
106 #define IO_MODE_TIMING_250NS (0x0 << 2)
107 #define IO_MODE_TIMING_120NS (0x1 << 2)
108 #define IO_MODE_TIMING_100NS (0x2 << 2)
109 #define IO_MODE_TIMING_80NS (0x3 << 2)
110
111 #define TRUEIDE_PIO_TIMING_MASK (0x7 << 4)
112 #define TRUEIDE_PIO_TIMING_SHIFT 4
113
114 #define TRUEIDE_MWORD_DMA_TIMING_MASK (0x7 << 7)
115 #define TRUEIDE_MWORD_DMA_TIMING_SHIFT 7
116
117 #define ULTRA_DMA_TIMING_MASK (0x7 << 10)
118 #define ULTRA_DMA_TIMING_SHIFT 10
119/* CF Transfer Address */
120#define XFER_ADDR 0x014
121 #define XFER_ADDR_MASK (0x7FF)
122 #define MAX_XFER_COUNT 0x20000u
123/* Transfer Control */
124#define XFER_CTR 0x01C
125 #define XFER_COUNT_MASK (0x3FFFF)
126 #define ADDR_INC_DISABLE (1 << 24)
127 #define XFER_WIDTH_MASK (1 << 25)
128 #define XFER_WIDTH_8B (0)
129 #define XFER_WIDTH_16B (1 << 25)
130
131 #define MEM_TYPE_MASK (1 << 26)
132 #define MEM_TYPE_COMMON (0)
133 #define MEM_TYPE_ATTRIBUTE (1 << 26)
134
135 #define MEM_IO_XFER_MASK (1 << 27)
136 #define MEM_XFER (0)
137 #define IO_XFER (1 << 27)
138
139 #define DMA_XFER_MODE (1 << 28)
140
141 #define AHB_BUS_NORMAL_PIO_OPRTN (~(1 << 29))
142 #define XFER_DIR_MASK (1 << 30)
143 #define XFER_READ (0)
144 #define XFER_WRITE (1 << 30)
145
146 #define XFER_START (1 << 31)
147/* Write Data Port */
148#define WRITE_PORT 0x024
149/* Read Data Port */
150#define READ_PORT 0x028
151/* ATA Data Port */
152#define ATA_DATA_PORT 0x030
153 #define ATA_DATA_PORT_MASK (0xFFFF)
154/* ATA Error/Features */
155#define ATA_ERR_FTR 0x034
156/* ATA Sector Count */
157#define ATA_SC 0x038
158/* ATA Sector Number */
159#define ATA_SN 0x03C
160/* ATA Cylinder Low */
161#define ATA_CL 0x040
162/* ATA Cylinder High */
163#define ATA_CH 0x044
164/* ATA Select Card/Head */
165#define ATA_SH 0x048
166/* ATA Status-Command */
167#define ATA_STS_CMD 0x04C
168/* ATA Alternate Status/Device Control */
169#define ATA_ASTS_DCTR 0x050
170/* Extended Write Data Port 0x200-0x3FC */
171#define EXT_WRITE_PORT 0x200
172/* Extended Read Data Port 0x400-0x5FC */
173#define EXT_READ_PORT 0x400
174 #define FIFO_SIZE 0x200u
175/* Global Interrupt Status */
176#define GIRQ_STS 0x800
177/* Global Interrupt Status enable */
178#define GIRQ_STS_EN 0x804
179/* Global Interrupt Signal enable */
180#define GIRQ_SGN_EN 0x808
181 #define GIRQ_CF (1)
182 #define GIRQ_XD (1 << 1)
183
184/* Compact Flash Controller Dev Structure */
185struct arasan_cf_dev {
186 /* pointer to ata_host structure */
187 struct ata_host *host;
d14fb1e9 188 /* clk structure */
a480167b 189 struct clk *clk;
a480167b
VK		 190
191 /* physical base address of controller */
192 dma_addr_t pbase;
193 /* virtual base address of controller */
194 void __iomem *vbase;
195 /* irq number*/
196 int irq;
197
198 /* status to be updated to framework regarding DMA transfer */
199 u8 dma_status;
200 /* Card is present or Not */
201 u8 card_present;
202
203 /* dma specific */
204 /* Completion for transfer complete interrupt from controller */
205 struct completion cf_completion;
206 /* Completion for DMA transfer complete. */
207 struct completion dma_completion;
208 /* Dma channel allocated */
209 struct dma_chan *dma_chan;
210 /* Mask for DMA transfers */
211 dma_cap_mask_t mask;
60a230e4
VK		 212 /* dma channel private data */
213 void *dma_priv;
a480167b
VK		 214 /* DMA transfer work */
215 struct work_struct work;
216 /* DMA delayed finish work */
217 struct delayed_work dwork;
218 /* qc to be transferred using DMA */
219 struct ata_queued_cmd *qc;
220};
221
222static struct scsi_host_template arasan_cf_sht = {
223 ATA_BASE_SHT(DRIVER_NAME),
224 .sg_tablesize = SG_NONE,
225 .dma_boundary = 0xFFFFFFFFUL,
226};
227
228static void cf_dumpregs(struct arasan_cf_dev *acdev)
229{
230 struct device *dev = acdev->host->dev;
231
232 dev_dbg(dev, ": =========== REGISTER DUMP ===========");
233 dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS));
234 dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS));
235 dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN));
236 dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE));
237 dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG));
238 dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG));
239 dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR));
240 dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS));
241 dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN));
242 dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN));
243 dev_dbg(dev, ": =====================================");
244}
245
246/* Enable/Disable global interrupts shared between CF and XD ctrlr. */
247static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable)
248{
249 /* enable should be 0 or 1 */
250 writel(enable, acdev->vbase + GIRQ_STS_EN);
251 writel(enable, acdev->vbase + GIRQ_SGN_EN);
252}
253
254/* Enable/Disable CF interrupts */
255static inline void
256cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable)
257{
258 u32 val = readl(acdev->vbase + IRQ_EN);
259 /* clear & enable/disable irqs */
260 if (enable) {
261 writel(mask, acdev->vbase + IRQ_STS);
262 writel(val | mask, acdev->vbase + IRQ_EN);
263 } else
264 writel(val & ~mask, acdev->vbase + IRQ_EN);
265}
266
267static inline void cf_card_reset(struct arasan_cf_dev *acdev)
268{
269 u32 val = readl(acdev->vbase + OP_MODE);
270
271 writel(val | CARD_RESET, acdev->vbase + OP_MODE);
272 udelay(200);
273 writel(val & ~CARD_RESET, acdev->vbase + OP_MODE);
274}
275
276static inline void cf_ctrl_reset(struct arasan_cf_dev *acdev)
277{
278 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
279 acdev->vbase + OP_MODE);
280 writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB,
281 acdev->vbase + OP_MODE);
282}
283
284static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged)
285{
286 struct ata_port *ap = acdev->host->ports[0];
287 struct ata_eh_info *ehi = &ap->link.eh_info;
288 u32 val = readl(acdev->vbase + CFI_STS);
289
290 /* Both CD1 & CD2 should be low if card inserted completely */
291 if (!(val & (CARD_DETECT1 | CARD_DETECT2))) {
292 if (acdev->card_present)
293 return;
294 acdev->card_present = 1;
295 cf_card_reset(acdev);
296 } else {
297 if (!acdev->card_present)
298 return;
299 acdev->card_present = 0;
300 }
301
302 if (hotplugged) {
303 ata_ehi_hotplugged(ehi);
304 ata_port_freeze(ap);
305 }
306}
307
308static int cf_init(struct arasan_cf_dev *acdev)
309{
310 struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev);
311 unsigned long flags;
312 int ret = 0;
313
3f09e6c0 314 ret = clk_prepare_enable(acdev->clk);
a480167b
VK		 315 if (ret) {
316 dev_dbg(acdev->host->dev, "clock enable failed");
317 return ret;
318 }
a480167b 319
9addf6af
VKS		 320 ret = clk_set_rate(acdev->clk, 166000000);
321 if (ret) {
322 dev_warn(acdev->host->dev, "clock set rate failed");
323 return ret;
324 }
325
a480167b
VK		 326 spin_lock_irqsave(&acdev->host->lock, flags);
327 /* configure CF interface clock */
328 writel((pdata->cf_if_clk <= CF_IF_CLK_200M) ? pdata->cf_if_clk :
329 CF_IF_CLK_166M, acdev->vbase + CLK_CFG);
330
331 writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
332 cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1);
333 cf_ginterrupt_enable(acdev, 1);
334 spin_unlock_irqrestore(&acdev->host->lock, flags);
335
336 return ret;
337}
338
339static void cf_exit(struct arasan_cf_dev *acdev)
340{
341 unsigned long flags;
342
343 spin_lock_irqsave(&acdev->host->lock, flags);
344 cf_ginterrupt_enable(acdev, 0);
345 cf_interrupt_enable(acdev, TRUE_IDE_IRQS, 0);
346 cf_card_reset(acdev);
347 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
348 acdev->vbase + OP_MODE);
349 spin_unlock_irqrestore(&acdev->host->lock, flags);
3f09e6c0 350 clk_disable_unprepare(acdev->clk);
a480167b
VK		 351}
352
353static void dma_callback(void *dev)
354{
355 struct arasan_cf_dev *acdev = (struct arasan_cf_dev *) dev;
356
357 complete(&acdev->dma_completion);
358}
359
360static bool filter(struct dma_chan *chan, void *slave)
361{
60a230e4 362 chan->private = slave;
a480167b
VK		 363 return true;
364}
365
366static inline void dma_complete(struct arasan_cf_dev *acdev)
367{
368 struct ata_queued_cmd *qc = acdev->qc;
369 unsigned long flags;
370
371 acdev->qc = NULL;
372 ata_sff_interrupt(acdev->irq, acdev->host);
373
374 spin_lock_irqsave(&acdev->host->lock, flags);
375 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
376 ata_ehi_push_desc(&qc->ap->link.eh_info, "DMA Failed: Timeout");
377 spin_unlock_irqrestore(&acdev->host->lock, flags);
378}
379
380static inline int wait4buf(struct arasan_cf_dev *acdev)
381{
382 if (!wait_for_completion_timeout(&acdev->cf_completion, TIMEOUT)) {
383 u32 rw = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
384
385 dev_err(acdev->host->dev, "%s TimeOut", rw ? "write" : "read");
386 return -ETIMEDOUT;
387 }
388
25985edc 389 /* Check if PIO Error interrupt has occurred */
a480167b
VK		 390 if (acdev->dma_status & ATA_DMA_ERR)
391 return -EAGAIN;
392
393 return 0;
394}
395
396static int
397dma_xfer(struct arasan_cf_dev *acdev, dma_addr_t src, dma_addr_t dest, u32 len)
398{
399 struct dma_async_tx_descriptor *tx;
400 struct dma_chan *chan = acdev->dma_chan;
401 dma_cookie_t cookie;
402 unsigned long flags = DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
403 DMA_COMPL_SKIP_DEST_UNMAP;
404 int ret = 0;
405
406 tx = chan->device->device_prep_dma_memcpy(chan, dest, src, len, flags);
407 if (!tx) {
408 dev_err(acdev->host->dev, "device_prep_dma_memcpy failed\n");
409 return -EAGAIN;
410 }
411
412 tx->callback = dma_callback;
413 tx->callback_param = acdev;
414 cookie = tx->tx_submit(tx);
415
416 ret = dma_submit_error(cookie);
417 if (ret) {
418 dev_err(acdev->host->dev, "dma_submit_error\n");
419 return ret;
420 }
421
422 chan->device->device_issue_pending(chan);
423
424 /* Wait for DMA to complete */
425 if (!wait_for_completion_timeout(&acdev->dma_completion, TIMEOUT)) {
426 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
427 dev_err(acdev->host->dev, "wait_for_completion_timeout\n");
428 return -ETIMEDOUT;
429 }
430
431 return ret;
432}
433
434static int sg_xfer(struct arasan_cf_dev *acdev, struct scatterlist *sg)
435{
436 dma_addr_t dest = 0, src = 0;
437 u32 xfer_cnt, sglen, dma_len, xfer_ctr;
438 u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
439 unsigned long flags;
440 int ret = 0;
441
442 sglen = sg_dma_len(sg);
443 if (write) {
444 src = sg_dma_address(sg);
445 dest = acdev->pbase + EXT_WRITE_PORT;
446 } else {
447 dest = sg_dma_address(sg);
448 src = acdev->pbase + EXT_READ_PORT;
449 }
450
451 /*
452 * For each sg:
453 * MAX_XFER_COUNT data will be transferred before we get transfer
25985edc 454 * complete interrupt. Between after FIFO_SIZE data
a480167b
VK		 455 * buffer available interrupt will be generated. At this time we will
456 * fill FIFO again: max FIFO_SIZE data.
457 */
458 while (sglen) {
459 xfer_cnt = min(sglen, MAX_XFER_COUNT);
460 spin_lock_irqsave(&acdev->host->lock, flags);
461 xfer_ctr = readl(acdev->vbase + XFER_CTR) &
462 ~XFER_COUNT_MASK;
463 writel(xfer_ctr | xfer_cnt | XFER_START,
464 acdev->vbase + XFER_CTR);
465 spin_unlock_irqrestore(&acdev->host->lock, flags);
466
25985edc 467 /* continue dma xfers until current sg is completed */
a480167b
VK		 468 while (xfer_cnt) {
469 /* wait for read to complete */
470 if (!write) {
471 ret = wait4buf(acdev);
472 if (ret)
473 goto fail;
474 }
475
476 /* read/write FIFO in chunk of FIFO_SIZE */
477 dma_len = min(xfer_cnt, FIFO_SIZE);
478 ret = dma_xfer(acdev, src, dest, dma_len);
479 if (ret) {
480 dev_err(acdev->host->dev, "dma failed");
481 goto fail;
482 }
483
484 if (write)
485 src += dma_len;
486 else
487 dest += dma_len;
488
489 sglen -= dma_len;
490 xfer_cnt -= dma_len;
491
492 /* wait for write to complete */
493 if (write) {
494 ret = wait4buf(acdev);
495 if (ret)
496 goto fail;
497 }
498 }
499 }
500
501fail:
502 spin_lock_irqsave(&acdev->host->lock, flags);
503 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
504 acdev->vbase + XFER_CTR);
505 spin_unlock_irqrestore(&acdev->host->lock, flags);
506
507 return ret;
508}
509
510/*
511 * This routine uses External DMA controller to read/write data to FIFO of CF
512 * controller. There are two xfer related interrupt supported by CF controller:
513 * - buf_avail: This interrupt is generated as soon as we have buffer of 512
514 * bytes available for reading or empty buffer available for writing.
515 * - xfer_done: This interrupt is generated on transfer of "xfer_size" amount of
516 * data to/from FIFO. xfer_size is programmed in XFER_CTR register.
517 *
518 * Max buffer size = FIFO_SIZE = 512 Bytes.
519 * Max xfer_size = MAX_XFER_COUNT = 256 KB.
520 */
521static void data_xfer(struct work_struct *work)
522{
523 struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
524 work);
525 struct ata_queued_cmd *qc = acdev->qc;
526 struct scatterlist *sg;
527 unsigned long flags;
528 u32 temp;
529 int ret = 0;
530
531 /* request dma channels */
532 /* dma_request_channel may sleep, so calling from process context */
60a230e4
VK		 533 acdev->dma_chan = dma_request_channel(acdev->mask, filter,
534 acdev->dma_priv);
a480167b
VK		 535 if (!acdev->dma_chan) {
536 dev_err(acdev->host->dev, "Unable to get dma_chan\n");
537 goto chan_request_fail;
538 }
539
540 for_each_sg(qc->sg, sg, qc->n_elem, temp) {
541 ret = sg_xfer(acdev, sg);
542 if (ret)
543 break;
544 }
545
546 dma_release_channel(acdev->dma_chan);
547
548 /* data xferred successfully */
549 if (!ret) {
550 u32 status;
551
552 spin_lock_irqsave(&acdev->host->lock, flags);
553 status = ioread8(qc->ap->ioaddr.altstatus_addr);
554 spin_unlock_irqrestore(&acdev->host->lock, flags);
555 if (status & (ATA_BUSY | ATA_DRQ)) {
556 ata_sff_queue_delayed_work(&acdev->dwork, 1);
557 return;
558 }
559
560 goto sff_intr;
561 }
562
563 cf_dumpregs(acdev);
564
565chan_request_fail:
566 spin_lock_irqsave(&acdev->host->lock, flags);
25985edc 567 /* error when transferring data to/from memory */
a480167b
VK		 568 qc->err_mask |= AC_ERR_HOST_BUS;
569 qc->ap->hsm_task_state = HSM_ST_ERR;
570
571 cf_ctrl_reset(acdev);
572 spin_unlock_irqrestore(qc->ap->lock, flags);
573sff_intr:
574 dma_complete(acdev);
575}
576
577static void delayed_finish(struct work_struct *work)
578{
579 struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
580 dwork.work);
581 struct ata_queued_cmd *qc = acdev->qc;
582 unsigned long flags;
583 u8 status;
584
585 spin_lock_irqsave(&acdev->host->lock, flags);
586 status = ioread8(qc->ap->ioaddr.altstatus_addr);
587 spin_unlock_irqrestore(&acdev->host->lock, flags);
588
589 if (status & (ATA_BUSY | ATA_DRQ))
590 ata_sff_queue_delayed_work(&acdev->dwork, 1);
591 else
592 dma_complete(acdev);
593}
594
595static irqreturn_t arasan_cf_interrupt(int irq, void *dev)
596{
597 struct arasan_cf_dev *acdev = ((struct ata_host *)dev)->private_data;
598 unsigned long flags;
599 u32 irqsts;
600
601 irqsts = readl(acdev->vbase + GIRQ_STS);
602 if (!(irqsts & GIRQ_CF))
603 return IRQ_NONE;
604
605 spin_lock_irqsave(&acdev->host->lock, flags);
606 irqsts = readl(acdev->vbase + IRQ_STS);
607 writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */
608 writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */
609
610 /* handle only relevant interrupts */
611 irqsts &= ~IGNORED_IRQS;
612
613 if (irqsts & CARD_DETECT_IRQ) {
614 cf_card_detect(acdev, 1);
615 spin_unlock_irqrestore(&acdev->host->lock, flags);
616 return IRQ_HANDLED;
617 }
618
619 if (irqsts & PIO_XFER_ERR_IRQ) {
620 acdev->dma_status = ATA_DMA_ERR;
621 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
622 acdev->vbase + XFER_CTR);
623 spin_unlock_irqrestore(&acdev->host->lock, flags);
624 complete(&acdev->cf_completion);
625 dev_err(acdev->host->dev, "pio xfer err irq\n");
626 return IRQ_HANDLED;
627 }
628
629 spin_unlock_irqrestore(&acdev->host->lock, flags);
630
631 if (irqsts & BUF_AVAIL_IRQ) {
632 complete(&acdev->cf_completion);
633 return IRQ_HANDLED;
634 }
635
636 if (irqsts & XFER_DONE_IRQ) {
637 struct ata_queued_cmd *qc = acdev->qc;
638
639 /* Send Complete only for write */
640 if (qc->tf.flags & ATA_TFLAG_WRITE)
641 complete(&acdev->cf_completion);
642 }
643
644 return IRQ_HANDLED;
645}
646
647static void arasan_cf_freeze(struct ata_port *ap)
648{
649 struct arasan_cf_dev *acdev = ap->host->private_data;
650
651 /* stop transfer and reset controller */
652 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
653 acdev->vbase + XFER_CTR);
654 cf_ctrl_reset(acdev);
655 acdev->dma_status = ATA_DMA_ERR;
656
657 ata_sff_dma_pause(ap);
658 ata_sff_freeze(ap);
659}
660
661void arasan_cf_error_handler(struct ata_port *ap)
662{
663 struct arasan_cf_dev *acdev = ap->host->private_data;
664
665 /*
666 * DMA transfers using an external DMA controller may be scheduled.
667 * Abort them before handling error. Refer data_xfer() for further
668 * details.
669 */
670 cancel_work_sync(&acdev->work);
671 cancel_delayed_work_sync(&acdev->dwork);
672 return ata_sff_error_handler(ap);
673}
674
675static void arasan_cf_dma_start(struct arasan_cf_dev *acdev)
676{
52bd4978
SS		 677 struct ata_queued_cmd *qc = acdev->qc;
678 struct ata_port *ap = qc->ap;
679 struct ata_taskfile *tf = &qc->tf;
a480167b 680 u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK;
52bd4978 681 u32 write = tf->flags & ATA_TFLAG_WRITE;
a480167b
VK		 682
683 xfer_ctr |= write ? XFER_WRITE : XFER_READ;
684 writel(xfer_ctr, acdev->vbase + XFER_CTR);
685
52bd4978 686 ap->ops->sff_exec_command(ap, tf);
a480167b
VK		 687 ata_sff_queue_work(&acdev->work);
688}
689
690unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc)
691{
692 struct ata_port *ap = qc->ap;
693 struct arasan_cf_dev *acdev = ap->host->private_data;
694
695 /* defer PIO handling to sff_qc_issue */
696 if (!ata_is_dma(qc->tf.protocol))
697 return ata_sff_qc_issue(qc);
698
699 /* select the device */
700 ata_wait_idle(ap);
701 ata_sff_dev_select(ap, qc->dev->devno);
702 ata_wait_idle(ap);
703
704 /* start the command */
705 switch (qc->tf.protocol) {
706 case ATA_PROT_DMA:
707 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
708
709 ap->ops->sff_tf_load(ap, &qc->tf);
710 acdev->dma_status = 0;
711 acdev->qc = qc;
712 arasan_cf_dma_start(acdev);
713 ap->hsm_task_state = HSM_ST_LAST;
714 break;
715
716 default:
717 WARN_ON(1);
718 return AC_ERR_SYSTEM;
719 }
720
721 return 0;
722}
723
724static void arasan_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
725{
726 struct arasan_cf_dev *acdev = ap->host->private_data;
727 u8 pio = adev->pio_mode - XFER_PIO_0;
728 unsigned long flags;
729 u32 val;
730
731 /* Arasan ctrl supports Mode0 -> Mode6 */
732 if (pio > 6) {
733 dev_err(ap->dev, "Unknown PIO mode\n");
734 return;
735 }
736
737 spin_lock_irqsave(&acdev->host->lock, flags);
738 val = readl(acdev->vbase + OP_MODE) &
739 ~(ULTRA_DMA_ENB | MULTI_WORD_DMA_ENB | DRQ_BLOCK_SIZE_MASK);
740 writel(val, acdev->vbase + OP_MODE);
741 val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK;
742 val |= pio << TRUEIDE_PIO_TIMING_SHIFT;
743 writel(val, acdev->vbase + TM_CFG);
744
745 cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 0);
746 cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 1);
747 spin_unlock_irqrestore(&acdev->host->lock, flags);
748}
749
750static void arasan_cf_set_dmamode(struct ata_port *ap, struct ata_device *adev)
751{
752 struct arasan_cf_dev *acdev = ap->host->private_data;
753 u32 opmode, tmcfg, dma_mode = adev->dma_mode;
754 unsigned long flags;
755
756 spin_lock_irqsave(&acdev->host->lock, flags);
757 opmode = readl(acdev->vbase + OP_MODE) &
758 ~(MULTI_WORD_DMA_ENB | ULTRA_DMA_ENB);
759 tmcfg = readl(acdev->vbase + TM_CFG);
760
761 if ((dma_mode >= XFER_UDMA_0) && (dma_mode <= XFER_UDMA_6)) {
762 opmode |= ULTRA_DMA_ENB;
763 tmcfg &= ~ULTRA_DMA_TIMING_MASK;
764 tmcfg |= (dma_mode - XFER_UDMA_0) << ULTRA_DMA_TIMING_SHIFT;
765 } else if ((dma_mode >= XFER_MW_DMA_0) && (dma_mode <= XFER_MW_DMA_4)) {
766 opmode |= MULTI_WORD_DMA_ENB;
767 tmcfg &= ~TRUEIDE_MWORD_DMA_TIMING_MASK;
768 tmcfg |= (dma_mode - XFER_MW_DMA_0) <<
769 TRUEIDE_MWORD_DMA_TIMING_SHIFT;
770 } else {
771 dev_err(ap->dev, "Unknown DMA mode\n");
772 spin_unlock_irqrestore(&acdev->host->lock, flags);
773 return;
774 }
775
776 writel(opmode, acdev->vbase + OP_MODE);
777 writel(tmcfg, acdev->vbase + TM_CFG);
778 writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR);
779
780 cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 0);
781 cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 1);
782 spin_unlock_irqrestore(&acdev->host->lock, flags);
783}
784
785static struct ata_port_operations arasan_cf_ops = {
786 .inherits = &ata_sff_port_ops,
787 .freeze = arasan_cf_freeze,
788 .error_handler = arasan_cf_error_handler,
789 .qc_issue = arasan_cf_qc_issue,
790 .set_piomode = arasan_cf_set_piomode,
791 .set_dmamode = arasan_cf_set_dmamode,
792};
793
0ec24914 794static int arasan_cf_probe(struct platform_device *pdev)
a480167b
VK		 795{
796 struct arasan_cf_dev *acdev;
797 struct arasan_cf_pdata *pdata = dev_get_platdata(&pdev->dev);
798 struct ata_host *host;
799 struct ata_port *ap;
800 struct resource *res;
801 irq_handler_t irq_handler = NULL;
802 int ret = 0;
803
804 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
805 if (!res)
806 return -EINVAL;
807
808 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
809 DRIVER_NAME)) {
810 dev_warn(&pdev->dev, "Failed to get memory region resource\n");
811 return -ENOENT;
812 }
813
814 acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL);
815 if (!acdev) {
816 dev_warn(&pdev->dev, "kzalloc fail\n");
817 return -ENOMEM;
818 }
819
820 /* if irq is 0, support only PIO */
821 acdev->irq = platform_get_irq(pdev, 0);
822 if (acdev->irq)
823 irq_handler = arasan_cf_interrupt;
824 else
825 pdata->quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
826
827 acdev->pbase = res->start;
828 acdev->vbase = devm_ioremap_nocache(&pdev->dev, res->start,
829 resource_size(res));
830 if (!acdev->vbase) {
831 dev_warn(&pdev->dev, "ioremap fail\n");
832 return -ENOMEM;
833 }
834
a480167b
VK		 835 acdev->clk = clk_get(&pdev->dev, NULL);
836 if (IS_ERR(acdev->clk)) {
837 dev_warn(&pdev->dev, "Clock not found\n");
838 return PTR_ERR(acdev->clk);
839 }
a480167b
VK		 840
841 /* allocate host */
842 host = ata_host_alloc(&pdev->dev, 1);
843 if (!host) {
844 ret = -ENOMEM;
845 dev_warn(&pdev->dev, "alloc host fail\n");
846 goto free_clk;
847 }
848
849 ap = host->ports[0];
850 host->private_data = acdev;
851 acdev->host = host;
852 ap->ops = &arasan_cf_ops;
853 ap->pio_mask = ATA_PIO6;
854 ap->mwdma_mask = ATA_MWDMA4;
855 ap->udma_mask = ATA_UDMA6;
856
857 init_completion(&acdev->cf_completion);
858 init_completion(&acdev->dma_completion);
859 INIT_WORK(&acdev->work, data_xfer);
860 INIT_DELAYED_WORK(&acdev->dwork, delayed_finish);
861 dma_cap_set(DMA_MEMCPY, acdev->mask);
60a230e4 862 acdev->dma_priv = pdata->dma_priv;
a480167b
VK		 863
864 /* Handle platform specific quirks */
865 if (pdata->quirk) {
866 if (pdata->quirk & CF_BROKEN_PIO) {
867 ap->ops->set_piomode = NULL;
868 ap->pio_mask = 0;
869 }
870 if (pdata->quirk & CF_BROKEN_MWDMA)
871 ap->mwdma_mask = 0;
872 if (pdata->quirk & CF_BROKEN_UDMA)
873 ap->udma_mask = 0;
874 }
875 ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI;
876
877 ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT;
878 ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT;
879 ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR;
880 ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR;
881 ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC;
882 ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN;
883 ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL;
884 ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH;
885 ap->ioaddr.device_addr = acdev->vbase + ATA_SH;
886 ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD;
887 ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD;
888 ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR;
889 ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR;
890
a17139b6
JG		 891 ata_port_desc(ap, "phy_addr %llx virt_addr %p",
892 (unsigned long long) res->start, acdev->vbase);
a480167b
VK		 893
894 ret = cf_init(acdev);
895 if (ret)
896 goto free_clk;
897
898 cf_card_detect(acdev, 0);
899
900 return ata_host_activate(host, acdev->irq, irq_handler, 0,
901 &arasan_cf_sht);
902
903free_clk:
a480167b 904 clk_put(acdev->clk);
a480167b
VK		 905 return ret;
906}
907
0ec24914 908static int arasan_cf_remove(struct platform_device *pdev)
a480167b
VK		 909{
910 struct ata_host *host = dev_get_drvdata(&pdev->dev);
911 struct arasan_cf_dev *acdev = host->ports[0]->private_data;
912
913 ata_host_detach(host);
914 cf_exit(acdev);
a480167b 915 clk_put(acdev->clk);
a480167b
VK		 916
917 return 0;
918}
919
29448ec1 920#ifdef CONFIG_PM_SLEEP
a480167b
VK		 921static int arasan_cf_suspend(struct device *dev)
922{
90f0adf0 923 struct ata_host *host = dev_get_drvdata(dev);
a480167b
VK		 924 struct arasan_cf_dev *acdev = host->ports[0]->private_data;
925
40679b3c 926 if (acdev->dma_chan)
a480167b
VK		 927 acdev->dma_chan->device->device_control(acdev->dma_chan,
928 DMA_TERMINATE_ALL, 0);
40679b3c 929
a480167b
VK		 930 cf_exit(acdev);
931 return ata_host_suspend(host, PMSG_SUSPEND);
932}
933
934static int arasan_cf_resume(struct device *dev)
935{
90f0adf0 936 struct ata_host *host = dev_get_drvdata(dev);
a480167b
VK		 937 struct arasan_cf_dev *acdev = host->ports[0]->private_data;
938
939 cf_init(acdev);
940 ata_host_resume(host);
941
942 return 0;
943}
fb9751d4 944#endif
a480167b 945
40679b3c 946static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume);
a480167b 947
26fdaa74
VK		 948#ifdef CONFIG_OF
949static const struct of_device_id arasan_cf_id_table[] = {
950 { .compatible = "arasan,cf-spear1340" },
951 {}
952};
953MODULE_DEVICE_TABLE(of, arasan_cf_id_table);
954#endif
955
a480167b
VK		 956static struct platform_driver arasan_cf_driver = {
957 .probe = arasan_cf_probe,
0ec24914 958 .remove = arasan_cf_remove,
a480167b
VK		 959 .driver = {
960 .name = DRIVER_NAME,
961 .owner = THIS_MODULE,
40679b3c 962 .pm = &arasan_cf_pm_ops,
26fdaa74 963 .of_match_table = of_match_ptr(arasan_cf_id_table),
a480167b
VK		 964 },
965};
966
99c8ea3e 967module_platform_driver(arasan_cf_driver);
a480167b 968
10d8935f 969MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
a480167b
VK		 970MODULE_DESCRIPTION("Arasan ATA Compact Flash driver");
971MODULE_LICENSE("GPL");
972MODULE_ALIAS("platform:" DRIVER_NAME);
kernel source for telekom puls (alcatel/mediatek)