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defconfig: exynos9610: Re-add dropped Wi-Fi AP options lost
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
9bb9a39c 27 * as Documentation/driver-api/libata.rst
365cfa1e
AV		 28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e 37#include <linux/module.h>
7ccd2c1b 38#include <linux/nospec.h>
365cfa1e
AV		 39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
d684a90d 47#include <linux/pci.h>
365cfa1e 48#include "ahci.h"
65fe1f0f 49#include "libata.h"
365cfa1e
AV		 50
51static int ahci_skip_host_reset;
52int ahci_ignore_sss;
53EXPORT_SYMBOL_GPL(ahci_ignore_sss);
54
55module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
56MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
57
58module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
59MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60
6b7ae954
TH		 61static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
62 unsigned hints);
365cfa1e
AV		 63static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
64static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
65 size_t size);
66static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
67 ssize_t size);
68
69
70
71static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
72static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 73static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74static int ahci_port_start(struct ata_port *ap);
75static void ahci_port_stop(struct ata_port *ap);
76static void ahci_qc_prep(struct ata_queued_cmd *qc);
77static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78static void ahci_freeze(struct ata_port *ap);
79static void ahci_thaw(struct ata_port *ap);
65fe1f0f 80static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 81static void ahci_enable_fbs(struct ata_port *ap);
82static void ahci_disable_fbs(struct ata_port *ap);
83static void ahci_pmp_attach(struct ata_port *ap);
84static void ahci_pmp_detach(struct ata_port *ap);
85static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
345347c5
YHC		 87static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
365cfa1e
AV		 89static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 92static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 93static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 94#ifdef CONFIG_PM
95static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96#endif
97static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100static void ahci_init_sw_activity(struct ata_link *link);
101
102static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
c0623166
HZ		 110static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
6e5fe5b1
HR		 115static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
f070d671 117static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
365cfa1e
AV		 118
119static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 123static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 125static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 126
fad16e7a 127struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
c0623166 135 &dev_attr_em_buffer,
6e5fe5b1 136 &dev_attr_em_message_supported,
365cfa1e
AV		 137 NULL
138};
fad16e7a 139EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 140
fad16e7a 141struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
84f95243 144 &dev_attr_ncq_prio_enable,
365cfa1e
AV		 145 NULL
146};
fad16e7a 147EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 148
149struct ata_port_operations ahci_ops = {
150 .inherits = &sata_pmp_port_ops,
151
152 .qc_defer = ahci_pmp_qc_defer,
153 .qc_prep = ahci_qc_prep,
154 .qc_issue = ahci_qc_issue,
155 .qc_fill_rtf = ahci_qc_fill_rtf,
156
157 .freeze = ahci_freeze,
158 .thaw = ahci_thaw,
159 .softreset = ahci_softreset,
160 .hardreset = ahci_hardreset,
161 .postreset = ahci_postreset,
162 .pmp_softreset = ahci_softreset,
163 .error_handler = ahci_error_handler,
164 .post_internal_cmd = ahci_post_internal_cmd,
165 .dev_config = ahci_dev_config,
166
167 .scr_read = ahci_scr_read,
168 .scr_write = ahci_scr_write,
169 .pmp_attach = ahci_pmp_attach,
170 .pmp_detach = ahci_pmp_detach,
171
6b7ae954 172 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 173 .em_show = ahci_led_show,
174 .em_store = ahci_led_store,
175 .sw_activity_show = ahci_activity_show,
176 .sw_activity_store = ahci_activity_store,
439d7a35 177 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 178#ifdef CONFIG_PM
179 .port_suspend = ahci_port_suspend,
180 .port_resume = ahci_port_resume,
181#endif
182 .port_start = ahci_port_start,
183 .port_stop = ahci_port_stop,
184};
185EXPORT_SYMBOL_GPL(ahci_ops);
186
345347c5
YHC		 187struct ata_port_operations ahci_pmp_retry_srst_ops = {
188 .inherits = &ahci_ops,
189 .softreset = ahci_pmp_retry_softreset,
190};
191EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192
ed08d40c 193static bool ahci_em_messages __read_mostly = true;
365cfa1e 194EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 195module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 196/* add other LED protocol types when they become supported */
197MODULE_PARM_DESC(ahci_em_messages,
008dbd61 198 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 199
ed08d40c
CL		 200/* device sleep idle timeout in ms */
201static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 202module_param(devslp_idle_timeout, int, 0644);
203MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
204
365cfa1e
AV		 205static void ahci_enable_ahci(void __iomem *mmio)
206{
207 int i;
208 u32 tmp;
209
210 /* turn on AHCI_EN */
211 tmp = readl(mmio + HOST_CTL);
212 if (tmp & HOST_AHCI_EN)
213 return;
214
215 /* Some controllers need AHCI_EN to be written multiple times.
216 * Try a few times before giving up.
217 */
218 for (i = 0; i < 5; i++) {
219 tmp |= HOST_AHCI_EN;
220 writel(tmp, mmio + HOST_CTL);
221 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
222 if (tmp & HOST_AHCI_EN)
223 return;
224 msleep(10);
225 }
226
227 WARN_ON(1);
228}
229
bb03c640
MW		 230/**
231 * ahci_rpm_get_port - Make sure the port is powered on
232 * @ap: Port to power on
233 *
234 * Whenever there is need to access the AHCI host registers outside of
235 * normal execution paths, call this function to make sure the host is
236 * actually powered on.
237 */
238static int ahci_rpm_get_port(struct ata_port *ap)
239{
240 return pm_runtime_get_sync(ap->dev);
241}
242
243/**
244 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
245 * @ap: Port to power down
246 *
247 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
248 * if it has no more active users.
249 */
250static void ahci_rpm_put_port(struct ata_port *ap)
251{
252 pm_runtime_put(ap->dev);
253}
254
365cfa1e
AV		 255static ssize_t ahci_show_host_caps(struct device *dev,
256 struct device_attribute *attr, char *buf)
257{
258 struct Scsi_Host *shost = class_to_shost(dev);
259 struct ata_port *ap = ata_shost_to_port(shost);
260 struct ahci_host_priv *hpriv = ap->host->private_data;
261
262 return sprintf(buf, "%x\n", hpriv->cap);
263}
264
265static ssize_t ahci_show_host_cap2(struct device *dev,
266 struct device_attribute *attr, char *buf)
267{
268 struct Scsi_Host *shost = class_to_shost(dev);
269 struct ata_port *ap = ata_shost_to_port(shost);
270 struct ahci_host_priv *hpriv = ap->host->private_data;
271
272 return sprintf(buf, "%x\n", hpriv->cap2);
273}
274
275static ssize_t ahci_show_host_version(struct device *dev,
276 struct device_attribute *attr, char *buf)
277{
278 struct Scsi_Host *shost = class_to_shost(dev);
279 struct ata_port *ap = ata_shost_to_port(shost);
280 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 281
8ea909cb 282 return sprintf(buf, "%x\n", hpriv->version);
365cfa1e
AV		 283}
284
285static ssize_t ahci_show_port_cmd(struct device *dev,
286 struct device_attribute *attr, char *buf)
287{
288 struct Scsi_Host *shost = class_to_shost(dev);
289 struct ata_port *ap = ata_shost_to_port(shost);
290 void __iomem *port_mmio = ahci_port_base(ap);
bb03c640 291 ssize_t ret;
365cfa1e 292
bb03c640
MW		 293 ahci_rpm_get_port(ap);
294 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
295 ahci_rpm_put_port(ap);
296
297 return ret;
365cfa1e
AV		 298}
299
c0623166
HZ		 300static ssize_t ahci_read_em_buffer(struct device *dev,
301 struct device_attribute *attr, char *buf)
302{
303 struct Scsi_Host *shost = class_to_shost(dev);
304 struct ata_port *ap = ata_shost_to_port(shost);
305 struct ahci_host_priv *hpriv = ap->host->private_data;
306 void __iomem *mmio = hpriv->mmio;
307 void __iomem *em_mmio = mmio + hpriv->em_loc;
308 u32 em_ctl, msg;
309 unsigned long flags;
310 size_t count;
311 int i;
312
bb03c640 313 ahci_rpm_get_port(ap);
c0623166
HZ		 314 spin_lock_irqsave(ap->lock, flags);
315
316 em_ctl = readl(mmio + HOST_EM_CTL);
317 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
318 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
319 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 320 ahci_rpm_put_port(ap);
c0623166
HZ		 321 return -EINVAL;
322 }
323
324 if (!(em_ctl & EM_CTL_MR)) {
325 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 326 ahci_rpm_put_port(ap);
c0623166
HZ		 327 return -EAGAIN;
328 }
329
330 if (!(em_ctl & EM_CTL_SMB))
331 em_mmio += hpriv->em_buf_sz;
332
333 count = hpriv->em_buf_sz;
334
335 /* the count should not be larger than PAGE_SIZE */
336 if (count > PAGE_SIZE) {
337 if (printk_ratelimit())
a9a79dfe
JP		 338 ata_port_warn(ap,
339 "EM read buffer size too large: "
340 "buffer size %u, page size %lu\n",
341 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 342 count = PAGE_SIZE;
343 }
344
345 for (i = 0; i < count; i += 4) {
346 msg = readl(em_mmio + i);
347 buf[i] = msg & 0xff;
348 buf[i + 1] = (msg >> 8) & 0xff;
349 buf[i + 2] = (msg >> 16) & 0xff;
350 buf[i + 3] = (msg >> 24) & 0xff;
351 }
352
353 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 354 ahci_rpm_put_port(ap);
c0623166
HZ		 355
356 return i;
357}
358
359static ssize_t ahci_store_em_buffer(struct device *dev,
360 struct device_attribute *attr,
361 const char *buf, size_t size)
362{
363 struct Scsi_Host *shost = class_to_shost(dev);
364 struct ata_port *ap = ata_shost_to_port(shost);
365 struct ahci_host_priv *hpriv = ap->host->private_data;
366 void __iomem *mmio = hpriv->mmio;
367 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 368 const unsigned char *msg_buf = buf;
c0623166
HZ		 369 u32 em_ctl, msg;
370 unsigned long flags;
371 int i;
372
373 /* check size validity */
374 if (!(ap->flags & ATA_FLAG_EM) ||
375 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
376 size % 4 || size > hpriv->em_buf_sz)
377 return -EINVAL;
378
bb03c640 379 ahci_rpm_get_port(ap);
c0623166
HZ		 380 spin_lock_irqsave(ap->lock, flags);
381
382 em_ctl = readl(mmio + HOST_EM_CTL);
383 if (em_ctl & EM_CTL_TM) {
384 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 385 ahci_rpm_put_port(ap);
c0623166
HZ		 386 return -EBUSY;
387 }
388
389 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 390 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
391 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 392 writel(msg, em_mmio + i);
393 }
394
395 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
396
397 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 398 ahci_rpm_put_port(ap);
c0623166
HZ		 399
400 return size;
401}
402
6e5fe5b1
HR		 403static ssize_t ahci_show_em_supported(struct device *dev,
404 struct device_attribute *attr, char *buf)
405{
406 struct Scsi_Host *shost = class_to_shost(dev);
407 struct ata_port *ap = ata_shost_to_port(shost);
408 struct ahci_host_priv *hpriv = ap->host->private_data;
409 void __iomem *mmio = hpriv->mmio;
410 u32 em_ctl;
411
bb03c640 412 ahci_rpm_get_port(ap);
6e5fe5b1 413 em_ctl = readl(mmio + HOST_EM_CTL);
bb03c640 414 ahci_rpm_put_port(ap);
6e5fe5b1
HR		 415
416 return sprintf(buf, "%s%s%s%s\n",
417 em_ctl & EM_CTL_LED ? "led " : "",
418 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
419 em_ctl & EM_CTL_SES ? "ses-2 " : "",
420 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
421}
422
365cfa1e
AV		 423/**
424 * ahci_save_initial_config - Save and fixup initial config values
425 * @dev: target AHCI device
426 * @hpriv: host private area to store config values
365cfa1e
AV		 427 *
428 * Some registers containing configuration info might be setup by
429 * BIOS and might be cleared on reset. This function saves the
430 * initial values of those registers into @hpriv such that they
431 * can be restored after controller reset.
432 *
433 * If inconsistent, config values are fixed up by this function.
434 *
039ece38
HG		 435 * If it is not set already this function sets hpriv->start_engine to
436 * ahci_start_engine.
437 *
365cfa1e
AV		 438 * LOCKING:
439 * None.
440 */
725c7b57 441void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
365cfa1e
AV		 442{
443 void __iomem *mmio = hpriv->mmio;
444 u32 cap, cap2, vers, port_map;
445 int i;
446
447 /* make sure AHCI mode is enabled before accessing CAP */
448 ahci_enable_ahci(mmio);
449
450 /* Values prefixed with saved_ are written back to host after
451 * reset. Values without are used for driver operation.
452 */
453 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
454 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
455
456 /* CAP2 register is only defined for AHCI 1.2 and later */
457 vers = readl(mmio + HOST_VERSION);
458 if ((vers >> 16) > 1 ||
459 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
460 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
461 else
462 hpriv->saved_cap2 = cap2 = 0;
463
464 /* some chips have errata preventing 64bit use */
465 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 466 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 467 cap &= ~HOST_CAP_64;
468 }
469
470 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 471 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 472 cap &= ~HOST_CAP_NCQ;
473 }
474
475 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 476 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 477 cap |= HOST_CAP_NCQ;
478 }
479
480 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 481 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 482 cap &= ~HOST_CAP_PMP;
483 }
484
485 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 486 dev_info(dev,
487 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 488 cap &= ~HOST_CAP_SNTF;
489 }
490
0cf4a7d6
JP		 491 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
492 dev_info(dev,
493 "controller can't do DEVSLP, turning off\n");
494 cap2 &= ~HOST_CAP2_SDS;
495 cap2 &= ~HOST_CAP2_SADM;
496 }
497
5f173107 498 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 499 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 500 cap |= HOST_CAP_FBS;
501 }
502
888d91a0
KW		 503 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
504 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
505 cap &= ~HOST_CAP_FBS;
506 }
507
ef0da1bf
DB		 508 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
509 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
510 cap |= HOST_CAP_ALPM;
511 }
512
725c7b57 513 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
a44fec1f 514 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
725c7b57
AT		 515 port_map, hpriv->force_port_map);
516 port_map = hpriv->force_port_map;
2fd0f46c 517 hpriv->saved_port_map = port_map;
365cfa1e
AV		 518 }
519
725c7b57 520 if (hpriv->mask_port_map) {
a44fec1f
JP		 521 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
522 port_map,
725c7b57
AT		 523 port_map & hpriv->mask_port_map);
524 port_map &= hpriv->mask_port_map;
365cfa1e
AV		 525 }
526
527 /* cross check port_map and cap.n_ports */
528 if (port_map) {
529 int map_ports = 0;
530
531 for (i = 0; i < AHCI_MAX_PORTS; i++)
532 if (port_map & (1 << i))
533 map_ports++;
534
535 /* If PI has more ports than n_ports, whine, clear
536 * port_map and let it be generated from n_ports.
537 */
538 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 539 dev_warn(dev,
540 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
541 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 542 port_map = 0;
543 }
544 }
545
566d1827
TH		 546 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
547 if (!port_map && vers < 0x10300) {
365cfa1e 548 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 549 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 550
551 /* write the fixed up value to the PI register */
552 hpriv->saved_port_map = port_map;
553 }
554
555 /* record values to use during operation */
556 hpriv->cap = cap;
557 hpriv->cap2 = cap2;
8ea909cb 558 hpriv->version = readl(mmio + HOST_VERSION);
365cfa1e 559 hpriv->port_map = port_map;
039ece38
HG		 560
561 if (!hpriv->start_engine)
562 hpriv->start_engine = ahci_start_engine;
f070d671 563
48c0bf9a
EW		 564 if (!hpriv->stop_engine)
565 hpriv->stop_engine = ahci_stop_engine;
566
f070d671 567 if (!hpriv->irq_handler)
d867b95f 568 hpriv->irq_handler = ahci_single_level_irq_intr;
365cfa1e
AV		 569}
570EXPORT_SYMBOL_GPL(ahci_save_initial_config);
571
572/**
573 * ahci_restore_initial_config - Restore initial config
574 * @host: target ATA host
575 *
576 * Restore initial config stored by ahci_save_initial_config().
577 *
578 * LOCKING:
579 * None.
580 */
581static void ahci_restore_initial_config(struct ata_host *host)
582{
583 struct ahci_host_priv *hpriv = host->private_data;
584 void __iomem *mmio = hpriv->mmio;
585
586 writel(hpriv->saved_cap, mmio + HOST_CAP);
587 if (hpriv->saved_cap2)
588 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
589 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
590 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
591}
592
593static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
594{
595 static const int offset[] = {
596 [SCR_STATUS] = PORT_SCR_STAT,
597 [SCR_CONTROL] = PORT_SCR_CTL,
598 [SCR_ERROR] = PORT_SCR_ERR,
599 [SCR_ACTIVE] = PORT_SCR_ACT,
600 [SCR_NOTIFICATION] = PORT_SCR_NTF,
601 };
602 struct ahci_host_priv *hpriv = ap->host->private_data;
603
604 if (sc_reg < ARRAY_SIZE(offset) &&
605 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
606 return offset[sc_reg];
607 return 0;
608}
609
610static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
611{
612 void __iomem *port_mmio = ahci_port_base(link->ap);
613 int offset = ahci_scr_offset(link->ap, sc_reg);
614
615 if (offset) {
616 *val = readl(port_mmio + offset);
617 return 0;
618 }
619 return -EINVAL;
620}
621
622static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
623{
624 void __iomem *port_mmio = ahci_port_base(link->ap);
625 int offset = ahci_scr_offset(link->ap, sc_reg);
626
627 if (offset) {
628 writel(val, port_mmio + offset);
629 return 0;
630 }
631 return -EINVAL;
632}
633
634void ahci_start_engine(struct ata_port *ap)
635{
636 void __iomem *port_mmio = ahci_port_base(ap);
637 u32 tmp;
638
639 /* start DMA */
640 tmp = readl(port_mmio + PORT_CMD);
641 tmp |= PORT_CMD_START;
642 writel(tmp, port_mmio + PORT_CMD);
643 readl(port_mmio + PORT_CMD); /* flush */
644}
645EXPORT_SYMBOL_GPL(ahci_start_engine);
646
647int ahci_stop_engine(struct ata_port *ap)
648{
649 void __iomem *port_mmio = ahci_port_base(ap);
fb329633 650 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 651 u32 tmp;
652
fb329633
DP		 653 /*
654 * On some controllers, stopping a port's DMA engine while the port
655 * is in ALPM state (partial or slumber) results in failures on
656 * subsequent DMA engine starts. For those controllers, put the
657 * port back in active state before stopping its DMA engine.
658 */
659 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
660 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
661 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
662 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
663 return -EIO;
664 }
665
365cfa1e
AV		 666 tmp = readl(port_mmio + PORT_CMD);
667
668 /* check if the HBA is idle */
669 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
670 return 0;
671
672 /* setting HBA to idle */
673 tmp &= ~PORT_CMD_START;
674 writel(tmp, port_mmio + PORT_CMD);
675
676 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 677 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 678 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
679 if (tmp & PORT_CMD_LIST_ON)
680 return -EIO;
681
682 return 0;
683}
684EXPORT_SYMBOL_GPL(ahci_stop_engine);
685
39e0ee99 686void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 687{
688 void __iomem *port_mmio = ahci_port_base(ap);
689 struct ahci_host_priv *hpriv = ap->host->private_data;
690 struct ahci_port_priv *pp = ap->private_data;
691 u32 tmp;
692
693 /* set FIS registers */
694 if (hpriv->cap & HOST_CAP_64)
695 writel((pp->cmd_slot_dma >> 16) >> 16,
696 port_mmio + PORT_LST_ADDR_HI);
697 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
698
699 if (hpriv->cap & HOST_CAP_64)
700 writel((pp->rx_fis_dma >> 16) >> 16,
701 port_mmio + PORT_FIS_ADDR_HI);
702 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
703
704 /* enable FIS reception */
705 tmp = readl(port_mmio + PORT_CMD);
706 tmp |= PORT_CMD_FIS_RX;
707 writel(tmp, port_mmio + PORT_CMD);
708
709 /* flush */
710 readl(port_mmio + PORT_CMD);
711}
39e0ee99 712EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 713
714static int ahci_stop_fis_rx(struct ata_port *ap)
715{
716 void __iomem *port_mmio = ahci_port_base(ap);
717 u32 tmp;
718
719 /* disable FIS reception */
720 tmp = readl(port_mmio + PORT_CMD);
721 tmp &= ~PORT_CMD_FIS_RX;
722 writel(tmp, port_mmio + PORT_CMD);
723
724 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 725 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 726 PORT_CMD_FIS_ON, 10, 1000);
727 if (tmp & PORT_CMD_FIS_ON)
728 return -EBUSY;
729
730 return 0;
731}
732
733static void ahci_power_up(struct ata_port *ap)
734{
735 struct ahci_host_priv *hpriv = ap->host->private_data;
736 void __iomem *port_mmio = ahci_port_base(ap);
737 u32 cmd;
738
739 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
740
741 /* spin up device */
742 if (hpriv->cap & HOST_CAP_SSS) {
743 cmd |= PORT_CMD_SPIN_UP;
744 writel(cmd, port_mmio + PORT_CMD);
745 }
746
747 /* wake up link */
748 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
749}
750
6b7ae954
TH		 751static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
752 unsigned int hints)
365cfa1e 753{
6b7ae954 754 struct ata_port *ap = link->ap;
365cfa1e 755 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 756 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 757 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 758
6b7ae954 759 if (policy != ATA_LPM_MAX_POWER) {
fb329633
DP		 760 /* wakeup flag only applies to the max power policy */
761 hints &= ~ATA_LPM_WAKE_ONLY;
762
365cfa1e 763 /*
6b7ae954
TH		 764 * Disable interrupts on Phy Ready. This keeps us from
765 * getting woken up due to spurious phy ready
766 * interrupts.
365cfa1e 767 */
6b7ae954
TH		 768 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
769 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
770
771 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 772 }
773
6b7ae954
TH		 774 if (hpriv->cap & HOST_CAP_ALPM) {
775 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 776
6b7ae954 777 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
fb329633
DP		 778 if (!(hints & ATA_LPM_WAKE_ONLY))
779 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
6b7ae954 780 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 781
6b7ae954
TH		 782 writel(cmd, port_mmio + PORT_CMD);
783 readl(port_mmio + PORT_CMD);
365cfa1e 784
6b7ae954 785 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 786 ata_msleep(ap, 10);
fb329633
DP		 787
788 if (hints & ATA_LPM_WAKE_ONLY)
789 return 0;
6b7ae954
TH		 790 } else {
791 cmd |= PORT_CMD_ALPE;
792 if (policy == ATA_LPM_MIN_POWER)
793 cmd |= PORT_CMD_ASP;
365cfa1e 794
6b7ae954
TH		 795 /* write out new cmd value */
796 writel(cmd, port_mmio + PORT_CMD);
797 }
798 }
365cfa1e 799
65fe1f0f
SH		 800 /* set aggressive device sleep */
801 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
802 (hpriv->cap2 & HOST_CAP2_SADM) &&
803 (link->device->flags & ATA_DFLAG_DEVSLP)) {
804 if (policy == ATA_LPM_MIN_POWER)
805 ahci_set_aggressive_devslp(ap, true);
806 else
807 ahci_set_aggressive_devslp(ap, false);
808 }
809
6b7ae954
TH		 810 if (policy == ATA_LPM_MAX_POWER) {
811 sata_link_scr_lpm(link, policy, false);
812
813 /* turn PHYRDY IRQ back on */
814 pp->intr_mask |= PORT_IRQ_PHYRDY;
815 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
816 }
365cfa1e 817
365cfa1e
AV		 818 return 0;
819}
820
821#ifdef CONFIG_PM
822static void ahci_power_down(struct ata_port *ap)
823{
824 struct ahci_host_priv *hpriv = ap->host->private_data;
825 void __iomem *port_mmio = ahci_port_base(ap);
826 u32 cmd, scontrol;
827
828 if (!(hpriv->cap & HOST_CAP_SSS))
829 return;
830
831 /* put device into listen mode, first set PxSCTL.DET to 0 */
832 scontrol = readl(port_mmio + PORT_SCR_CTL);
833 scontrol &= ~0xf;
834 writel(scontrol, port_mmio + PORT_SCR_CTL);
835
836 /* then set PxCMD.SUD to 0 */
837 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
838 cmd &= ~PORT_CMD_SPIN_UP;
839 writel(cmd, port_mmio + PORT_CMD);
840}
841#endif
842
843static void ahci_start_port(struct ata_port *ap)
844{
66583c9f 845 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 846 struct ahci_port_priv *pp = ap->private_data;
847 struct ata_link *link;
848 struct ahci_em_priv *emp;
849 ssize_t rc;
850 int i;
851
852 /* enable FIS reception */
853 ahci_start_fis_rx(ap);
854
66583c9f
BN		 855 /* enable DMA */
856 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 857 hpriv->start_engine(ap);
66583c9f 858
365cfa1e
AV		 859 /* turn on LEDs */
860 if (ap->flags & ATA_FLAG_EM) {
861 ata_for_each_link(link, ap, EDGE) {
862 emp = &pp->em_priv[link->pmp];
863
864 /* EM Transmit bit maybe busy during init */
865 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 866 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 867 emp->led_state,
868 4);
fa070ee6
LD		 869 /*
870 * If busy, give a breather but do not
871 * release EH ownership by using msleep()
872 * instead of ata_msleep(). EM Transmit
873 * bit is busy for the whole host and
874 * releasing ownership will cause other
875 * ports to fail the same way.
876 */
365cfa1e 877 if (rc == -EBUSY)
fa070ee6 878 msleep(1);
365cfa1e
AV		 879 else
880 break;
881 }
882 }
883 }
884
885 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
886 ata_for_each_link(link, ap, EDGE)
887 ahci_init_sw_activity(link);
888
889}
890
891static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
892{
893 int rc;
48c0bf9a 894 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 895
896 /* disable DMA */
48c0bf9a 897 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 898 if (rc) {
899 *emsg = "failed to stop engine";
900 return rc;
901 }
902
903 /* disable FIS reception */
904 rc = ahci_stop_fis_rx(ap);
905 if (rc) {
906 *emsg = "failed stop FIS RX";
907 return rc;
908 }
909
910 return 0;
911}
912
913int ahci_reset_controller(struct ata_host *host)
914{
915 struct ahci_host_priv *hpriv = host->private_data;
916 void __iomem *mmio = hpriv->mmio;
917 u32 tmp;
918
919 /* we must be in AHCI mode, before using anything
920 * AHCI-specific, such as HOST_RESET.
921 */
922 ahci_enable_ahci(mmio);
923
924 /* global controller reset */
925 if (!ahci_skip_host_reset) {
926 tmp = readl(mmio + HOST_CTL);
927 if ((tmp & HOST_RESET) == 0) {
928 writel(tmp | HOST_RESET, mmio + HOST_CTL);
929 readl(mmio + HOST_CTL); /* flush */
930 }
931
932 /*
933 * to perform host reset, OS should set HOST_RESET
934 * and poll until this bit is read to be "0".
935 * reset must complete within 1 second, or
936 * the hardware should be considered fried.
937 */
97750ceb 938 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 939 HOST_RESET, 10, 1000);
940
941 if (tmp & HOST_RESET) {
a44fec1f
JP		 942 dev_err(host->dev, "controller reset failed (0x%x)\n",
943 tmp);
365cfa1e
AV		 944 return -EIO;
945 }
946
947 /* turn on AHCI mode */
948 ahci_enable_ahci(mmio);
949
950 /* Some registers might be cleared on reset. Restore
951 * initial values.
952 */
7fab72f8
DB		 953 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
954 ahci_restore_initial_config(host);
365cfa1e 955 } else
a44fec1f 956 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 957
958 return 0;
959}
960EXPORT_SYMBOL_GPL(ahci_reset_controller);
961
962static void ahci_sw_activity(struct ata_link *link)
963{
964 struct ata_port *ap = link->ap;
965 struct ahci_port_priv *pp = ap->private_data;
966 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
967
968 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
969 return;
970
971 emp->activity++;
972 if (!timer_pending(&emp->timer))
973 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
974}
975
976static void ahci_sw_activity_blink(unsigned long arg)
977{
978 struct ata_link *link = (struct ata_link *)arg;
979 struct ata_port *ap = link->ap;
980 struct ahci_port_priv *pp = ap->private_data;
981 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
982 unsigned long led_message = emp->led_state;
983 u32 activity_led_state;
984 unsigned long flags;
985
986 led_message &= EM_MSG_LED_VALUE;
987 led_message |= ap->port_no | (link->pmp << 8);
988
989 /* check to see if we've had activity. If so,
990 * toggle state of LED and reset timer. If not,
991 * turn LED to desired idle state.
992 */
993 spin_lock_irqsave(ap->lock, flags);
994 if (emp->saved_activity != emp->activity) {
995 emp->saved_activity = emp->activity;
996 /* get the current LED state */
997 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
998
999 if (activity_led_state)
1000 activity_led_state = 0;
1001 else
1002 activity_led_state = 1;
1003
1004 /* clear old state */
1005 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1006
1007 /* toggle state */
1008 led_message |= (activity_led_state << 16);
1009 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1010 } else {
1011 /* switch to idle */
1012 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1013 if (emp->blink_policy == BLINK_OFF)
1014 led_message |= (1 << 16);
1015 }
1016 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 1017 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 1018}
1019
1020static void ahci_init_sw_activity(struct ata_link *link)
1021{
1022 struct ata_port *ap = link->ap;
1023 struct ahci_port_priv *pp = ap->private_data;
1024 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1025
1026 /* init activity stats, setup timer */
1027 emp->saved_activity = emp->activity = 0;
1028 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1029
1030 /* check our blink policy and set flag for link if it's enabled */
1031 if (emp->blink_policy)
1032 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1033}
1034
1035int ahci_reset_em(struct ata_host *host)
1036{
1037 struct ahci_host_priv *hpriv = host->private_data;
1038 void __iomem *mmio = hpriv->mmio;
1039 u32 em_ctl;
1040
1041 em_ctl = readl(mmio + HOST_EM_CTL);
1042 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1043 return -EINVAL;
1044
1045 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1046 return 0;
1047}
1048EXPORT_SYMBOL_GPL(ahci_reset_em);
1049
1050static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1051 ssize_t size)
1052{
1053 struct ahci_host_priv *hpriv = ap->host->private_data;
1054 struct ahci_port_priv *pp = ap->private_data;
1055 void __iomem *mmio = hpriv->mmio;
1056 u32 em_ctl;
1057 u32 message[] = {0, 0};
1058 unsigned long flags;
1059 int pmp;
1060 struct ahci_em_priv *emp;
1061
1062 /* get the slot number from the message */
1063 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1064 if (pmp < EM_MAX_SLOTS)
1065 emp = &pp->em_priv[pmp];
1066 else
1067 return -EINVAL;
1068
bb03c640 1069 ahci_rpm_get_port(ap);
365cfa1e
AV		 1070 spin_lock_irqsave(ap->lock, flags);
1071
1072 /*
1073 * if we are still busy transmitting a previous message,
1074 * do not allow
1075 */
1076 em_ctl = readl(mmio + HOST_EM_CTL);
1077 if (em_ctl & EM_CTL_TM) {
1078 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 1079 ahci_rpm_put_port(ap);
365cfa1e
AV		 1080 return -EBUSY;
1081 }
1082
008dbd61
HZ		 1083 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1084 /*
1085 * create message header - this is all zero except for
1086 * the message size, which is 4 bytes.
1087 */
1088 message[0] |= (4 << 8);
365cfa1e 1089
008dbd61
HZ		 1090 /* ignore 0:4 of byte zero, fill in port info yourself */
1091 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1092
008dbd61
HZ		 1093 /* write message to EM_LOC */
1094 writel(message[0], mmio + hpriv->em_loc);
1095 writel(message[1], mmio + hpriv->em_loc+4);
1096
1097 /*
1098 * tell hardware to transmit the message
1099 */
1100 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1101 }
365cfa1e
AV		 1102
1103 /* save off new led state for port/slot */
1104 emp->led_state = state;
1105
365cfa1e 1106 spin_unlock_irqrestore(ap->lock, flags);
bb03c640
MW		 1107 ahci_rpm_put_port(ap);
1108
365cfa1e
AV		 1109 return size;
1110}
1111
1112static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1113{
1114 struct ahci_port_priv *pp = ap->private_data;
1115 struct ata_link *link;
1116 struct ahci_em_priv *emp;
1117 int rc = 0;
1118
1119 ata_for_each_link(link, ap, EDGE) {
1120 emp = &pp->em_priv[link->pmp];
1121 rc += sprintf(buf, "%lx\n", emp->led_state);
1122 }
1123 return rc;
1124}
1125
1126static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1127 size_t size)
1128{
b2a52b6a 1129 unsigned int state;
365cfa1e
AV		 1130 int pmp;
1131 struct ahci_port_priv *pp = ap->private_data;
1132 struct ahci_em_priv *emp;
1133
b2a52b6a
DY		 1134 if (kstrtouint(buf, 0, &state) < 0)
1135 return -EINVAL;
365cfa1e
AV		 1136
1137 /* get the slot number from the message */
1138 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
7ccd2c1b
JG		 1139 if (pmp < EM_MAX_SLOTS) {
1140 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
365cfa1e 1141 emp = &pp->em_priv[pmp];
7ccd2c1b 1142 } else {
365cfa1e 1143 return -EINVAL;
7ccd2c1b 1144 }
365cfa1e
AV		 1145
1146 /* mask off the activity bits if we are in sw_activity
1147 * mode, user should turn off sw_activity before setting
1148 * activity led through em_message
1149 */
1150 if (emp->blink_policy)
1151 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1152
439d7a35 1153 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1154}
1155
1156static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1157{
1158 struct ata_link *link = dev->link;
1159 struct ata_port *ap = link->ap;
1160 struct ahci_port_priv *pp = ap->private_data;
1161 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1162 u32 port_led_state = emp->led_state;
1163
1164 /* save the desired Activity LED behavior */
1165 if (val == OFF) {
1166 /* clear LFLAG */
1167 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1168
1169 /* set the LED to OFF */
1170 port_led_state &= EM_MSG_LED_VALUE_OFF;
1171 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1172 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1173 } else {
1174 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1175 if (val == BLINK_OFF) {
1176 /* set LED to ON for idle */
1177 port_led_state &= EM_MSG_LED_VALUE_OFF;
1178 port_led_state |= (ap->port_no | (link->pmp << 8));
1179 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1180 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1181 }
1182 }
1183 emp->blink_policy = val;
1184 return 0;
1185}
1186
1187static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1188{
1189 struct ata_link *link = dev->link;
1190 struct ata_port *ap = link->ap;
1191 struct ahci_port_priv *pp = ap->private_data;
1192 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1193
1194 /* display the saved value of activity behavior for this
1195 * disk.
1196 */
1197 return sprintf(buf, "%d\n", emp->blink_policy);
1198}
1199
1200static void ahci_port_init(struct device *dev, struct ata_port *ap,
1201 int port_no, void __iomem *mmio,
1202 void __iomem *port_mmio)
1203{
8a3e33cf 1204 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1205 const char *emsg = NULL;
1206 int rc;
1207 u32 tmp;
1208
1209 /* make sure port is not active */
1210 rc = ahci_deinit_port(ap, &emsg);
1211 if (rc)
1212 dev_warn(dev, "%s (%d)\n", emsg, rc);
1213
1214 /* clear SError */
1215 tmp = readl(port_mmio + PORT_SCR_ERR);
1216 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1217 writel(tmp, port_mmio + PORT_SCR_ERR);
1218
1219 /* clear port IRQ */
1220 tmp = readl(port_mmio + PORT_IRQ_STAT);
1221 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1222 if (tmp)
1223 writel(tmp, port_mmio + PORT_IRQ_STAT);
1224
1225 writel(1 << port_no, mmio + HOST_IRQ_STAT);
8a3e33cf
ML		 1226
1227 /* mark esata ports */
1228 tmp = readl(port_mmio + PORT_CMD);
dc8b4afc 1229 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
8a3e33cf 1230 ap->pflags |= ATA_PFLAG_EXTERNAL;
365cfa1e
AV		 1231}
1232
1233void ahci_init_controller(struct ata_host *host)
1234{
1235 struct ahci_host_priv *hpriv = host->private_data;
1236 void __iomem *mmio = hpriv->mmio;
1237 int i;
1238 void __iomem *port_mmio;
1239 u32 tmp;
1240
1241 for (i = 0; i < host->n_ports; i++) {
1242 struct ata_port *ap = host->ports[i];
1243
1244 port_mmio = ahci_port_base(ap);
1245 if (ata_port_is_dummy(ap))
1246 continue;
1247
1248 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1249 }
1250
1251 tmp = readl(mmio + HOST_CTL);
1252 VPRINTK("HOST_CTL 0x%x\n", tmp);
1253 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1254 tmp = readl(mmio + HOST_CTL);
1255 VPRINTK("HOST_CTL 0x%x\n", tmp);
1256}
1257EXPORT_SYMBOL_GPL(ahci_init_controller);
1258
1259static void ahci_dev_config(struct ata_device *dev)
1260{
1261 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1262
1263 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1264 dev->max_sectors = 255;
a9a79dfe
JP		 1265 ata_dev_info(dev,
1266 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1267 }
1268}
1269
bbb4ab43 1270unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1271{
1272 void __iomem *port_mmio = ahci_port_base(ap);
1273 struct ata_taskfile tf;
1274 u32 tmp;
1275
1276 tmp = readl(port_mmio + PORT_SIG);
1277 tf.lbah = (tmp >> 24) & 0xff;
1278 tf.lbam = (tmp >> 16) & 0xff;
1279 tf.lbal = (tmp >> 8) & 0xff;
1280 tf.nsect = (tmp) & 0xff;
1281
1282 return ata_dev_classify(&tf);
1283}
bbb4ab43 1284EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1285
02cdfcf0
DM		 1286void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1287 u32 opts)
365cfa1e
AV		 1288{
1289 dma_addr_t cmd_tbl_dma;
1290
1291 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1292
1293 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1294 pp->cmd_slot[tag].status = 0;
1295 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1296 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1297}
02cdfcf0 1298EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1299
1300int ahci_kick_engine(struct ata_port *ap)
1301{
1302 void __iomem *port_mmio = ahci_port_base(ap);
1303 struct ahci_host_priv *hpriv = ap->host->private_data;
1304 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1305 u32 tmp;
1306 int busy, rc;
1307
1308 /* stop engine */
48c0bf9a 1309 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 1310 if (rc)
1311 goto out_restart;
1312
1313 /* need to do CLO?
1314 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1315 */
1316 busy = status & (ATA_BUSY | ATA_DRQ);
1317 if (!busy && !sata_pmp_attached(ap)) {
1318 rc = 0;
1319 goto out_restart;
1320 }
1321
1322 if (!(hpriv->cap & HOST_CAP_CLO)) {
1323 rc = -EOPNOTSUPP;
1324 goto out_restart;
1325 }
1326
1327 /* perform CLO */
1328 tmp = readl(port_mmio + PORT_CMD);
1329 tmp |= PORT_CMD_CLO;
1330 writel(tmp, port_mmio + PORT_CMD);
1331
1332 rc = 0;
97750ceb 1333 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1334 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1335 if (tmp & PORT_CMD_CLO)
1336 rc = -EIO;
1337
1338 /* restart engine */
1339 out_restart:
039ece38 1340 hpriv->start_engine(ap);
365cfa1e
AV		 1341 return rc;
1342}
1343EXPORT_SYMBOL_GPL(ahci_kick_engine);
1344
1345static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1346 struct ata_taskfile *tf, int is_cmd, u16 flags,
1347 unsigned long timeout_msec)
1348{
1349 const u32 cmd_fis_len = 5; /* five dwords */
1350 struct ahci_port_priv *pp = ap->private_data;
1351 void __iomem *port_mmio = ahci_port_base(ap);
1352 u8 *fis = pp->cmd_tbl;
1353 u32 tmp;
1354
1355 /* prep the command */
1356 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1357 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1358
023113d2
XY		 1359 /* set port value for softreset of Port Multiplier */
1360 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1361 tmp = readl(port_mmio + PORT_FBS);
1362 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1363 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1364 writel(tmp, port_mmio + PORT_FBS);
1365 pp->fbs_last_dev = pmp;
1366 }
1367
365cfa1e
AV		 1368 /* issue & wait */
1369 writel(1, port_mmio + PORT_CMD_ISSUE);
1370
1371 if (timeout_msec) {
97750ceb
TH		 1372 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1373 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1374 if (tmp & 0x1) {
1375 ahci_kick_engine(ap);
1376 return -EBUSY;
1377 }
1378 } else
1379 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1380
1381 return 0;
1382}
1383
1384int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1385 int pmp, unsigned long deadline,
1386 int (*check_ready)(struct ata_link *link))
1387{
1388 struct ata_port *ap = link->ap;
1389 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1390 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1391 const char *reason = NULL;
1392 unsigned long now, msecs;
1393 struct ata_taskfile tf;
89dafa20 1394 bool fbs_disabled = false;
365cfa1e
AV		 1395 int rc;
1396
1397 DPRINTK("ENTER\n");
1398
1399 /* prepare for SRST (AHCI-1.1 10.4.1) */
1400 rc = ahci_kick_engine(ap);
1401 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1402 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1403
89dafa20 1404 /*
1405 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1406 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1407 * that is attached to port multiplier.
1408 */
1409 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1410 ahci_disable_fbs(ap);
1411 fbs_disabled = true;
1412 }
1413
365cfa1e
AV		 1414 ata_tf_init(link->device, &tf);
1415
08fc4756 1416 /* issue the first H2D Register FIS */
365cfa1e
AV		 1417 msecs = 0;
1418 now = jiffies;
f1f5a807 1419 if (time_after(deadline, now))
365cfa1e
AV		 1420 msecs = jiffies_to_msecs(deadline - now);
1421
1422 tf.ctl |= ATA_SRST;
1423 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1424 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1425 rc = -EIO;
1426 reason = "1st FIS failed";
1427 goto fail;
1428 }
1429
1430 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1431 ata_msleep(ap, 1);
365cfa1e 1432
08fc4756 1433 /* issue the second H2D Register FIS */
365cfa1e
AV		 1434 tf.ctl &= ~ATA_SRST;
1435 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1436
1437 /* wait for link to become ready */
1438 rc = ata_wait_after_reset(link, deadline, check_ready);
1439 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1440 /*
1441 * Workaround for cases where link online status can't
1442 * be trusted. Treat device readiness timeout as link
1443 * offline.
1444 */
a9a79dfe 1445 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1446 *class = ATA_DEV_NONE;
1447 } else if (rc) {
1448 /* link occupied, -ENODEV too is an error */
1449 reason = "device not ready";
1450 goto fail;
1451 } else
1452 *class = ahci_dev_classify(ap);
1453
89dafa20 1454 /* re-enable FBS if disabled before */
1455 if (fbs_disabled)
1456 ahci_enable_fbs(ap);
1457
365cfa1e
AV		 1458 DPRINTK("EXIT, class=%u\n", *class);
1459 return 0;
1460
1461 fail:
a9a79dfe 1462 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1463 return rc;
1464}
1465
1466int ahci_check_ready(struct ata_link *link)
1467{
1468 void __iomem *port_mmio = ahci_port_base(link->ap);
1469 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1470
1471 return ata_check_ready(status);
1472}
1473EXPORT_SYMBOL_GPL(ahci_check_ready);
1474
1475static int ahci_softreset(struct ata_link *link, unsigned int *class,
1476 unsigned long deadline)
1477{
1478 int pmp = sata_srst_pmp(link);
1479
1480 DPRINTK("ENTER\n");
1481
1482 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1483}
1484EXPORT_SYMBOL_GPL(ahci_do_softreset);
1485
345347c5
YHC		 1486static int ahci_bad_pmp_check_ready(struct ata_link *link)
1487{
1488 void __iomem *port_mmio = ahci_port_base(link->ap);
1489 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1490 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1491
1492 /*
1493 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1494 * which can save timeout delay.
1495 */
1496 if (irq_status & PORT_IRQ_BAD_PMP)
1497 return -EIO;
1498
1499 return ata_check_ready(status);
1500}
1501
35186d05
DY		 1502static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1503 unsigned long deadline)
345347c5
YHC		 1504{
1505 struct ata_port *ap = link->ap;
1506 void __iomem *port_mmio = ahci_port_base(ap);
1507 int pmp = sata_srst_pmp(link);
1508 int rc;
1509 u32 irq_sts;
1510
1511 DPRINTK("ENTER\n");
1512
1513 rc = ahci_do_softreset(link, class, pmp, deadline,
1514 ahci_bad_pmp_check_ready);
1515
1516 /*
1517 * Soft reset fails with IPMS set when PMP is enabled but
1518 * SATA HDD/ODD is connected to SATA port, do soft reset
1519 * again to port 0.
1520 */
1521 if (rc == -EIO) {
1522 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1523 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1524 ata_link_warn(link,
345347c5
YHC		 1525 "applying PMP SRST workaround "
1526 "and retrying\n");
1527 rc = ahci_do_softreset(link, class, 0, deadline,
1528 ahci_check_ready);
1529 }
1530 }
1531
1532 return rc;
1533}
1534
d436501e
BG		 1535int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1536 unsigned long deadline, bool *online)
365cfa1e
AV		 1537{
1538 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1539 struct ata_port *ap = link->ap;
1540 struct ahci_port_priv *pp = ap->private_data;
039ece38 1541 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1542 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1543 struct ata_taskfile tf;
365cfa1e
AV		 1544 int rc;
1545
1546 DPRINTK("ENTER\n");
1547
48c0bf9a 1548 hpriv->stop_engine(ap);
365cfa1e
AV		 1549
1550 /* clear D2H reception area to properly wait for D2H FIS */
1551 ata_tf_init(link->device, &tf);
9bbb1b0e 1552 tf.command = ATA_BUSY;
365cfa1e
AV		 1553 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1554
d436501e 1555 rc = sata_link_hardreset(link, timing, deadline, online,
365cfa1e
AV		 1556 ahci_check_ready);
1557
039ece38 1558 hpriv->start_engine(ap);
365cfa1e 1559
d436501e 1560 if (*online)
365cfa1e
AV		 1561 *class = ahci_dev_classify(ap);
1562
1563 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1564 return rc;
1565}
d436501e
BG		 1566EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1567
1568static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1569 unsigned long deadline)
1570{
1571 bool online;
1572
1573 return ahci_do_hardreset(link, class, deadline, &online);
1574}
365cfa1e
AV		 1575
1576static void ahci_postreset(struct ata_link *link, unsigned int *class)
1577{
1578 struct ata_port *ap = link->ap;
1579 void __iomem *port_mmio = ahci_port_base(ap);
1580 u32 new_tmp, tmp;
1581
1582 ata_std_postreset(link, class);
1583
1584 /* Make sure port's ATAPI bit is set appropriately */
1585 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1586 if (*class == ATA_DEV_ATAPI)
1587 new_tmp |= PORT_CMD_ATAPI;
1588 else
1589 new_tmp &= ~PORT_CMD_ATAPI;
1590 if (new_tmp != tmp) {
1591 writel(new_tmp, port_mmio + PORT_CMD);
1592 readl(port_mmio + PORT_CMD); /* flush */
1593 }
1594}
1595
1596static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1597{
1598 struct scatterlist *sg;
1599 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1600 unsigned int si;
1601
1602 VPRINTK("ENTER\n");
1603
1604 /*
1605 * Next, the S/G list.
1606 */
1607 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1608 dma_addr_t addr = sg_dma_address(sg);
1609 u32 sg_len = sg_dma_len(sg);
1610
1611 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1612 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1613 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1614 }
1615
1616 return si;
1617}
1618
1619static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1620{
1621 struct ata_port *ap = qc->ap;
1622 struct ahci_port_priv *pp = ap->private_data;
1623
1624 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1625 return ata_std_qc_defer(qc);
1626 else
1627 return sata_pmp_qc_defer_cmd_switch(qc);
1628}
1629
1630static void ahci_qc_prep(struct ata_queued_cmd *qc)
1631{
1632 struct ata_port *ap = qc->ap;
1633 struct ahci_port_priv *pp = ap->private_data;
1634 int is_atapi = ata_is_atapi(qc->tf.protocol);
1635 void *cmd_tbl;
1636 u32 opts;
1637 const u32 cmd_fis_len = 5; /* five dwords */
1638 unsigned int n_elem;
1639
1640 /*
1641 * Fill in command table information. First, the header,
1642 * a SATA Register - Host to Device command FIS.
1643 */
1644 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1645
1646 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1647 if (is_atapi) {
1648 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1649 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1650 }
1651
1652 n_elem = 0;
1653 if (qc->flags & ATA_QCFLAG_DMAMAP)
1654 n_elem = ahci_fill_sg(qc, cmd_tbl);
1655
1656 /*
1657 * Fill in command slot information.
1658 */
1659 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1660 if (qc->tf.flags & ATA_TFLAG_WRITE)
1661 opts |= AHCI_CMD_WRITE;
1662 if (is_atapi)
1663 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1664
1665 ahci_fill_cmd_slot(pp, qc->tag, opts);
1666}
1667
1668static void ahci_fbs_dec_intr(struct ata_port *ap)
1669{
1670 struct ahci_port_priv *pp = ap->private_data;
1671 void __iomem *port_mmio = ahci_port_base(ap);
1672 u32 fbs = readl(port_mmio + PORT_FBS);
1673 int retries = 3;
1674
1675 DPRINTK("ENTER\n");
1676 BUG_ON(!pp->fbs_enabled);
1677
1678 /* time to wait for DEC is not specified by AHCI spec,
1679 * add a retry loop for safety.
1680 */
1681 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1682 fbs = readl(port_mmio + PORT_FBS);
1683 while ((fbs & PORT_FBS_DEC) && retries--) {
1684 udelay(1);
1685 fbs = readl(port_mmio + PORT_FBS);
1686 }
1687
1688 if (fbs & PORT_FBS_DEC)
a44fec1f 1689 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1690}
1691
1692static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1693{
1694 struct ahci_host_priv *hpriv = ap->host->private_data;
1695 struct ahci_port_priv *pp = ap->private_data;
1696 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1697 struct ata_link *link = NULL;
1698 struct ata_queued_cmd *active_qc;
1699 struct ata_eh_info *active_ehi;
1700 bool fbs_need_dec = false;
1701 u32 serror;
1702
1703 /* determine active link with error */
1704 if (pp->fbs_enabled) {
1705 void __iomem *port_mmio = ahci_port_base(ap);
1706 u32 fbs = readl(port_mmio + PORT_FBS);
1707 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1708
912b9ac6 1709 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1710 link = &ap->pmp_link[pmp];
1711 fbs_need_dec = true;
1712 }
1713
1714 } else
1715 ata_for_each_link(link, ap, EDGE)
1716 if (ata_link_active(link))
1717 break;
1718
1719 if (!link)
1720 link = &ap->link;
1721
1722 active_qc = ata_qc_from_tag(ap, link->active_tag);
1723 active_ehi = &link->eh_info;
1724
1725 /* record irq stat */
1726 ata_ehi_clear_desc(host_ehi);
1727 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1728
1729 /* AHCI needs SError cleared; otherwise, it might lock up */
1730 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1731 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1732 host_ehi->serror |= serror;
1733
1734 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1735 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1736 irq_stat &= ~PORT_IRQ_IF_ERR;
1737
1738 if (irq_stat & PORT_IRQ_TF_ERR) {
1739 /* If qc is active, charge it; otherwise, the active
1740 * link. There's no active qc on NCQ errors. It will
1741 * be determined by EH by reading log page 10h.
1742 */
1743 if (active_qc)
1744 active_qc->err_mask |= AC_ERR_DEV;
1745 else
1746 active_ehi->err_mask |= AC_ERR_DEV;
1747
1748 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1749 host_ehi->serror &= ~SERR_INTERNAL;
1750 }
1751
1752 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1753 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1754
1755 active_ehi->err_mask |= AC_ERR_HSM;
1756 active_ehi->action |= ATA_EH_RESET;
1757 ata_ehi_push_desc(active_ehi,
1758 "unknown FIS %08x %08x %08x %08x" ,
1759 unk[0], unk[1], unk[2], unk[3]);
1760 }
1761
1762 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1763 active_ehi->err_mask |= AC_ERR_HSM;
1764 active_ehi->action |= ATA_EH_RESET;
1765 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1766 }
1767
1768 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1769 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1770 host_ehi->action |= ATA_EH_RESET;
1771 ata_ehi_push_desc(host_ehi, "host bus error");
1772 }
1773
1774 if (irq_stat & PORT_IRQ_IF_ERR) {
1775 if (fbs_need_dec)
1776 active_ehi->err_mask |= AC_ERR_DEV;
1777 else {
1778 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1779 host_ehi->action |= ATA_EH_RESET;
1780 }
1781
1782 ata_ehi_push_desc(host_ehi, "interface fatal error");
1783 }
1784
1785 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1786 ata_ehi_hotplugged(host_ehi);
1787 ata_ehi_push_desc(host_ehi, "%s",
1788 irq_stat & PORT_IRQ_CONNECT ?
1789 "connection status changed" : "PHY RDY changed");
1790 }
1791
1792 /* okay, let's hand over to EH */
1793
1794 if (irq_stat & PORT_IRQ_FREEZE)
1795 ata_port_freeze(ap);
1796 else if (fbs_need_dec) {
1797 ata_link_abort(link);
1798 ahci_fbs_dec_intr(ap);
1799 } else
1800 ata_port_abort(ap);
1801}
1802
5ca72c4f
AG		 1803static void ahci_handle_port_interrupt(struct ata_port *ap,
1804 void __iomem *port_mmio, u32 status)
365cfa1e 1805{
365cfa1e
AV		 1806 struct ata_eh_info *ehi = &ap->link.eh_info;
1807 struct ahci_port_priv *pp = ap->private_data;
1808 struct ahci_host_priv *hpriv = ap->host->private_data;
1809 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1810 u32 qc_active = 0;
365cfa1e
AV		 1811 int rc;
1812
365cfa1e
AV		 1813 /* ignore BAD_PMP while resetting */
1814 if (unlikely(resetting))
1815 status &= ~PORT_IRQ_BAD_PMP;
1816
8393b811 1817 if (sata_lpm_ignore_phy_events(&ap->link)) {
365cfa1e 1818 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1819 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1820 }
1821
1822 if (unlikely(status & PORT_IRQ_ERROR)) {
1823 ahci_error_intr(ap, status);
1824 return;
1825 }
1826
1827 if (status & PORT_IRQ_SDB_FIS) {
1828 /* If SNotification is available, leave notification
1829 * handling to sata_async_notification(). If not,
1830 * emulate it by snooping SDB FIS RX area.
1831 *
1832 * Snooping FIS RX area is probably cheaper than
1833 * poking SNotification but some constrollers which
1834 * implement SNotification, ICH9 for example, don't
1835 * store AN SDB FIS into receive area.
1836 */
1837 if (hpriv->cap & HOST_CAP_SNTF)
1838 sata_async_notification(ap);
1839 else {
1840 /* If the 'N' bit in word 0 of the FIS is set,
1841 * we just received asynchronous notification.
1842 * Tell libata about it.
1843 *
1844 * Lack of SNotification should not appear in
1845 * ahci 1.2, so the workaround is unnecessary
1846 * when FBS is enabled.
1847 */
1848 if (pp->fbs_enabled)
1849 WARN_ON_ONCE(1);
1850 else {
1851 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1852 u32 f0 = le32_to_cpu(f[0]);
1853 if (f0 & (1 << 15))
1854 sata_async_notification(ap);
1855 }
1856 }
1857 }
1858
1859 /* pp->active_link is not reliable once FBS is enabled, both
1860 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1861 * NCQ and non-NCQ commands may be in flight at the same time.
1862 */
1863 if (pp->fbs_enabled) {
1864 if (ap->qc_active) {
1865 qc_active = readl(port_mmio + PORT_SCR_ACT);
1866 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1867 }
1868 } else {
1869 /* pp->active_link is valid iff any command is in flight */
1870 if (ap->qc_active && pp->active_link->sactive)
1871 qc_active = readl(port_mmio + PORT_SCR_ACT);
1872 else
1873 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1874 }
1875
1876
1877 rc = ata_qc_complete_multiple(ap, qc_active);
1878
1879 /* while resetting, invalid completions are expected */
1880 if (unlikely(rc < 0 && !resetting)) {
1881 ehi->err_mask |= AC_ERR_HSM;
1882 ehi->action |= ATA_EH_RESET;
1883 ata_port_freeze(ap);
1884 }
1885}
1886
7865f83f 1887static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1888{
1889 void __iomem *port_mmio = ahci_port_base(ap);
1890 u32 status;
1891
1892 status = readl(port_mmio + PORT_IRQ_STAT);
1893 writel(status, port_mmio + PORT_IRQ_STAT);
1894
7865f83f 1895 ahci_handle_port_interrupt(ap, port_mmio, status);
5ca72c4f
AG		 1896}
1897
a6b7fb76 1898static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
5ca72c4f
AG		 1899{
1900 struct ata_port *ap = dev_instance;
5ca72c4f 1901 void __iomem *port_mmio = ahci_port_base(ap);
5ca72c4f
AG		 1902 u32 status;
1903
5ca72c4f
AG		 1904 VPRINTK("ENTER\n");
1905
227dfb4d
AG		 1906 status = readl(port_mmio + PORT_IRQ_STAT);
1907 writel(status, port_mmio + PORT_IRQ_STAT);
5ca72c4f 1908
a6b7fb76
DW		 1909 spin_lock(ap->lock);
1910 ahci_handle_port_interrupt(ap, port_mmio, status);
1911 spin_unlock(ap->lock);
5ca72c4f
AG		 1912
1913 VPRINTK("EXIT\n");
1914
a6b7fb76 1915 return IRQ_HANDLED;
5ca72c4f 1916}
5ca72c4f 1917
f070d671 1918u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
365cfa1e 1919{
365cfa1e 1920 unsigned int i, handled = 0;
03e83cbd 1921
365cfa1e
AV		 1922 for (i = 0; i < host->n_ports; i++) {
1923 struct ata_port *ap;
1924
1925 if (!(irq_masked & (1 << i)))
1926 continue;
1927
1928 ap = host->ports[i];
1929 if (ap) {
7865f83f 1930 ahci_port_intr(ap);
365cfa1e
AV		 1931 VPRINTK("port %u\n", i);
1932 } else {
1933 VPRINTK("port %u (no irq)\n", i);
1934 if (ata_ratelimit())
a44fec1f
JP		 1935 dev_warn(host->dev,
1936 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1937 }
1938
1939 handled = 1;
1940 }
1941
a129db89
ST		 1942 return handled;
1943}
f070d671 1944EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
a129db89
ST		 1945
1946static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1947{
1948 struct ata_host *host = dev_instance;
1949 struct ahci_host_priv *hpriv;
1950 unsigned int rc = 0;
1951 void __iomem *mmio;
1952 u32 irq_stat, irq_masked;
1953
1954 VPRINTK("ENTER\n");
1955
1956 hpriv = host->private_data;
1957 mmio = hpriv->mmio;
1958
1959 /* sigh. 0xffffffff is a valid return from h/w */
1960 irq_stat = readl(mmio + HOST_IRQ_STAT);
1961 if (!irq_stat)
1962 return IRQ_NONE;
1963
1964 irq_masked = irq_stat & hpriv->port_map;
1965
1966 spin_lock(&host->lock);
1967
1968 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e
AV		 1969
1970 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1971 * it should be cleared after all the port events are cleared;
1972 * otherwise, it will raise a spurious interrupt after each
1973 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1974 * information.
1975 *
1976 * Also, use the unmasked value to clear interrupt as spurious
1977 * pending event on a dummy port might cause screaming IRQ.
1978 */
1979 writel(irq_stat, mmio + HOST_IRQ_STAT);
1980
03e83cbd
TH		 1981 spin_unlock(&host->lock);
1982
365cfa1e
AV		 1983 VPRINTK("EXIT\n");
1984
a129db89 1985 return IRQ_RETVAL(rc);
365cfa1e 1986}
365cfa1e 1987
39e0ee99 1988unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1989{
1990 struct ata_port *ap = qc->ap;
1991 void __iomem *port_mmio = ahci_port_base(ap);
1992 struct ahci_port_priv *pp = ap->private_data;
1993
1994 /* Keep track of the currently active link. It will be used
1995 * in completion path to determine whether NCQ phase is in
1996 * progress.
1997 */
1998 pp->active_link = qc->dev->link;
1999
179b310a 2000 if (ata_is_ncq(qc->tf.protocol))
365cfa1e
AV		 2001 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2002
2003 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2004 u32 fbs = readl(port_mmio + PORT_FBS);
2005 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2006 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2007 writel(fbs, port_mmio + PORT_FBS);
2008 pp->fbs_last_dev = qc->dev->link->pmp;
2009 }
2010
2011 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2012
2013 ahci_sw_activity(qc->dev->link);
2014
2015 return 0;
2016}
39e0ee99 2017EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 2018
2019static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2020{
2021 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 2022 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 2023
2024 if (pp->fbs_enabled)
6ad60195
TH		 2025 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2026
2027 /*
2028 * After a successful execution of an ATA PIO data-in command,
2029 * the device doesn't send D2H Reg FIS to update the TF and
2030 * the host should take TF and E_Status from the preceding PIO
2031 * Setup FIS.
2032 */
2033 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2034 !(qc->flags & ATA_QCFLAG_FAILED)) {
2035 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2036 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2037 } else
2038 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 2039
365cfa1e
AV		 2040 return true;
2041}
2042
2043static void ahci_freeze(struct ata_port *ap)
2044{
2045 void __iomem *port_mmio = ahci_port_base(ap);
2046
2047 /* turn IRQ off */
2048 writel(0, port_mmio + PORT_IRQ_MASK);
2049}
2050
2051static void ahci_thaw(struct ata_port *ap)
2052{
2053 struct ahci_host_priv *hpriv = ap->host->private_data;
2054 void __iomem *mmio = hpriv->mmio;
2055 void __iomem *port_mmio = ahci_port_base(ap);
2056 u32 tmp;
2057 struct ahci_port_priv *pp = ap->private_data;
2058
2059 /* clear IRQ */
2060 tmp = readl(port_mmio + PORT_IRQ_STAT);
2061 writel(tmp, port_mmio + PORT_IRQ_STAT);
2062 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2063
2064 /* turn IRQ back on */
2065 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2066}
2067
8b789d89 2068void ahci_error_handler(struct ata_port *ap)
365cfa1e 2069{
039ece38
HG		 2070 struct ahci_host_priv *hpriv = ap->host->private_data;
2071
365cfa1e
AV		 2072 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2073 /* restart engine */
48c0bf9a 2074 hpriv->stop_engine(ap);
039ece38 2075 hpriv->start_engine(ap);
365cfa1e
AV		 2076 }
2077
2078 sata_pmp_error_handler(ap);
0ee71952
TH		 2079
2080 if (!ata_dev_enabled(ap->link.device))
48c0bf9a 2081 hpriv->stop_engine(ap);
365cfa1e 2082}
8b789d89 2083EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2084
2085static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2086{
2087 struct ata_port *ap = qc->ap;
2088
2089 /* make DMA engine forget about the failed command */
2090 if (qc->flags & ATA_QCFLAG_FAILED)
2091 ahci_kick_engine(ap);
2092}
2093
65fe1f0f
SH		 2094static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2095{
039ece38 2096 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2097 void __iomem *port_mmio = ahci_port_base(ap);
2098 struct ata_device *dev = ap->link.device;
7cadaaa9 2099 u32 devslp, dm, dito, mdat, deto, dito_conf;
65fe1f0f
SH		 2100 int rc;
2101 unsigned int err_mask;
2102
2103 devslp = readl(port_mmio + PORT_DEVSLP);
2104 if (!(devslp & PORT_DEVSLP_DSP)) {
95bbbe9a 2105 dev_info(ap->host->dev, "port does not support device sleep\n");
65fe1f0f
SH		 2106 return;
2107 }
2108
2109 /* disable device sleep */
2110 if (!sleep) {
2111 if (devslp & PORT_DEVSLP_ADSE) {
2112 writel(devslp & ~PORT_DEVSLP_ADSE,
2113 port_mmio + PORT_DEVSLP);
2114 err_mask = ata_dev_set_feature(dev,
2115 SETFEATURES_SATA_DISABLE,
2116 SATA_DEVSLP);
2117 if (err_mask && err_mask != AC_ERR_DEV)
2118 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2119 }
2120 return;
2121 }
2122
7cadaaa9
SP		 2123 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2124 dito = devslp_idle_timeout / (dm + 1);
2125 if (dito > 0x3ff)
2126 dito = 0x3ff;
2127
2128 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2129
2130 /* device sleep was already enabled and same dito */
2131 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
65fe1f0f
SH		 2132 return;
2133
2134 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
48c0bf9a 2135 rc = hpriv->stop_engine(ap);
65fe1f0f
SH		 2136 if (rc)
2137 return;
2138
65fe1f0f
SH		 2139 /* Use the nominal value 10 ms if the read MDAT is zero,
2140 * the nominal value of DETO is 20 ms.
2141 */
803739d2 2142 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2143 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2144 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2145 ATA_LOG_DEVSLP_MDAT_MASK;
2146 if (!mdat)
2147 mdat = 10;
803739d2 2148 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2149 if (!deto)
2150 deto = 20;
2151 } else {
2152 mdat = 10;
2153 deto = 20;
2154 }
2155
62128a8d
SP		 2156 /* Make dito, mdat, deto bits to 0s */
2157 devslp &= ~GENMASK_ULL(24, 2);
65fe1f0f
SH		 2158 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2159 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2160 (deto << PORT_DEVSLP_DETO_OFFSET) |
2161 PORT_DEVSLP_ADSE);
2162 writel(devslp, port_mmio + PORT_DEVSLP);
2163
039ece38 2164 hpriv->start_engine(ap);
65fe1f0f
SH		 2165
2166 /* enable device sleep feature for the drive */
2167 err_mask = ata_dev_set_feature(dev,
2168 SETFEATURES_SATA_ENABLE,
2169 SATA_DEVSLP);
2170 if (err_mask && err_mask != AC_ERR_DEV)
2171 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2172}
2173
365cfa1e
AV		 2174static void ahci_enable_fbs(struct ata_port *ap)
2175{
039ece38 2176 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2177 struct ahci_port_priv *pp = ap->private_data;
2178 void __iomem *port_mmio = ahci_port_base(ap);
2179 u32 fbs;
2180 int rc;
2181
2182 if (!pp->fbs_supported)
2183 return;
2184
2185 fbs = readl(port_mmio + PORT_FBS);
2186 if (fbs & PORT_FBS_EN) {
2187 pp->fbs_enabled = true;
2188 pp->fbs_last_dev = -1; /* initialization */
2189 return;
2190 }
2191
48c0bf9a 2192 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 2193 if (rc)
2194 return;
2195
2196 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2197 fbs = readl(port_mmio + PORT_FBS);
2198 if (fbs & PORT_FBS_EN) {
a44fec1f 2199 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2200 pp->fbs_enabled = true;
2201 pp->fbs_last_dev = -1; /* initialization */
2202 } else
a44fec1f 2203 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2204
039ece38 2205 hpriv->start_engine(ap);
365cfa1e
AV		 2206}
2207
2208static void ahci_disable_fbs(struct ata_port *ap)
2209{
039ece38 2210 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2211 struct ahci_port_priv *pp = ap->private_data;
2212 void __iomem *port_mmio = ahci_port_base(ap);
2213 u32 fbs;
2214 int rc;
2215
2216 if (!pp->fbs_supported)
2217 return;
2218
2219 fbs = readl(port_mmio + PORT_FBS);
2220 if ((fbs & PORT_FBS_EN) == 0) {
2221 pp->fbs_enabled = false;
2222 return;
2223 }
2224
48c0bf9a 2225 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 2226 if (rc)
2227 return;
2228
2229 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2230 fbs = readl(port_mmio + PORT_FBS);
2231 if (fbs & PORT_FBS_EN)
a44fec1f 2232 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2233 else {
a44fec1f 2234 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2235 pp->fbs_enabled = false;
2236 }
2237
039ece38 2238 hpriv->start_engine(ap);
365cfa1e
AV		 2239}
2240
2241static void ahci_pmp_attach(struct ata_port *ap)
2242{
2243 void __iomem *port_mmio = ahci_port_base(ap);
2244 struct ahci_port_priv *pp = ap->private_data;
2245 u32 cmd;
2246
2247 cmd = readl(port_mmio + PORT_CMD);
2248 cmd |= PORT_CMD_PMP;
2249 writel(cmd, port_mmio + PORT_CMD);
2250
2251 ahci_enable_fbs(ap);
2252
2253 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2254
2255 /*
2256 * We must not change the port interrupt mask register if the
2257 * port is marked frozen, the value in pp->intr_mask will be
2258 * restored later when the port is thawed.
2259 *
2260 * Note that during initialization, the port is marked as
2261 * frozen since the irq handler is not yet registered.
2262 */
2263 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2264 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2265}
2266
2267static void ahci_pmp_detach(struct ata_port *ap)
2268{
2269 void __iomem *port_mmio = ahci_port_base(ap);
2270 struct ahci_port_priv *pp = ap->private_data;
2271 u32 cmd;
2272
2273 ahci_disable_fbs(ap);
2274
2275 cmd = readl(port_mmio + PORT_CMD);
2276 cmd &= ~PORT_CMD_PMP;
2277 writel(cmd, port_mmio + PORT_CMD);
2278
2279 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2280
2281 /* see comment above in ahci_pmp_attach() */
2282 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2283 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2284}
2285
02cdfcf0 2286int ahci_port_resume(struct ata_port *ap)
365cfa1e 2287{
bb03c640
MW		 2288 ahci_rpm_get_port(ap);
2289
365cfa1e
AV		 2290 ahci_power_up(ap);
2291 ahci_start_port(ap);
2292
2293 if (sata_pmp_attached(ap))
2294 ahci_pmp_attach(ap);
2295 else
2296 ahci_pmp_detach(ap);
2297
2298 return 0;
2299}
02cdfcf0 2300EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2301
2302#ifdef CONFIG_PM
2303static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2304{
2305 const char *emsg = NULL;
2306 int rc;
2307
2308 rc = ahci_deinit_port(ap, &emsg);
2309 if (rc == 0)
2310 ahci_power_down(ap);
2311 else {
a9a79dfe 2312 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2313 ata_port_freeze(ap);
365cfa1e
AV		 2314 }
2315
bb03c640 2316 ahci_rpm_put_port(ap);
365cfa1e
AV		 2317 return rc;
2318}
2319#endif
2320
2321static int ahci_port_start(struct ata_port *ap)
2322{
2323 struct ahci_host_priv *hpriv = ap->host->private_data;
2324 struct device *dev = ap->host->dev;
2325 struct ahci_port_priv *pp;
2326 void *mem;
2327 dma_addr_t mem_dma;
2328 size_t dma_sz, rx_fis_sz;
2329
2330 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2331 if (!pp)
2332 return -ENOMEM;
2333
b29900e6
AG		 2334 if (ap->host->n_ports > 1) {
2335 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2336 if (!pp->irq_desc) {
2337 devm_kfree(dev, pp);
2338 return -ENOMEM;
2339 }
2340 snprintf(pp->irq_desc, 8,
2341 "%s%d", dev_driver_string(dev), ap->port_no);
2342 }
2343
365cfa1e
AV		 2344 /* check FBS capability */
2345 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2346 void __iomem *port_mmio = ahci_port_base(ap);
2347 u32 cmd = readl(port_mmio + PORT_CMD);
2348 if (cmd & PORT_CMD_FBSCP)
2349 pp->fbs_supported = true;
5f173107 2350 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2351 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2352 ap->port_no);
5f173107
TH		 2353 pp->fbs_supported = true;
2354 } else
a44fec1f
JP		 2355 dev_warn(dev, "port %d is not capable of FBS\n",
2356 ap->port_no);
365cfa1e
AV		 2357 }
2358
2359 if (pp->fbs_supported) {
2360 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2361 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2362 } else {
2363 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2364 rx_fis_sz = AHCI_RX_FIS_SZ;
2365 }
2366
2367 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2368 if (!mem)
2369 return -ENOMEM;
2370 memset(mem, 0, dma_sz);
2371
2372 /*
2373 * First item in chunk of DMA memory: 32-slot command table,
2374 * 32 bytes each in size
2375 */
2376 pp->cmd_slot = mem;
2377 pp->cmd_slot_dma = mem_dma;
2378
2379 mem += AHCI_CMD_SLOT_SZ;
2380 mem_dma += AHCI_CMD_SLOT_SZ;
2381
2382 /*
2383 * Second item: Received-FIS area
2384 */
2385 pp->rx_fis = mem;
2386 pp->rx_fis_dma = mem_dma;
2387
2388 mem += rx_fis_sz;
2389 mem_dma += rx_fis_sz;
2390
2391 /*
2392 * Third item: data area for storing a single command
2393 * and its scatter-gather table
2394 */
2395 pp->cmd_tbl = mem;
2396 pp->cmd_tbl_dma = mem_dma;
2397
2398 /*
2399 * Save off initial list of interrupts to be enabled.
2400 * This could be changed later
2401 */
2402 pp->intr_mask = DEF_PORT_IRQ;
2403
7865f83f
TH		 2404 /*
2405 * Switch to per-port locking in case each port has its own MSI vector.
2406 */
0b9e2988 2407 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
7865f83f
TH		 2408 spin_lock_init(&pp->lock);
2409 ap->lock = &pp->lock;
2410 }
5ca72c4f 2411
365cfa1e
AV		 2412 ap->private_data = pp;
2413
2414 /* engage engines, captain */
2415 return ahci_port_resume(ap);
2416}
2417
2418static void ahci_port_stop(struct ata_port *ap)
2419{
2420 const char *emsg = NULL;
0516900a
PR		 2421 struct ahci_host_priv *hpriv = ap->host->private_data;
2422 void __iomem *host_mmio = hpriv->mmio;
365cfa1e
AV		 2423 int rc;
2424
2425 /* de-initialize port */
2426 rc = ahci_deinit_port(ap, &emsg);
2427 if (rc)
a9a79dfe 2428 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
0516900a
PR		 2429
2430 /*
2431 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2432 * re-enabling INTx.
2433 */
2434 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
365cfa1e
AV		 2435}
2436
2437void ahci_print_info(struct ata_host *host, const char *scc_s)
2438{
2439 struct ahci_host_priv *hpriv = host->private_data;
365cfa1e
AV		 2440 u32 vers, cap, cap2, impl, speed;
2441 const char *speed_s;
2442
8ea909cb 2443 vers = hpriv->version;
365cfa1e
AV		 2444 cap = hpriv->cap;
2445 cap2 = hpriv->cap2;
2446 impl = hpriv->port_map;
2447
2448 speed = (cap >> 20) & 0xf;
2449 if (speed == 1)
2450 speed_s = "1.5";
2451 else if (speed == 2)
2452 speed_s = "3";
2453 else if (speed == 3)
2454 speed_s = "6";
2455 else
2456 speed_s = "?";
2457
2458 dev_info(host->dev,
2459 "AHCI %02x%02x.%02x%02x "
2460 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2461 ,
2462
2463 (vers >> 24) & 0xff,
2464 (vers >> 16) & 0xff,
2465 (vers >> 8) & 0xff,
2466 vers & 0xff,
2467
2468 ((cap >> 8) & 0x1f) + 1,
2469 (cap & 0x1f) + 1,
2470 speed_s,
2471 impl,
2472 scc_s);
2473
2474 dev_info(host->dev,
2475 "flags: "
2476 "%s%s%s%s%s%s%s"
2477 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2478 "%s%s%s%s%s%s%s"
2479 "%s%s\n"
365cfa1e
AV		 2480 ,
2481
2482 cap & HOST_CAP_64 ? "64bit " : "",
2483 cap & HOST_CAP_NCQ ? "ncq " : "",
2484 cap & HOST_CAP_SNTF ? "sntf " : "",
2485 cap & HOST_CAP_MPS ? "ilck " : "",
2486 cap & HOST_CAP_SSS ? "stag " : "",
2487 cap & HOST_CAP_ALPM ? "pm " : "",
2488 cap & HOST_CAP_LED ? "led " : "",
2489 cap & HOST_CAP_CLO ? "clo " : "",
2490 cap & HOST_CAP_ONLY ? "only " : "",
2491 cap & HOST_CAP_PMP ? "pmp " : "",
2492 cap & HOST_CAP_FBS ? "fbs " : "",
2493 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2494 cap & HOST_CAP_SSC ? "slum " : "",
2495 cap & HOST_CAP_PART ? "part " : "",
2496 cap & HOST_CAP_CCC ? "ccc " : "",
2497 cap & HOST_CAP_EMS ? "ems " : "",
2498 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2499 cap2 & HOST_CAP2_DESO ? "deso " : "",
2500 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2501 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2502 cap2 & HOST_CAP2_APST ? "apst " : "",
2503 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2504 cap2 & HOST_CAP2_BOH ? "boh " : ""
2505 );
2506}
2507EXPORT_SYMBOL_GPL(ahci_print_info);
2508
2509void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2510 struct ata_port_info *pi)
2511{
2512 u8 messages;
2513 void __iomem *mmio = hpriv->mmio;
2514 u32 em_loc = readl(mmio + HOST_EM_LOC);
2515 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2516
2517 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2518 return;
2519
2520 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2521
008dbd61 2522 if (messages) {
365cfa1e
AV		 2523 /* store em_loc */
2524 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2525 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2526 hpriv->em_msg_type = messages;
365cfa1e
AV		 2527 pi->flags |= ATA_FLAG_EM;
2528 if (!(em_ctl & EM_CTL_ALHD))
2529 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2530 }
2531}
2532EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2533
d684a90d 2534static int ahci_host_activate_multi_irqs(struct ata_host *host,
d1028e2f 2535 struct scsi_host_template *sht)
1c62854f 2536{
d684a90d 2537 struct ahci_host_priv *hpriv = host->private_data;
1c62854f
AG		 2538 int i, rc;
2539
2540 rc = ata_host_start(host);
2541 if (rc)
2542 return rc;
21bfd1aa
RR		 2543 /*
2544 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2545 * allocated. That is one MSI per port, starting from @irq.
2546 */
1c62854f
AG		 2547 for (i = 0; i < host->n_ports; i++) {
2548 struct ahci_port_priv *pp = host->ports[i]->private_data;
0b9e2988 2549 int irq = hpriv->get_irq_vector(host, i);
1c62854f
AG		 2550
2551 /* Do not receive interrupts sent by dummy ports */
2552 if (!pp) {
9b4b3f6a 2553 disable_irq(irq);
1c62854f
AG		 2554 continue;
2555 }
2556
a6b7fb76
DW		 2557 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2558 0, pp->irq_desc, host->ports[i]);
2559
1c62854f 2560 if (rc)
0a142b26 2561 return rc;
d684a90d 2562 ata_port_desc(host->ports[i], "irq %d", irq);
0a142b26 2563 }
d684a90d 2564
0a142b26 2565 return ata_host_register(host, sht);
1c62854f 2566}
d1028e2f
AG		 2567
2568/**
2569 * ahci_host_activate - start AHCI host, request IRQs and register it
2570 * @host: target ATA host
d1028e2f
AG		 2571 * @sht: scsi_host_template to use when registering the host
2572 *
d1028e2f
AG		 2573 * LOCKING:
2574 * Inherited from calling layer (may sleep).
2575 *
2576 * RETURNS:
2577 * 0 on success, -errno otherwise.
2578 */
21bfd1aa 2579int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
d1028e2f
AG		 2580{
2581 struct ahci_host_priv *hpriv = host->private_data;
21bfd1aa 2582 int irq = hpriv->irq;
d1028e2f
AG		 2583 int rc;
2584
0b9e2988 2585 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
f070d671 2586 if (hpriv->irq_handler)
d991c872
SE		 2587 dev_warn(host->dev,
2588 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
0b9e2988
CH		 2589 if (!hpriv->get_irq_vector) {
2590 dev_err(host->dev,
2591 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2592 return -EIO;
2593 }
f070d671 2594
d684a90d 2595 rc = ahci_host_activate_multi_irqs(host, sht);
f070d671
ST		 2596 } else {
2597 rc = ata_host_activate(host, irq, hpriv->irq_handler,
7865f83f 2598 IRQF_SHARED, sht);
f070d671
ST		 2599 }
2600
2601
d1028e2f
AG		 2602 return rc;
2603}
1c62854f
AG		 2604EXPORT_SYMBOL_GPL(ahci_host_activate);
2605
365cfa1e
AV		 2606MODULE_AUTHOR("Jeff Garzik");
2607MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2608MODULE_LICENSE("GPL");