Commit | Line | Data |
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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
ab771630 | 17 | * Copyright (C) 2003 Red Hat Inc |
af36d7f0 JG |
18 | * |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed | 40 | * Documentation |
25985edc LDM |
41 | * Publicly available from Intel web site. Errata documentation |
42 | * is also publicly available. As an aide to anyone hacking on this | |
2c5ff671 | 43 | * driver the list of errata that are relevant is below, going back to |
d96212ed AC |
44 | * PIIX4. Older device documentation is now a bit tricky to find. |
45 | * | |
88393161 | 46 | * The chipsets all follow very much the same design. The original Triton |
25985edc | 47 | * series chipsets do _not_ support independent device timings, but this |
d96212ed AC |
48 | * is fixed in Triton II. With the odd mobile exception the chips then |
49 | * change little except in gaining more modes until SATA arrives. This | |
25985edc | 50 | * driver supports only the chips with independent timing (that is those |
d96212ed AC |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
c611bed7 | 75 | * ICH7 errata #16 - MWDMA1 timings are incorrect |
d96212ed AC |
76 | * |
77 | * Should have been BIOS fixed: | |
78 | * 450NX: errata #19 - DMA hangs on old 450NX | |
79 | * 450NX: errata #20 - DMA hangs on old 450NX | |
80 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
81 | * ICH3 errata #15 - IDE deadlock under high load | |
82 | * (BIOS must set dev 31 fn 0 bit 23) | |
83 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
84 | */ |
85 | ||
86 | #include <linux/kernel.h> | |
87 | #include <linux/module.h> | |
88 | #include <linux/pci.h> | |
89 | #include <linux/init.h> | |
90 | #include <linux/blkdev.h> | |
91 | #include <linux/delay.h> | |
6248e647 | 92 | #include <linux/device.h> |
5a0e3ad6 | 93 | #include <linux/gfp.h> |
1da177e4 LT |
94 | #include <scsi/scsi_host.h> |
95 | #include <linux/libata.h> | |
b8b275ef | 96 | #include <linux/dmi.h> |
1da177e4 LT |
97 | |
98 | #define DRV_NAME "ata_piix" | |
c611bed7 | 99 | #define DRV_VERSION "2.13" |
1da177e4 LT |
100 | |
101 | enum { | |
102 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
103 | ICH5_PMR = 0x90, /* port mapping register */ | |
104 | ICH5_PCS = 0x92, /* port control and status */ | |
c7290724 TH |
105 | PIIX_SIDPR_BAR = 5, |
106 | PIIX_SIDPR_LEN = 16, | |
107 | PIIX_SIDPR_IDX = 0, | |
108 | PIIX_SIDPR_DATA = 4, | |
1da177e4 | 109 | |
ff0fc146 | 110 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
c7290724 | 111 | PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ |
1da177e4 | 112 | |
800b3996 TH |
113 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
114 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, | |
b3362f88 | 115 | |
5e5a4f5d ML |
116 | PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/ |
117 | ||
1da177e4 LT |
118 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
119 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
120 | ||
d33f58b8 TH |
121 | /* constants for mapping table */ |
122 | P0 = 0, /* port 0 */ | |
123 | P1 = 1, /* port 1 */ | |
124 | P2 = 2, /* port 2 */ | |
125 | P3 = 3, /* port 3 */ | |
126 | IDE = -1, /* IDE */ | |
25985edc | 127 | NA = -2, /* not available */ |
d33f58b8 TH |
128 | RV = -3, /* reserved */ |
129 | ||
7b6dbd68 | 130 | PIIX_AHCI_DEVICE = 6, |
b8b275ef TH |
131 | |
132 | /* host->flags bits */ | |
133 | PIIX_HOST_BROKEN_SUSPEND = (1 << 24), | |
1da177e4 LT |
134 | }; |
135 | ||
9cde9ed1 TH |
136 | enum piix_controller_ids { |
137 | /* controller IDs */ | |
138 | piix_pata_mwdma, /* PIIX3 MWDMA only */ | |
139 | piix_pata_33, /* PIIX4 at 33Mhz */ | |
140 | ich_pata_33, /* ICH up to UDMA 33 only */ | |
141 | ich_pata_66, /* ICH up to 66 Mhz */ | |
142 | ich_pata_100, /* ICH up to UDMA 100 */ | |
c611bed7 | 143 | ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/ |
9cde9ed1 TH |
144 | ich5_sata, |
145 | ich6_sata, | |
9c0bf675 TH |
146 | ich6m_sata, |
147 | ich8_sata, | |
9cde9ed1 | 148 | ich8_2port_sata, |
9c0bf675 TH |
149 | ich8m_apple_sata, /* locks up on second port enable */ |
150 | tolapai_sata, | |
9cde9ed1 | 151 | piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ |
5e5a4f5d | 152 | ich8_sata_snb, |
9cde9ed1 TH |
153 | }; |
154 | ||
d33f58b8 TH |
155 | struct piix_map_db { |
156 | const u32 mask; | |
73291a1c | 157 | const u16 port_enable; |
d33f58b8 TH |
158 | const int map[][4]; |
159 | }; | |
160 | ||
d96715c1 TH |
161 | struct piix_host_priv { |
162 | const int *map; | |
2852bcf7 | 163 | u32 saved_iocfg; |
c7290724 | 164 | void __iomem *sidpr; |
d96715c1 TH |
165 | }; |
166 | ||
2dcb407e JG |
167 | static int piix_init_one(struct pci_dev *pdev, |
168 | const struct pci_device_id *ent); | |
2852bcf7 | 169 | static void piix_remove_one(struct pci_dev *pdev); |
a1efdaba | 170 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); |
2dcb407e JG |
171 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); |
172 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
173 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
eb4a2c7f | 174 | static int ich_pata_cable_detect(struct ata_port *ap); |
25f98131 | 175 | static u8 piix_vmw_bmdma_status(struct ata_port *ap); |
82ef04fb TH |
176 | static int piix_sidpr_scr_read(struct ata_link *link, |
177 | unsigned int reg, u32 *val); | |
178 | static int piix_sidpr_scr_write(struct ata_link *link, | |
179 | unsigned int reg, u32 val); | |
a97c4006 TH |
180 | static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, |
181 | unsigned hints); | |
27943620 | 182 | static bool piix_irq_check(struct ata_port *ap); |
5e5a4f5d | 183 | static int piix_port_start(struct ata_port *ap); |
b8b275ef TH |
184 | #ifdef CONFIG_PM |
185 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
186 | static int piix_pci_device_resume(struct pci_dev *pdev); | |
187 | #endif | |
1da177e4 LT |
188 | |
189 | static unsigned int in_module_init = 1; | |
190 | ||
3b7d697d | 191 | static const struct pci_device_id piix_pci_tbl[] = { |
d2cdfc0d AC |
192 | /* Intel PIIX3 for the 430HX etc */ |
193 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, | |
25f98131 TH |
194 | /* VMware ICH4 */ |
195 | { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, | |
669a5db4 JG |
196 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
197 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ | |
198 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
669a5db4 JG |
199 | /* Intel PIIX4 */ |
200 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
201 | /* Intel PIIX4 */ | |
202 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
203 | /* Intel PIIX */ | |
204 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
205 | /* Intel ICH (i810, i815, i840) UDMA 66*/ | |
206 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, | |
207 | /* Intel ICH0 : UDMA 33*/ | |
208 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, | |
209 | /* Intel ICH2M */ | |
210 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
211 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ | |
212 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
213 | /* Intel ICH3M */ | |
214 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
215 | /* Intel ICH3 (E7500/1) UDMA 100 */ | |
216 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
4bb969db BH |
217 | /* Intel ICH4-L */ |
218 | { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
669a5db4 JG |
219 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ |
220 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
221 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
222 | /* Intel ICH5 */ | |
2eb829e9 | 223 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 JG |
224 | /* C-ICH (i810E2) */ |
225 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
85cd7251 | 226 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
669a5db4 JG |
227 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
228 | /* ICH6 (and 6) (i915) UDMA 100 */ | |
229 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
230 | /* ICH7/7-R (i945, i975) UDMA 100*/ | |
c611bed7 AC |
231 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, |
232 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, | |
c1e6f28c CL |
233 | /* ICH8 Mobile PATA Controller */ |
234 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
1da177e4 | 235 | |
7654db1a | 236 | /* SATA ports */ |
4fca377f | 237 | |
1d076e5b | 238 | /* 82801EB (ICH5) */ |
1da177e4 | 239 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 240 | /* 82801EB (ICH5) */ |
1da177e4 | 241 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 242 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
5e56a37c | 243 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 244 | /* 6300ESB pretending RAID */ |
5e56a37c | 245 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 246 | /* 82801FB/FW (ICH6/ICH6W) */ |
1da177e4 | 247 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 248 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
9c0bf675 | 249 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
5016d7d2 TH |
250 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). |
251 | * Attach iff the controller is in IDE mode. */ | |
252 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, | |
9c0bf675 | 253 | PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, |
1d076e5b | 254 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
9c0bf675 | 255 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 256 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
9c0bf675 | 257 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, |
f98b6573 | 258 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
9c0bf675 | 259 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
f98b6573 | 260 | /* SATA Controller 1 IDE (ICH8) */ |
9c0bf675 | 261 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
f98b6573 | 262 | /* SATA Controller 2 IDE (ICH8) */ |
00242ec8 | 263 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
8d8ef2fb | 264 | /* Mobile SATA Controller IDE (ICH8M), Apple */ |
9c0bf675 | 265 | { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, |
23cf296e | 266 | { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, |
487eff68 | 267 | { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, |
23cf296e TH |
268 | /* Mobile SATA Controller IDE (ICH8M) */ |
269 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
f98b6573 | 270 | /* SATA Controller IDE (ICH9) */ |
9c0bf675 | 271 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
f98b6573 | 272 | /* SATA Controller IDE (ICH9) */ |
00242ec8 | 273 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 274 | /* SATA Controller IDE (ICH9) */ |
00242ec8 | 275 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 276 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 277 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 278 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 279 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 280 | /* SATA Controller IDE (ICH9M) */ |
9c0bf675 | 281 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
c5cf0ffa | 282 | /* SATA Controller IDE (Tolapai) */ |
9c0bf675 | 283 | { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, |
bf7f22b9 | 284 | /* SATA Controller IDE (ICH10) */ |
9c0bf675 | 285 | { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
bf7f22b9 JG |
286 | /* SATA Controller IDE (ICH10) */ |
287 | { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
288 | /* SATA Controller IDE (ICH10) */ | |
9c0bf675 | 289 | { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
bf7f22b9 JG |
290 | /* SATA Controller IDE (ICH10) */ |
291 | { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
c6c6a1af SH |
292 | /* SATA Controller IDE (PCH) */ |
293 | { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
294 | /* SATA Controller IDE (PCH) */ | |
0395e61b SH |
295 | { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
296 | /* SATA Controller IDE (PCH) */ | |
c6c6a1af SH |
297 | { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
298 | /* SATA Controller IDE (PCH) */ | |
0395e61b SH |
299 | { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
300 | /* SATA Controller IDE (PCH) */ | |
c6c6a1af SH |
301 | { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
302 | /* SATA Controller IDE (PCH) */ | |
303 | { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
88e8201e | 304 | /* SATA Controller IDE (CPT) */ |
5e5a4f5d | 305 | { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, |
88e8201e | 306 | /* SATA Controller IDE (CPT) */ |
5e5a4f5d | 307 | { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, |
88e8201e SH |
308 | /* SATA Controller IDE (CPT) */ |
309 | { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
310 | /* SATA Controller IDE (CPT) */ | |
311 | { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
238e149c | 312 | /* SATA Controller IDE (PBG) */ |
5e5a4f5d | 313 | { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, |
238e149c SH |
314 | /* SATA Controller IDE (PBG) */ |
315 | { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
4a836c70 | 316 | /* SATA Controller IDE (Panther Point) */ |
5e5a4f5d | 317 | { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, |
4a836c70 | 318 | /* SATA Controller IDE (Panther Point) */ |
5e5a4f5d | 319 | { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, |
4a836c70 SH |
320 | /* SATA Controller IDE (Panther Point) */ |
321 | { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
322 | /* SATA Controller IDE (Panther Point) */ | |
323 | { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
1da177e4 LT |
324 | { } /* terminate list */ |
325 | }; | |
326 | ||
327 | static struct pci_driver piix_pci_driver = { | |
328 | .name = DRV_NAME, | |
329 | .id_table = piix_pci_tbl, | |
330 | .probe = piix_init_one, | |
2852bcf7 | 331 | .remove = piix_remove_one, |
438ac6d5 | 332 | #ifdef CONFIG_PM |
b8b275ef TH |
333 | .suspend = piix_pci_device_suspend, |
334 | .resume = piix_pci_device_resume, | |
438ac6d5 | 335 | #endif |
1da177e4 LT |
336 | }; |
337 | ||
193515d5 | 338 | static struct scsi_host_template piix_sht = { |
68d1d07b | 339 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
340 | }; |
341 | ||
27943620 | 342 | static struct ata_port_operations piix_sata_ops = { |
871af121 | 343 | .inherits = &ata_bmdma32_port_ops, |
27943620 | 344 | .sff_irq_check = piix_irq_check, |
5e5a4f5d | 345 | .port_start = piix_port_start, |
27943620 TH |
346 | }; |
347 | ||
348 | static struct ata_port_operations piix_pata_ops = { | |
349 | .inherits = &piix_sata_ops, | |
029cfd6b | 350 | .cable_detect = ata_cable_40wire, |
1da177e4 LT |
351 | .set_piomode = piix_set_piomode, |
352 | .set_dmamode = piix_set_dmamode, | |
a1efdaba | 353 | .prereset = piix_pata_prereset, |
1da177e4 LT |
354 | }; |
355 | ||
029cfd6b TH |
356 | static struct ata_port_operations piix_vmw_ops = { |
357 | .inherits = &piix_pata_ops, | |
358 | .bmdma_status = piix_vmw_bmdma_status, | |
669a5db4 JG |
359 | }; |
360 | ||
029cfd6b TH |
361 | static struct ata_port_operations ich_pata_ops = { |
362 | .inherits = &piix_pata_ops, | |
363 | .cable_detect = ich_pata_cable_detect, | |
364 | .set_dmamode = ich_set_dmamode, | |
1da177e4 LT |
365 | }; |
366 | ||
a97c4006 TH |
367 | static struct device_attribute *piix_sidpr_shost_attrs[] = { |
368 | &dev_attr_link_power_management_policy, | |
369 | NULL | |
370 | }; | |
371 | ||
372 | static struct scsi_host_template piix_sidpr_sht = { | |
373 | ATA_BMDMA_SHT(DRV_NAME), | |
374 | .shost_attrs = piix_sidpr_shost_attrs, | |
375 | }; | |
376 | ||
029cfd6b TH |
377 | static struct ata_port_operations piix_sidpr_sata_ops = { |
378 | .inherits = &piix_sata_ops, | |
57c9efdf | 379 | .hardreset = sata_std_hardreset, |
c7290724 TH |
380 | .scr_read = piix_sidpr_scr_read, |
381 | .scr_write = piix_sidpr_scr_write, | |
a97c4006 | 382 | .set_lpm = piix_sidpr_set_lpm, |
c7290724 TH |
383 | }; |
384 | ||
d96715c1 | 385 | static const struct piix_map_db ich5_map_db = { |
d33f58b8 | 386 | .mask = 0x7, |
ea35d29e | 387 | .port_enable = 0x3, |
d33f58b8 TH |
388 | .map = { |
389 | /* PM PS SM SS MAP */ | |
390 | { P0, NA, P1, NA }, /* 000b */ | |
391 | { P1, NA, P0, NA }, /* 001b */ | |
392 | { RV, RV, RV, RV }, | |
393 | { RV, RV, RV, RV }, | |
394 | { P0, P1, IDE, IDE }, /* 100b */ | |
395 | { P1, P0, IDE, IDE }, /* 101b */ | |
396 | { IDE, IDE, P0, P1 }, /* 110b */ | |
397 | { IDE, IDE, P1, P0 }, /* 111b */ | |
398 | }, | |
399 | }; | |
400 | ||
d96715c1 | 401 | static const struct piix_map_db ich6_map_db = { |
d33f58b8 | 402 | .mask = 0x3, |
ea35d29e | 403 | .port_enable = 0xf, |
d33f58b8 TH |
404 | .map = { |
405 | /* PM PS SM SS MAP */ | |
79ea24e7 | 406 | { P0, P2, P1, P3 }, /* 00b */ |
d33f58b8 TH |
407 | { IDE, IDE, P1, P3 }, /* 01b */ |
408 | { P0, P2, IDE, IDE }, /* 10b */ | |
409 | { RV, RV, RV, RV }, | |
410 | }, | |
411 | }; | |
412 | ||
d96715c1 | 413 | static const struct piix_map_db ich6m_map_db = { |
d33f58b8 | 414 | .mask = 0x3, |
ea35d29e | 415 | .port_enable = 0x5, |
67083741 TH |
416 | |
417 | /* Map 01b isn't specified in the doc but some notebooks use | |
c6446a4c TH |
418 | * it anyway. MAP 01b have been spotted on both ICH6M and |
419 | * ICH7M. | |
67083741 TH |
420 | */ |
421 | .map = { | |
422 | /* PM PS SM SS MAP */ | |
e04b3b9d | 423 | { P0, P2, NA, NA }, /* 00b */ |
67083741 TH |
424 | { IDE, IDE, P1, P3 }, /* 01b */ |
425 | { P0, P2, IDE, IDE }, /* 10b */ | |
426 | { RV, RV, RV, RV }, | |
427 | }, | |
428 | }; | |
429 | ||
08f12edc JG |
430 | static const struct piix_map_db ich8_map_db = { |
431 | .mask = 0x3, | |
a0ce9aca | 432 | .port_enable = 0xf, |
08f12edc JG |
433 | .map = { |
434 | /* PM PS SM SS MAP */ | |
158f30c8 | 435 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
08f12edc | 436 | { RV, RV, RV, RV }, |
ac2b0437 | 437 | { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ |
08f12edc JG |
438 | { RV, RV, RV, RV }, |
439 | }, | |
440 | }; | |
441 | ||
00242ec8 | 442 | static const struct piix_map_db ich8_2port_map_db = { |
e2d352af JG |
443 | .mask = 0x3, |
444 | .port_enable = 0x3, | |
445 | .map = { | |
446 | /* PM PS SM SS MAP */ | |
447 | { P0, NA, P1, NA }, /* 00b */ | |
448 | { RV, RV, RV, RV }, /* 01b */ | |
449 | { RV, RV, RV, RV }, /* 10b */ | |
450 | { RV, RV, RV, RV }, | |
451 | }, | |
c5cf0ffa JG |
452 | }; |
453 | ||
8d8ef2fb TR |
454 | static const struct piix_map_db ich8m_apple_map_db = { |
455 | .mask = 0x3, | |
456 | .port_enable = 0x1, | |
457 | .map = { | |
458 | /* PM PS SM SS MAP */ | |
459 | { P0, NA, NA, NA }, /* 00b */ | |
460 | { RV, RV, RV, RV }, | |
461 | { P0, P2, IDE, IDE }, /* 10b */ | |
462 | { RV, RV, RV, RV }, | |
463 | }, | |
464 | }; | |
465 | ||
00242ec8 | 466 | static const struct piix_map_db tolapai_map_db = { |
8f73a688 JG |
467 | .mask = 0x3, |
468 | .port_enable = 0x3, | |
469 | .map = { | |
470 | /* PM PS SM SS MAP */ | |
471 | { P0, NA, P1, NA }, /* 00b */ | |
472 | { RV, RV, RV, RV }, /* 01b */ | |
473 | { RV, RV, RV, RV }, /* 10b */ | |
474 | { RV, RV, RV, RV }, | |
475 | }, | |
476 | }; | |
477 | ||
d96715c1 TH |
478 | static const struct piix_map_db *piix_map_db_table[] = { |
479 | [ich5_sata] = &ich5_map_db, | |
d96715c1 | 480 | [ich6_sata] = &ich6_map_db, |
9c0bf675 TH |
481 | [ich6m_sata] = &ich6m_map_db, |
482 | [ich8_sata] = &ich8_map_db, | |
00242ec8 | 483 | [ich8_2port_sata] = &ich8_2port_map_db, |
9c0bf675 TH |
484 | [ich8m_apple_sata] = &ich8m_apple_map_db, |
485 | [tolapai_sata] = &tolapai_map_db, | |
5e5a4f5d | 486 | [ich8_sata_snb] = &ich8_map_db, |
d96715c1 TH |
487 | }; |
488 | ||
1da177e4 | 489 | static struct ata_port_info piix_port_info[] = { |
00242ec8 TH |
490 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ |
491 | { | |
00242ec8 | 492 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
493 | .pio_mask = ATA_PIO4, |
494 | .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
00242ec8 TH |
495 | .port_ops = &piix_pata_ops, |
496 | }, | |
497 | ||
ec300d99 | 498 | [piix_pata_33] = /* PIIX4 at 33MHz */ |
1d076e5b | 499 | { |
b3362f88 | 500 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
501 | .pio_mask = ATA_PIO4, |
502 | .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
503 | .udma_mask = ATA_UDMA2, | |
1d076e5b TH |
504 | .port_ops = &piix_pata_ops, |
505 | }, | |
506 | ||
ec300d99 | 507 | [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ |
669a5db4 | 508 | { |
b3362f88 | 509 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
510 | .pio_mask = ATA_PIO4, |
511 | .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ | |
512 | .udma_mask = ATA_UDMA2, | |
669a5db4 JG |
513 | .port_ops = &ich_pata_ops, |
514 | }, | |
ec300d99 JG |
515 | |
516 | [ich_pata_66] = /* ICH controllers up to 66MHz */ | |
1da177e4 | 517 | { |
b3362f88 | 518 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
519 | .pio_mask = ATA_PIO4, |
520 | .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ | |
669a5db4 JG |
521 | .udma_mask = ATA_UDMA4, |
522 | .port_ops = &ich_pata_ops, | |
523 | }, | |
85cd7251 | 524 | |
ec300d99 | 525 | [ich_pata_100] = |
669a5db4 | 526 | { |
b3362f88 | 527 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
14bdef98 EIB |
528 | .pio_mask = ATA_PIO4, |
529 | .mwdma_mask = ATA_MWDMA12_ONLY, | |
530 | .udma_mask = ATA_UDMA5, | |
669a5db4 | 531 | .port_ops = &ich_pata_ops, |
1da177e4 LT |
532 | }, |
533 | ||
c611bed7 AC |
534 | [ich_pata_100_nomwdma1] = |
535 | { | |
536 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, | |
537 | .pio_mask = ATA_PIO4, | |
538 | .mwdma_mask = ATA_MWDMA2_ONLY, | |
539 | .udma_mask = ATA_UDMA5, | |
540 | .port_ops = &ich_pata_ops, | |
541 | }, | |
542 | ||
ec300d99 | 543 | [ich5_sata] = |
1da177e4 | 544 | { |
228c1590 | 545 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
546 | .pio_mask = ATA_PIO4, |
547 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 548 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
549 | .port_ops = &piix_sata_ops, |
550 | }, | |
551 | ||
ec300d99 | 552 | [ich6_sata] = |
1da177e4 | 553 | { |
723159c5 | 554 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
555 | .pio_mask = ATA_PIO4, |
556 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 557 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
558 | .port_ops = &piix_sata_ops, |
559 | }, | |
560 | ||
9c0bf675 | 561 | [ich6m_sata] = |
c368ca4e | 562 | { |
5016d7d2 | 563 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
564 | .pio_mask = ATA_PIO4, |
565 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 566 | .udma_mask = ATA_UDMA6, |
c368ca4e JG |
567 | .port_ops = &piix_sata_ops, |
568 | }, | |
1d076e5b | 569 | |
9c0bf675 | 570 | [ich8_sata] = |
08f12edc | 571 | { |
5016d7d2 | 572 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
14bdef98 EIB |
573 | .pio_mask = ATA_PIO4, |
574 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 575 | .udma_mask = ATA_UDMA6, |
08f12edc JG |
576 | .port_ops = &piix_sata_ops, |
577 | }, | |
669a5db4 | 578 | |
00242ec8 | 579 | [ich8_2port_sata] = |
c5cf0ffa | 580 | { |
5016d7d2 | 581 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
14bdef98 EIB |
582 | .pio_mask = ATA_PIO4, |
583 | .mwdma_mask = ATA_MWDMA2, | |
c5cf0ffa JG |
584 | .udma_mask = ATA_UDMA6, |
585 | .port_ops = &piix_sata_ops, | |
586 | }, | |
8f73a688 | 587 | |
9c0bf675 | 588 | [tolapai_sata] = |
8f73a688 | 589 | { |
5016d7d2 | 590 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
591 | .pio_mask = ATA_PIO4, |
592 | .mwdma_mask = ATA_MWDMA2, | |
8f73a688 JG |
593 | .udma_mask = ATA_UDMA6, |
594 | .port_ops = &piix_sata_ops, | |
595 | }, | |
8d8ef2fb | 596 | |
9c0bf675 | 597 | [ich8m_apple_sata] = |
8d8ef2fb | 598 | { |
23cf296e | 599 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
600 | .pio_mask = ATA_PIO4, |
601 | .mwdma_mask = ATA_MWDMA2, | |
8d8ef2fb TR |
602 | .udma_mask = ATA_UDMA6, |
603 | .port_ops = &piix_sata_ops, | |
604 | }, | |
605 | ||
25f98131 TH |
606 | [piix_pata_vmw] = |
607 | { | |
25f98131 | 608 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
609 | .pio_mask = ATA_PIO4, |
610 | .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
611 | .udma_mask = ATA_UDMA2, | |
25f98131 TH |
612 | .port_ops = &piix_vmw_ops, |
613 | }, | |
614 | ||
5e5a4f5d ML |
615 | /* |
616 | * some Sandybridge chipsets have broken 32 mode up to now, | |
617 | * see https://bugzilla.kernel.org/show_bug.cgi?id=40592 | |
618 | */ | |
619 | [ich8_sata_snb] = | |
620 | { | |
621 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16, | |
622 | .pio_mask = ATA_PIO4, | |
623 | .mwdma_mask = ATA_MWDMA2, | |
624 | .udma_mask = ATA_UDMA6, | |
625 | .port_ops = &piix_sata_ops, | |
626 | }, | |
627 | ||
1da177e4 LT |
628 | }; |
629 | ||
630 | static struct pci_bits piix_enable_bits[] = { | |
631 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
632 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
633 | }; | |
634 | ||
635 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
636 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
637 | MODULE_LICENSE("GPL"); | |
638 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
639 | MODULE_VERSION(DRV_VERSION); | |
640 | ||
fc085150 AC |
641 | struct ich_laptop { |
642 | u16 device; | |
643 | u16 subvendor; | |
644 | u16 subdevice; | |
645 | }; | |
646 | ||
647 | /* | |
648 | * List of laptops that use short cables rather than 80 wire | |
649 | */ | |
650 | ||
651 | static const struct ich_laptop ich_laptop[] = { | |
652 | /* devid, subvendor, subdev */ | |
653 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ | |
2655e2ce | 654 | { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ |
babfb682 | 655 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
6034734d | 656 | { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */ |
12340106 | 657 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
54174db3 | 658 | { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
af901ca1 | 659 | { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */ |
d09addf6 | 660 | { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ |
6034734d | 661 | { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */ |
b33620f9 | 662 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
e1fefea9 CIK |
663 | { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ |
664 | { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ | |
01ce2601 | 665 | { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ |
124a6eec | 666 | { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */ |
fc085150 AC |
667 | /* end marker */ |
668 | { 0, } | |
669 | }; | |
670 | ||
5e5a4f5d ML |
671 | static int piix_port_start(struct ata_port *ap) |
672 | { | |
673 | if (!(ap->flags & PIIX_FLAG_PIO16)) | |
674 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; | |
675 | ||
676 | return ata_bmdma_port_start(ap); | |
677 | } | |
678 | ||
1da177e4 | 679 | /** |
eb4a2c7f | 680 | * ich_pata_cable_detect - Probe host controller cable detect info |
1da177e4 LT |
681 | * @ap: Port for which cable detect info is desired |
682 | * | |
683 | * Read 80c cable indicator from ATA PCI device's PCI config | |
684 | * register. This register is normally set by firmware (BIOS). | |
685 | * | |
686 | * LOCKING: | |
687 | * None (inherited from caller). | |
688 | */ | |
669a5db4 | 689 | |
eb4a2c7f | 690 | static int ich_pata_cable_detect(struct ata_port *ap) |
1da177e4 | 691 | { |
cca3974e | 692 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
2852bcf7 | 693 | struct piix_host_priv *hpriv = ap->host->private_data; |
fc085150 | 694 | const struct ich_laptop *lap = &ich_laptop[0]; |
2852bcf7 | 695 | u8 mask; |
1da177e4 | 696 | |
fc085150 AC |
697 | /* Check for specials - Acer Aspire 5602WLMi */ |
698 | while (lap->device) { | |
699 | if (lap->device == pdev->device && | |
700 | lap->subvendor == pdev->subsystem_vendor && | |
2dcb407e | 701 | lap->subdevice == pdev->subsystem_device) |
eb4a2c7f | 702 | return ATA_CBL_PATA40_SHORT; |
2dcb407e | 703 | |
fc085150 AC |
704 | lap++; |
705 | } | |
706 | ||
1da177e4 | 707 | /* check BIOS cable detect results */ |
2a88d1ac | 708 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
2852bcf7 | 709 | if ((hpriv->saved_iocfg & mask) == 0) |
eb4a2c7f AC |
710 | return ATA_CBL_PATA40; |
711 | return ATA_CBL_PATA80; | |
1da177e4 LT |
712 | } |
713 | ||
714 | /** | |
ccc4672a | 715 | * piix_pata_prereset - prereset for PATA host controller |
cc0680a5 | 716 | * @link: Target link |
d4b2bab4 | 717 | * @deadline: deadline jiffies for the operation |
1da177e4 | 718 | * |
573db6b8 TH |
719 | * LOCKING: |
720 | * None (inherited from caller). | |
721 | */ | |
cc0680a5 | 722 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) |
1da177e4 | 723 | { |
cc0680a5 | 724 | struct ata_port *ap = link->ap; |
cca3974e | 725 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 726 | |
c961922b AC |
727 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
728 | return -ENOENT; | |
9363c382 | 729 | return ata_sff_prereset(link, deadline); |
ccc4672a TH |
730 | } |
731 | ||
60c3be38 BZ |
732 | static DEFINE_SPINLOCK(piix_lock); |
733 | ||
1da177e4 LT |
734 | /** |
735 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
736 | * @ap: Port whose timings we are configuring | |
737 | * @adev: um | |
1da177e4 LT |
738 | * |
739 | * Set PIO mode for device, in host controller PCI config space. | |
740 | * | |
741 | * LOCKING: | |
742 | * None (inherited from caller). | |
743 | */ | |
744 | ||
2dcb407e | 745 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) |
1da177e4 | 746 | { |
cca3974e | 747 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
60c3be38 BZ |
748 | unsigned long flags; |
749 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
1da177e4 | 750 | unsigned int is_slave = (adev->devno != 0); |
2a88d1ac | 751 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
1da177e4 LT |
752 | unsigned int slave_port = 0x44; |
753 | u16 master_data; | |
754 | u8 slave_data; | |
669a5db4 JG |
755 | u8 udma_enable; |
756 | int control = 0; | |
85cd7251 | 757 | |
669a5db4 JG |
758 | /* |
759 | * See Intel Document 298600-004 for the timing programing rules | |
760 | * for ICH controllers. | |
761 | */ | |
1da177e4 LT |
762 | |
763 | static const /* ISP RTC */ | |
764 | u8 timings[][2] = { { 0, 0 }, | |
765 | { 0, 0 }, | |
766 | { 1, 0 }, | |
767 | { 2, 1 }, | |
768 | { 2, 3 }, }; | |
769 | ||
669a5db4 JG |
770 | if (pio >= 2) |
771 | control |= 1; /* TIME1 enable */ | |
772 | if (ata_pio_need_iordy(adev)) | |
773 | control |= 2; /* IE enable */ | |
774 | ||
85cd7251 | 775 | /* Intel specifies that the PPE functionality is for disk only */ |
669a5db4 JG |
776 | if (adev->class == ATA_DEV_ATA) |
777 | control |= 4; /* PPE enable */ | |
778 | ||
60c3be38 BZ |
779 | spin_lock_irqsave(&piix_lock, flags); |
780 | ||
a5bf5f5a TH |
781 | /* PIO configuration clears DTE unconditionally. It will be |
782 | * programmed in set_dmamode which is guaranteed to be called | |
783 | * after set_piomode if any DMA mode is available. | |
784 | */ | |
1da177e4 LT |
785 | pci_read_config_word(dev, master_port, &master_data); |
786 | if (is_slave) { | |
a5bf5f5a TH |
787 | /* clear TIME1|IE1|PPE1|DTE1 */ |
788 | master_data &= 0xff0f; | |
669a5db4 JG |
789 | /* enable PPE1, IE1 and TIME1 as needed */ |
790 | master_data |= (control << 4); | |
1da177e4 | 791 | pci_read_config_byte(dev, slave_port, &slave_data); |
2a88d1ac | 792 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 | 793 | /* Load the timing nibble for this slave */ |
a5bf5f5a TH |
794 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
795 | << (ap->port_no ? 4 : 0); | |
1da177e4 | 796 | } else { |
a5bf5f5a TH |
797 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
798 | master_data &= 0xccf0; | |
669a5db4 JG |
799 | /* Enable PPE, IE and TIME as appropriate */ |
800 | master_data |= control; | |
a5bf5f5a | 801 | /* load ISP and RCT */ |
1da177e4 LT |
802 | master_data |= |
803 | (timings[pio][0] << 12) | | |
804 | (timings[pio][1] << 8); | |
805 | } | |
ce986690 BZ |
806 | |
807 | /* Enable SITRE (separate slave timing register) */ | |
808 | master_data |= 0x4000; | |
1da177e4 LT |
809 | pci_write_config_word(dev, master_port, master_data); |
810 | if (is_slave) | |
811 | pci_write_config_byte(dev, slave_port, slave_data); | |
669a5db4 JG |
812 | |
813 | /* Ensure the UDMA bit is off - it will be turned back on if | |
814 | UDMA is selected */ | |
85cd7251 | 815 | |
669a5db4 JG |
816 | if (ap->udma_mask) { |
817 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
818 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); | |
819 | pci_write_config_byte(dev, 0x48, udma_enable); | |
820 | } | |
60c3be38 BZ |
821 | |
822 | spin_unlock_irqrestore(&piix_lock, flags); | |
1da177e4 LT |
823 | } |
824 | ||
825 | /** | |
669a5db4 | 826 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
1da177e4 | 827 | * @ap: Port whose timings we are configuring |
669a5db4 | 828 | * @adev: Drive in question |
c32a8fd7 | 829 | * @isich: set if the chip is an ICH device |
1da177e4 LT |
830 | * |
831 | * Set UDMA mode for device, in host controller PCI config space. | |
832 | * | |
833 | * LOCKING: | |
834 | * None (inherited from caller). | |
835 | */ | |
836 | ||
2dcb407e | 837 | static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) |
1da177e4 | 838 | { |
cca3974e | 839 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
60c3be38 | 840 | unsigned long flags; |
669a5db4 JG |
841 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
842 | u16 master_data; | |
843 | u8 speed = adev->dma_mode; | |
844 | int devid = adev->devno + 2 * ap->port_no; | |
dedf61db | 845 | u8 udma_enable = 0; |
85cd7251 | 846 | |
669a5db4 JG |
847 | static const /* ISP RTC */ |
848 | u8 timings[][2] = { { 0, 0 }, | |
849 | { 0, 0 }, | |
850 | { 1, 0 }, | |
851 | { 2, 1 }, | |
852 | { 2, 3 }, }; | |
853 | ||
60c3be38 BZ |
854 | spin_lock_irqsave(&piix_lock, flags); |
855 | ||
669a5db4 | 856 | pci_read_config_word(dev, master_port, &master_data); |
d2cdfc0d AC |
857 | if (ap->udma_mask) |
858 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
1da177e4 LT |
859 | |
860 | if (speed >= XFER_UDMA_0) { | |
669a5db4 JG |
861 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
862 | u16 udma_timing; | |
863 | u16 ideconf; | |
864 | int u_clock, u_speed; | |
85cd7251 | 865 | |
669a5db4 | 866 | /* |
2dcb407e | 867 | * UDMA is handled by a combination of clock switching and |
85cd7251 JG |
868 | * selection of dividers |
869 | * | |
669a5db4 | 870 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
85cd7251 | 871 | * except UDMA0 which is 00 |
669a5db4 JG |
872 | */ |
873 | u_speed = min(2 - (udma & 1), udma); | |
874 | if (udma == 5) | |
875 | u_clock = 0x1000; /* 100Mhz */ | |
876 | else if (udma > 2) | |
877 | u_clock = 1; /* 66Mhz */ | |
878 | else | |
879 | u_clock = 0; /* 33Mhz */ | |
85cd7251 | 880 | |
669a5db4 | 881 | udma_enable |= (1 << devid); |
85cd7251 | 882 | |
669a5db4 JG |
883 | /* Load the CT/RP selection */ |
884 | pci_read_config_word(dev, 0x4A, &udma_timing); | |
885 | udma_timing &= ~(3 << (4 * devid)); | |
886 | udma_timing |= u_speed << (4 * devid); | |
887 | pci_write_config_word(dev, 0x4A, udma_timing); | |
888 | ||
85cd7251 | 889 | if (isich) { |
669a5db4 JG |
890 | /* Select a 33/66/100Mhz clock */ |
891 | pci_read_config_word(dev, 0x54, &ideconf); | |
892 | ideconf &= ~(0x1001 << devid); | |
893 | ideconf |= u_clock << devid; | |
894 | /* For ICH or later we should set bit 10 for better | |
895 | performance (WR_PingPong_En) */ | |
896 | pci_write_config_word(dev, 0x54, ideconf); | |
1da177e4 | 897 | } |
1da177e4 | 898 | } else { |
669a5db4 JG |
899 | /* |
900 | * MWDMA is driven by the PIO timings. We must also enable | |
901 | * IORDY unconditionally along with TIME1. PPE has already | |
902 | * been set when the PIO timing was set. | |
903 | */ | |
904 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
905 | unsigned int control; | |
906 | u8 slave_data; | |
907 | const unsigned int needed_pio[3] = { | |
908 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
909 | }; | |
910 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
85cd7251 | 911 | |
669a5db4 | 912 | control = 3; /* IORDY|TIME1 */ |
85cd7251 | 913 | |
669a5db4 JG |
914 | /* If the drive MWDMA is faster than it can do PIO then |
915 | we must force PIO into PIO0 */ | |
85cd7251 | 916 | |
669a5db4 JG |
917 | if (adev->pio_mode < needed_pio[mwdma]) |
918 | /* Enable DMA timing only */ | |
919 | control |= 8; /* PIO cycles in PIO0 */ | |
920 | ||
921 | if (adev->devno) { /* Slave */ | |
922 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ | |
923 | master_data |= control << 4; | |
924 | pci_read_config_byte(dev, 0x44, &slave_data); | |
a5bf5f5a | 925 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 JG |
926 | /* Load the matching timing */ |
927 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
928 | pci_write_config_byte(dev, 0x44, slave_data); | |
929 | } else { /* Master */ | |
85cd7251 | 930 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
669a5db4 JG |
931 | and master timing bits */ |
932 | master_data |= control; | |
933 | master_data |= | |
934 | (timings[pio][0] << 12) | | |
935 | (timings[pio][1] << 8); | |
936 | } | |
a5bf5f5a | 937 | |
69385943 | 938 | if (ap->udma_mask) |
a5bf5f5a | 939 | udma_enable &= ~(1 << devid); |
69385943 BZ |
940 | |
941 | pci_write_config_word(dev, master_port, master_data); | |
1da177e4 | 942 | } |
669a5db4 JG |
943 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
944 | if (ap->udma_mask) | |
945 | pci_write_config_byte(dev, 0x48, udma_enable); | |
60c3be38 BZ |
946 | |
947 | spin_unlock_irqrestore(&piix_lock, flags); | |
669a5db4 JG |
948 | } |
949 | ||
950 | /** | |
951 | * piix_set_dmamode - Initialize host controller PATA DMA timings | |
952 | * @ap: Port whose timings we are configuring | |
953 | * @adev: um | |
954 | * | |
955 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
956 | * | |
957 | * LOCKING: | |
958 | * None (inherited from caller). | |
959 | */ | |
960 | ||
2dcb407e | 961 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
962 | { |
963 | do_pata_set_dmamode(ap, adev, 0); | |
964 | } | |
965 | ||
966 | /** | |
967 | * ich_set_dmamode - Initialize host controller PATA DMA timings | |
968 | * @ap: Port whose timings we are configuring | |
969 | * @adev: um | |
970 | * | |
971 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
972 | * | |
973 | * LOCKING: | |
974 | * None (inherited from caller). | |
975 | */ | |
976 | ||
2dcb407e | 977 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
978 | { |
979 | do_pata_set_dmamode(ap, adev, 1); | |
1da177e4 LT |
980 | } |
981 | ||
c7290724 TH |
982 | /* |
983 | * Serial ATA Index/Data Pair Superset Registers access | |
984 | * | |
985 | * Beginning from ICH8, there's a sane way to access SCRs using index | |
be77e43a TH |
986 | * and data register pair located at BAR5 which means that we have |
987 | * separate SCRs for master and slave. This is handled using libata | |
988 | * slave_link facility. | |
c7290724 TH |
989 | */ |
990 | static const int piix_sidx_map[] = { | |
991 | [SCR_STATUS] = 0, | |
992 | [SCR_ERROR] = 2, | |
993 | [SCR_CONTROL] = 1, | |
994 | }; | |
995 | ||
be77e43a | 996 | static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) |
c7290724 | 997 | { |
be77e43a | 998 | struct ata_port *ap = link->ap; |
c7290724 TH |
999 | struct piix_host_priv *hpriv = ap->host->private_data; |
1000 | ||
be77e43a | 1001 | iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], |
c7290724 TH |
1002 | hpriv->sidpr + PIIX_SIDPR_IDX); |
1003 | } | |
1004 | ||
82ef04fb TH |
1005 | static int piix_sidpr_scr_read(struct ata_link *link, |
1006 | unsigned int reg, u32 *val) | |
c7290724 | 1007 | { |
be77e43a | 1008 | struct piix_host_priv *hpriv = link->ap->host->private_data; |
c7290724 TH |
1009 | |
1010 | if (reg >= ARRAY_SIZE(piix_sidx_map)) | |
1011 | return -EINVAL; | |
1012 | ||
be77e43a TH |
1013 | piix_sidpr_sel(link, reg); |
1014 | *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); | |
c7290724 TH |
1015 | return 0; |
1016 | } | |
1017 | ||
82ef04fb TH |
1018 | static int piix_sidpr_scr_write(struct ata_link *link, |
1019 | unsigned int reg, u32 val) | |
c7290724 | 1020 | { |
be77e43a | 1021 | struct piix_host_priv *hpriv = link->ap->host->private_data; |
82ef04fb | 1022 | |
c7290724 TH |
1023 | if (reg >= ARRAY_SIZE(piix_sidx_map)) |
1024 | return -EINVAL; | |
1025 | ||
be77e43a TH |
1026 | piix_sidpr_sel(link, reg); |
1027 | iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); | |
c7290724 TH |
1028 | return 0; |
1029 | } | |
1030 | ||
a97c4006 TH |
1031 | static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, |
1032 | unsigned hints) | |
1033 | { | |
1034 | return sata_link_scr_lpm(link, policy, false); | |
1035 | } | |
1036 | ||
27943620 TH |
1037 | static bool piix_irq_check(struct ata_port *ap) |
1038 | { | |
1039 | if (unlikely(!ap->ioaddr.bmdma_addr)) | |
1040 | return false; | |
1041 | ||
1042 | return ap->ops->bmdma_status(ap) & ATA_DMA_INTR; | |
1043 | } | |
1044 | ||
b8b275ef | 1045 | #ifdef CONFIG_PM |
8c3832eb TH |
1046 | static int piix_broken_suspend(void) |
1047 | { | |
1855256c | 1048 | static const struct dmi_system_id sysids[] = { |
4c74d4ec TH |
1049 | { |
1050 | .ident = "TECRA M3", | |
1051 | .matches = { | |
1052 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1053 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), | |
1054 | }, | |
1055 | }, | |
04d86d6f PS |
1056 | { |
1057 | .ident = "TECRA M3", | |
1058 | .matches = { | |
1059 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1060 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), | |
1061 | }, | |
1062 | }, | |
d1aa690a PS |
1063 | { |
1064 | .ident = "TECRA M4", | |
1065 | .matches = { | |
1066 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1067 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), | |
1068 | }, | |
1069 | }, | |
040dee53 TH |
1070 | { |
1071 | .ident = "TECRA M4", | |
1072 | .matches = { | |
1073 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1074 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), | |
1075 | }, | |
1076 | }, | |
8c3832eb TH |
1077 | { |
1078 | .ident = "TECRA M5", | |
1079 | .matches = { | |
1080 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1081 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), | |
1082 | }, | |
b8b275ef | 1083 | }, |
ffe188dd PS |
1084 | { |
1085 | .ident = "TECRA M6", | |
1086 | .matches = { | |
1087 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1088 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), | |
1089 | }, | |
1090 | }, | |
5c08ea01 TH |
1091 | { |
1092 | .ident = "TECRA M7", | |
1093 | .matches = { | |
1094 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1095 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), | |
1096 | }, | |
1097 | }, | |
04d86d6f PS |
1098 | { |
1099 | .ident = "TECRA A8", | |
1100 | .matches = { | |
1101 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1102 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), | |
1103 | }, | |
1104 | }, | |
ffe188dd PS |
1105 | { |
1106 | .ident = "Satellite R20", | |
1107 | .matches = { | |
1108 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1109 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), | |
1110 | }, | |
1111 | }, | |
04d86d6f PS |
1112 | { |
1113 | .ident = "Satellite R25", | |
1114 | .matches = { | |
1115 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1116 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), | |
1117 | }, | |
1118 | }, | |
3cc0b9d3 TH |
1119 | { |
1120 | .ident = "Satellite U200", | |
1121 | .matches = { | |
1122 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1123 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), | |
1124 | }, | |
1125 | }, | |
04d86d6f PS |
1126 | { |
1127 | .ident = "Satellite U200", | |
1128 | .matches = { | |
1129 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1130 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), | |
1131 | }, | |
1132 | }, | |
62320e23 YC |
1133 | { |
1134 | .ident = "Satellite Pro U200", | |
1135 | .matches = { | |
1136 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1137 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), | |
1138 | }, | |
1139 | }, | |
8c3832eb TH |
1140 | { |
1141 | .ident = "Satellite U205", | |
1142 | .matches = { | |
1143 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1144 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), | |
1145 | }, | |
b8b275ef | 1146 | }, |
de753e5e TH |
1147 | { |
1148 | .ident = "SATELLITE U205", | |
1149 | .matches = { | |
1150 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1151 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), | |
1152 | }, | |
1153 | }, | |
8c3832eb TH |
1154 | { |
1155 | .ident = "Portege M500", | |
1156 | .matches = { | |
1157 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1158 | DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), | |
1159 | }, | |
b8b275ef | 1160 | }, |
c3f93b8f TH |
1161 | { |
1162 | .ident = "VGN-BX297XP", | |
1163 | .matches = { | |
1164 | DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), | |
1165 | DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), | |
1166 | }, | |
1167 | }, | |
7d051548 JG |
1168 | |
1169 | { } /* terminate list */ | |
8c3832eb | 1170 | }; |
7abe79c3 TH |
1171 | static const char *oemstrs[] = { |
1172 | "Tecra M3,", | |
1173 | }; | |
1174 | int i; | |
8c3832eb TH |
1175 | |
1176 | if (dmi_check_system(sysids)) | |
1177 | return 1; | |
1178 | ||
7abe79c3 TH |
1179 | for (i = 0; i < ARRAY_SIZE(oemstrs); i++) |
1180 | if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) | |
1181 | return 1; | |
1182 | ||
1eedb4a9 TH |
1183 | /* TECRA M4 sometimes forgets its identify and reports bogus |
1184 | * DMI information. As the bogus information is a bit | |
1185 | * generic, match as many entries as possible. This manual | |
1186 | * matching is necessary because dmi_system_id.matches is | |
1187 | * limited to four entries. | |
1188 | */ | |
3c387730 JS |
1189 | if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && |
1190 | dmi_match(DMI_PRODUCT_NAME, "000000") && | |
1191 | dmi_match(DMI_PRODUCT_VERSION, "000000") && | |
1192 | dmi_match(DMI_PRODUCT_SERIAL, "000000") && | |
1193 | dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && | |
1194 | dmi_match(DMI_BOARD_NAME, "Portable PC") && | |
1195 | dmi_match(DMI_BOARD_VERSION, "Version A0")) | |
1eedb4a9 TH |
1196 | return 1; |
1197 | ||
8c3832eb TH |
1198 | return 0; |
1199 | } | |
b8b275ef TH |
1200 | |
1201 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
1202 | { | |
1203 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1204 | unsigned long flags; | |
1205 | int rc = 0; | |
1206 | ||
1207 | rc = ata_host_suspend(host, mesg); | |
1208 | if (rc) | |
1209 | return rc; | |
1210 | ||
1211 | /* Some braindamaged ACPI suspend implementations expect the | |
1212 | * controller to be awake on entry; otherwise, it burns cpu | |
1213 | * cycles and power trying to do something to the sleeping | |
1214 | * beauty. | |
1215 | */ | |
3a2d5b70 | 1216 | if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { |
b8b275ef TH |
1217 | pci_save_state(pdev); |
1218 | ||
1219 | /* mark its power state as "unknown", since we don't | |
1220 | * know if e.g. the BIOS will change its device state | |
1221 | * when we suspend. | |
1222 | */ | |
1223 | if (pdev->current_state == PCI_D0) | |
1224 | pdev->current_state = PCI_UNKNOWN; | |
1225 | ||
1226 | /* tell resume that it's waking up from broken suspend */ | |
1227 | spin_lock_irqsave(&host->lock, flags); | |
1228 | host->flags |= PIIX_HOST_BROKEN_SUSPEND; | |
1229 | spin_unlock_irqrestore(&host->lock, flags); | |
1230 | } else | |
1231 | ata_pci_device_do_suspend(pdev, mesg); | |
1232 | ||
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | static int piix_pci_device_resume(struct pci_dev *pdev) | |
1237 | { | |
1238 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1239 | unsigned long flags; | |
1240 | int rc; | |
1241 | ||
1242 | if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { | |
1243 | spin_lock_irqsave(&host->lock, flags); | |
1244 | host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; | |
1245 | spin_unlock_irqrestore(&host->lock, flags); | |
1246 | ||
1247 | pci_set_power_state(pdev, PCI_D0); | |
1248 | pci_restore_state(pdev); | |
1249 | ||
1250 | /* PCI device wasn't disabled during suspend. Use | |
0b62e13b TH |
1251 | * pci_reenable_device() to avoid affecting the enable |
1252 | * count. | |
b8b275ef | 1253 | */ |
0b62e13b | 1254 | rc = pci_reenable_device(pdev); |
b8b275ef | 1255 | if (rc) |
a44fec1f JP |
1256 | dev_err(&pdev->dev, |
1257 | "failed to enable device after resume (%d)\n", | |
1258 | rc); | |
b8b275ef TH |
1259 | } else |
1260 | rc = ata_pci_device_do_resume(pdev); | |
1261 | ||
1262 | if (rc == 0) | |
1263 | ata_host_resume(host); | |
1264 | ||
1265 | return rc; | |
1266 | } | |
1267 | #endif | |
1268 | ||
25f98131 TH |
1269 | static u8 piix_vmw_bmdma_status(struct ata_port *ap) |
1270 | { | |
1271 | return ata_bmdma_status(ap) & ~ATA_DMA_ERR; | |
1272 | } | |
1273 | ||
1da177e4 LT |
1274 | #define AHCI_PCI_BAR 5 |
1275 | #define AHCI_GLOBAL_CTL 0x04 | |
1276 | #define AHCI_ENABLE (1 << 31) | |
1277 | static int piix_disable_ahci(struct pci_dev *pdev) | |
1278 | { | |
ea6ba10b | 1279 | void __iomem *mmio; |
1da177e4 LT |
1280 | u32 tmp; |
1281 | int rc = 0; | |
1282 | ||
1283 | /* BUG: pci_enable_device has not yet been called. This | |
1284 | * works because this device is usually set up by BIOS. | |
1285 | */ | |
1286 | ||
374b1873 JG |
1287 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
1288 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 1289 | return 0; |
7b6dbd68 | 1290 | |
374b1873 | 1291 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
1292 | if (!mmio) |
1293 | return -ENOMEM; | |
7b6dbd68 | 1294 | |
c47a631f | 1295 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1296 | if (tmp & AHCI_ENABLE) { |
1297 | tmp &= ~AHCI_ENABLE; | |
c47a631f | 1298 | iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); |
1da177e4 | 1299 | |
c47a631f | 1300 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1301 | if (tmp & AHCI_ENABLE) |
1302 | rc = -EIO; | |
1303 | } | |
7b6dbd68 | 1304 | |
374b1873 | 1305 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
1306 | return rc; |
1307 | } | |
1308 | ||
c621b140 AC |
1309 | /** |
1310 | * piix_check_450nx_errata - Check for problem 450NX setup | |
c893a3ae | 1311 | * @ata_dev: the PCI device to check |
2e9edbf8 | 1312 | * |
c621b140 AC |
1313 | * Check for the present of 450NX errata #19 and errata #25. If |
1314 | * they are found return an error code so we can turn off DMA | |
1315 | */ | |
1316 | ||
1317 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) | |
1318 | { | |
1319 | struct pci_dev *pdev = NULL; | |
1320 | u16 cfg; | |
c621b140 | 1321 | int no_piix_dma = 0; |
2e9edbf8 | 1322 | |
2dcb407e | 1323 | while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { |
c621b140 AC |
1324 | /* Look for 450NX PXB. Check for problem configurations |
1325 | A PCI quirk checks bit 6 already */ | |
c621b140 AC |
1326 | pci_read_config_word(pdev, 0x41, &cfg); |
1327 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 1328 | if (pdev->revision == 0x00) |
c621b140 AC |
1329 | no_piix_dma = 1; |
1330 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 1331 | else if (cfg & (1<<14) && pdev->revision < 5) |
c621b140 AC |
1332 | no_piix_dma = 2; |
1333 | } | |
31a34fe7 | 1334 | if (no_piix_dma) |
a44fec1f JP |
1335 | dev_warn(&ata_dev->dev, |
1336 | "450NX errata present, disabling IDE DMA%s\n", | |
1337 | no_piix_dma == 2 ? " - a BIOS update may resolve this" | |
1338 | : ""); | |
1339 | ||
c621b140 | 1340 | return no_piix_dma; |
2e9edbf8 | 1341 | } |
c621b140 | 1342 | |
8b09f0da | 1343 | static void __devinit piix_init_pcs(struct ata_host *host, |
ea35d29e JG |
1344 | const struct piix_map_db *map_db) |
1345 | { | |
8b09f0da | 1346 | struct pci_dev *pdev = to_pci_dev(host->dev); |
ea35d29e JG |
1347 | u16 pcs, new_pcs; |
1348 | ||
1349 | pci_read_config_word(pdev, ICH5_PCS, &pcs); | |
1350 | ||
1351 | new_pcs = pcs | map_db->port_enable; | |
1352 | ||
1353 | if (new_pcs != pcs) { | |
1354 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); | |
1355 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); | |
1356 | msleep(150); | |
1357 | } | |
1358 | } | |
1359 | ||
8b09f0da TH |
1360 | static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, |
1361 | struct ata_port_info *pinfo, | |
1362 | const struct piix_map_db *map_db) | |
d33f58b8 | 1363 | { |
b4482a4b | 1364 | const int *map; |
d33f58b8 TH |
1365 | int i, invalid_map = 0; |
1366 | u8 map_value; | |
1367 | ||
1368 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); | |
1369 | ||
1370 | map = map_db->map[map_value & map_db->mask]; | |
1371 | ||
a44fec1f | 1372 | dev_info(&pdev->dev, "MAP ["); |
d33f58b8 TH |
1373 | for (i = 0; i < 4; i++) { |
1374 | switch (map[i]) { | |
1375 | case RV: | |
1376 | invalid_map = 1; | |
a44fec1f | 1377 | pr_cont(" XX"); |
d33f58b8 TH |
1378 | break; |
1379 | ||
1380 | case NA: | |
a44fec1f | 1381 | pr_cont(" --"); |
d33f58b8 TH |
1382 | break; |
1383 | ||
1384 | case IDE: | |
1385 | WARN_ON((i & 1) || map[i + 1] != IDE); | |
669a5db4 | 1386 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
d33f58b8 | 1387 | i++; |
a44fec1f | 1388 | pr_cont(" IDE IDE"); |
d33f58b8 TH |
1389 | break; |
1390 | ||
1391 | default: | |
a44fec1f | 1392 | pr_cont(" P%d", map[i]); |
d33f58b8 | 1393 | if (i & 1) |
cca3974e | 1394 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
d33f58b8 TH |
1395 | break; |
1396 | } | |
1397 | } | |
a44fec1f | 1398 | pr_cont(" ]\n"); |
d33f58b8 TH |
1399 | |
1400 | if (invalid_map) | |
a44fec1f | 1401 | dev_err(&pdev->dev, "invalid MAP value %u\n", map_value); |
d33f58b8 | 1402 | |
8b09f0da | 1403 | return map; |
d33f58b8 TH |
1404 | } |
1405 | ||
e9c1670c TH |
1406 | static bool piix_no_sidpr(struct ata_host *host) |
1407 | { | |
1408 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1409 | ||
1410 | /* | |
1411 | * Samsung DB-P70 only has three ATA ports exposed and | |
1412 | * curiously the unconnected first port reports link online | |
1413 | * while not responding to SRST protocol causing excessive | |
1414 | * detection delay. | |
1415 | * | |
1416 | * Unfortunately, the system doesn't carry enough DMI | |
1417 | * information to identify the machine but does have subsystem | |
1418 | * vendor and device set. As it's unclear whether the | |
1419 | * subsystem vendor/device is used only for this specific | |
1420 | * board, the port can't be disabled solely with the | |
1421 | * information; however, turning off SIDPR access works around | |
1422 | * the problem. Turn it off. | |
1423 | * | |
1424 | * This problem is reported in bnc#441240. | |
1425 | * | |
1426 | * https://bugzilla.novell.com/show_bug.cgi?id=441420 | |
1427 | */ | |
1428 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && | |
1429 | pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && | |
1430 | pdev->subsystem_device == 0xb049) { | |
a44fec1f JP |
1431 | dev_warn(host->dev, |
1432 | "Samsung DB-P70 detected, disabling SIDPR\n"); | |
e9c1670c TH |
1433 | return true; |
1434 | } | |
1435 | ||
1436 | return false; | |
1437 | } | |
1438 | ||
be77e43a | 1439 | static int __devinit piix_init_sidpr(struct ata_host *host) |
c7290724 TH |
1440 | { |
1441 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1442 | struct piix_host_priv *hpriv = host->private_data; | |
be77e43a | 1443 | struct ata_link *link0 = &host->ports[0]->link; |
cb6716c8 | 1444 | u32 scontrol; |
be77e43a | 1445 | int i, rc; |
c7290724 TH |
1446 | |
1447 | /* check for availability */ | |
1448 | for (i = 0; i < 4; i++) | |
1449 | if (hpriv->map[i] == IDE) | |
be77e43a | 1450 | return 0; |
c7290724 | 1451 | |
e9c1670c TH |
1452 | /* is it blacklisted? */ |
1453 | if (piix_no_sidpr(host)) | |
1454 | return 0; | |
1455 | ||
c7290724 | 1456 | if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) |
be77e43a | 1457 | return 0; |
c7290724 TH |
1458 | |
1459 | if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || | |
1460 | pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) | |
be77e43a | 1461 | return 0; |
c7290724 TH |
1462 | |
1463 | if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) | |
be77e43a | 1464 | return 0; |
c7290724 TH |
1465 | |
1466 | hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; | |
cb6716c8 TH |
1467 | |
1468 | /* SCR access via SIDPR doesn't work on some configurations. | |
1469 | * Give it a test drive by inhibiting power save modes which | |
1470 | * we'll do anyway. | |
1471 | */ | |
be77e43a | 1472 | piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); |
cb6716c8 TH |
1473 | |
1474 | /* if IPM is already 3, SCR access is probably working. Don't | |
1475 | * un-inhibit power save modes as BIOS might have inhibited | |
1476 | * them for a reason. | |
1477 | */ | |
1478 | if ((scontrol & 0xf00) != 0x300) { | |
1479 | scontrol |= 0x300; | |
be77e43a TH |
1480 | piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); |
1481 | piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); | |
cb6716c8 TH |
1482 | |
1483 | if ((scontrol & 0xf00) != 0x300) { | |
a44fec1f JP |
1484 | dev_info(host->dev, |
1485 | "SCR access via SIDPR is available but doesn't work\n"); | |
be77e43a | 1486 | return 0; |
cb6716c8 TH |
1487 | } |
1488 | } | |
1489 | ||
be77e43a TH |
1490 | /* okay, SCRs available, set ops and ask libata for slave_link */ |
1491 | for (i = 0; i < 2; i++) { | |
1492 | struct ata_port *ap = host->ports[i]; | |
1493 | ||
1494 | ap->ops = &piix_sidpr_sata_ops; | |
1495 | ||
1496 | if (ap->flags & ATA_FLAG_SLAVE_POSS) { | |
1497 | rc = ata_slave_link_init(ap); | |
1498 | if (rc) | |
1499 | return rc; | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | return 0; | |
c7290724 TH |
1504 | } |
1505 | ||
2852bcf7 | 1506 | static void piix_iocfg_bit18_quirk(struct ata_host *host) |
43a98f05 | 1507 | { |
1855256c | 1508 | static const struct dmi_system_id sysids[] = { |
43a98f05 TH |
1509 | { |
1510 | /* Clevo M570U sets IOCFG bit 18 if the cdrom | |
1511 | * isn't used to boot the system which | |
1512 | * disables the channel. | |
1513 | */ | |
1514 | .ident = "M570U", | |
1515 | .matches = { | |
1516 | DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), | |
1517 | DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), | |
1518 | }, | |
1519 | }, | |
7d051548 JG |
1520 | |
1521 | { } /* terminate list */ | |
43a98f05 | 1522 | }; |
2852bcf7 TH |
1523 | struct pci_dev *pdev = to_pci_dev(host->dev); |
1524 | struct piix_host_priv *hpriv = host->private_data; | |
43a98f05 TH |
1525 | |
1526 | if (!dmi_check_system(sysids)) | |
1527 | return; | |
1528 | ||
1529 | /* The datasheet says that bit 18 is NOOP but certain systems | |
1530 | * seem to use it to disable a channel. Clear the bit on the | |
1531 | * affected systems. | |
1532 | */ | |
2852bcf7 | 1533 | if (hpriv->saved_iocfg & (1 << 18)) { |
a44fec1f | 1534 | dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n"); |
2852bcf7 TH |
1535 | pci_write_config_dword(pdev, PIIX_IOCFG, |
1536 | hpriv->saved_iocfg & ~(1 << 18)); | |
43a98f05 TH |
1537 | } |
1538 | } | |
1539 | ||
5f451fe1 RW |
1540 | static bool piix_broken_system_poweroff(struct pci_dev *pdev) |
1541 | { | |
1542 | static const struct dmi_system_id broken_systems[] = { | |
1543 | { | |
1544 | .ident = "HP Compaq 2510p", | |
1545 | .matches = { | |
1546 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1547 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), | |
1548 | }, | |
1549 | /* PCI slot number of the controller */ | |
1550 | .driver_data = (void *)0x1FUL, | |
1551 | }, | |
65e31643 VS |
1552 | { |
1553 | .ident = "HP Compaq nc6000", | |
1554 | .matches = { | |
1555 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1556 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"), | |
1557 | }, | |
1558 | /* PCI slot number of the controller */ | |
1559 | .driver_data = (void *)0x1FUL, | |
1560 | }, | |
5f451fe1 RW |
1561 | |
1562 | { } /* terminate list */ | |
1563 | }; | |
1564 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); | |
1565 | ||
1566 | if (dmi) { | |
1567 | unsigned long slot = (unsigned long)dmi->driver_data; | |
1568 | /* apply the quirk only to on-board controllers */ | |
1569 | return slot == PCI_SLOT(pdev->devfn); | |
1570 | } | |
1571 | ||
1572 | return false; | |
1573 | } | |
1574 | ||
1da177e4 LT |
1575 | /** |
1576 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
1577 | * @pdev: PCI device to register | |
1578 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
1579 | * | |
1580 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
1581 | * and then hand over control to libata, for it to do the rest. | |
1582 | * | |
1583 | * LOCKING: | |
1584 | * Inherited from PCI layer (may sleep). | |
1585 | * | |
1586 | * RETURNS: | |
1587 | * Zero on success, or -ERRNO value. | |
1588 | */ | |
1589 | ||
bc5468f5 AB |
1590 | static int __devinit piix_init_one(struct pci_dev *pdev, |
1591 | const struct pci_device_id *ent) | |
1da177e4 | 1592 | { |
24dc5f33 | 1593 | struct device *dev = &pdev->dev; |
d33f58b8 | 1594 | struct ata_port_info port_info[2]; |
1626aeb8 | 1595 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
a97c4006 | 1596 | struct scsi_host_template *sht = &piix_sht; |
cca3974e | 1597 | unsigned long port_flags; |
8b09f0da TH |
1598 | struct ata_host *host; |
1599 | struct piix_host_priv *hpriv; | |
1600 | int rc; | |
1da177e4 | 1601 | |
06296a1e | 1602 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1da177e4 | 1603 | |
347979a0 AC |
1604 | /* no hotplugging support for later devices (FIXME) */ |
1605 | if (!in_module_init && ent->driver_data >= ich5_sata) | |
1da177e4 LT |
1606 | return -ENODEV; |
1607 | ||
5f451fe1 RW |
1608 | if (piix_broken_system_poweroff(pdev)) { |
1609 | piix_port_info[ent->driver_data].flags |= | |
1610 | ATA_FLAG_NO_POWEROFF_SPINDOWN | | |
1611 | ATA_FLAG_NO_HIBERNATE_SPINDOWN; | |
1612 | dev_info(&pdev->dev, "quirky BIOS, skipping spindown " | |
1613 | "on poweroff and hibernation\n"); | |
1614 | } | |
1615 | ||
8b09f0da TH |
1616 | port_info[0] = piix_port_info[ent->driver_data]; |
1617 | port_info[1] = piix_port_info[ent->driver_data]; | |
1618 | ||
1619 | port_flags = port_info[0].flags; | |
1620 | ||
1621 | /* enable device and prepare host */ | |
1622 | rc = pcim_enable_device(pdev); | |
1623 | if (rc) | |
1624 | return rc; | |
1625 | ||
2852bcf7 TH |
1626 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1627 | if (!hpriv) | |
1628 | return -ENOMEM; | |
1629 | ||
1630 | /* Save IOCFG, this will be used for cable detection, quirk | |
1631 | * detection and restoration on detach. This is necessary | |
1632 | * because some ACPI implementations mess up cable related | |
1633 | * bits on _STM. Reported on kernel bz#11879. | |
1634 | */ | |
1635 | pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); | |
1636 | ||
5016d7d2 TH |
1637 | /* ICH6R may be driven by either ata_piix or ahci driver |
1638 | * regardless of BIOS configuration. Make sure AHCI mode is | |
1639 | * off. | |
1640 | */ | |
1641 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { | |
da3ceb22 | 1642 | rc = piix_disable_ahci(pdev); |
5016d7d2 TH |
1643 | if (rc) |
1644 | return rc; | |
1645 | } | |
1646 | ||
8b09f0da | 1647 | /* SATA map init can change port_info, do it before prepping host */ |
8b09f0da TH |
1648 | if (port_flags & ATA_FLAG_SATA) |
1649 | hpriv->map = piix_init_sata_map(pdev, port_info, | |
1650 | piix_map_db_table[ent->driver_data]); | |
1da177e4 | 1651 | |
1c5afdf7 | 1652 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); |
8b09f0da TH |
1653 | if (rc) |
1654 | return rc; | |
1655 | host->private_data = hpriv; | |
ff0fc146 | 1656 | |
8b09f0da | 1657 | /* initialize controller */ |
c7290724 | 1658 | if (port_flags & ATA_FLAG_SATA) { |
8b09f0da | 1659 | piix_init_pcs(host, piix_map_db_table[ent->driver_data]); |
be77e43a TH |
1660 | rc = piix_init_sidpr(host); |
1661 | if (rc) | |
1662 | return rc; | |
a97c4006 TH |
1663 | if (host->ports[0]->ops == &piix_sidpr_sata_ops) |
1664 | sht = &piix_sidpr_sht; | |
c7290724 | 1665 | } |
1da177e4 | 1666 | |
43a98f05 | 1667 | /* apply IOCFG bit18 quirk */ |
2852bcf7 | 1668 | piix_iocfg_bit18_quirk(host); |
43a98f05 | 1669 | |
1da177e4 LT |
1670 | /* On ICH5, some BIOSen disable the interrupt using the |
1671 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
1672 | * On ICH6, this bit has the same effect, but only when | |
1673 | * MSI is disabled (and it is disabled, as we don't use | |
1674 | * message-signalled interrupts currently). | |
1675 | */ | |
cca3974e | 1676 | if (port_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ff | 1677 | pci_intx(pdev, 1); |
1da177e4 | 1678 | |
c621b140 AC |
1679 | if (piix_check_450nx_errata(pdev)) { |
1680 | /* This writes into the master table but it does not | |
1681 | really matter for this errata as we will apply it to | |
1682 | all the PIIX devices on the board */ | |
8b09f0da TH |
1683 | host->ports[0]->mwdma_mask = 0; |
1684 | host->ports[0]->udma_mask = 0; | |
1685 | host->ports[1]->mwdma_mask = 0; | |
1686 | host->ports[1]->udma_mask = 0; | |
c621b140 | 1687 | } |
517d3cc1 | 1688 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
8b09f0da TH |
1689 | |
1690 | pci_set_master(pdev); | |
a97c4006 | 1691 | return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); |
1da177e4 LT |
1692 | } |
1693 | ||
2852bcf7 TH |
1694 | static void piix_remove_one(struct pci_dev *pdev) |
1695 | { | |
1696 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1697 | struct piix_host_priv *hpriv = host->private_data; | |
1698 | ||
1699 | pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); | |
1700 | ||
1701 | ata_pci_remove_one(pdev); | |
1702 | } | |
1703 | ||
1da177e4 LT |
1704 | static int __init piix_init(void) |
1705 | { | |
1706 | int rc; | |
1707 | ||
b7887196 PR |
1708 | DPRINTK("pci_register_driver\n"); |
1709 | rc = pci_register_driver(&piix_pci_driver); | |
1da177e4 LT |
1710 | if (rc) |
1711 | return rc; | |
1712 | ||
1713 | in_module_init = 0; | |
1714 | ||
1715 | DPRINTK("done\n"); | |
1716 | return 0; | |
1717 | } | |
1718 | ||
1da177e4 LT |
1719 | static void __exit piix_exit(void) |
1720 | { | |
1721 | pci_unregister_driver(&piix_pci_driver); | |
1722 | } | |
1723 | ||
1724 | module_init(piix_init); | |
1725 | module_exit(piix_exit); |