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ahci: Store interrupt value
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ata / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
b8b275ef 94#include <linux/dmi.h>
1da177e4
LT		 95
96#define DRV_NAME "ata_piix"
2a3103ce 97#define DRV_VERSION "2.12"
1da177e4
LT		 98
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 103 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 104
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 108
800b3996
TH		 109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 111
1da177e4
LT		 112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
1d076e5b 121 /* controller IDs */
d2cdfc0d 122 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
669a5db4
JG		 123 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
124 ich_pata_66 = 2, /* ICH up to 66 Mhz */
125 ich_pata_100 = 3, /* ICH up to UDMA 100 */
126 ich_pata_133 = 4, /* ICH up to UDMA 133 */
127 ich5_sata = 5,
5e56a37c
TH		 128 ich6_sata = 6,
129 ich6_sata_ahci = 7,
130 ich6m_sata_ahci = 8,
131 ich8_sata_ahci = 9,
d2cdfc0d 132 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
c5cf0ffa 133 tolapai_sata_ahci = 11,
85cd7251 134
d33f58b8
TH		 135 /* constants for mapping table */
136 P0 = 0, /* port 0 */
137 P1 = 1, /* port 1 */
138 P2 = 2, /* port 2 */
139 P3 = 3, /* port 3 */
140 IDE = -1, /* IDE */
141 NA = -2, /* not avaliable */
142 RV = -3, /* reserved */
143
7b6dbd68 144 PIIX_AHCI_DEVICE = 6,
b8b275ef
TH		 145
146 /* host->flags bits */
147 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
1da177e4
LT		 148};
149
d33f58b8
TH		 150struct piix_map_db {
151 const u32 mask;
73291a1c 152 const u16 port_enable;
d33f58b8
TH		 153 const int map[][4];
154};
155
d96715c1
TH		 156struct piix_host_priv {
157 const int *map;
158};
159
1da177e4
LT		 160static int piix_init_one (struct pci_dev *pdev,
161 const struct pci_device_id *ent);
ccc4672a 162static void piix_pata_error_handler(struct ata_port *ap);
669a5db4
JG		 163static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
164static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
165static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
eb4a2c7f 166static int ich_pata_cable_detect(struct ata_port *ap);
b8b275ef
TH		 167#ifdef CONFIG_PM
168static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
169static int piix_pci_device_resume(struct pci_dev *pdev);
170#endif
1da177e4
LT		 171
172static unsigned int in_module_init = 1;
173
3b7d697d 174static const struct pci_device_id piix_pci_tbl[] = {
d2cdfc0d
AC		 175 /* Intel PIIX3 for the 430HX etc */
176 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
669a5db4
JG		 177 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
178 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
179 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
669a5db4
JG		 180 /* Intel PIIX4 */
181 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 /* Intel PIIX4 */
183 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
184 /* Intel PIIX */
185 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
186 /* Intel ICH (i810, i815, i840) UDMA 66*/
187 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
188 /* Intel ICH0 : UDMA 33*/
189 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
190 /* Intel ICH2M */
191 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
193 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH3M */
195 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 /* Intel ICH3 (E7500/1) UDMA 100 */
197 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
199 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH5 */
202 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
203 /* C-ICH (i810E2) */
204 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 205 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 206 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* ICH6 (and 6) (i915) UDMA 100 */
208 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* ICH7/7-R (i945, i975) UDMA 100*/
210 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
211 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
c1e6f28c
CL		 212 /* ICH8 Mobile PATA Controller */
213 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 214
215 /* NOTE: The following PCI ids must be kept in sync with the
216 * list in drivers/pci/quirks.c.
217 */
218
1d076e5b 219 /* 82801EB (ICH5) */
1da177e4 220 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 221 /* 82801EB (ICH5) */
1da177e4 222 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 223 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 224 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 225 /* 6300ESB pretending RAID */
5e56a37c 226 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 227 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 228 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 229 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 230 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 231 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
232 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
233 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 234 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 235 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 236 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 237 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 238 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 239 /* SATA Controller 1 IDE (ICH8) */
08f12edc 240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 241 /* SATA Controller 2 IDE (ICH8) */
08f12edc 242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 243 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 244 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573
JG		 245 /* SATA Controller IDE (ICH9) */
246 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
247 /* SATA Controller IDE (ICH9) */
248 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
249 /* SATA Controller IDE (ICH9) */
250 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
251 /* SATA Controller IDE (ICH9M) */
252 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
253 /* SATA Controller IDE (ICH9M) */
254 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
255 /* SATA Controller IDE (ICH9M) */
256 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
c5cf0ffa
JG		 257 /* SATA Controller IDE (Tolapai) */
258 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
1da177e4
LT		 259
260 { } /* terminate list */
261};
262
263static struct pci_driver piix_pci_driver = {
264 .name = DRV_NAME,
265 .id_table = piix_pci_tbl,
266 .probe = piix_init_one,
267 .remove = ata_pci_remove_one,
438ac6d5 268#ifdef CONFIG_PM
b8b275ef
TH		 269 .suspend = piix_pci_device_suspend,
270 .resume = piix_pci_device_resume,
438ac6d5 271#endif
1da177e4
LT		 272};
273
193515d5 274static struct scsi_host_template piix_sht = {
1da177e4
LT		 275 .module = THIS_MODULE,
276 .name = DRV_NAME,
277 .ioctl = ata_scsi_ioctl,
278 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 279 .can_queue = ATA_DEF_QUEUE,
280 .this_id = ATA_SHT_THIS_ID,
281 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 282 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
283 .emulated = ATA_SHT_EMULATED,
284 .use_clustering = ATA_SHT_USE_CLUSTERING,
285 .proc_name = DRV_NAME,
286 .dma_boundary = ATA_DMA_BOUNDARY,
287 .slave_configure = ata_scsi_slave_config,
ccf68c34 288 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 289 .bios_param = ata_std_bios_param,
1da177e4
LT		 290};
291
057ace5e 292static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 293 .port_disable = ata_port_disable,
294 .set_piomode = piix_set_piomode,
295 .set_dmamode = piix_set_dmamode,
89bad589 296 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 297
298 .tf_load = ata_tf_load,
299 .tf_read = ata_tf_read,
300 .check_status = ata_check_status,
301 .exec_command = ata_exec_command,
302 .dev_select = ata_std_dev_select,
303
1da177e4
LT		 304 .bmdma_setup = ata_bmdma_setup,
305 .bmdma_start = ata_bmdma_start,
306 .bmdma_stop = ata_bmdma_stop,
307 .bmdma_status = ata_bmdma_status,
308 .qc_prep = ata_qc_prep,
309 .qc_issue = ata_qc_issue_prot,
0d5ff566 310 .data_xfer = ata_data_xfer,
1da177e4 311
3f037db0
TH		 312 .freeze = ata_bmdma_freeze,
313 .thaw = ata_bmdma_thaw,
ccc4672a 314 .error_handler = piix_pata_error_handler,
3f037db0 315 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 316 .cable_detect = ata_cable_40wire,
1da177e4
LT		 317
318 .irq_handler = ata_interrupt,
319 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 320 .irq_on = ata_irq_on,
321 .irq_ack = ata_irq_ack,
1da177e4
LT		 322
323 .port_start = ata_port_start,
1da177e4
LT		 324};
325
669a5db4
JG		 326static const struct ata_port_operations ich_pata_ops = {
327 .port_disable = ata_port_disable,
328 .set_piomode = piix_set_piomode,
329 .set_dmamode = ich_set_dmamode,
330 .mode_filter = ata_pci_default_filter,
331
332 .tf_load = ata_tf_load,
333 .tf_read = ata_tf_read,
334 .check_status = ata_check_status,
335 .exec_command = ata_exec_command,
336 .dev_select = ata_std_dev_select,
337
338 .bmdma_setup = ata_bmdma_setup,
339 .bmdma_start = ata_bmdma_start,
340 .bmdma_stop = ata_bmdma_stop,
341 .bmdma_status = ata_bmdma_status,
342 .qc_prep = ata_qc_prep,
343 .qc_issue = ata_qc_issue_prot,
0d5ff566 344 .data_xfer = ata_data_xfer,
669a5db4
JG		 345
346 .freeze = ata_bmdma_freeze,
347 .thaw = ata_bmdma_thaw,
eb4a2c7f 348 .error_handler = piix_pata_error_handler,
669a5db4 349 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 350 .cable_detect = ich_pata_cable_detect,
669a5db4
JG		 351
352 .irq_handler = ata_interrupt,
353 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 354 .irq_on = ata_irq_on,
355 .irq_ack = ata_irq_ack,
669a5db4
JG		 356
357 .port_start = ata_port_start,
669a5db4
JG		 358};
359
057ace5e 360static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 361 .port_disable = ata_port_disable,
362
363 .tf_load = ata_tf_load,
364 .tf_read = ata_tf_read,
365 .check_status = ata_check_status,
366 .exec_command = ata_exec_command,
367 .dev_select = ata_std_dev_select,
368
1da177e4
LT		 369 .bmdma_setup = ata_bmdma_setup,
370 .bmdma_start = ata_bmdma_start,
371 .bmdma_stop = ata_bmdma_stop,
372 .bmdma_status = ata_bmdma_status,
373 .qc_prep = ata_qc_prep,
374 .qc_issue = ata_qc_issue_prot,
0d5ff566 375 .data_xfer = ata_data_xfer,
1da177e4 376
3f037db0
TH		 377 .freeze = ata_bmdma_freeze,
378 .thaw = ata_bmdma_thaw,
2f91d81d 379 .error_handler = ata_bmdma_error_handler,
3f037db0 380 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 381
382 .irq_handler = ata_interrupt,
383 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 384 .irq_on = ata_irq_on,
385 .irq_ack = ata_irq_ack,
1da177e4
LT		 386
387 .port_start = ata_port_start,
1da177e4
LT		 388};
389
d96715c1 390static const struct piix_map_db ich5_map_db = {
d33f58b8 391 .mask = 0x7,
ea35d29e 392 .port_enable = 0x3,
d33f58b8
TH		 393 .map = {
394 /* PM PS SM SS MAP */
395 { P0, NA, P1, NA }, /* 000b */
396 { P1, NA, P0, NA }, /* 001b */
397 { RV, RV, RV, RV },
398 { RV, RV, RV, RV },
399 { P0, P1, IDE, IDE }, /* 100b */
400 { P1, P0, IDE, IDE }, /* 101b */
401 { IDE, IDE, P0, P1 }, /* 110b */
402 { IDE, IDE, P1, P0 }, /* 111b */
403 },
404};
405
d96715c1 406static const struct piix_map_db ich6_map_db = {
d33f58b8 407 .mask = 0x3,
ea35d29e 408 .port_enable = 0xf,
d33f58b8
TH		 409 .map = {
410 /* PM PS SM SS MAP */
79ea24e7 411 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 412 { IDE, IDE, P1, P3 }, /* 01b */
413 { P0, P2, IDE, IDE }, /* 10b */
414 { RV, RV, RV, RV },
415 },
416};
417
d96715c1 418static const struct piix_map_db ich6m_map_db = {
d33f58b8 419 .mask = 0x3,
ea35d29e 420 .port_enable = 0x5,
67083741
TH		 421
422 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 423 * it anyway. MAP 01b have been spotted on both ICH6M and
424 * ICH7M.
67083741
TH		 425 */
426 .map = {
427 /* PM PS SM SS MAP */
e04b3b9d 428 { P0, P2, NA, NA }, /* 00b */
67083741
TH		 429 { IDE, IDE, P1, P3 }, /* 01b */
430 { P0, P2, IDE, IDE }, /* 10b */
431 { RV, RV, RV, RV },
432 },
433};
434
08f12edc
JG		 435static const struct piix_map_db ich8_map_db = {
436 .mask = 0x3,
437 .port_enable = 0x3,
08f12edc
JG		 438 .map = {
439 /* PM PS SM SS MAP */
158f30c8 440 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 441 { RV, RV, RV, RV },
ac2b0437 442 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
08f12edc
JG		 443 { RV, RV, RV, RV },
444 },
445};
446
c5cf0ffa
JG		 447static const struct piix_map_db tolapai_map_db = {
448 .mask = 0x3,
449 .port_enable = 0x3,
450 .map = {
451 /* PM PS SM SS MAP */
452 { P0, NA, P1, NA }, /* 00b */
453 { RV, RV, RV, RV }, /* 01b */
454 { RV, RV, RV, RV }, /* 10b */
455 { RV, RV, RV, RV },
456 },
457};
458
d96715c1
TH		 459static const struct piix_map_db *piix_map_db_table[] = {
460 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 461 [ich6_sata] = &ich6_map_db,
462 [ich6_sata_ahci] = &ich6_map_db,
463 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 464 [ich8_sata_ahci] = &ich8_map_db,
c5cf0ffa 465 [tolapai_sata_ahci] = &tolapai_map_db,
d96715c1
TH		 466};
467
1da177e4 468static struct ata_port_info piix_port_info[] = {
d2cdfc0d 469 /* piix_pata_33: 0: PIIX4 at 33MHz */
1d076e5b
TH		 470 {
471 .sht = &piix_sht,
b3362f88 472 .flags = PIIX_PATA_FLAGS,
1d076e5b 473 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 474 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 475 .udma_mask = ATA_UDMA_MASK_40C,
476 .port_ops = &piix_pata_ops,
477 },
478
669a5db4
JG		 479 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
480 {
481 .sht = &piix_sht,
b3362f88 482 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 483 .pio_mask = 0x1f, /* pio 0-4 */
484 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
485 .udma_mask = ATA_UDMA2, /* UDMA33 */
486 .port_ops = &ich_pata_ops,
487 },
488 /* ich_pata_66: 2 ICH controllers up to 66MHz */
1da177e4
LT		 489 {
490 .sht = &piix_sht,
b3362f88 491 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 492 .pio_mask = 0x1f, /* pio 0-4 */
493 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
494 .udma_mask = ATA_UDMA4,
495 .port_ops = &ich_pata_ops,
496 },
85cd7251 497
669a5db4
JG		 498 /* ich_pata_100: 3 */
499 {
500 .sht = &piix_sht,
b3362f88 501 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 502 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 503 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 504 .udma_mask = ATA_UDMA5, /* udma0-5 */
505 .port_ops = &ich_pata_ops,
1da177e4
LT		 506 },
507
669a5db4
JG		 508 /* ich_pata_133: 4 ICH with full UDMA6 */
509 {
510 .sht = &piix_sht,
b3362f88 511 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
669a5db4
JG		 512 .pio_mask = 0x1f, /* pio 0-4 */
513 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
514 .udma_mask = ATA_UDMA6, /* UDMA133 */
515 .port_ops = &ich_pata_ops,
516 },
517
518 /* ich5_sata: 5 */
1da177e4
LT		 519 {
520 .sht = &piix_sht,
228c1590 521 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 522 .pio_mask = 0x1f, /* pio0-4 */
523 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 524 .udma_mask = ATA_UDMA6,
1da177e4
LT		 525 .port_ops = &piix_sata_ops,
526 },
527
5e56a37c 528 /* ich6_sata: 6 */
1da177e4
LT		 529 {
530 .sht = &piix_sht,
b3362f88 531 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 532 .pio_mask = 0x1f, /* pio0-4 */
533 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 534 .udma_mask = ATA_UDMA6,
1da177e4
LT		 535 .port_ops = &piix_sata_ops,
536 },
537
5e56a37c 538 /* ich6_sata_ahci: 7 */
c368ca4e
JG		 539 {
540 .sht = &piix_sht,
b3362f88 541 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 542 PIIX_FLAG_AHCI,
c368ca4e
JG		 543 .pio_mask = 0x1f, /* pio0-4 */
544 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 545 .udma_mask = ATA_UDMA6,
c368ca4e
JG		 546 .port_ops = &piix_sata_ops,
547 },
1d076e5b 548
5e56a37c 549 /* ich6m_sata_ahci: 8 */
1d076e5b
TH		 550 {
551 .sht = &piix_sht,
b3362f88 552 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 553 PIIX_FLAG_AHCI,
1d076e5b
TH		 554 .pio_mask = 0x1f, /* pio0-4 */
555 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 556 .udma_mask = ATA_UDMA6,
1d076e5b
TH		 557 .port_ops = &piix_sata_ops,
558 },
08f12edc 559
5e56a37c 560 /* ich8_sata_ahci: 9 */
08f12edc
JG		 561 {
562 .sht = &piix_sht,
b3362f88 563 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 564 PIIX_FLAG_AHCI,
565 .pio_mask = 0x1f, /* pio0-4 */
566 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 567 .udma_mask = ATA_UDMA6,
08f12edc
JG		 568 .port_ops = &piix_sata_ops,
569 },
669a5db4 570
d2cdfc0d
AC		 571 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
572 {
573 .sht = &piix_sht,
574 .flags = PIIX_PATA_FLAGS,
575 .pio_mask = 0x1f, /* pio0-4 */
576 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
577 .port_ops = &piix_pata_ops,
578 },
c5cf0ffa
JG		 579
580 /* tolapai_sata_ahci: 11: */
581 {
582 .sht = &piix_sht,
583 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
584 PIIX_FLAG_AHCI,
585 .pio_mask = 0x1f, /* pio0-4 */
586 .mwdma_mask = 0x07, /* mwdma0-2 */
587 .udma_mask = ATA_UDMA6,
588 .port_ops = &piix_sata_ops,
589 },
1da177e4
LT		 590};
591
592static struct pci_bits piix_enable_bits[] = {
593 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
594 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
595};
596
597MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
598MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
599MODULE_LICENSE("GPL");
600MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
601MODULE_VERSION(DRV_VERSION);
602
fc085150
AC		 603struct ich_laptop {
604 u16 device;
605 u16 subvendor;
606 u16 subdevice;
607};
608
609/*
610 * List of laptops that use short cables rather than 80 wire
611 */
612
613static const struct ich_laptop ich_laptop[] = {
614 /* devid, subvendor, subdev */
615 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
babfb682 616 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
12340106 617 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
b33620f9 618 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
fc085150
AC		 619 /* end marker */
620 { 0, }
621};
622
1da177e4 623/**
eb4a2c7f 624 * ich_pata_cable_detect - Probe host controller cable detect info
1da177e4
LT		 625 * @ap: Port for which cable detect info is desired
626 *
627 * Read 80c cable indicator from ATA PCI device's PCI config
628 * register. This register is normally set by firmware (BIOS).
629 *
630 * LOCKING:
631 * None (inherited from caller).
632 */
669a5db4 633
eb4a2c7f 634static int ich_pata_cable_detect(struct ata_port *ap)
1da177e4 635{
cca3974e 636 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 637 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 638 u8 tmp, mask;
639
fc085150
AC		 640 /* Check for specials - Acer Aspire 5602WLMi */
641 while (lap->device) {
642 if (lap->device == pdev->device &&
643 lap->subvendor == pdev->subsystem_vendor &&
644 lap->subdevice == pdev->subsystem_device) {
eb4a2c7f 645 return ATA_CBL_PATA40_SHORT;
fc085150
AC		 646 }
647 lap++;
648 }
649
1da177e4 650 /* check BIOS cable detect results */
2a88d1ac 651 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 652 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
653 if ((tmp & mask) == 0)
eb4a2c7f
AC		 654 return ATA_CBL_PATA40;
655 return ATA_CBL_PATA80;
1da177e4
LT		 656}
657
658/**
ccc4672a 659 * piix_pata_prereset - prereset for PATA host controller
cc0680a5 660 * @link: Target link
d4b2bab4 661 * @deadline: deadline jiffies for the operation
1da177e4 662 *
573db6b8
TH		 663 * LOCKING:
664 * None (inherited from caller).
665 */
cc0680a5 666static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
1da177e4 667{
cc0680a5 668 struct ata_port *ap = link->ap;
cca3974e 669 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 670
c961922b
AC		 671 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
672 return -ENOENT;
cc0680a5 673 return ata_std_prereset(link, deadline);
ccc4672a
TH		 674}
675
676static void piix_pata_error_handler(struct ata_port *ap)
677{
678 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
679 ata_std_postreset);
1da177e4
LT		 680}
681
1da177e4
LT		 682/**
683 * piix_set_piomode - Initialize host controller PATA PIO timings
684 * @ap: Port whose timings we are configuring
685 * @adev: um
1da177e4
LT		 686 *
687 * Set PIO mode for device, in host controller PCI config space.
688 *
689 * LOCKING:
690 * None (inherited from caller).
691 */
692
693static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
694{
695 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 696 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 697 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 698 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 699 unsigned int slave_port = 0x44;
700 u16 master_data;
701 u8 slave_data;
669a5db4
JG		 702 u8 udma_enable;
703 int control = 0;
85cd7251 704
669a5db4
JG		 705 /*
706 * See Intel Document 298600-004 for the timing programing rules
707 * for ICH controllers.
708 */
1da177e4
LT		 709
710 static const /* ISP RTC */
711 u8 timings[][2] = { { 0, 0 },
712 { 0, 0 },
713 { 1, 0 },
714 { 2, 1 },
715 { 2, 3 }, };
716
669a5db4
JG		 717 if (pio >= 2)
718 control |= 1; /* TIME1 enable */
719 if (ata_pio_need_iordy(adev))
720 control |= 2; /* IE enable */
721
85cd7251 722 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 723 if (adev->class == ATA_DEV_ATA)
724 control |= 4; /* PPE enable */
725
a5bf5f5a
TH		 726 /* PIO configuration clears DTE unconditionally. It will be
727 * programmed in set_dmamode which is guaranteed to be called
728 * after set_piomode if any DMA mode is available.
729 */
1da177e4
LT		 730 pci_read_config_word(dev, master_port, &master_data);
731 if (is_slave) {
a5bf5f5a
TH		 732 /* clear TIME1|IE1|PPE1|DTE1 */
733 master_data &= 0xff0f;
669a5db4 734 /* Enable SITRE (seperate slave timing register) */
1da177e4 735 master_data |= 0x4000;
669a5db4
JG		 736 /* enable PPE1, IE1 and TIME1 as needed */
737 master_data |= (control << 4);
1da177e4 738 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 739 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4 740 /* Load the timing nibble for this slave */
a5bf5f5a
TH		 741 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
742 << (ap->port_no ? 4 : 0);
1da177e4 743 } else {
a5bf5f5a
TH		 744 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
745 master_data &= 0xccf0;
669a5db4
JG		 746 /* Enable PPE, IE and TIME as appropriate */
747 master_data |= control;
a5bf5f5a 748 /* load ISP and RCT */
1da177e4
LT		 749 master_data |=
750 (timings[pio][0] << 12) |
751 (timings[pio][1] << 8);
752 }
753 pci_write_config_word(dev, master_port, master_data);
754 if (is_slave)
755 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 756
757 /* Ensure the UDMA bit is off - it will be turned back on if
758 UDMA is selected */
85cd7251 759
669a5db4
JG		 760 if (ap->udma_mask) {
761 pci_read_config_byte(dev, 0x48, &udma_enable);
762 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
763 pci_write_config_byte(dev, 0x48, udma_enable);
764 }
1da177e4
LT		 765}
766
767/**
669a5db4 768 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 769 * @ap: Port whose timings we are configuring
669a5db4 770 * @adev: Drive in question
1da177e4 771 * @udma: udma mode, 0 - 6
c32a8fd7 772 * @isich: set if the chip is an ICH device
1da177e4
LT		 773 *
774 * Set UDMA mode for device, in host controller PCI config space.
775 *
776 * LOCKING:
777 * None (inherited from caller).
778 */
779
669a5db4 780static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 781{
cca3974e 782 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 783 u8 master_port = ap->port_no ? 0x42 : 0x40;
784 u16 master_data;
785 u8 speed = adev->dma_mode;
786 int devid = adev->devno + 2 * ap->port_no;
dedf61db 787 u8 udma_enable = 0;
85cd7251 788
669a5db4
JG		 789 static const /* ISP RTC */
790 u8 timings[][2] = { { 0, 0 },
791 { 0, 0 },
792 { 1, 0 },
793 { 2, 1 },
794 { 2, 3 }, };
795
796 pci_read_config_word(dev, master_port, &master_data);
d2cdfc0d
AC		 797 if (ap->udma_mask)
798 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 799
800 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 801 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
802 u16 udma_timing;
803 u16 ideconf;
804 int u_clock, u_speed;
85cd7251 805
669a5db4
JG		 806 /*
807 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 808 * selection of dividers
809 *
669a5db4 810 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 811 * except UDMA0 which is 00
669a5db4
JG		 812 */
813 u_speed = min(2 - (udma & 1), udma);
814 if (udma == 5)
815 u_clock = 0x1000; /* 100Mhz */
816 else if (udma > 2)
817 u_clock = 1; /* 66Mhz */
818 else
819 u_clock = 0; /* 33Mhz */
85cd7251 820
669a5db4 821 udma_enable |= (1 << devid);
85cd7251 822
669a5db4
JG		 823 /* Load the CT/RP selection */
824 pci_read_config_word(dev, 0x4A, &udma_timing);
825 udma_timing &= ~(3 << (4 * devid));
826 udma_timing |= u_speed << (4 * devid);
827 pci_write_config_word(dev, 0x4A, udma_timing);
828
85cd7251 829 if (isich) {
669a5db4
JG		 830 /* Select a 33/66/100Mhz clock */
831 pci_read_config_word(dev, 0x54, &ideconf);
832 ideconf &= ~(0x1001 << devid);
833 ideconf |= u_clock << devid;
834 /* For ICH or later we should set bit 10 for better
835 performance (WR_PingPong_En) */
836 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 837 }
1da177e4 838 } else {
669a5db4
JG		 839 /*
840 * MWDMA is driven by the PIO timings. We must also enable
841 * IORDY unconditionally along with TIME1. PPE has already
842 * been set when the PIO timing was set.
843 */
844 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
845 unsigned int control;
846 u8 slave_data;
847 const unsigned int needed_pio[3] = {
848 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
849 };
850 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 851
669a5db4 852 control = 3; /* IORDY|TIME1 */
85cd7251 853
669a5db4
JG		 854 /* If the drive MWDMA is faster than it can do PIO then
855 we must force PIO into PIO0 */
85cd7251 856
669a5db4
JG		 857 if (adev->pio_mode < needed_pio[mwdma])
858 /* Enable DMA timing only */
859 control |= 8; /* PIO cycles in PIO0 */
860
861 if (adev->devno) { /* Slave */
862 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
863 master_data |= control << 4;
864 pci_read_config_byte(dev, 0x44, &slave_data);
a5bf5f5a 865 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 866 /* Load the matching timing */
867 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
868 pci_write_config_byte(dev, 0x44, slave_data);
869 } else { /* Master */
85cd7251 870 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 871 and master timing bits */
872 master_data |= control;
873 master_data |=
874 (timings[pio][0] << 12) |
875 (timings[pio][1] << 8);
876 }
a5bf5f5a
TH		 877
878 if (ap->udma_mask) {
879 udma_enable &= ~(1 << devid);
880 pci_write_config_word(dev, master_port, master_data);
881 }
1da177e4 882 }
669a5db4
JG		 883 /* Don't scribble on 0x48 if the controller does not support UDMA */
884 if (ap->udma_mask)
885 pci_write_config_byte(dev, 0x48, udma_enable);
886}
887
888/**
889 * piix_set_dmamode - Initialize host controller PATA DMA timings
890 * @ap: Port whose timings we are configuring
891 * @adev: um
892 *
893 * Set MW/UDMA mode for device, in host controller PCI config space.
894 *
895 * LOCKING:
896 * None (inherited from caller).
897 */
898
899static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
900{
901 do_pata_set_dmamode(ap, adev, 0);
902}
903
904/**
905 * ich_set_dmamode - Initialize host controller PATA DMA timings
906 * @ap: Port whose timings we are configuring
907 * @adev: um
908 *
909 * Set MW/UDMA mode for device, in host controller PCI config space.
910 *
911 * LOCKING:
912 * None (inherited from caller).
913 */
914
915static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
916{
917 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 918}
919
b8b275ef 920#ifdef CONFIG_PM
8c3832eb
TH		 921static int piix_broken_suspend(void)
922{
1855256c 923 static const struct dmi_system_id sysids[] = {
4c74d4ec
TH		 924 {
925 .ident = "TECRA M3",
926 .matches = {
927 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
928 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
929 },
930 },
8c3832eb
TH		 931 {
932 .ident = "TECRA M5",
933 .matches = {
934 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
935 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
936 },
b8b275ef 937 },
5c08ea01
TH		 938 {
939 .ident = "TECRA M7",
940 .matches = {
941 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
942 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
943 },
944 },
3cc0b9d3
TH		 945 {
946 .ident = "Satellite U200",
947 .matches = {
948 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
949 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
950 },
951 },
8c3832eb
TH		 952 {
953 .ident = "Satellite U205",
954 .matches = {
955 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
956 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
957 },
b8b275ef 958 },
8c3832eb
TH		 959 {
960 .ident = "Portege M500",
961 .matches = {
962 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
963 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
964 },
b8b275ef 965 },
7d051548
JG		 966
967 { } /* terminate list */
8c3832eb 968 };
7abe79c3
TH		 969 static const char *oemstrs[] = {
970 "Tecra M3,",
971 };
972 int i;
8c3832eb
TH		 973
974 if (dmi_check_system(sysids))
975 return 1;
976
7abe79c3
TH		 977 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
978 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
979 return 1;
980
8c3832eb
TH		 981 return 0;
982}
b8b275ef
TH		 983
984static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
985{
986 struct ata_host *host = dev_get_drvdata(&pdev->dev);
987 unsigned long flags;
988 int rc = 0;
989
990 rc = ata_host_suspend(host, mesg);
991 if (rc)
992 return rc;
993
994 /* Some braindamaged ACPI suspend implementations expect the
995 * controller to be awake on entry; otherwise, it burns cpu
996 * cycles and power trying to do something to the sleeping
997 * beauty.
998 */
8c3832eb 999 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
b8b275ef
TH		 1000 pci_save_state(pdev);
1001
1002 /* mark its power state as "unknown", since we don't
1003 * know if e.g. the BIOS will change its device state
1004 * when we suspend.
1005 */
1006 if (pdev->current_state == PCI_D0)
1007 pdev->current_state = PCI_UNKNOWN;
1008
1009 /* tell resume that it's waking up from broken suspend */
1010 spin_lock_irqsave(&host->lock, flags);
1011 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1012 spin_unlock_irqrestore(&host->lock, flags);
1013 } else
1014 ata_pci_device_do_suspend(pdev, mesg);
1015
1016 return 0;
1017}
1018
1019static int piix_pci_device_resume(struct pci_dev *pdev)
1020{
1021 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1022 unsigned long flags;
1023 int rc;
1024
1025 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1026 spin_lock_irqsave(&host->lock, flags);
1027 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1028 spin_unlock_irqrestore(&host->lock, flags);
1029
1030 pci_set_power_state(pdev, PCI_D0);
1031 pci_restore_state(pdev);
1032
1033 /* PCI device wasn't disabled during suspend. Use
0b62e13b
TH		 1034 * pci_reenable_device() to avoid affecting the enable
1035 * count.
b8b275ef 1036 */
0b62e13b 1037 rc = pci_reenable_device(pdev);
b8b275ef
TH		 1038 if (rc)
1039 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1040 "device after resume (%d)\n", rc);
1041 } else
1042 rc = ata_pci_device_do_resume(pdev);
1043
1044 if (rc == 0)
1045 ata_host_resume(host);
1046
1047 return rc;
1048}
1049#endif
1050
1da177e4
LT		 1051#define AHCI_PCI_BAR 5
1052#define AHCI_GLOBAL_CTL 0x04
1053#define AHCI_ENABLE (1 << 31)
1054static int piix_disable_ahci(struct pci_dev *pdev)
1055{
ea6ba10b 1056 void __iomem *mmio;
1da177e4
LT		 1057 u32 tmp;
1058 int rc = 0;
1059
1060 /* BUG: pci_enable_device has not yet been called. This
1061 * works because this device is usually set up by BIOS.
1062 */
1063
374b1873
JG		 1064 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1065 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 1066 return 0;
7b6dbd68 1067
374b1873 1068 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 1069 if (!mmio)
1070 return -ENOMEM;
7b6dbd68 1071
1da177e4
LT		 1072 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1073 if (tmp & AHCI_ENABLE) {
1074 tmp &= ~AHCI_ENABLE;
1075 writel(tmp, mmio + AHCI_GLOBAL_CTL);
1076
1077 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1078 if (tmp & AHCI_ENABLE)
1079 rc = -EIO;
1080 }
7b6dbd68 1081
374b1873 1082 pci_iounmap(pdev, mmio);
1da177e4
LT		 1083 return rc;
1084}
1085
c621b140
AC		 1086/**
1087 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 1088 * @ata_dev: the PCI device to check
2e9edbf8 1089 *
c621b140
AC		 1090 * Check for the present of 450NX errata #19 and errata #25. If
1091 * they are found return an error code so we can turn off DMA
1092 */
1093
1094static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1095{
1096 struct pci_dev *pdev = NULL;
1097 u16 cfg;
c621b140 1098 int no_piix_dma = 0;
2e9edbf8 1099
c621b140
AC		 1100 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
1101 {
1102 /* Look for 450NX PXB. Check for problem configurations
1103 A PCI quirk checks bit 6 already */
c621b140
AC		 1104 pci_read_config_word(pdev, 0x41, &cfg);
1105 /* Only on the original revision: IDE DMA can hang */
44c10138 1106 if (pdev->revision == 0x00)
c621b140
AC		 1107 no_piix_dma = 1;
1108 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138 1109 else if (cfg & (1<<14) && pdev->revision < 5)
c621b140
AC		 1110 no_piix_dma = 2;
1111 }
31a34fe7 1112 if (no_piix_dma)
c621b140 1113 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 1114 if (no_piix_dma == 2)
c621b140
AC		 1115 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1116 return no_piix_dma;
2e9edbf8 1117}
c621b140 1118
ea35d29e 1119static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 1120 struct ata_port_info *pinfo,
ea35d29e
JG		 1121 const struct piix_map_db *map_db)
1122{
1123 u16 pcs, new_pcs;
1124
1125 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1126
1127 new_pcs = pcs | map_db->port_enable;
1128
1129 if (new_pcs != pcs) {
1130 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1131 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1132 msleep(150);
1133 }
1134}
1135
d33f58b8 1136static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 1137 struct ata_port_info *pinfo,
1138 const struct piix_map_db *map_db)
d33f58b8 1139{
d96715c1 1140 struct piix_host_priv *hpriv = pinfo[0].private_data;
d33f58b8
TH		 1141 const unsigned int *map;
1142 int i, invalid_map = 0;
1143 u8 map_value;
1144
1145 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1146
1147 map = map_db->map[map_value & map_db->mask];
1148
1149 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1150 for (i = 0; i < 4; i++) {
1151 switch (map[i]) {
1152 case RV:
1153 invalid_map = 1;
1154 printk(" XX");
1155 break;
1156
1157 case NA:
1158 printk(" --");
1159 break;
1160
1161 case IDE:
1162 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1163 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1164 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1165 i++;
1166 printk(" IDE IDE");
1167 break;
1168
1169 default:
1170 printk(" P%d", map[i]);
1171 if (i & 1)
cca3974e 1172 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1173 break;
1174 }
1175 }
1176 printk(" ]\n");
1177
1178 if (invalid_map)
1179 dev_printk(KERN_ERR, &pdev->dev,
1180 "invalid MAP value %u\n", map_value);
1181
d96715c1 1182 hpriv->map = map;
d33f58b8
TH		 1183}
1184
43a98f05
TH		 1185static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1186{
1855256c 1187 static const struct dmi_system_id sysids[] = {
43a98f05
TH		 1188 {
1189 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1190 * isn't used to boot the system which
1191 * disables the channel.
1192 */
1193 .ident = "M570U",
1194 .matches = {
1195 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1196 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1197 },
1198 },
7d051548
JG		 1199
1200 { } /* terminate list */
43a98f05
TH		 1201 };
1202 u32 iocfg;
1203
1204 if (!dmi_check_system(sysids))
1205 return;
1206
1207 /* The datasheet says that bit 18 is NOOP but certain systems
1208 * seem to use it to disable a channel. Clear the bit on the
1209 * affected systems.
1210 */
1211 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1212 if (iocfg & (1 << 18)) {
1213 dev_printk(KERN_INFO, &pdev->dev,
1214 "applying IOCFG bit18 quirk\n");
1215 iocfg &= ~(1 << 18);
1216 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1217 }
1218}
1219
1da177e4
LT		 1220/**
1221 * piix_init_one - Register PIIX ATA PCI device with kernel services
1222 * @pdev: PCI device to register
1223 * @ent: Entry in piix_pci_tbl matching with @pdev
1224 *
1225 * Called from kernel PCI layer. We probe for combined mode (sigh),
1226 * and then hand over control to libata, for it to do the rest.
1227 *
1228 * LOCKING:
1229 * Inherited from PCI layer (may sleep).
1230 *
1231 * RETURNS:
1232 * Zero on success, or -ERRNO value.
1233 */
1234
1235static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1236{
1237 static int printed_version;
24dc5f33 1238 struct device *dev = &pdev->dev;
d33f58b8 1239 struct ata_port_info port_info[2];
1626aeb8 1240 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
d96715c1 1241 struct piix_host_priv *hpriv;
cca3974e 1242 unsigned long port_flags;
1da177e4
LT		 1243
1244 if (!printed_version++)
6248e647
JG		 1245 dev_printk(KERN_DEBUG, &pdev->dev,
1246 "version " DRV_VERSION "\n");
1da177e4
LT		 1247
1248 /* no hotplugging support (FIXME) */
1249 if (!in_module_init)
1250 return -ENODEV;
1251
24dc5f33 1252 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
d96715c1
TH		 1253 if (!hpriv)
1254 return -ENOMEM;
1255
d33f58b8
TH		 1256 port_info[0] = piix_port_info[ent->driver_data];
1257 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1258 port_info[0].private_data = hpriv;
1259 port_info[1].private_data = hpriv;
1da177e4 1260
cca3974e 1261 port_flags = port_info[0].flags;
ff0fc146 1262
cca3974e 1263 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1264 u8 tmp;
1265 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1266 if (tmp == PIIX_AHCI_DEVICE) {
1267 int rc = piix_disable_ahci(pdev);
1268 if (rc)
1269 return rc;
1270 }
1da177e4
LT		 1271 }
1272
d33f58b8 1273 /* Initialize SATA map */
cca3974e 1274 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1275 piix_init_sata_map(pdev, port_info,
1276 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1277 piix_init_pcs(pdev, port_info,
1278 piix_map_db_table[ent->driver_data]);
ea35d29e 1279 }
1da177e4 1280
43a98f05
TH		 1281 /* apply IOCFG bit18 quirk */
1282 piix_iocfg_bit18_quirk(pdev);
1283
1da177e4
LT		 1284 /* On ICH5, some BIOSen disable the interrupt using the
1285 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1286 * On ICH6, this bit has the same effect, but only when
1287 * MSI is disabled (and it is disabled, as we don't use
1288 * message-signalled interrupts currently).
1289 */
cca3974e 1290 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1291 pci_intx(pdev, 1);
1da177e4 1292
c621b140
AC		 1293 if (piix_check_450nx_errata(pdev)) {
1294 /* This writes into the master table but it does not
1295 really matter for this errata as we will apply it to
1296 all the PIIX devices on the board */
d33f58b8
TH		 1297 port_info[0].mwdma_mask = 0;
1298 port_info[0].udma_mask = 0;
1299 port_info[1].mwdma_mask = 0;
1300 port_info[1].udma_mask = 0;
c621b140 1301 }
1626aeb8 1302 return ata_pci_init_one(pdev, ppi);
1da177e4
LT		 1303}
1304
1da177e4
LT		 1305static int __init piix_init(void)
1306{
1307 int rc;
1308
b7887196
PR		 1309 DPRINTK("pci_register_driver\n");
1310 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1311 if (rc)
1312 return rc;
1313
1314 in_module_init = 0;
1315
1316 DPRINTK("done\n");
1317 return 0;
1318}
1319
1da177e4
LT		 1320static void __exit piix_exit(void)
1321{
1322 pci_unregister_driver(&piix_pci_driver);
1323}
1324
1325module_init(piix_init);
1326module_exit(piix_exit);