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AVR32 PATA driver
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / ata / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
b8b275ef 94#include <linux/dmi.h>
1da177e4
LT		 95
96#define DRV_NAME "ata_piix"
2a3103ce 97#define DRV_VERSION "2.12"
1da177e4
LT		 98
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 103 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 104
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 108
800b3996
TH		 109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 111
1da177e4
LT		 112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
1d076e5b 121 /* controller IDs */
d2cdfc0d 122 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
669a5db4
JG		 123 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
124 ich_pata_66 = 2, /* ICH up to 66 Mhz */
125 ich_pata_100 = 3, /* ICH up to UDMA 100 */
2eb829e9 126 /* ICH up to UDMA 133 is not supported */
669a5db4 127 ich5_sata = 5,
5e56a37c
TH		 128 ich6_sata = 6,
129 ich6_sata_ahci = 7,
130 ich6m_sata_ahci = 8,
131 ich8_sata_ahci = 9,
d2cdfc0d 132 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
c5cf0ffa 133 tolapai_sata_ahci = 11,
85cd7251 134
d33f58b8
TH		 135 /* constants for mapping table */
136 P0 = 0, /* port 0 */
137 P1 = 1, /* port 1 */
138 P2 = 2, /* port 2 */
139 P3 = 3, /* port 3 */
140 IDE = -1, /* IDE */
141 NA = -2, /* not avaliable */
142 RV = -3, /* reserved */
143
7b6dbd68 144 PIIX_AHCI_DEVICE = 6,
b8b275ef
TH		 145
146 /* host->flags bits */
147 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
1da177e4
LT		 148};
149
d33f58b8
TH		 150struct piix_map_db {
151 const u32 mask;
73291a1c 152 const u16 port_enable;
d33f58b8
TH		 153 const int map[][4];
154};
155
d96715c1
TH		 156struct piix_host_priv {
157 const int *map;
158};
159
1da177e4
LT		 160static int piix_init_one (struct pci_dev *pdev,
161 const struct pci_device_id *ent);
ccc4672a 162static void piix_pata_error_handler(struct ata_port *ap);
669a5db4
JG		 163static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
164static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
165static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
eb4a2c7f 166static int ich_pata_cable_detect(struct ata_port *ap);
b8b275ef
TH		 167#ifdef CONFIG_PM
168static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
169static int piix_pci_device_resume(struct pci_dev *pdev);
170#endif
1da177e4
LT		 171
172static unsigned int in_module_init = 1;
173
3b7d697d 174static const struct pci_device_id piix_pci_tbl[] = {
d2cdfc0d
AC		 175 /* Intel PIIX3 for the 430HX etc */
176 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
669a5db4
JG		 177 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
178 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
179 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
669a5db4
JG		 180 /* Intel PIIX4 */
181 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 /* Intel PIIX4 */
183 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
184 /* Intel PIIX */
185 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
186 /* Intel ICH (i810, i815, i840) UDMA 66*/
187 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
188 /* Intel ICH0 : UDMA 33*/
189 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
190 /* Intel ICH2M */
191 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
193 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH3M */
195 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 /* Intel ICH3 (E7500/1) UDMA 100 */
197 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
199 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH5 */
2eb829e9 202 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4
JG		 203 /* C-ICH (i810E2) */
204 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 205 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 206 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* ICH6 (and 6) (i915) UDMA 100 */
208 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* ICH7/7-R (i945, i975) UDMA 100*/
2eb829e9 210 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4 211 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
c1e6f28c
CL		 212 /* ICH8 Mobile PATA Controller */
213 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 214
215 /* NOTE: The following PCI ids must be kept in sync with the
216 * list in drivers/pci/quirks.c.
217 */
218
1d076e5b 219 /* 82801EB (ICH5) */
1da177e4 220 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 221 /* 82801EB (ICH5) */
1da177e4 222 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 223 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 224 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 225 /* 6300ESB pretending RAID */
5e56a37c 226 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 227 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 228 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 229 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 230 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 231 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
232 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
233 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 234 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 235 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 236 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 237 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 238 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 239 /* SATA Controller 1 IDE (ICH8) */
08f12edc 240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 241 /* SATA Controller 2 IDE (ICH8) */
08f12edc 242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 243 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 244 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573
JG		 245 /* SATA Controller IDE (ICH9) */
246 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
247 /* SATA Controller IDE (ICH9) */
248 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
249 /* SATA Controller IDE (ICH9) */
250 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
251 /* SATA Controller IDE (ICH9M) */
252 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
253 /* SATA Controller IDE (ICH9M) */
254 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
255 /* SATA Controller IDE (ICH9M) */
256 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
c5cf0ffa
JG		 257 /* SATA Controller IDE (Tolapai) */
258 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
1da177e4
LT		 259
260 { } /* terminate list */
261};
262
263static struct pci_driver piix_pci_driver = {
264 .name = DRV_NAME,
265 .id_table = piix_pci_tbl,
266 .probe = piix_init_one,
267 .remove = ata_pci_remove_one,
438ac6d5 268#ifdef CONFIG_PM
b8b275ef
TH		 269 .suspend = piix_pci_device_suspend,
270 .resume = piix_pci_device_resume,
438ac6d5 271#endif
1da177e4
LT		 272};
273
193515d5 274static struct scsi_host_template piix_sht = {
1da177e4
LT		 275 .module = THIS_MODULE,
276 .name = DRV_NAME,
277 .ioctl = ata_scsi_ioctl,
278 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 279 .can_queue = ATA_DEF_QUEUE,
280 .this_id = ATA_SHT_THIS_ID,
281 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 282 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
283 .emulated = ATA_SHT_EMULATED,
284 .use_clustering = ATA_SHT_USE_CLUSTERING,
285 .proc_name = DRV_NAME,
286 .dma_boundary = ATA_DMA_BOUNDARY,
287 .slave_configure = ata_scsi_slave_config,
ccf68c34 288 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 289 .bios_param = ata_std_bios_param,
1da177e4
LT		 290};
291
057ace5e 292static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 293 .set_piomode = piix_set_piomode,
294 .set_dmamode = piix_set_dmamode,
89bad589 295 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 296
297 .tf_load = ata_tf_load,
298 .tf_read = ata_tf_read,
299 .check_status = ata_check_status,
300 .exec_command = ata_exec_command,
301 .dev_select = ata_std_dev_select,
302
1da177e4
LT		 303 .bmdma_setup = ata_bmdma_setup,
304 .bmdma_start = ata_bmdma_start,
305 .bmdma_stop = ata_bmdma_stop,
306 .bmdma_status = ata_bmdma_status,
307 .qc_prep = ata_qc_prep,
308 .qc_issue = ata_qc_issue_prot,
0d5ff566 309 .data_xfer = ata_data_xfer,
1da177e4 310
3f037db0
TH		 311 .freeze = ata_bmdma_freeze,
312 .thaw = ata_bmdma_thaw,
ccc4672a 313 .error_handler = piix_pata_error_handler,
3f037db0 314 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 315 .cable_detect = ata_cable_40wire,
1da177e4
LT		 316
317 .irq_handler = ata_interrupt,
318 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 319 .irq_on = ata_irq_on,
1da177e4
LT		 320
321 .port_start = ata_port_start,
1da177e4
LT		 322};
323
669a5db4 324static const struct ata_port_operations ich_pata_ops = {
669a5db4
JG		 325 .set_piomode = piix_set_piomode,
326 .set_dmamode = ich_set_dmamode,
327 .mode_filter = ata_pci_default_filter,
328
329 .tf_load = ata_tf_load,
330 .tf_read = ata_tf_read,
331 .check_status = ata_check_status,
332 .exec_command = ata_exec_command,
333 .dev_select = ata_std_dev_select,
334
335 .bmdma_setup = ata_bmdma_setup,
336 .bmdma_start = ata_bmdma_start,
337 .bmdma_stop = ata_bmdma_stop,
338 .bmdma_status = ata_bmdma_status,
339 .qc_prep = ata_qc_prep,
340 .qc_issue = ata_qc_issue_prot,
0d5ff566 341 .data_xfer = ata_data_xfer,
669a5db4
JG		 342
343 .freeze = ata_bmdma_freeze,
344 .thaw = ata_bmdma_thaw,
eb4a2c7f 345 .error_handler = piix_pata_error_handler,
669a5db4 346 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 347 .cable_detect = ich_pata_cable_detect,
669a5db4
JG		 348
349 .irq_handler = ata_interrupt,
350 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 351 .irq_on = ata_irq_on,
669a5db4
JG		 352
353 .port_start = ata_port_start,
669a5db4
JG		 354};
355
057ace5e 356static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 357 .tf_load = ata_tf_load,
358 .tf_read = ata_tf_read,
359 .check_status = ata_check_status,
360 .exec_command = ata_exec_command,
361 .dev_select = ata_std_dev_select,
362
1da177e4
LT		 363 .bmdma_setup = ata_bmdma_setup,
364 .bmdma_start = ata_bmdma_start,
365 .bmdma_stop = ata_bmdma_stop,
366 .bmdma_status = ata_bmdma_status,
367 .qc_prep = ata_qc_prep,
368 .qc_issue = ata_qc_issue_prot,
0d5ff566 369 .data_xfer = ata_data_xfer,
1da177e4 370
3f037db0
TH		 371 .freeze = ata_bmdma_freeze,
372 .thaw = ata_bmdma_thaw,
2f91d81d 373 .error_handler = ata_bmdma_error_handler,
3f037db0 374 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 375
376 .irq_handler = ata_interrupt,
377 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 378 .irq_on = ata_irq_on,
1da177e4
LT		 379
380 .port_start = ata_port_start,
1da177e4
LT		 381};
382
d96715c1 383static const struct piix_map_db ich5_map_db = {
d33f58b8 384 .mask = 0x7,
ea35d29e 385 .port_enable = 0x3,
d33f58b8
TH		 386 .map = {
387 /* PM PS SM SS MAP */
388 { P0, NA, P1, NA }, /* 000b */
389 { P1, NA, P0, NA }, /* 001b */
390 { RV, RV, RV, RV },
391 { RV, RV, RV, RV },
392 { P0, P1, IDE, IDE }, /* 100b */
393 { P1, P0, IDE, IDE }, /* 101b */
394 { IDE, IDE, P0, P1 }, /* 110b */
395 { IDE, IDE, P1, P0 }, /* 111b */
396 },
397};
398
d96715c1 399static const struct piix_map_db ich6_map_db = {
d33f58b8 400 .mask = 0x3,
ea35d29e 401 .port_enable = 0xf,
d33f58b8
TH		 402 .map = {
403 /* PM PS SM SS MAP */
79ea24e7 404 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 405 { IDE, IDE, P1, P3 }, /* 01b */
406 { P0, P2, IDE, IDE }, /* 10b */
407 { RV, RV, RV, RV },
408 },
409};
410
d96715c1 411static const struct piix_map_db ich6m_map_db = {
d33f58b8 412 .mask = 0x3,
ea35d29e 413 .port_enable = 0x5,
67083741
TH		 414
415 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 416 * it anyway. MAP 01b have been spotted on both ICH6M and
417 * ICH7M.
67083741
TH		 418 */
419 .map = {
420 /* PM PS SM SS MAP */
e04b3b9d 421 { P0, P2, NA, NA }, /* 00b */
67083741
TH		 422 { IDE, IDE, P1, P3 }, /* 01b */
423 { P0, P2, IDE, IDE }, /* 10b */
424 { RV, RV, RV, RV },
425 },
426};
427
08f12edc
JG		 428static const struct piix_map_db ich8_map_db = {
429 .mask = 0x3,
430 .port_enable = 0x3,
08f12edc
JG		 431 .map = {
432 /* PM PS SM SS MAP */
158f30c8 433 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 434 { RV, RV, RV, RV },
ac2b0437 435 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
08f12edc
JG		 436 { RV, RV, RV, RV },
437 },
438};
439
c5cf0ffa
JG		 440static const struct piix_map_db tolapai_map_db = {
441 .mask = 0x3,
442 .port_enable = 0x3,
443 .map = {
444 /* PM PS SM SS MAP */
445 { P0, NA, P1, NA }, /* 00b */
446 { RV, RV, RV, RV }, /* 01b */
447 { RV, RV, RV, RV }, /* 10b */
448 { RV, RV, RV, RV },
449 },
450};
451
d96715c1
TH		 452static const struct piix_map_db *piix_map_db_table[] = {
453 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 454 [ich6_sata] = &ich6_map_db,
455 [ich6_sata_ahci] = &ich6_map_db,
456 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 457 [ich8_sata_ahci] = &ich8_map_db,
c5cf0ffa 458 [tolapai_sata_ahci] = &tolapai_map_db,
d96715c1
TH		 459};
460
1da177e4 461static struct ata_port_info piix_port_info[] = {
d2cdfc0d 462 /* piix_pata_33: 0: PIIX4 at 33MHz */
1d076e5b
TH		 463 {
464 .sht = &piix_sht,
b3362f88 465 .flags = PIIX_PATA_FLAGS,
1d076e5b 466 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 467 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 468 .udma_mask = ATA_UDMA_MASK_40C,
469 .port_ops = &piix_pata_ops,
470 },
471
669a5db4
JG		 472 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
473 {
474 .sht = &piix_sht,
b3362f88 475 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 476 .pio_mask = 0x1f, /* pio 0-4 */
477 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
478 .udma_mask = ATA_UDMA2, /* UDMA33 */
479 .port_ops = &ich_pata_ops,
480 },
481 /* ich_pata_66: 2 ICH controllers up to 66MHz */
1da177e4
LT		 482 {
483 .sht = &piix_sht,
b3362f88 484 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 485 .pio_mask = 0x1f, /* pio 0-4 */
486 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
487 .udma_mask = ATA_UDMA4,
488 .port_ops = &ich_pata_ops,
489 },
85cd7251 490
669a5db4
JG		 491 /* ich_pata_100: 3 */
492 {
493 .sht = &piix_sht,
b3362f88 494 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 495 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 496 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 497 .udma_mask = ATA_UDMA5, /* udma0-5 */
498 .port_ops = &ich_pata_ops,
1da177e4
LT		 499 },
500
2eb829e9 501 /* ich_pata_133: 4 - Not supported - */
669a5db4
JG		 502 {
503 .sht = &piix_sht,
b3362f88 504 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
669a5db4
JG		 505 .pio_mask = 0x1f, /* pio 0-4 */
506 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
507 .udma_mask = ATA_UDMA6, /* UDMA133 */
508 .port_ops = &ich_pata_ops,
509 },
510
511 /* ich5_sata: 5 */
1da177e4
LT		 512 {
513 .sht = &piix_sht,
228c1590 514 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 515 .pio_mask = 0x1f, /* pio0-4 */
516 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 517 .udma_mask = ATA_UDMA6,
1da177e4
LT		 518 .port_ops = &piix_sata_ops,
519 },
520
5e56a37c 521 /* ich6_sata: 6 */
1da177e4
LT		 522 {
523 .sht = &piix_sht,
b3362f88 524 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 525 .pio_mask = 0x1f, /* pio0-4 */
526 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 527 .udma_mask = ATA_UDMA6,
1da177e4
LT		 528 .port_ops = &piix_sata_ops,
529 },
530
5e56a37c 531 /* ich6_sata_ahci: 7 */
c368ca4e
JG		 532 {
533 .sht = &piix_sht,
b3362f88 534 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 535 PIIX_FLAG_AHCI,
c368ca4e
JG		 536 .pio_mask = 0x1f, /* pio0-4 */
537 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 538 .udma_mask = ATA_UDMA6,
c368ca4e
JG		 539 .port_ops = &piix_sata_ops,
540 },
1d076e5b 541
5e56a37c 542 /* ich6m_sata_ahci: 8 */
1d076e5b
TH		 543 {
544 .sht = &piix_sht,
b3362f88 545 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 546 PIIX_FLAG_AHCI,
1d076e5b
TH		 547 .pio_mask = 0x1f, /* pio0-4 */
548 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 549 .udma_mask = ATA_UDMA6,
1d076e5b
TH		 550 .port_ops = &piix_sata_ops,
551 },
08f12edc 552
5e56a37c 553 /* ich8_sata_ahci: 9 */
08f12edc
JG		 554 {
555 .sht = &piix_sht,
b3362f88 556 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 557 PIIX_FLAG_AHCI,
558 .pio_mask = 0x1f, /* pio0-4 */
559 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 560 .udma_mask = ATA_UDMA6,
08f12edc
JG		 561 .port_ops = &piix_sata_ops,
562 },
669a5db4 563
d2cdfc0d
AC		 564 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
565 {
566 .sht = &piix_sht,
567 .flags = PIIX_PATA_FLAGS,
568 .pio_mask = 0x1f, /* pio0-4 */
569 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
570 .port_ops = &piix_pata_ops,
571 },
c5cf0ffa
JG		 572
573 /* tolapai_sata_ahci: 11: */
574 {
575 .sht = &piix_sht,
576 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
577 PIIX_FLAG_AHCI,
578 .pio_mask = 0x1f, /* pio0-4 */
579 .mwdma_mask = 0x07, /* mwdma0-2 */
580 .udma_mask = ATA_UDMA6,
581 .port_ops = &piix_sata_ops,
582 },
1da177e4
LT		 583};
584
585static struct pci_bits piix_enable_bits[] = {
586 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
587 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
588};
589
590MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
591MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
592MODULE_LICENSE("GPL");
593MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
594MODULE_VERSION(DRV_VERSION);
595
fc085150
AC		 596struct ich_laptop {
597 u16 device;
598 u16 subvendor;
599 u16 subdevice;
600};
601
602/*
603 * List of laptops that use short cables rather than 80 wire
604 */
605
606static const struct ich_laptop ich_laptop[] = {
607 /* devid, subvendor, subdev */
608 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
babfb682 609 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
12340106 610 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
b33620f9 611 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
fc085150
AC		 612 /* end marker */
613 { 0, }
614};
615
1da177e4 616/**
eb4a2c7f 617 * ich_pata_cable_detect - Probe host controller cable detect info
1da177e4
LT		 618 * @ap: Port for which cable detect info is desired
619 *
620 * Read 80c cable indicator from ATA PCI device's PCI config
621 * register. This register is normally set by firmware (BIOS).
622 *
623 * LOCKING:
624 * None (inherited from caller).
625 */
669a5db4 626
eb4a2c7f 627static int ich_pata_cable_detect(struct ata_port *ap)
1da177e4 628{
cca3974e 629 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 630 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 631 u8 tmp, mask;
632
fc085150
AC		 633 /* Check for specials - Acer Aspire 5602WLMi */
634 while (lap->device) {
635 if (lap->device == pdev->device &&
636 lap->subvendor == pdev->subsystem_vendor &&
637 lap->subdevice == pdev->subsystem_device) {
eb4a2c7f 638 return ATA_CBL_PATA40_SHORT;
fc085150
AC		 639 }
640 lap++;
641 }
642
1da177e4 643 /* check BIOS cable detect results */
2a88d1ac 644 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 645 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
646 if ((tmp & mask) == 0)
eb4a2c7f
AC		 647 return ATA_CBL_PATA40;
648 return ATA_CBL_PATA80;
1da177e4
LT		 649}
650
651/**
ccc4672a 652 * piix_pata_prereset - prereset for PATA host controller
cc0680a5 653 * @link: Target link
d4b2bab4 654 * @deadline: deadline jiffies for the operation
1da177e4 655 *
573db6b8
TH		 656 * LOCKING:
657 * None (inherited from caller).
658 */
cc0680a5 659static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
1da177e4 660{
cc0680a5 661 struct ata_port *ap = link->ap;
cca3974e 662 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 663
c961922b
AC		 664 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
665 return -ENOENT;
cc0680a5 666 return ata_std_prereset(link, deadline);
ccc4672a
TH		 667}
668
669static void piix_pata_error_handler(struct ata_port *ap)
670{
671 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
672 ata_std_postreset);
1da177e4
LT		 673}
674
1da177e4
LT		 675/**
676 * piix_set_piomode - Initialize host controller PATA PIO timings
677 * @ap: Port whose timings we are configuring
678 * @adev: um
1da177e4
LT		 679 *
680 * Set PIO mode for device, in host controller PCI config space.
681 *
682 * LOCKING:
683 * None (inherited from caller).
684 */
685
686static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
687{
688 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 689 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 690 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 691 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 692 unsigned int slave_port = 0x44;
693 u16 master_data;
694 u8 slave_data;
669a5db4
JG		 695 u8 udma_enable;
696 int control = 0;
85cd7251 697
669a5db4
JG		 698 /*
699 * See Intel Document 298600-004 for the timing programing rules
700 * for ICH controllers.
701 */
1da177e4
LT		 702
703 static const /* ISP RTC */
704 u8 timings[][2] = { { 0, 0 },
705 { 0, 0 },
706 { 1, 0 },
707 { 2, 1 },
708 { 2, 3 }, };
709
669a5db4
JG		 710 if (pio >= 2)
711 control |= 1; /* TIME1 enable */
712 if (ata_pio_need_iordy(adev))
713 control |= 2; /* IE enable */
714
85cd7251 715 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 716 if (adev->class == ATA_DEV_ATA)
717 control |= 4; /* PPE enable */
718
a5bf5f5a
TH		 719 /* PIO configuration clears DTE unconditionally. It will be
720 * programmed in set_dmamode which is guaranteed to be called
721 * after set_piomode if any DMA mode is available.
722 */
1da177e4
LT		 723 pci_read_config_word(dev, master_port, &master_data);
724 if (is_slave) {
a5bf5f5a
TH		 725 /* clear TIME1|IE1|PPE1|DTE1 */
726 master_data &= 0xff0f;
669a5db4 727 /* Enable SITRE (seperate slave timing register) */
1da177e4 728 master_data |= 0x4000;
669a5db4
JG		 729 /* enable PPE1, IE1 and TIME1 as needed */
730 master_data |= (control << 4);
1da177e4 731 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 732 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4 733 /* Load the timing nibble for this slave */
a5bf5f5a
TH		 734 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
735 << (ap->port_no ? 4 : 0);
1da177e4 736 } else {
a5bf5f5a
TH		 737 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
738 master_data &= 0xccf0;
669a5db4
JG		 739 /* Enable PPE, IE and TIME as appropriate */
740 master_data |= control;
a5bf5f5a 741 /* load ISP and RCT */
1da177e4
LT		 742 master_data |=
743 (timings[pio][0] << 12) |
744 (timings[pio][1] << 8);
745 }
746 pci_write_config_word(dev, master_port, master_data);
747 if (is_slave)
748 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 749
750 /* Ensure the UDMA bit is off - it will be turned back on if
751 UDMA is selected */
85cd7251 752
669a5db4
JG		 753 if (ap->udma_mask) {
754 pci_read_config_byte(dev, 0x48, &udma_enable);
755 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
756 pci_write_config_byte(dev, 0x48, udma_enable);
757 }
1da177e4
LT		 758}
759
760/**
669a5db4 761 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 762 * @ap: Port whose timings we are configuring
669a5db4 763 * @adev: Drive in question
1da177e4 764 * @udma: udma mode, 0 - 6
c32a8fd7 765 * @isich: set if the chip is an ICH device
1da177e4
LT		 766 *
767 * Set UDMA mode for device, in host controller PCI config space.
768 *
769 * LOCKING:
770 * None (inherited from caller).
771 */
772
669a5db4 773static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 774{
cca3974e 775 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 776 u8 master_port = ap->port_no ? 0x42 : 0x40;
777 u16 master_data;
778 u8 speed = adev->dma_mode;
779 int devid = adev->devno + 2 * ap->port_no;
dedf61db 780 u8 udma_enable = 0;
85cd7251 781
669a5db4
JG		 782 static const /* ISP RTC */
783 u8 timings[][2] = { { 0, 0 },
784 { 0, 0 },
785 { 1, 0 },
786 { 2, 1 },
787 { 2, 3 }, };
788
789 pci_read_config_word(dev, master_port, &master_data);
d2cdfc0d
AC		 790 if (ap->udma_mask)
791 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 792
793 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 794 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
795 u16 udma_timing;
796 u16 ideconf;
797 int u_clock, u_speed;
85cd7251 798
669a5db4
JG		 799 /*
800 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 801 * selection of dividers
802 *
669a5db4 803 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 804 * except UDMA0 which is 00
669a5db4
JG		 805 */
806 u_speed = min(2 - (udma & 1), udma);
807 if (udma == 5)
808 u_clock = 0x1000; /* 100Mhz */
809 else if (udma > 2)
810 u_clock = 1; /* 66Mhz */
811 else
812 u_clock = 0; /* 33Mhz */
85cd7251 813
669a5db4 814 udma_enable |= (1 << devid);
85cd7251 815
669a5db4
JG		 816 /* Load the CT/RP selection */
817 pci_read_config_word(dev, 0x4A, &udma_timing);
818 udma_timing &= ~(3 << (4 * devid));
819 udma_timing |= u_speed << (4 * devid);
820 pci_write_config_word(dev, 0x4A, udma_timing);
821
85cd7251 822 if (isich) {
669a5db4
JG		 823 /* Select a 33/66/100Mhz clock */
824 pci_read_config_word(dev, 0x54, &ideconf);
825 ideconf &= ~(0x1001 << devid);
826 ideconf |= u_clock << devid;
827 /* For ICH or later we should set bit 10 for better
828 performance (WR_PingPong_En) */
829 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 830 }
1da177e4 831 } else {
669a5db4
JG		 832 /*
833 * MWDMA is driven by the PIO timings. We must also enable
834 * IORDY unconditionally along with TIME1. PPE has already
835 * been set when the PIO timing was set.
836 */
837 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
838 unsigned int control;
839 u8 slave_data;
840 const unsigned int needed_pio[3] = {
841 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
842 };
843 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 844
669a5db4 845 control = 3; /* IORDY|TIME1 */
85cd7251 846
669a5db4
JG		 847 /* If the drive MWDMA is faster than it can do PIO then
848 we must force PIO into PIO0 */
85cd7251 849
669a5db4
JG		 850 if (adev->pio_mode < needed_pio[mwdma])
851 /* Enable DMA timing only */
852 control |= 8; /* PIO cycles in PIO0 */
853
854 if (adev->devno) { /* Slave */
855 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
856 master_data |= control << 4;
857 pci_read_config_byte(dev, 0x44, &slave_data);
a5bf5f5a 858 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 859 /* Load the matching timing */
860 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
861 pci_write_config_byte(dev, 0x44, slave_data);
862 } else { /* Master */
85cd7251 863 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 864 and master timing bits */
865 master_data |= control;
866 master_data |=
867 (timings[pio][0] << 12) |
868 (timings[pio][1] << 8);
869 }
a5bf5f5a
TH		 870
871 if (ap->udma_mask) {
872 udma_enable &= ~(1 << devid);
873 pci_write_config_word(dev, master_port, master_data);
874 }
1da177e4 875 }
669a5db4
JG		 876 /* Don't scribble on 0x48 if the controller does not support UDMA */
877 if (ap->udma_mask)
878 pci_write_config_byte(dev, 0x48, udma_enable);
879}
880
881/**
882 * piix_set_dmamode - Initialize host controller PATA DMA timings
883 * @ap: Port whose timings we are configuring
884 * @adev: um
885 *
886 * Set MW/UDMA mode for device, in host controller PCI config space.
887 *
888 * LOCKING:
889 * None (inherited from caller).
890 */
891
892static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
893{
894 do_pata_set_dmamode(ap, adev, 0);
895}
896
897/**
898 * ich_set_dmamode - Initialize host controller PATA DMA timings
899 * @ap: Port whose timings we are configuring
900 * @adev: um
901 *
902 * Set MW/UDMA mode for device, in host controller PCI config space.
903 *
904 * LOCKING:
905 * None (inherited from caller).
906 */
907
908static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
909{
910 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 911}
912
b8b275ef 913#ifdef CONFIG_PM
8c3832eb
TH		 914static int piix_broken_suspend(void)
915{
1855256c 916 static const struct dmi_system_id sysids[] = {
4c74d4ec
TH		 917 {
918 .ident = "TECRA M3",
919 .matches = {
920 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
921 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
922 },
923 },
8c3832eb
TH		 924 {
925 .ident = "TECRA M5",
926 .matches = {
927 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
928 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
929 },
b8b275ef 930 },
5c08ea01
TH		 931 {
932 .ident = "TECRA M7",
933 .matches = {
934 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
935 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
936 },
937 },
3cc0b9d3
TH		 938 {
939 .ident = "Satellite U200",
940 .matches = {
941 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
942 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
943 },
944 },
8c3832eb
TH		 945 {
946 .ident = "Satellite U205",
947 .matches = {
948 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
949 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
950 },
b8b275ef 951 },
8c3832eb
TH		 952 {
953 .ident = "Portege M500",
954 .matches = {
955 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
956 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
957 },
b8b275ef 958 },
7d051548
JG		 959
960 { } /* terminate list */
8c3832eb 961 };
7abe79c3
TH		 962 static const char *oemstrs[] = {
963 "Tecra M3,",
964 };
965 int i;
8c3832eb
TH		 966
967 if (dmi_check_system(sysids))
968 return 1;
969
7abe79c3
TH		 970 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
971 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
972 return 1;
973
8c3832eb
TH		 974 return 0;
975}
b8b275ef
TH		 976
977static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
978{
979 struct ata_host *host = dev_get_drvdata(&pdev->dev);
980 unsigned long flags;
981 int rc = 0;
982
983 rc = ata_host_suspend(host, mesg);
984 if (rc)
985 return rc;
986
987 /* Some braindamaged ACPI suspend implementations expect the
988 * controller to be awake on entry; otherwise, it burns cpu
989 * cycles and power trying to do something to the sleeping
990 * beauty.
991 */
8c3832eb 992 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
b8b275ef
TH		 993 pci_save_state(pdev);
994
995 /* mark its power state as "unknown", since we don't
996 * know if e.g. the BIOS will change its device state
997 * when we suspend.
998 */
999 if (pdev->current_state == PCI_D0)
1000 pdev->current_state = PCI_UNKNOWN;
1001
1002 /* tell resume that it's waking up from broken suspend */
1003 spin_lock_irqsave(&host->lock, flags);
1004 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1005 spin_unlock_irqrestore(&host->lock, flags);
1006 } else
1007 ata_pci_device_do_suspend(pdev, mesg);
1008
1009 return 0;
1010}
1011
1012static int piix_pci_device_resume(struct pci_dev *pdev)
1013{
1014 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1015 unsigned long flags;
1016 int rc;
1017
1018 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1019 spin_lock_irqsave(&host->lock, flags);
1020 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1021 spin_unlock_irqrestore(&host->lock, flags);
1022
1023 pci_set_power_state(pdev, PCI_D0);
1024 pci_restore_state(pdev);
1025
1026 /* PCI device wasn't disabled during suspend. Use
0b62e13b
TH		 1027 * pci_reenable_device() to avoid affecting the enable
1028 * count.
b8b275ef 1029 */
0b62e13b 1030 rc = pci_reenable_device(pdev);
b8b275ef
TH		 1031 if (rc)
1032 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1033 "device after resume (%d)\n", rc);
1034 } else
1035 rc = ata_pci_device_do_resume(pdev);
1036
1037 if (rc == 0)
1038 ata_host_resume(host);
1039
1040 return rc;
1041}
1042#endif
1043
1da177e4
LT		 1044#define AHCI_PCI_BAR 5
1045#define AHCI_GLOBAL_CTL 0x04
1046#define AHCI_ENABLE (1 << 31)
1047static int piix_disable_ahci(struct pci_dev *pdev)
1048{
ea6ba10b 1049 void __iomem *mmio;
1da177e4
LT		 1050 u32 tmp;
1051 int rc = 0;
1052
1053 /* BUG: pci_enable_device has not yet been called. This
1054 * works because this device is usually set up by BIOS.
1055 */
1056
374b1873
JG		 1057 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1058 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 1059 return 0;
7b6dbd68 1060
374b1873 1061 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 1062 if (!mmio)
1063 return -ENOMEM;
7b6dbd68 1064
1da177e4
LT		 1065 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1066 if (tmp & AHCI_ENABLE) {
1067 tmp &= ~AHCI_ENABLE;
1068 writel(tmp, mmio + AHCI_GLOBAL_CTL);
1069
1070 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1071 if (tmp & AHCI_ENABLE)
1072 rc = -EIO;
1073 }
7b6dbd68 1074
374b1873 1075 pci_iounmap(pdev, mmio);
1da177e4
LT		 1076 return rc;
1077}
1078
c621b140
AC		 1079/**
1080 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 1081 * @ata_dev: the PCI device to check
2e9edbf8 1082 *
c621b140
AC		 1083 * Check for the present of 450NX errata #19 and errata #25. If
1084 * they are found return an error code so we can turn off DMA
1085 */
1086
1087static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1088{
1089 struct pci_dev *pdev = NULL;
1090 u16 cfg;
c621b140 1091 int no_piix_dma = 0;
2e9edbf8 1092
c621b140
AC		 1093 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
1094 {
1095 /* Look for 450NX PXB. Check for problem configurations
1096 A PCI quirk checks bit 6 already */
c621b140
AC		 1097 pci_read_config_word(pdev, 0x41, &cfg);
1098 /* Only on the original revision: IDE DMA can hang */
44c10138 1099 if (pdev->revision == 0x00)
c621b140
AC		 1100 no_piix_dma = 1;
1101 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138 1102 else if (cfg & (1<<14) && pdev->revision < 5)
c621b140
AC		 1103 no_piix_dma = 2;
1104 }
31a34fe7 1105 if (no_piix_dma)
c621b140 1106 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 1107 if (no_piix_dma == 2)
c621b140
AC		 1108 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1109 return no_piix_dma;
2e9edbf8 1110}
c621b140 1111
ea35d29e 1112static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 1113 struct ata_port_info *pinfo,
ea35d29e
JG		 1114 const struct piix_map_db *map_db)
1115{
1116 u16 pcs, new_pcs;
1117
1118 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1119
1120 new_pcs = pcs | map_db->port_enable;
1121
1122 if (new_pcs != pcs) {
1123 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1124 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1125 msleep(150);
1126 }
1127}
1128
d33f58b8 1129static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 1130 struct ata_port_info *pinfo,
1131 const struct piix_map_db *map_db)
d33f58b8 1132{
d96715c1 1133 struct piix_host_priv *hpriv = pinfo[0].private_data;
d33f58b8
TH		 1134 const unsigned int *map;
1135 int i, invalid_map = 0;
1136 u8 map_value;
1137
1138 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1139
1140 map = map_db->map[map_value & map_db->mask];
1141
1142 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1143 for (i = 0; i < 4; i++) {
1144 switch (map[i]) {
1145 case RV:
1146 invalid_map = 1;
1147 printk(" XX");
1148 break;
1149
1150 case NA:
1151 printk(" --");
1152 break;
1153
1154 case IDE:
1155 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1156 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1157 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1158 i++;
1159 printk(" IDE IDE");
1160 break;
1161
1162 default:
1163 printk(" P%d", map[i]);
1164 if (i & 1)
cca3974e 1165 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1166 break;
1167 }
1168 }
1169 printk(" ]\n");
1170
1171 if (invalid_map)
1172 dev_printk(KERN_ERR, &pdev->dev,
1173 "invalid MAP value %u\n", map_value);
1174
d96715c1 1175 hpriv->map = map;
d33f58b8
TH		 1176}
1177
43a98f05
TH		 1178static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1179{
1855256c 1180 static const struct dmi_system_id sysids[] = {
43a98f05
TH		 1181 {
1182 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1183 * isn't used to boot the system which
1184 * disables the channel.
1185 */
1186 .ident = "M570U",
1187 .matches = {
1188 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1189 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1190 },
1191 },
7d051548
JG		 1192
1193 { } /* terminate list */
43a98f05
TH		 1194 };
1195 u32 iocfg;
1196
1197 if (!dmi_check_system(sysids))
1198 return;
1199
1200 /* The datasheet says that bit 18 is NOOP but certain systems
1201 * seem to use it to disable a channel. Clear the bit on the
1202 * affected systems.
1203 */
1204 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1205 if (iocfg & (1 << 18)) {
1206 dev_printk(KERN_INFO, &pdev->dev,
1207 "applying IOCFG bit18 quirk\n");
1208 iocfg &= ~(1 << 18);
1209 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1210 }
1211}
1212
1da177e4
LT		 1213/**
1214 * piix_init_one - Register PIIX ATA PCI device with kernel services
1215 * @pdev: PCI device to register
1216 * @ent: Entry in piix_pci_tbl matching with @pdev
1217 *
1218 * Called from kernel PCI layer. We probe for combined mode (sigh),
1219 * and then hand over control to libata, for it to do the rest.
1220 *
1221 * LOCKING:
1222 * Inherited from PCI layer (may sleep).
1223 *
1224 * RETURNS:
1225 * Zero on success, or -ERRNO value.
1226 */
1227
1228static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1229{
1230 static int printed_version;
24dc5f33 1231 struct device *dev = &pdev->dev;
d33f58b8 1232 struct ata_port_info port_info[2];
1626aeb8 1233 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
d96715c1 1234 struct piix_host_priv *hpriv;
cca3974e 1235 unsigned long port_flags;
1da177e4
LT		 1236
1237 if (!printed_version++)
6248e647
JG		 1238 dev_printk(KERN_DEBUG, &pdev->dev,
1239 "version " DRV_VERSION "\n");
1da177e4
LT		 1240
1241 /* no hotplugging support (FIXME) */
1242 if (!in_module_init)
1243 return -ENODEV;
1244
24dc5f33 1245 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
d96715c1
TH		 1246 if (!hpriv)
1247 return -ENOMEM;
1248
d33f58b8
TH		 1249 port_info[0] = piix_port_info[ent->driver_data];
1250 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1251 port_info[0].private_data = hpriv;
1252 port_info[1].private_data = hpriv;
1da177e4 1253
cca3974e 1254 port_flags = port_info[0].flags;
ff0fc146 1255
cca3974e 1256 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1257 u8 tmp;
1258 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1259 if (tmp == PIIX_AHCI_DEVICE) {
1260 int rc = piix_disable_ahci(pdev);
1261 if (rc)
1262 return rc;
1263 }
1da177e4
LT		 1264 }
1265
d33f58b8 1266 /* Initialize SATA map */
cca3974e 1267 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1268 piix_init_sata_map(pdev, port_info,
1269 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1270 piix_init_pcs(pdev, port_info,
1271 piix_map_db_table[ent->driver_data]);
ea35d29e 1272 }
1da177e4 1273
43a98f05
TH		 1274 /* apply IOCFG bit18 quirk */
1275 piix_iocfg_bit18_quirk(pdev);
1276
1da177e4
LT		 1277 /* On ICH5, some BIOSen disable the interrupt using the
1278 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1279 * On ICH6, this bit has the same effect, but only when
1280 * MSI is disabled (and it is disabled, as we don't use
1281 * message-signalled interrupts currently).
1282 */
cca3974e 1283 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1284 pci_intx(pdev, 1);
1da177e4 1285
c621b140
AC		 1286 if (piix_check_450nx_errata(pdev)) {
1287 /* This writes into the master table but it does not
1288 really matter for this errata as we will apply it to
1289 all the PIIX devices on the board */
d33f58b8
TH		 1290 port_info[0].mwdma_mask = 0;
1291 port_info[0].udma_mask = 0;
1292 port_info[1].mwdma_mask = 0;
1293 port_info[1].udma_mask = 0;
c621b140 1294 }
1626aeb8 1295 return ata_pci_init_one(pdev, ppi);
1da177e4
LT		 1296}
1297
1da177e4
LT		 1298static int __init piix_init(void)
1299{
1300 int rc;
1301
b7887196
PR		 1302 DPRINTK("pci_register_driver\n");
1303 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1304 if (rc)
1305 return rc;
1306
1307 in_module_init = 0;
1308
1309 DPRINTK("done\n");
1310 return 0;
1311}
1312
1da177e4
LT		 1313static void __exit piix_exit(void)
1314{
1315 pci_unregister_driver(&piix_pci_driver);
1316}
1317
1318module_init(piix_init);
1319module_exit(piix_exit);