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Fix "delayed_work_pending()" macro expansion
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / ata / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
fc085150 96#define DRV_VERSION "2.00ac7"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
d4358048 104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 107
800b3996
TH		 108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 110
1da177e4
LT		 111 /* combined mode. if set, PATA is channel 0.
112 * if clear, PATA is channel 1.
113 */
6a690df5
HR		 114 PIIX_PORT_ENABLED = (1 << 0),
115 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 116
117 PIIX_80C_PRI = (1 << 5) | (1 << 4),
118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119
1d076e5b 120 /* controller IDs */
669a5db4
JG		 121 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
123 ich_pata_66 = 2, /* ICH up to 66 Mhz */
124 ich_pata_100 = 3, /* ICH up to UDMA 100 */
125 ich_pata_133 = 4, /* ICH up to UDMA 133 */
126 ich5_sata = 5,
5e56a37c
TH		 127 ich6_sata = 6,
128 ich6_sata_ahci = 7,
129 ich6m_sata_ahci = 8,
130 ich8_sata_ahci = 9,
85cd7251 131
d33f58b8
TH		 132 /* constants for mapping table */
133 P0 = 0, /* port 0 */
134 P1 = 1, /* port 1 */
135 P2 = 2, /* port 2 */
136 P3 = 3, /* port 3 */
137 IDE = -1, /* IDE */
138 NA = -2, /* not avaliable */
139 RV = -3, /* reserved */
140
7b6dbd68 141 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 142};
143
d33f58b8
TH		 144struct piix_map_db {
145 const u32 mask;
73291a1c 146 const u16 port_enable;
d33f58b8
TH		 147 const int map[][4];
148};
149
d96715c1
TH		 150struct piix_host_priv {
151 const int *map;
152};
153
1da177e4
LT		 154static int piix_init_one (struct pci_dev *pdev,
155 const struct pci_device_id *ent);
cca3974e 156static void piix_host_stop(struct ata_host *host);
ccc4672a 157static void piix_pata_error_handler(struct ata_port *ap);
669a5db4 158static void ich_pata_error_handler(struct ata_port *ap);
ccc4672a 159static void piix_sata_error_handler(struct ata_port *ap);
669a5db4
JG		 160static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
161static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
162static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
1da177e4
LT		 163
164static unsigned int in_module_init = 1;
165
3b7d697d 166static const struct pci_device_id piix_pci_tbl[] = {
1da177e4 167#ifdef ATA_ENABLE_PATA
669a5db4
JG		 168 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
169 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
170 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
171 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
172 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
173 /* Intel PIIX4 */
174 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
175 /* Intel PIIX4 */
176 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
177 /* Intel PIIX */
178 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
179 /* Intel ICH (i810, i815, i840) UDMA 66*/
180 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
181 /* Intel ICH0 : UDMA 33*/
182 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
183 /* Intel ICH2M */
184 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
185 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
186 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
187 /* Intel ICH3M */
188 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189 /* Intel ICH3 (E7500/1) UDMA 100 */
190 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
192 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH5 */
195 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
196 /* C-ICH (i810E2) */
197 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 198 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 199 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* ICH6 (and 6) (i915) UDMA 100 */
201 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* ICH7/7-R (i945, i975) UDMA 100*/
203 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
204 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 205#endif
206
207 /* NOTE: The following PCI ids must be kept in sync with the
208 * list in drivers/pci/quirks.c.
209 */
210
1d076e5b 211 /* 82801EB (ICH5) */
1da177e4 212 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 213 /* 82801EB (ICH5) */
1da177e4 214 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 215 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 216 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 217 /* 6300ESB pretending RAID */
5e56a37c 218 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 219 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 220 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 221 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 222 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 223 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
224 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
225 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 226 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 227 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 228 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
1d076e5b 229 /* Enterprise Southbridge 2 (where's the datasheet?) */
1c24a412 230 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 231 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
08f12edc 232 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1d076e5b 233 /* SATA Controller 2 IDE (ICH8, ditto) */
08f12edc 234 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1d076e5b 235 /* Mobile SATA Controller IDE (ICH8M, ditto) */
08f12edc 236 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1da177e4
LT		 237
238 { } /* terminate list */
239};
240
241static struct pci_driver piix_pci_driver = {
242 .name = DRV_NAME,
243 .id_table = piix_pci_tbl,
244 .probe = piix_init_one,
245 .remove = ata_pci_remove_one,
9b847548
JA		 246 .suspend = ata_pci_device_suspend,
247 .resume = ata_pci_device_resume,
1da177e4
LT		 248};
249
193515d5 250static struct scsi_host_template piix_sht = {
1da177e4
LT		 251 .module = THIS_MODULE,
252 .name = DRV_NAME,
253 .ioctl = ata_scsi_ioctl,
254 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 255 .can_queue = ATA_DEF_QUEUE,
256 .this_id = ATA_SHT_THIS_ID,
257 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 258 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
259 .emulated = ATA_SHT_EMULATED,
260 .use_clustering = ATA_SHT_USE_CLUSTERING,
261 .proc_name = DRV_NAME,
262 .dma_boundary = ATA_DMA_BOUNDARY,
263 .slave_configure = ata_scsi_slave_config,
ccf68c34 264 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 265 .bios_param = ata_std_bios_param,
9b847548
JA		 266 .resume = ata_scsi_device_resume,
267 .suspend = ata_scsi_device_suspend,
1da177e4
LT		 268};
269
057ace5e 270static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 271 .port_disable = ata_port_disable,
272 .set_piomode = piix_set_piomode,
273 .set_dmamode = piix_set_dmamode,
89bad589 274 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 275
276 .tf_load = ata_tf_load,
277 .tf_read = ata_tf_read,
278 .check_status = ata_check_status,
279 .exec_command = ata_exec_command,
280 .dev_select = ata_std_dev_select,
281
1da177e4
LT		 282 .bmdma_setup = ata_bmdma_setup,
283 .bmdma_start = ata_bmdma_start,
284 .bmdma_stop = ata_bmdma_stop,
285 .bmdma_status = ata_bmdma_status,
286 .qc_prep = ata_qc_prep,
287 .qc_issue = ata_qc_issue_prot,
89bad589 288 .data_xfer = ata_pio_data_xfer,
1da177e4 289
3f037db0
TH		 290 .freeze = ata_bmdma_freeze,
291 .thaw = ata_bmdma_thaw,
ccc4672a 292 .error_handler = piix_pata_error_handler,
3f037db0 293 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 294
295 .irq_handler = ata_interrupt,
296 .irq_clear = ata_bmdma_irq_clear,
297
298 .port_start = ata_port_start,
299 .port_stop = ata_port_stop,
d96715c1 300 .host_stop = piix_host_stop,
1da177e4
LT		 301};
302
669a5db4
JG		 303static const struct ata_port_operations ich_pata_ops = {
304 .port_disable = ata_port_disable,
305 .set_piomode = piix_set_piomode,
306 .set_dmamode = ich_set_dmamode,
307 .mode_filter = ata_pci_default_filter,
308
309 .tf_load = ata_tf_load,
310 .tf_read = ata_tf_read,
311 .check_status = ata_check_status,
312 .exec_command = ata_exec_command,
313 .dev_select = ata_std_dev_select,
314
315 .bmdma_setup = ata_bmdma_setup,
316 .bmdma_start = ata_bmdma_start,
317 .bmdma_stop = ata_bmdma_stop,
318 .bmdma_status = ata_bmdma_status,
319 .qc_prep = ata_qc_prep,
320 .qc_issue = ata_qc_issue_prot,
321 .data_xfer = ata_pio_data_xfer,
322
323 .freeze = ata_bmdma_freeze,
324 .thaw = ata_bmdma_thaw,
325 .error_handler = ich_pata_error_handler,
326 .post_internal_cmd = ata_bmdma_post_internal_cmd,
327
328 .irq_handler = ata_interrupt,
329 .irq_clear = ata_bmdma_irq_clear,
330
331 .port_start = ata_port_start,
332 .port_stop = ata_port_stop,
333 .host_stop = ata_host_stop,
334};
335
057ace5e 336static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 337 .port_disable = ata_port_disable,
338
339 .tf_load = ata_tf_load,
340 .tf_read = ata_tf_read,
341 .check_status = ata_check_status,
342 .exec_command = ata_exec_command,
343 .dev_select = ata_std_dev_select,
344
1da177e4
LT		 345 .bmdma_setup = ata_bmdma_setup,
346 .bmdma_start = ata_bmdma_start,
347 .bmdma_stop = ata_bmdma_stop,
348 .bmdma_status = ata_bmdma_status,
349 .qc_prep = ata_qc_prep,
350 .qc_issue = ata_qc_issue_prot,
89bad589 351 .data_xfer = ata_pio_data_xfer,
1da177e4 352
3f037db0
TH		 353 .freeze = ata_bmdma_freeze,
354 .thaw = ata_bmdma_thaw,
ccc4672a 355 .error_handler = piix_sata_error_handler,
3f037db0 356 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 357
358 .irq_handler = ata_interrupt,
359 .irq_clear = ata_bmdma_irq_clear,
360
361 .port_start = ata_port_start,
362 .port_stop = ata_port_stop,
d96715c1 363 .host_stop = piix_host_stop,
1da177e4
LT		 364};
365
d96715c1 366static const struct piix_map_db ich5_map_db = {
d33f58b8 367 .mask = 0x7,
ea35d29e 368 .port_enable = 0x3,
d33f58b8
TH		 369 .map = {
370 /* PM PS SM SS MAP */
371 { P0, NA, P1, NA }, /* 000b */
372 { P1, NA, P0, NA }, /* 001b */
373 { RV, RV, RV, RV },
374 { RV, RV, RV, RV },
375 { P0, P1, IDE, IDE }, /* 100b */
376 { P1, P0, IDE, IDE }, /* 101b */
377 { IDE, IDE, P0, P1 }, /* 110b */
378 { IDE, IDE, P1, P0 }, /* 111b */
379 },
380};
381
d96715c1 382static const struct piix_map_db ich6_map_db = {
d33f58b8 383 .mask = 0x3,
ea35d29e 384 .port_enable = 0xf,
d33f58b8
TH		 385 .map = {
386 /* PM PS SM SS MAP */
79ea24e7 387 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 388 { IDE, IDE, P1, P3 }, /* 01b */
389 { P0, P2, IDE, IDE }, /* 10b */
390 { RV, RV, RV, RV },
391 },
392};
393
d96715c1 394static const struct piix_map_db ich6m_map_db = {
d33f58b8 395 .mask = 0x3,
ea35d29e 396 .port_enable = 0x5,
67083741
TH		 397
398 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 399 * it anyway. MAP 01b have been spotted on both ICH6M and
400 * ICH7M.
67083741
TH		 401 */
402 .map = {
403 /* PM PS SM SS MAP */
404 { P0, P2, RV, RV }, /* 00b */
405 { IDE, IDE, P1, P3 }, /* 01b */
406 { P0, P2, IDE, IDE }, /* 10b */
407 { RV, RV, RV, RV },
408 },
409};
410
08f12edc
JG		 411static const struct piix_map_db ich8_map_db = {
412 .mask = 0x3,
413 .port_enable = 0x3,
08f12edc
JG		 414 .map = {
415 /* PM PS SM SS MAP */
158f30c8 416 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 417 { RV, RV, RV, RV },
158f30c8 418 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
08f12edc
JG		 419 { RV, RV, RV, RV },
420 },
421};
422
d96715c1
TH		 423static const struct piix_map_db *piix_map_db_table[] = {
424 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 425 [ich6_sata] = &ich6_map_db,
426 [ich6_sata_ahci] = &ich6_map_db,
427 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 428 [ich8_sata_ahci] = &ich8_map_db,
d96715c1
TH		 429};
430
1da177e4 431static struct ata_port_info piix_port_info[] = {
669a5db4 432 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
1d076e5b
TH		 433 {
434 .sht = &piix_sht,
b3362f88 435 .flags = PIIX_PATA_FLAGS,
1d076e5b 436 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 437 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 438 .udma_mask = ATA_UDMA_MASK_40C,
439 .port_ops = &piix_pata_ops,
440 },
441
669a5db4
JG		 442 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
443 {
444 .sht = &piix_sht,
b3362f88 445 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 446 .pio_mask = 0x1f, /* pio 0-4 */
447 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
448 .udma_mask = ATA_UDMA2, /* UDMA33 */
449 .port_ops = &ich_pata_ops,
450 },
451 /* ich_pata_66: 2 ICH controllers up to 66MHz */
1da177e4
LT		 452 {
453 .sht = &piix_sht,
b3362f88 454 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 455 .pio_mask = 0x1f, /* pio 0-4 */
456 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
457 .udma_mask = ATA_UDMA4,
458 .port_ops = &ich_pata_ops,
459 },
85cd7251 460
669a5db4
JG		 461 /* ich_pata_100: 3 */
462 {
463 .sht = &piix_sht,
b3362f88 464 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 465 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 466 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 467 .udma_mask = ATA_UDMA5, /* udma0-5 */
468 .port_ops = &ich_pata_ops,
1da177e4
LT		 469 },
470
669a5db4
JG		 471 /* ich_pata_133: 4 ICH with full UDMA6 */
472 {
473 .sht = &piix_sht,
b3362f88 474 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
669a5db4
JG		 475 .pio_mask = 0x1f, /* pio 0-4 */
476 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
477 .udma_mask = ATA_UDMA6, /* UDMA133 */
478 .port_ops = &ich_pata_ops,
479 },
480
481 /* ich5_sata: 5 */
1da177e4
LT		 482 {
483 .sht = &piix_sht,
228c1590 484 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 485 .pio_mask = 0x1f, /* pio0-4 */
486 .mwdma_mask = 0x07, /* mwdma0-2 */
487 .udma_mask = 0x7f, /* udma0-6 */
488 .port_ops = &piix_sata_ops,
489 },
490
5e56a37c 491 /* ich6_sata: 6 */
1da177e4
LT		 492 {
493 .sht = &piix_sht,
b3362f88 494 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 495 .pio_mask = 0x1f, /* pio0-4 */
496 .mwdma_mask = 0x07, /* mwdma0-2 */
497 .udma_mask = 0x7f, /* udma0-6 */
498 .port_ops = &piix_sata_ops,
499 },
500
5e56a37c 501 /* ich6_sata_ahci: 7 */
c368ca4e
JG		 502 {
503 .sht = &piix_sht,
b3362f88 504 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 505 PIIX_FLAG_AHCI,
c368ca4e
JG		 506 .pio_mask = 0x1f, /* pio0-4 */
507 .mwdma_mask = 0x07, /* mwdma0-2 */
508 .udma_mask = 0x7f, /* udma0-6 */
509 .port_ops = &piix_sata_ops,
510 },
1d076e5b 511
5e56a37c 512 /* ich6m_sata_ahci: 8 */
1d076e5b
TH		 513 {
514 .sht = &piix_sht,
b3362f88 515 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 516 PIIX_FLAG_AHCI,
1d076e5b
TH		 517 .pio_mask = 0x1f, /* pio0-4 */
518 .mwdma_mask = 0x07, /* mwdma0-2 */
519 .udma_mask = 0x7f, /* udma0-6 */
520 .port_ops = &piix_sata_ops,
521 },
08f12edc 522
5e56a37c 523 /* ich8_sata_ahci: 9 */
08f12edc
JG		 524 {
525 .sht = &piix_sht,
b3362f88 526 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 527 PIIX_FLAG_AHCI,
528 .pio_mask = 0x1f, /* pio0-4 */
529 .mwdma_mask = 0x07, /* mwdma0-2 */
530 .udma_mask = 0x7f, /* udma0-6 */
531 .port_ops = &piix_sata_ops,
532 },
669a5db4 533
1da177e4
LT		 534};
535
536static struct pci_bits piix_enable_bits[] = {
537 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
538 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
539};
540
541MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
542MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
543MODULE_LICENSE("GPL");
544MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
545MODULE_VERSION(DRV_VERSION);
546
fc085150
AC		 547struct ich_laptop {
548 u16 device;
549 u16 subvendor;
550 u16 subdevice;
551};
552
553/*
554 * List of laptops that use short cables rather than 80 wire
555 */
556
557static const struct ich_laptop ich_laptop[] = {
558 /* devid, subvendor, subdev */
559 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
560 /* end marker */
561 { 0, }
562};
563
1da177e4
LT		 564/**
565 * piix_pata_cbl_detect - Probe host controller cable detect info
566 * @ap: Port for which cable detect info is desired
567 *
568 * Read 80c cable indicator from ATA PCI device's PCI config
569 * register. This register is normally set by firmware (BIOS).
570 *
571 * LOCKING:
572 * None (inherited from caller).
573 */
669a5db4
JG		 574
575static void ich_pata_cbl_detect(struct ata_port *ap)
1da177e4 576{
cca3974e 577 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 578 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 579 u8 tmp, mask;
580
581 /* no 80c support in host controller? */
582 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
583 goto cbl40;
584
fc085150
AC		 585 /* Check for specials - Acer Aspire 5602WLMi */
586 while (lap->device) {
587 if (lap->device == pdev->device &&
588 lap->subvendor == pdev->subsystem_vendor &&
589 lap->subdevice == pdev->subsystem_device) {
590 ap->cbl = ATA_CBL_PATA40_SHORT;
591 return;
592 }
593 lap++;
594 }
595
1da177e4 596 /* check BIOS cable detect results */
2a88d1ac 597 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 598 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
599 if ((tmp & mask) == 0)
600 goto cbl40;
601
602 ap->cbl = ATA_CBL_PATA80;
603 return;
604
605cbl40:
606 ap->cbl = ATA_CBL_PATA40;
1da177e4
LT		 607}
608
609/**
ccc4672a 610 * piix_pata_prereset - prereset for PATA host controller
573db6b8 611 * @ap: Target port
1da177e4 612 *
573db6b8
TH		 613 *
614 * LOCKING:
615 * None (inherited from caller).
616 */
ccc4672a 617static int piix_pata_prereset(struct ata_port *ap)
1da177e4 618{
cca3974e 619 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 620
c961922b
AC		 621 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
622 return -ENOENT;
623
669a5db4 624 ap->cbl = ATA_CBL_PATA40;
ccc4672a
TH		 625 return ata_std_prereset(ap);
626}
627
628static void piix_pata_error_handler(struct ata_port *ap)
629{
630 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
631 ata_std_postreset);
1da177e4
LT		 632}
633
669a5db4
JG		 634
635/**
636 * ich_pata_prereset - prereset for PATA host controller
637 * @ap: Target port
638 *
639 *
640 * LOCKING:
641 * None (inherited from caller).
642 */
643static int ich_pata_prereset(struct ata_port *ap)
644{
645 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
646
647 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
648 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
649 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
650 return 0;
651 }
652
653 ich_pata_cbl_detect(ap);
654
655 return ata_std_prereset(ap);
656}
657
658static void ich_pata_error_handler(struct ata_port *ap)
659{
660 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
661 ata_std_postreset);
662}
663
ccc4672a
TH		 664static void piix_sata_error_handler(struct ata_port *ap)
665{
228c1590 666 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
ccc4672a 667 ata_std_postreset);
1da177e4
LT		 668}
669
670/**
671 * piix_set_piomode - Initialize host controller PATA PIO timings
672 * @ap: Port whose timings we are configuring
673 * @adev: um
1da177e4
LT		 674 *
675 * Set PIO mode for device, in host controller PCI config space.
676 *
677 * LOCKING:
678 * None (inherited from caller).
679 */
680
681static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
682{
683 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 684 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 685 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 686 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 687 unsigned int slave_port = 0x44;
688 u16 master_data;
689 u8 slave_data;
669a5db4
JG		 690 u8 udma_enable;
691 int control = 0;
85cd7251 692
669a5db4
JG		 693 /*
694 * See Intel Document 298600-004 for the timing programing rules
695 * for ICH controllers.
696 */
1da177e4
LT		 697
698 static const /* ISP RTC */
699 u8 timings[][2] = { { 0, 0 },
700 { 0, 0 },
701 { 1, 0 },
702 { 2, 1 },
703 { 2, 3 }, };
704
669a5db4
JG		 705 if (pio >= 2)
706 control |= 1; /* TIME1 enable */
707 if (ata_pio_need_iordy(adev))
708 control |= 2; /* IE enable */
709
85cd7251 710 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 711 if (adev->class == ATA_DEV_ATA)
712 control |= 4; /* PPE enable */
713
1da177e4
LT		 714 pci_read_config_word(dev, master_port, &master_data);
715 if (is_slave) {
669a5db4 716 /* Enable SITRE (seperate slave timing register) */
1da177e4 717 master_data |= 0x4000;
669a5db4
JG		 718 /* enable PPE1, IE1 and TIME1 as needed */
719 master_data |= (control << 4);
1da177e4 720 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 721 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 722 /* Load the timing nibble for this slave */
723 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
1da177e4 724 } else {
669a5db4 725 /* Master keeps the bits in a different format */
1da177e4 726 master_data &= 0xccf8;
669a5db4
JG		 727 /* Enable PPE, IE and TIME as appropriate */
728 master_data |= control;
1da177e4
LT		 729 master_data |=
730 (timings[pio][0] << 12) |
731 (timings[pio][1] << 8);
732 }
733 pci_write_config_word(dev, master_port, master_data);
734 if (is_slave)
735 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 736
737 /* Ensure the UDMA bit is off - it will be turned back on if
738 UDMA is selected */
85cd7251 739
669a5db4
JG		 740 if (ap->udma_mask) {
741 pci_read_config_byte(dev, 0x48, &udma_enable);
742 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
743 pci_write_config_byte(dev, 0x48, udma_enable);
744 }
1da177e4
LT		 745}
746
747/**
669a5db4 748 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 749 * @ap: Port whose timings we are configuring
669a5db4 750 * @adev: Drive in question
1da177e4 751 * @udma: udma mode, 0 - 6
c32a8fd7 752 * @isich: set if the chip is an ICH device
1da177e4
LT		 753 *
754 * Set UDMA mode for device, in host controller PCI config space.
755 *
756 * LOCKING:
757 * None (inherited from caller).
758 */
759
669a5db4 760static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 761{
cca3974e 762 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 763 u8 master_port = ap->port_no ? 0x42 : 0x40;
764 u16 master_data;
765 u8 speed = adev->dma_mode;
766 int devid = adev->devno + 2 * ap->port_no;
767 u8 udma_enable;
85cd7251 768
669a5db4
JG		 769 static const /* ISP RTC */
770 u8 timings[][2] = { { 0, 0 },
771 { 0, 0 },
772 { 1, 0 },
773 { 2, 1 },
774 { 2, 3 }, };
775
776 pci_read_config_word(dev, master_port, &master_data);
777 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 778
779 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 780 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
781 u16 udma_timing;
782 u16 ideconf;
783 int u_clock, u_speed;
85cd7251 784
669a5db4
JG		 785 /*
786 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 787 * selection of dividers
788 *
669a5db4 789 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 790 * except UDMA0 which is 00
669a5db4
JG		 791 */
792 u_speed = min(2 - (udma & 1), udma);
793 if (udma == 5)
794 u_clock = 0x1000; /* 100Mhz */
795 else if (udma > 2)
796 u_clock = 1; /* 66Mhz */
797 else
798 u_clock = 0; /* 33Mhz */
85cd7251 799
669a5db4 800 udma_enable |= (1 << devid);
85cd7251 801
669a5db4
JG		 802 /* Load the CT/RP selection */
803 pci_read_config_word(dev, 0x4A, &udma_timing);
804 udma_timing &= ~(3 << (4 * devid));
805 udma_timing |= u_speed << (4 * devid);
806 pci_write_config_word(dev, 0x4A, udma_timing);
807
85cd7251 808 if (isich) {
669a5db4
JG		 809 /* Select a 33/66/100Mhz clock */
810 pci_read_config_word(dev, 0x54, &ideconf);
811 ideconf &= ~(0x1001 << devid);
812 ideconf |= u_clock << devid;
813 /* For ICH or later we should set bit 10 for better
814 performance (WR_PingPong_En) */
815 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 816 }
1da177e4 817 } else {
669a5db4
JG		 818 /*
819 * MWDMA is driven by the PIO timings. We must also enable
820 * IORDY unconditionally along with TIME1. PPE has already
821 * been set when the PIO timing was set.
822 */
823 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
824 unsigned int control;
825 u8 slave_data;
826 const unsigned int needed_pio[3] = {
827 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
828 };
829 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 830
669a5db4 831 control = 3; /* IORDY|TIME1 */
85cd7251 832
669a5db4
JG		 833 /* If the drive MWDMA is faster than it can do PIO then
834 we must force PIO into PIO0 */
85cd7251 835
669a5db4
JG		 836 if (adev->pio_mode < needed_pio[mwdma])
837 /* Enable DMA timing only */
838 control |= 8; /* PIO cycles in PIO0 */
839
840 if (adev->devno) { /* Slave */
841 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
842 master_data |= control << 4;
843 pci_read_config_byte(dev, 0x44, &slave_data);
844 slave_data &= (0x0F + 0xE1 * ap->port_no);
845 /* Load the matching timing */
846 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
847 pci_write_config_byte(dev, 0x44, slave_data);
848 } else { /* Master */
85cd7251 849 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 850 and master timing bits */
851 master_data |= control;
852 master_data |=
853 (timings[pio][0] << 12) |
854 (timings[pio][1] << 8);
855 }
856 udma_enable &= ~(1 << devid);
857 pci_write_config_word(dev, master_port, master_data);
1da177e4 858 }
669a5db4
JG		 859 /* Don't scribble on 0x48 if the controller does not support UDMA */
860 if (ap->udma_mask)
861 pci_write_config_byte(dev, 0x48, udma_enable);
862}
863
864/**
865 * piix_set_dmamode - Initialize host controller PATA DMA timings
866 * @ap: Port whose timings we are configuring
867 * @adev: um
868 *
869 * Set MW/UDMA mode for device, in host controller PCI config space.
870 *
871 * LOCKING:
872 * None (inherited from caller).
873 */
874
875static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
876{
877 do_pata_set_dmamode(ap, adev, 0);
878}
879
880/**
881 * ich_set_dmamode - Initialize host controller PATA DMA timings
882 * @ap: Port whose timings we are configuring
883 * @adev: um
884 *
885 * Set MW/UDMA mode for device, in host controller PCI config space.
886 *
887 * LOCKING:
888 * None (inherited from caller).
889 */
890
891static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
892{
893 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 894}
895
1da177e4
LT		 896#define AHCI_PCI_BAR 5
897#define AHCI_GLOBAL_CTL 0x04
898#define AHCI_ENABLE (1 << 31)
899static int piix_disable_ahci(struct pci_dev *pdev)
900{
ea6ba10b 901 void __iomem *mmio;
1da177e4
LT		 902 u32 tmp;
903 int rc = 0;
904
905 /* BUG: pci_enable_device has not yet been called. This
906 * works because this device is usually set up by BIOS.
907 */
908
374b1873
JG		 909 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
910 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 911 return 0;
7b6dbd68 912
374b1873 913 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 914 if (!mmio)
915 return -ENOMEM;
7b6dbd68 916
1da177e4
LT		 917 tmp = readl(mmio + AHCI_GLOBAL_CTL);
918 if (tmp & AHCI_ENABLE) {
919 tmp &= ~AHCI_ENABLE;
920 writel(tmp, mmio + AHCI_GLOBAL_CTL);
921
922 tmp = readl(mmio + AHCI_GLOBAL_CTL);
923 if (tmp & AHCI_ENABLE)
924 rc = -EIO;
925 }
7b6dbd68 926
374b1873 927 pci_iounmap(pdev, mmio);
1da177e4
LT		 928 return rc;
929}
930
c621b140
AC		 931/**
932 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 933 * @ata_dev: the PCI device to check
2e9edbf8 934 *
c621b140
AC		 935 * Check for the present of 450NX errata #19 and errata #25. If
936 * they are found return an error code so we can turn off DMA
937 */
938
939static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
940{
941 struct pci_dev *pdev = NULL;
942 u16 cfg;
943 u8 rev;
944 int no_piix_dma = 0;
2e9edbf8 945
c621b140
AC		 946 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
947 {
948 /* Look for 450NX PXB. Check for problem configurations
949 A PCI quirk checks bit 6 already */
950 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
951 pci_read_config_word(pdev, 0x41, &cfg);
952 /* Only on the original revision: IDE DMA can hang */
31a34fe7 953 if (rev == 0x00)
c621b140
AC		 954 no_piix_dma = 1;
955 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
31a34fe7 956 else if (cfg & (1<<14) && rev < 5)
c621b140
AC		 957 no_piix_dma = 2;
958 }
31a34fe7 959 if (no_piix_dma)
c621b140 960 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 961 if (no_piix_dma == 2)
c621b140
AC		 962 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
963 return no_piix_dma;
2e9edbf8 964}
c621b140 965
ea35d29e 966static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 967 struct ata_port_info *pinfo,
ea35d29e
JG		 968 const struct piix_map_db *map_db)
969{
970 u16 pcs, new_pcs;
971
972 pci_read_config_word(pdev, ICH5_PCS, &pcs);
973
974 new_pcs = pcs | map_db->port_enable;
975
976 if (new_pcs != pcs) {
977 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
978 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
979 msleep(150);
980 }
981}
982
d33f58b8 983static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 984 struct ata_port_info *pinfo,
985 const struct piix_map_db *map_db)
d33f58b8 986{
d96715c1 987 struct piix_host_priv *hpriv = pinfo[0].private_data;
d33f58b8
TH		 988 const unsigned int *map;
989 int i, invalid_map = 0;
990 u8 map_value;
991
992 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
993
994 map = map_db->map[map_value & map_db->mask];
995
996 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
997 for (i = 0; i < 4; i++) {
998 switch (map[i]) {
999 case RV:
1000 invalid_map = 1;
1001 printk(" XX");
1002 break;
1003
1004 case NA:
1005 printk(" --");
1006 break;
1007
1008 case IDE:
1009 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1010 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1011 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1012 i++;
1013 printk(" IDE IDE");
1014 break;
1015
1016 default:
1017 printk(" P%d", map[i]);
1018 if (i & 1)
cca3974e 1019 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1020 break;
1021 }
1022 }
1023 printk(" ]\n");
1024
1025 if (invalid_map)
1026 dev_printk(KERN_ERR, &pdev->dev,
1027 "invalid MAP value %u\n", map_value);
1028
d96715c1 1029 hpriv->map = map;
d33f58b8
TH		 1030}
1031
1da177e4
LT		 1032/**
1033 * piix_init_one - Register PIIX ATA PCI device with kernel services
1034 * @pdev: PCI device to register
1035 * @ent: Entry in piix_pci_tbl matching with @pdev
1036 *
1037 * Called from kernel PCI layer. We probe for combined mode (sigh),
1038 * and then hand over control to libata, for it to do the rest.
1039 *
1040 * LOCKING:
1041 * Inherited from PCI layer (may sleep).
1042 *
1043 * RETURNS:
1044 * Zero on success, or -ERRNO value.
1045 */
1046
1047static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1048{
1049 static int printed_version;
d33f58b8
TH		 1050 struct ata_port_info port_info[2];
1051 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
d96715c1 1052 struct piix_host_priv *hpriv;
cca3974e 1053 unsigned long port_flags;
1da177e4
LT		 1054
1055 if (!printed_version++)
6248e647
JG		 1056 dev_printk(KERN_DEBUG, &pdev->dev,
1057 "version " DRV_VERSION "\n");
1da177e4
LT		 1058
1059 /* no hotplugging support (FIXME) */
1060 if (!in_module_init)
1061 return -ENODEV;
1062
d96715c1
TH		 1063 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1064 if (!hpriv)
1065 return -ENOMEM;
1066
d33f58b8
TH		 1067 port_info[0] = piix_port_info[ent->driver_data];
1068 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1069 port_info[0].private_data = hpriv;
1070 port_info[1].private_data = hpriv;
1da177e4 1071
cca3974e 1072 port_flags = port_info[0].flags;
ff0fc146 1073
cca3974e 1074 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1075 u8 tmp;
1076 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1077 if (tmp == PIIX_AHCI_DEVICE) {
1078 int rc = piix_disable_ahci(pdev);
1079 if (rc)
1080 return rc;
1081 }
1da177e4
LT		 1082 }
1083
d33f58b8 1084 /* Initialize SATA map */
cca3974e 1085 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1086 piix_init_sata_map(pdev, port_info,
1087 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1088 piix_init_pcs(pdev, port_info,
1089 piix_map_db_table[ent->driver_data]);
ea35d29e 1090 }
1da177e4
LT		 1091
1092 /* On ICH5, some BIOSen disable the interrupt using the
1093 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1094 * On ICH6, this bit has the same effect, but only when
1095 * MSI is disabled (and it is disabled, as we don't use
1096 * message-signalled interrupts currently).
1097 */
cca3974e 1098 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1099 pci_intx(pdev, 1);
1da177e4 1100
c621b140
AC		 1101 if (piix_check_450nx_errata(pdev)) {
1102 /* This writes into the master table but it does not
1103 really matter for this errata as we will apply it to
1104 all the PIIX devices on the board */
d33f58b8
TH		 1105 port_info[0].mwdma_mask = 0;
1106 port_info[0].udma_mask = 0;
1107 port_info[1].mwdma_mask = 0;
1108 port_info[1].udma_mask = 0;
c621b140 1109 }
d33f58b8 1110 return ata_pci_init_one(pdev, ppinfo, 2);
1da177e4
LT		 1111}
1112
cca3974e 1113static void piix_host_stop(struct ata_host *host)
d96715c1 1114{
cca3974e 1115 struct piix_host_priv *hpriv = host->private_data;
24dd01bf 1116
cca3974e 1117 ata_host_stop(host);
24dd01bf
JG		 1118
1119 kfree(hpriv);
d96715c1
TH		 1120}
1121
1da177e4
LT		 1122static int __init piix_init(void)
1123{
1124 int rc;
1125
b7887196
PR		 1126 DPRINTK("pci_register_driver\n");
1127 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1128 if (rc)
1129 return rc;
1130
1131 in_module_init = 0;
1132
1133 DPRINTK("done\n");
1134 return 0;
1135}
1136
1da177e4
LT		 1137static void __exit piix_exit(void)
1138{
1139 pci_unregister_driver(&piix_pci_driver);
1140}
1141
1142module_init(piix_init);
1143module_exit(piix_exit);