projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
libata: kill ATA_LFLAG_SKIP_D2H_BSY
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
a22e6444
TH		 52static int ahci_skip_host_reset;
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
31556594
KCA		 56static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58static void ahci_disable_alpm(struct ata_port *ap);
1da177e4
LT		 59
60enum {
61 AHCI_PCI_BAR = 5,
648a88be 62 AHCI_MAX_PORTS = 32,
1da177e4
LT		 63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
be5d8218 65 AHCI_USE_CLUSTERING = 1,
12fad3f9 66 AHCI_MAX_CMDS = 32,
dd410ff1 67 AHCI_CMD_SZ = 32,
12fad3f9 68 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 69 AHCI_RX_FIS_SZ = 256,
a0ea7328 70 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 71 AHCI_CMD_TBL_HDR_SZ = 0x80,
72 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
73 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
74 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 75 AHCI_RX_FIS_SZ,
76 AHCI_IRQ_ON_SG = (1 << 31),
77 AHCI_CMD_ATAPI = (1 << 5),
78 AHCI_CMD_WRITE = (1 << 6),
4b10e559 79 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 80 AHCI_CMD_RESET = (1 << 8),
81 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 82
83 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 84 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 85 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 86
87 board_ahci = 0,
7a234aff
TH		 88 board_ahci_vt8251 = 1,
89 board_ahci_ign_iferr = 2,
90 board_ahci_sb600 = 3,
91 board_ahci_mv = 4,
e39fc8c9 92 board_ahci_sb700 = 5,
1da177e4
LT		 93
94 /* global controller registers */
95 HOST_CAP = 0x00, /* host capabilities */
96 HOST_CTL = 0x04, /* global host control */
97 HOST_IRQ_STAT = 0x08, /* interrupt status */
98 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
99 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
100
101 /* HOST_CTL bits */
102 HOST_RESET = (1 << 0), /* reset controller; self-clear */
103 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
104 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
105
106 /* HOST_CAP bits */
0be0aa98 107 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 108 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 109 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 110 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 111 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 112 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 113 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 114 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 115
116 /* registers for each SATA port */
117 PORT_LST_ADDR = 0x00, /* command list DMA addr */
118 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
119 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
120 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
121 PORT_IRQ_STAT = 0x10, /* interrupt status */
122 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
123 PORT_CMD = 0x18, /* port command */
124 PORT_TFDATA = 0x20, /* taskfile data */
125 PORT_SIG = 0x24, /* device TF signature */
126 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 127 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
128 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
129 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
130 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 131 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 132
133 /* PORT_IRQ_{STAT,MASK} bits */
134 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
135 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
136 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
137 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
138 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
139 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
140 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
141 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
142
143 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
144 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
145 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
146 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
147 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
148 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
149 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
150 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
151 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
152
78cd52d0
TH		 153 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
154 PORT_IRQ_IF_ERR |
155 PORT_IRQ_CONNECT |
4296971d 156 PORT_IRQ_PHYRDY |
7d50b60b
TH		 157 PORT_IRQ_UNK_FIS |
158 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 159 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
160 PORT_IRQ_TF_ERR |
161 PORT_IRQ_HBUS_DATA_ERR,
162 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
163 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
164 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 165
166 /* PORT_CMD bits */
31556594
KCA		 167 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
168 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 169 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 170 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 171 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
172 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
173 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 174 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 175 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
176 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
177 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
178
0be0aa98 179 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 180 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
181 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
182 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 183
417a1a6d
TH		 184 /* hpriv->flags bits */
185 AHCI_HFLAG_NO_NCQ = (1 << 0),
186 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
187 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
188 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
189 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
190 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 191 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 192 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
a878539e 193 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
417a1a6d 194
bf2af2a2 195 /* ap->flags bits */
1188c0d8
TH		 196
197 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
198 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 199 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
200 ATA_FLAG_IPM,
c4f7792c
TH		 201
202 ICH_MAP = 0x90, /* ICH MAP register */
1da177e4
LT		 203};
204
205struct ahci_cmd_hdr {
4ca4e439
AV		 206 __le32 opts;
207 __le32 status;
208 __le32 tbl_addr;
209 __le32 tbl_addr_hi;
210 __le32 reserved[4];
1da177e4
LT		 211};
212
213struct ahci_sg {
4ca4e439
AV		 214 __le32 addr;
215 __le32 addr_hi;
216 __le32 reserved;
217 __le32 flags_size;
1da177e4
LT		 218};
219
220struct ahci_host_priv {
417a1a6d 221 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 222 u32 cap; /* cap to use */
223 u32 port_map; /* port map to use */
224 u32 saved_cap; /* saved initial cap */
225 u32 saved_port_map; /* saved initial port_map */
1da177e4
LT		 226};
227
228struct ahci_port_priv {
7d50b60b 229 struct ata_link *active_link;
1da177e4
LT		 230 struct ahci_cmd_hdr *cmd_slot;
231 dma_addr_t cmd_slot_dma;
232 void *cmd_tbl;
233 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 234 void *rx_fis;
235 dma_addr_t rx_fis_dma;
0291f95f 236 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 237 unsigned int ncq_saw_d2h:1;
238 unsigned int ncq_saw_dmas:1;
afb2d552 239 unsigned int ncq_saw_sdb:1;
a7384925 240 u32 intr_mask; /* interrupts to enable */
1da177e4
LT		 241};
242
da3dbb17
TH		 243static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
244static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
2dcb407e 245static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 246static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 247static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 248static int ahci_port_start(struct ata_port *ap);
249static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 250static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
251static void ahci_qc_prep(struct ata_queued_cmd *qc);
252static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 253static void ahci_freeze(struct ata_port *ap);
254static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 255static void ahci_pmp_attach(struct ata_port *ap);
256static void ahci_pmp_detach(struct ata_port *ap);
78cd52d0 257static void ahci_error_handler(struct ata_port *ap);
ad616ffb 258static void ahci_vt8251_error_handler(struct ata_port *ap);
edc93052 259static void ahci_p5wdh_error_handler(struct ata_port *ap);
78cd52d0 260static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 261static int ahci_port_resume(struct ata_port *ap);
a878539e 262static void ahci_dev_config(struct ata_device *dev);
dab632e8
JG		 263static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
264static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
265 u32 opts);
438ac6d5 266#ifdef CONFIG_PM
c1332875 267static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 268static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
269static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 270#endif
1da177e4 271
31556594
KCA		 272static struct class_device_attribute *ahci_shost_attrs[] = {
273 &class_device_attr_link_power_management_policy,
274 NULL
275};
276
193515d5 277static struct scsi_host_template ahci_sht = {
1da177e4
LT		 278 .module = THIS_MODULE,
279 .name = DRV_NAME,
280 .ioctl = ata_scsi_ioctl,
281 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 282 .change_queue_depth = ata_scsi_change_queue_depth,
283 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 284 .this_id = ATA_SHT_THIS_ID,
285 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 286 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
287 .emulated = ATA_SHT_EMULATED,
288 .use_clustering = AHCI_USE_CLUSTERING,
289 .proc_name = DRV_NAME,
290 .dma_boundary = AHCI_DMA_BOUNDARY,
291 .slave_configure = ata_scsi_slave_config,
ccf68c34 292 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 293 .bios_param = ata_std_bios_param,
31556594 294 .shost_attrs = ahci_shost_attrs,
1da177e4
LT		 295};
296
057ace5e 297static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 298 .check_status = ahci_check_status,
299 .check_altstatus = ahci_check_status,
1da177e4
LT		 300 .dev_select = ata_noop_dev_select,
301
a878539e
JG		 302 .dev_config = ahci_dev_config,
303
1da177e4
LT		 304 .tf_read = ahci_tf_read,
305
7d50b60b 306 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 307 .qc_prep = ahci_qc_prep,
308 .qc_issue = ahci_qc_issue,
309
1da177e4
LT		 310 .irq_clear = ahci_irq_clear,
311
312 .scr_read = ahci_scr_read,
313 .scr_write = ahci_scr_write,
314
78cd52d0
TH		 315 .freeze = ahci_freeze,
316 .thaw = ahci_thaw,
317
318 .error_handler = ahci_error_handler,
319 .post_internal_cmd = ahci_post_internal_cmd,
320
7d50b60b
TH		 321 .pmp_attach = ahci_pmp_attach,
322 .pmp_detach = ahci_pmp_detach,
7d50b60b 323
438ac6d5 324#ifdef CONFIG_PM
c1332875
TH		 325 .port_suspend = ahci_port_suspend,
326 .port_resume = ahci_port_resume,
438ac6d5 327#endif
31556594
KCA		 328 .enable_pm = ahci_enable_alpm,
329 .disable_pm = ahci_disable_alpm,
c1332875 330
1da177e4
LT		 331 .port_start = ahci_port_start,
332 .port_stop = ahci_port_stop,
1da177e4
LT		 333};
334
ad616ffb 335static const struct ata_port_operations ahci_vt8251_ops = {
ad616ffb
TH		 336 .check_status = ahci_check_status,
337 .check_altstatus = ahci_check_status,
338 .dev_select = ata_noop_dev_select,
339
340 .tf_read = ahci_tf_read,
341
7d50b60b 342 .qc_defer = sata_pmp_qc_defer_cmd_switch,
ad616ffb
TH		 343 .qc_prep = ahci_qc_prep,
344 .qc_issue = ahci_qc_issue,
345
ad616ffb
TH		 346 .irq_clear = ahci_irq_clear,
347
348 .scr_read = ahci_scr_read,
349 .scr_write = ahci_scr_write,
350
351 .freeze = ahci_freeze,
352 .thaw = ahci_thaw,
353
354 .error_handler = ahci_vt8251_error_handler,
355 .post_internal_cmd = ahci_post_internal_cmd,
356
7d50b60b
TH		 357 .pmp_attach = ahci_pmp_attach,
358 .pmp_detach = ahci_pmp_detach,
7d50b60b 359
438ac6d5 360#ifdef CONFIG_PM
ad616ffb
TH		 361 .port_suspend = ahci_port_suspend,
362 .port_resume = ahci_port_resume,
438ac6d5 363#endif
ad616ffb
TH		 364
365 .port_start = ahci_port_start,
366 .port_stop = ahci_port_stop,
367};
368
edc93052
TH		 369static const struct ata_port_operations ahci_p5wdh_ops = {
370 .check_status = ahci_check_status,
371 .check_altstatus = ahci_check_status,
372 .dev_select = ata_noop_dev_select,
373
374 .tf_read = ahci_tf_read,
375
376 .qc_defer = sata_pmp_qc_defer_cmd_switch,
377 .qc_prep = ahci_qc_prep,
378 .qc_issue = ahci_qc_issue,
379
380 .irq_clear = ahci_irq_clear,
381
382 .scr_read = ahci_scr_read,
383 .scr_write = ahci_scr_write,
384
385 .freeze = ahci_freeze,
386 .thaw = ahci_thaw,
387
388 .error_handler = ahci_p5wdh_error_handler,
389 .post_internal_cmd = ahci_post_internal_cmd,
390
391 .pmp_attach = ahci_pmp_attach,
392 .pmp_detach = ahci_pmp_detach,
393
394#ifdef CONFIG_PM
395 .port_suspend = ahci_port_suspend,
396 .port_resume = ahci_port_resume,
397#endif
398
399 .port_start = ahci_port_start,
400 .port_stop = ahci_port_stop,
401};
402
417a1a6d
TH		 403#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
404
98ac62de 405static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 406 /* board_ahci */
407 {
1188c0d8 408 .flags = AHCI_FLAG_COMMON,
7da79312 409 .pio_mask = 0x1f, /* pio0-4 */
469248ab 410 .udma_mask = ATA_UDMA6,
1da177e4
LT		 411 .port_ops = &ahci_ops,
412 },
bf2af2a2
BJ		 413 /* board_ahci_vt8251 */
414 {
6949b914 415 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 416 .flags = AHCI_FLAG_COMMON,
bf2af2a2 417 .pio_mask = 0x1f, /* pio0-4 */
469248ab 418 .udma_mask = ATA_UDMA6,
ad616ffb 419 .port_ops = &ahci_vt8251_ops,
bf2af2a2 420 },
41669553
TH		 421 /* board_ahci_ign_iferr */
422 {
417a1a6d
TH		 423 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
424 .flags = AHCI_FLAG_COMMON,
41669553 425 .pio_mask = 0x1f, /* pio0-4 */
469248ab 426 .udma_mask = ATA_UDMA6,
41669553
TH		 427 .port_ops = &ahci_ops,
428 },
55a61604
CH		 429 /* board_ahci_sb600 */
430 {
417a1a6d 431 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
4cde32fc 432 AHCI_HFLAG_32BIT_ONLY |
a878539e 433 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
417a1a6d 434 .flags = AHCI_FLAG_COMMON,
55a61604 435 .pio_mask = 0x1f, /* pio0-4 */
469248ab 436 .udma_mask = ATA_UDMA6,
55a61604
CH		 437 .port_ops = &ahci_ops,
438 },
cd70c266
JG		 439 /* board_ahci_mv */
440 {
417a1a6d
TH		 441 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
442 AHCI_HFLAG_MV_PATA),
cd70c266 443 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 444 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
cd70c266
JG		 445 .pio_mask = 0x1f, /* pio0-4 */
446 .udma_mask = ATA_UDMA6,
447 .port_ops = &ahci_ops,
448 },
e39fc8c9
SH		 449 /* board_ahci_sb700 */
450 {
451 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
452 AHCI_HFLAG_NO_PMP),
453 .flags = AHCI_FLAG_COMMON,
e39fc8c9
SH		 454 .pio_mask = 0x1f, /* pio0-4 */
455 .udma_mask = ATA_UDMA6,
456 .port_ops = &ahci_ops,
457 },
1da177e4
LT		 458};
459
3b7d697d 460static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 461 /* Intel */
54bb3a94
JG		 462 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
463 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
464 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
465 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
466 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 467 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 468 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
469 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
470 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
471 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 472 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
473 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
474 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
475 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
476 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
477 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
479 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
480 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
481 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
482 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
484 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
485 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
486 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
487 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
488 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 489 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
490 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9
JG		 491 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
492 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
fe7fa31a 493
e34bb370
TH		 494 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
495 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
496 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 497
498 /* ATI */
c65ec1c2 499 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 500 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
501 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
504 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
505 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a
JG		 506
507 /* VIA */
54bb3a94 508 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 509 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 510
511 /* NVIDIA */
54bb3a94
JG		 512 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
513 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 516 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
518 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
519 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
520 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
521 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 524 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
531 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 532 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
533 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
543 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
544 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
555 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 556 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
557 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 560 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
567 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
70d562cf 568 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
569 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
574 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
578 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
579 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
fe7fa31a 580
95916edd 581 /* SiS */
54bb3a94
JG		 582 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
583 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
584 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 585
cd70c266
JG		 586 /* Marvell */
587 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 588 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 589
415ae2b5
JG		 590 /* Generic, PCI class code for AHCI */
591 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 592 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 593
1da177e4
LT		 594 { } /* terminate list */
595};
596
597
598static struct pci_driver ahci_pci_driver = {
599 .name = DRV_NAME,
600 .id_table = ahci_pci_tbl,
601 .probe = ahci_init_one,
24dc5f33 602 .remove = ata_pci_remove_one,
438ac6d5 603#ifdef CONFIG_PM
c1332875
TH		 604 .suspend = ahci_pci_device_suspend,
605 .resume = ahci_pci_device_resume,
438ac6d5 606#endif
1da177e4
LT		 607};
608
609
98fa4b60
TH		 610static inline int ahci_nr_ports(u32 cap)
611{
612 return (cap & 0x1f) + 1;
613}
614
dab632e8
JG		 615static inline void __iomem *__ahci_port_base(struct ata_host *host,
616 unsigned int port_no)
1da177e4 617{
dab632e8 618 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 619
dab632e8
JG		 620 return mmio + 0x100 + (port_no * 0x80);
621}
622
623static inline void __iomem *ahci_port_base(struct ata_port *ap)
624{
625 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 626}
627
b710a1f4
TH		 628static void ahci_enable_ahci(void __iomem *mmio)
629{
630 u32 tmp;
631
632 /* turn on AHCI_EN */
633 tmp = readl(mmio + HOST_CTL);
634 if (!(tmp & HOST_AHCI_EN)) {
635 tmp |= HOST_AHCI_EN;
636 writel(tmp, mmio + HOST_CTL);
637 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
638 WARN_ON(!(tmp & HOST_AHCI_EN));
639 }
640}
641
d447df14
TH		 642/**
643 * ahci_save_initial_config - Save and fixup initial config values
4447d351 644 * @pdev: target PCI device
4447d351 645 * @hpriv: host private area to store config values
d447df14
TH		 646 *
647 * Some registers containing configuration info might be setup by
648 * BIOS and might be cleared on reset. This function saves the
649 * initial values of those registers into @hpriv such that they
650 * can be restored after controller reset.
651 *
652 * If inconsistent, config values are fixed up by this function.
653 *
654 * LOCKING:
655 * None.
656 */
4447d351 657static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 658 struct ahci_host_priv *hpriv)
d447df14 659{
4447d351 660 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 661 u32 cap, port_map;
17199b18 662 int i;
c40e7cb8 663 int mv;
d447df14 664
b710a1f4
TH		 665 /* make sure AHCI mode is enabled before accessing CAP */
666 ahci_enable_ahci(mmio);
667
d447df14
TH		 668 /* Values prefixed with saved_ are written back to host after
669 * reset. Values without are used for driver operation.
670 */
671 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
672 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
673
274c1fde 674 /* some chips have errata preventing 64bit use */
417a1a6d 675 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 676 dev_printk(KERN_INFO, &pdev->dev,
677 "controller can't do 64bit DMA, forcing 32bit\n");
678 cap &= ~HOST_CAP_64;
679 }
680
417a1a6d 681 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 682 dev_printk(KERN_INFO, &pdev->dev,
683 "controller can't do NCQ, turning off CAP_NCQ\n");
684 cap &= ~HOST_CAP_NCQ;
685 }
686
258cd846 687 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
6949b914
TH		 688 dev_printk(KERN_INFO, &pdev->dev,
689 "controller can't do PMP, turning off CAP_PMP\n");
690 cap &= ~HOST_CAP_PMP;
691 }
692
cd70c266
JG		 693 /*
694 * Temporary Marvell 6145 hack: PATA port presence
695 * is asserted through the standard AHCI port
696 * presence register, as bit 4 (counting from 0)
697 */
417a1a6d 698 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 699 if (pdev->device == 0x6121)
700 mv = 0x3;
701 else
702 mv = 0xf;
cd70c266
JG		 703 dev_printk(KERN_ERR, &pdev->dev,
704 "MV_AHCI HACK: port_map %x -> %x\n",
c40e7cb8
JAR		 705 port_map,
706 port_map & mv);
cd70c266 707
c40e7cb8 708 port_map &= mv;
cd70c266
JG		 709 }
710
17199b18 711 /* cross check port_map and cap.n_ports */
7a234aff 712 if (port_map) {
837f5f8f 713 int map_ports = 0;
17199b18 714
837f5f8f
TH		 715 for (i = 0; i < AHCI_MAX_PORTS; i++)
716 if (port_map & (1 << i))
717 map_ports++;
17199b18 718
837f5f8f
TH		 719 /* If PI has more ports than n_ports, whine, clear
720 * port_map and let it be generated from n_ports.
17199b18 721 */
837f5f8f 722 if (map_ports > ahci_nr_ports(cap)) {
4447d351 723 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 724 "implemented port map (0x%x) contains more "
725 "ports than nr_ports (%u), using nr_ports\n",
726 port_map, ahci_nr_ports(cap));
7a234aff
TH		 727 port_map = 0;
728 }
729 }
730
731 /* fabricate port_map from cap.nr_ports */
732 if (!port_map) {
17199b18 733 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 734 dev_printk(KERN_WARNING, &pdev->dev,
735 "forcing PORTS_IMPL to 0x%x\n", port_map);
736
737 /* write the fixed up value to the PI register */
738 hpriv->saved_port_map = port_map;
17199b18
TH		 739 }
740
d447df14
TH		 741 /* record values to use during operation */
742 hpriv->cap = cap;
743 hpriv->port_map = port_map;
744}
745
746/**
747 * ahci_restore_initial_config - Restore initial config
4447d351 748 * @host: target ATA host
d447df14
TH		 749 *
750 * Restore initial config stored by ahci_save_initial_config().
751 *
752 * LOCKING:
753 * None.
754 */
4447d351 755static void ahci_restore_initial_config(struct ata_host *host)
d447df14 756{
4447d351
TH		 757 struct ahci_host_priv *hpriv = host->private_data;
758 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
759
d447df14
TH		 760 writel(hpriv->saved_cap, mmio + HOST_CAP);
761 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
762 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
763}
764
203ef6c4 765static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 766{
203ef6c4
TH		 767 static const int offset[] = {
768 [SCR_STATUS] = PORT_SCR_STAT,
769 [SCR_CONTROL] = PORT_SCR_CTL,
770 [SCR_ERROR] = PORT_SCR_ERR,
771 [SCR_ACTIVE] = PORT_SCR_ACT,
772 [SCR_NOTIFICATION] = PORT_SCR_NTF,
773 };
774 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 775
203ef6c4
TH		 776 if (sc_reg < ARRAY_SIZE(offset) &&
777 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
778 return offset[sc_reg];
da3dbb17 779 return 0;
1da177e4
LT		 780}
781
203ef6c4 782static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 783{
203ef6c4
TH		 784 void __iomem *port_mmio = ahci_port_base(ap);
785 int offset = ahci_scr_offset(ap, sc_reg);
786
787 if (offset) {
788 *val = readl(port_mmio + offset);
789 return 0;
1da177e4 790 }
203ef6c4
TH		 791 return -EINVAL;
792}
1da177e4 793
203ef6c4
TH		 794static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
795{
796 void __iomem *port_mmio = ahci_port_base(ap);
797 int offset = ahci_scr_offset(ap, sc_reg);
798
799 if (offset) {
800 writel(val, port_mmio + offset);
801 return 0;
802 }
803 return -EINVAL;
1da177e4
LT		 804}
805
4447d351 806static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 807{
4447d351 808 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 809 u32 tmp;
810
d8fcd116 811 /* start DMA */
9f592056 812 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 813 tmp |= PORT_CMD_START;
814 writel(tmp, port_mmio + PORT_CMD);
815 readl(port_mmio + PORT_CMD); /* flush */
816}
817
4447d351 818static int ahci_stop_engine(struct ata_port *ap)
254950cd 819{
4447d351 820 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 821 u32 tmp;
822
823 tmp = readl(port_mmio + PORT_CMD);
824
d8fcd116 825 /* check if the HBA is idle */
254950cd
TH		 826 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
827 return 0;
828
d8fcd116 829 /* setting HBA to idle */
254950cd
TH		 830 tmp &= ~PORT_CMD_START;
831 writel(tmp, port_mmio + PORT_CMD);
832
d8fcd116 833 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 834 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 835 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 836 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 837 return -EIO;
838
839 return 0;
840}
841
4447d351 842static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 843{
4447d351
TH		 844 void __iomem *port_mmio = ahci_port_base(ap);
845 struct ahci_host_priv *hpriv = ap->host->private_data;
846 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 847 u32 tmp;
848
849 /* set FIS registers */
4447d351
TH		 850 if (hpriv->cap & HOST_CAP_64)
851 writel((pp->cmd_slot_dma >> 16) >> 16,
852 port_mmio + PORT_LST_ADDR_HI);
853 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 854
4447d351
TH		 855 if (hpriv->cap & HOST_CAP_64)
856 writel((pp->rx_fis_dma >> 16) >> 16,
857 port_mmio + PORT_FIS_ADDR_HI);
858 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 859
860 /* enable FIS reception */
861 tmp = readl(port_mmio + PORT_CMD);
862 tmp |= PORT_CMD_FIS_RX;
863 writel(tmp, port_mmio + PORT_CMD);
864
865 /* flush */
866 readl(port_mmio + PORT_CMD);
867}
868
4447d351 869static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 870{
4447d351 871 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 872 u32 tmp;
873
874 /* disable FIS reception */
875 tmp = readl(port_mmio + PORT_CMD);
876 tmp &= ~PORT_CMD_FIS_RX;
877 writel(tmp, port_mmio + PORT_CMD);
878
879 /* wait for completion, spec says 500ms, give it 1000 */
880 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
881 PORT_CMD_FIS_ON, 10, 1000);
882 if (tmp & PORT_CMD_FIS_ON)
883 return -EBUSY;
884
885 return 0;
886}
887
4447d351 888static void ahci_power_up(struct ata_port *ap)
0be0aa98 889{
4447d351
TH		 890 struct ahci_host_priv *hpriv = ap->host->private_data;
891 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 892 u32 cmd;
893
894 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
895
896 /* spin up device */
4447d351 897 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 898 cmd |= PORT_CMD_SPIN_UP;
899 writel(cmd, port_mmio + PORT_CMD);
900 }
901
902 /* wake up link */
903 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
904}
905
31556594
KCA		 906static void ahci_disable_alpm(struct ata_port *ap)
907{
908 struct ahci_host_priv *hpriv = ap->host->private_data;
909 void __iomem *port_mmio = ahci_port_base(ap);
910 u32 cmd;
911 struct ahci_port_priv *pp = ap->private_data;
912
913 /* IPM bits should be disabled by libata-core */
914 /* get the existing command bits */
915 cmd = readl(port_mmio + PORT_CMD);
916
917 /* disable ALPM and ASP */
918 cmd &= ~PORT_CMD_ASP;
919 cmd &= ~PORT_CMD_ALPE;
920
921 /* force the interface back to active */
922 cmd |= PORT_CMD_ICC_ACTIVE;
923
924 /* write out new cmd value */
925 writel(cmd, port_mmio + PORT_CMD);
926 cmd = readl(port_mmio + PORT_CMD);
927
928 /* wait 10ms to be sure we've come out of any low power state */
929 msleep(10);
930
931 /* clear out any PhyRdy stuff from interrupt status */
932 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
933
934 /* go ahead and clean out PhyRdy Change from Serror too */
935 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
936
937 /*
938 * Clear flag to indicate that we should ignore all PhyRdy
939 * state changes
940 */
941 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
942
943 /*
944 * Enable interrupts on Phy Ready.
945 */
946 pp->intr_mask |= PORT_IRQ_PHYRDY;
947 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
948
949 /*
950 * don't change the link pm policy - we can be called
951 * just to turn of link pm temporarily
952 */
953}
954
955static int ahci_enable_alpm(struct ata_port *ap,
956 enum link_pm policy)
957{
958 struct ahci_host_priv *hpriv = ap->host->private_data;
959 void __iomem *port_mmio = ahci_port_base(ap);
960 u32 cmd;
961 struct ahci_port_priv *pp = ap->private_data;
962 u32 asp;
963
964 /* Make sure the host is capable of link power management */
965 if (!(hpriv->cap & HOST_CAP_ALPM))
966 return -EINVAL;
967
968 switch (policy) {
969 case MAX_PERFORMANCE:
970 case NOT_AVAILABLE:
971 /*
972 * if we came here with NOT_AVAILABLE,
973 * it just means this is the first time we
974 * have tried to enable - default to max performance,
975 * and let the user go to lower power modes on request.
976 */
977 ahci_disable_alpm(ap);
978 return 0;
979 case MIN_POWER:
980 /* configure HBA to enter SLUMBER */
981 asp = PORT_CMD_ASP;
982 break;
983 case MEDIUM_POWER:
984 /* configure HBA to enter PARTIAL */
985 asp = 0;
986 break;
987 default:
988 return -EINVAL;
989 }
990
991 /*
992 * Disable interrupts on Phy Ready. This keeps us from
993 * getting woken up due to spurious phy ready interrupts
994 * TBD - Hot plug should be done via polling now, is
995 * that even supported?
996 */
997 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
998 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
999
1000 /*
1001 * Set a flag to indicate that we should ignore all PhyRdy
1002 * state changes since these can happen now whenever we
1003 * change link state
1004 */
1005 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1006
1007 /* get the existing command bits */
1008 cmd = readl(port_mmio + PORT_CMD);
1009
1010 /*
1011 * Set ASP based on Policy
1012 */
1013 cmd |= asp;
1014
1015 /*
1016 * Setting this bit will instruct the HBA to aggressively
1017 * enter a lower power link state when it's appropriate and
1018 * based on the value set above for ASP
1019 */
1020 cmd |= PORT_CMD_ALPE;
1021
1022 /* write out new cmd value */
1023 writel(cmd, port_mmio + PORT_CMD);
1024 cmd = readl(port_mmio + PORT_CMD);
1025
1026 /* IPM bits should be set by libata-core */
1027 return 0;
1028}
1029
438ac6d5 1030#ifdef CONFIG_PM
4447d351 1031static void ahci_power_down(struct ata_port *ap)
0be0aa98 1032{
4447d351
TH		 1033 struct ahci_host_priv *hpriv = ap->host->private_data;
1034 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1035 u32 cmd, scontrol;
1036
4447d351 1037 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1038 return;
0be0aa98 1039
07c53dac
TH		 1040 /* put device into listen mode, first set PxSCTL.DET to 0 */
1041 scontrol = readl(port_mmio + PORT_SCR_CTL);
1042 scontrol &= ~0xf;
1043 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1044
07c53dac
TH		 1045 /* then set PxCMD.SUD to 0 */
1046 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1047 cmd &= ~PORT_CMD_SPIN_UP;
1048 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1049}
438ac6d5 1050#endif
0be0aa98 1051
df69c9c5 1052static void ahci_start_port(struct ata_port *ap)
0be0aa98 1053{
0be0aa98 1054 /* enable FIS reception */
4447d351 1055 ahci_start_fis_rx(ap);
0be0aa98
TH		 1056
1057 /* enable DMA */
4447d351 1058 ahci_start_engine(ap);
0be0aa98
TH		 1059}
1060
4447d351 1061static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1062{
1063 int rc;
1064
1065 /* disable DMA */
4447d351 1066 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1067 if (rc) {
1068 *emsg = "failed to stop engine";
1069 return rc;
1070 }
1071
1072 /* disable FIS reception */
4447d351 1073 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1074 if (rc) {
1075 *emsg = "failed stop FIS RX";
1076 return rc;
1077 }
1078
0be0aa98
TH		 1079 return 0;
1080}
1081
4447d351 1082static int ahci_reset_controller(struct ata_host *host)
d91542c1 1083{
4447d351 1084 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1085 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1086 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1087 u32 tmp;
d91542c1 1088
3cc3eb11
JG		 1089 /* we must be in AHCI mode, before using anything
1090 * AHCI-specific, such as HOST_RESET.
1091 */
b710a1f4 1092 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1093
1094 /* global controller reset */
a22e6444
TH		 1095 if (!ahci_skip_host_reset) {
1096 tmp = readl(mmio + HOST_CTL);
1097 if ((tmp & HOST_RESET) == 0) {
1098 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1099 readl(mmio + HOST_CTL); /* flush */
1100 }
d91542c1 1101
a22e6444
TH		 1102 /* reset must complete within 1 second, or
1103 * the hardware should be considered fried.
1104 */
1105 ssleep(1);
d91542c1 1106
a22e6444
TH		 1107 tmp = readl(mmio + HOST_CTL);
1108 if (tmp & HOST_RESET) {
1109 dev_printk(KERN_ERR, host->dev,
1110 "controller reset failed (0x%x)\n", tmp);
1111 return -EIO;
1112 }
d91542c1 1113
a22e6444
TH		 1114 /* turn on AHCI mode */
1115 ahci_enable_ahci(mmio);
98fa4b60 1116
a22e6444
TH		 1117 /* Some registers might be cleared on reset. Restore
1118 * initial values.
1119 */
1120 ahci_restore_initial_config(host);
1121 } else
1122 dev_printk(KERN_INFO, host->dev,
1123 "skipping global host reset\n");
d91542c1
TH		 1124
1125 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1126 u16 tmp16;
1127
1128 /* configure PCS */
1129 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1130 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1131 tmp16 |= hpriv->port_map;
1132 pci_write_config_word(pdev, 0x92, tmp16);
1133 }
d91542c1
TH		 1134 }
1135
1136 return 0;
1137}
1138
2bcd866b
JG		 1139static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1140 int port_no, void __iomem *mmio,
1141 void __iomem *port_mmio)
1142{
1143 const char *emsg = NULL;
1144 int rc;
1145 u32 tmp;
1146
1147 /* make sure port is not active */
1148 rc = ahci_deinit_port(ap, &emsg);
1149 if (rc)
1150 dev_printk(KERN_WARNING, &pdev->dev,
1151 "%s (%d)\n", emsg, rc);
1152
1153 /* clear SError */
1154 tmp = readl(port_mmio + PORT_SCR_ERR);
1155 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1156 writel(tmp, port_mmio + PORT_SCR_ERR);
1157
1158 /* clear port IRQ */
1159 tmp = readl(port_mmio + PORT_IRQ_STAT);
1160 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1161 if (tmp)
1162 writel(tmp, port_mmio + PORT_IRQ_STAT);
1163
1164 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1165}
1166
4447d351 1167static void ahci_init_controller(struct ata_host *host)
d91542c1 1168{
417a1a6d 1169 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1170 struct pci_dev *pdev = to_pci_dev(host->dev);
1171 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1172 int i;
cd70c266 1173 void __iomem *port_mmio;
d91542c1 1174 u32 tmp;
c40e7cb8 1175 int mv;
d91542c1 1176
417a1a6d 1177 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 1178 if (pdev->device == 0x6121)
1179 mv = 2;
1180 else
1181 mv = 4;
1182 port_mmio = __ahci_port_base(host, mv);
cd70c266
JG		 1183
1184 writel(0, port_mmio + PORT_IRQ_MASK);
1185
1186 /* clear port IRQ */
1187 tmp = readl(port_mmio + PORT_IRQ_STAT);
1188 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1189 if (tmp)
1190 writel(tmp, port_mmio + PORT_IRQ_STAT);
1191 }
1192
4447d351
TH		 1193 for (i = 0; i < host->n_ports; i++) {
1194 struct ata_port *ap = host->ports[i];
d91542c1 1195
cd70c266 1196 port_mmio = ahci_port_base(ap);
4447d351 1197 if (ata_port_is_dummy(ap))
d91542c1 1198 continue;
d91542c1 1199
2bcd866b 1200 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1201 }
1202
1203 tmp = readl(mmio + HOST_CTL);
1204 VPRINTK("HOST_CTL 0x%x\n", tmp);
1205 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1206 tmp = readl(mmio + HOST_CTL);
1207 VPRINTK("HOST_CTL 0x%x\n", tmp);
1208}
1209
a878539e
JG		 1210static void ahci_dev_config(struct ata_device *dev)
1211{
1212 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1213
4cde32fc 1214 if (hpriv->flags & AHCI_HFLAG_SECT255) {
a878539e 1215 dev->max_sectors = 255;
4cde32fc
JG		 1216 ata_dev_printk(dev, KERN_INFO,
1217 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1218 }
a878539e
JG		 1219}
1220
422b7595 1221static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1222{
4447d351 1223 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1224 struct ata_taskfile tf;
422b7595
TH		 1225 u32 tmp;
1226
1227 tmp = readl(port_mmio + PORT_SIG);
1228 tf.lbah = (tmp >> 24) & 0xff;
1229 tf.lbam = (tmp >> 16) & 0xff;
1230 tf.lbal = (tmp >> 8) & 0xff;
1231 tf.nsect = (tmp) & 0xff;
1232
1233 return ata_dev_classify(&tf);
1234}
1235
12fad3f9
TH		 1236static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1237 u32 opts)
cc9278ed 1238{
12fad3f9
TH		 1239 dma_addr_t cmd_tbl_dma;
1240
1241 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1242
1243 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1244 pp->cmd_slot[tag].status = 0;
1245 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1246 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1247}
1248
d2e75dff 1249static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1250{
0d5ff566 1251 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 1252 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2 1253 u32 tmp;
d2e75dff 1254 int busy, rc;
bf2af2a2 1255
d2e75dff
TH		 1256 /* do we need to kick the port? */
1257 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1258 if (!busy && !force_restart)
1259 return 0;
1260
1261 /* stop engine */
1262 rc = ahci_stop_engine(ap);
1263 if (rc)
1264 goto out_restart;
1265
1266 /* need to do CLO? */
1267 if (!busy) {
1268 rc = 0;
1269 goto out_restart;
1270 }
1271
1272 if (!(hpriv->cap & HOST_CAP_CLO)) {
1273 rc = -EOPNOTSUPP;
1274 goto out_restart;
1275 }
bf2af2a2 1276
d2e75dff 1277 /* perform CLO */
bf2af2a2
BJ		 1278 tmp = readl(port_mmio + PORT_CMD);
1279 tmp |= PORT_CMD_CLO;
1280 writel(tmp, port_mmio + PORT_CMD);
1281
d2e75dff 1282 rc = 0;
bf2af2a2
BJ		 1283 tmp = ata_wait_register(port_mmio + PORT_CMD,
1284 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1285 if (tmp & PORT_CMD_CLO)
d2e75dff 1286 rc = -EIO;
bf2af2a2 1287
d2e75dff
TH		 1288 /* restart engine */
1289 out_restart:
1290 ahci_start_engine(ap);
1291 return rc;
bf2af2a2
BJ		 1292}
1293
91c4a2e0
TH		 1294static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1295 struct ata_taskfile *tf, int is_cmd, u16 flags,
1296 unsigned long timeout_msec)
bf2af2a2 1297{
91c4a2e0 1298 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1299 struct ahci_port_priv *pp = ap->private_data;
4447d351 1300 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1301 u8 *fis = pp->cmd_tbl;
1302 u32 tmp;
1303
1304 /* prep the command */
1305 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1306 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1307
1308 /* issue & wait */
1309 writel(1, port_mmio + PORT_CMD_ISSUE);
1310
1311 if (timeout_msec) {
1312 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1313 1, timeout_msec);
1314 if (tmp & 0x1) {
1315 ahci_kick_engine(ap, 1);
1316 return -EBUSY;
1317 }
1318 } else
1319 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1320
1321 return 0;
1322}
1323
cc0680a5 1324static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85 1325 int pmp, unsigned long deadline)
91c4a2e0 1326{
cc0680a5 1327 struct ata_port *ap = link->ap;
4658f79b 1328 const char *reason = NULL;
2cbb79eb 1329 unsigned long now, msecs;
4658f79b 1330 struct ata_taskfile tf;
4658f79b
TH		 1331 int rc;
1332
1333 DPRINTK("ENTER\n");
1334
cc0680a5 1335 if (ata_link_offline(link)) {
c2a65852
TH		 1336 DPRINTK("PHY reports no device\n");
1337 *class = ATA_DEV_NONE;
1338 return 0;
1339 }
1340
4658f79b 1341 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1342 rc = ahci_kick_engine(ap, 1);
994056d7 1343 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1344 ata_link_printk(link, KERN_WARNING,
994056d7 1345 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1346
cc0680a5 1347 ata_tf_init(link->device, &tf);
4658f79b
TH		 1348
1349 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1350 msecs = 0;
1351 now = jiffies;
1352 if (time_after(now, deadline))
1353 msecs = jiffies_to_msecs(deadline - now);
1354
4658f79b 1355 tf.ctl |= ATA_SRST;
a9cf5e85 1356 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1357 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1358 rc = -EIO;
1359 reason = "1st FIS failed";
1360 goto fail;
1361 }
1362
1363 /* spec says at least 5us, but be generous and sleep for 1ms */
1364 msleep(1);
1365
1366 /* issue the second D2H Register FIS */
4658f79b 1367 tf.ctl &= ~ATA_SRST;
a9cf5e85 1368 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1369
88ff6eaf
TH		 1370 /* wait a while before checking status */
1371 ata_wait_after_reset(ap, deadline);
4658f79b 1372
9b89391c
TH		 1373 rc = ata_wait_ready(ap, deadline);
1374 /* link occupied, -ENODEV too is an error */
1375 if (rc) {
1376 reason = "device not ready";
1377 goto fail;
4658f79b 1378 }
9b89391c 1379 *class = ahci_dev_classify(ap);
4658f79b
TH		 1380
1381 DPRINTK("EXIT, class=%u\n", *class);
1382 return 0;
1383
4658f79b 1384 fail:
cc0680a5 1385 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1386 return rc;
1387}
1388
cc0680a5 1389static int ahci_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85
TH		 1390 unsigned long deadline)
1391{
7d50b60b
TH		 1392 int pmp = 0;
1393
1394 if (link->ap->flags & ATA_FLAG_PMP)
1395 pmp = SATA_PMP_CTRL_PORT;
1396
1397 return ahci_do_softreset(link, class, pmp, deadline);
a9cf5e85
TH		 1398}
1399
cc0680a5 1400static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1401 unsigned long deadline)
422b7595 1402{
cc0680a5 1403 struct ata_port *ap = link->ap;
4296971d
TH		 1404 struct ahci_port_priv *pp = ap->private_data;
1405 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1406 struct ata_taskfile tf;
4bd00f6a
TH		 1407 int rc;
1408
1409 DPRINTK("ENTER\n");
1da177e4 1410
4447d351 1411 ahci_stop_engine(ap);
4296971d
TH		 1412
1413 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1414 ata_tf_init(link->device, &tf);
dfd7a3db 1415 tf.command = 0x80;
9977126c 1416 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1417
cc0680a5 1418 rc = sata_std_hardreset(link, class, deadline);
4296971d 1419
4447d351 1420 ahci_start_engine(ap);
1da177e4 1421
cc0680a5 1422 if (rc == 0 && ata_link_online(link))
4bd00f6a 1423 *class = ahci_dev_classify(ap);
7d50b60b 1424 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
4bd00f6a 1425 *class = ATA_DEV_NONE;
1da177e4 1426
4bd00f6a
TH		 1427 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1428 return rc;
1429}
1430
cc0680a5 1431static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1432 unsigned long deadline)
ad616ffb 1433{
cc0680a5 1434 struct ata_port *ap = link->ap;
da3dbb17 1435 u32 serror;
ad616ffb
TH		 1436 int rc;
1437
1438 DPRINTK("ENTER\n");
1439
4447d351 1440 ahci_stop_engine(ap);
ad616ffb 1441
cc0680a5 1442 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
d4b2bab4 1443 deadline);
ad616ffb
TH		 1444
1445 /* vt8251 needs SError cleared for the port to operate */
da3dbb17
TH		 1446 ahci_scr_read(ap, SCR_ERROR, &serror);
1447 ahci_scr_write(ap, SCR_ERROR, serror);
ad616ffb 1448
4447d351 1449 ahci_start_engine(ap);
ad616ffb
TH		 1450
1451 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1452
1453 /* vt8251 doesn't clear BSY on signature FIS reception,
1454 * request follow-up softreset.
1455 */
1456 return rc ?: -EAGAIN;
1457}
1458
edc93052
TH		 1459static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1460 unsigned long deadline)
1461{
1462 struct ata_port *ap = link->ap;
1463 struct ahci_port_priv *pp = ap->private_data;
1464 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1465 struct ata_taskfile tf;
1466 int rc;
1467
1468 ahci_stop_engine(ap);
1469
1470 /* clear D2H reception area to properly wait for D2H FIS */
1471 ata_tf_init(link->device, &tf);
1472 tf.command = 0x80;
1473 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1474
1475 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1476 deadline);
1477
1478 ahci_start_engine(ap);
1479
1480 if (rc || ata_link_offline(link))
1481 return rc;
1482
1483 /* spec mandates ">= 2ms" before checking status */
1484 msleep(150);
1485
1486 /* The pseudo configuration device on SIMG4726 attached to
1487 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1488 * hardreset if no device is attached to the first downstream
1489 * port && the pseudo device locks up on SRST w/ PMP==0. To
1490 * work around this, wait for !BSY only briefly. If BSY isn't
1491 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1492 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1493 *
1494 * Wait for two seconds. Devices attached to downstream port
1495 * which can't process the following IDENTIFY after this will
1496 * have to be reset again. For most cases, this should
1497 * suffice while making probing snappish enough.
1498 */
1499 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1500 if (rc)
1501 ahci_kick_engine(ap, 0);
1502
1503 return 0;
1504}
1505
cc0680a5 1506static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1507{
cc0680a5 1508 struct ata_port *ap = link->ap;
4447d351 1509 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1510 u32 new_tmp, tmp;
1511
cc0680a5 1512 ata_std_postreset(link, class);
02eaa666
JG		 1513
1514 /* Make sure port's ATAPI bit is set appropriately */
1515 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1516 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1517 new_tmp |= PORT_CMD_ATAPI;
1518 else
1519 new_tmp &= ~PORT_CMD_ATAPI;
1520 if (new_tmp != tmp) {
1521 writel(new_tmp, port_mmio + PORT_CMD);
1522 readl(port_mmio + PORT_CMD); /* flush */
1523 }
1da177e4
LT		 1524}
1525
7d50b60b
TH		 1526static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1527 unsigned long deadline)
1528{
1529 return ahci_do_softreset(link, class, link->pmp, deadline);
1530}
1531
1da177e4
LT		 1532static u8 ahci_check_status(struct ata_port *ap)
1533{
0d5ff566 1534 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1535
1536 return readl(mmio + PORT_TFDATA) & 0xFF;
1537}
1538
1da177e4
LT		 1539static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1540{
1541 struct ahci_port_priv *pp = ap->private_data;
1542 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1543
1544 ata_tf_from_fis(d2h_fis, tf);
1545}
1546
12fad3f9 1547static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1548{
cedc9a47 1549 struct scatterlist *sg;
ff2aeb1e
TH		 1550 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1551 unsigned int si;
1da177e4
LT		 1552
1553 VPRINTK("ENTER\n");
1554
1555 /*
1556 * Next, the S/G list.
1557 */
ff2aeb1e 1558 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 1559 dma_addr_t addr = sg_dma_address(sg);
1560 u32 sg_len = sg_dma_len(sg);
1561
ff2aeb1e
TH		 1562 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1563 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1564 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 1565 }
828d09de 1566
ff2aeb1e 1567 return si;
1da177e4
LT		 1568}
1569
1570static void ahci_qc_prep(struct ata_queued_cmd *qc)
1571{
a0ea7328
JG		 1572 struct ata_port *ap = qc->ap;
1573 struct ahci_port_priv *pp = ap->private_data;
405e66b3 1574 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 1575 void *cmd_tbl;
1da177e4
LT		 1576 u32 opts;
1577 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1578 unsigned int n_elem;
1da177e4 1579
1da177e4
LT		 1580 /*
1581 * Fill in command table information. First, the header,
1582 * a SATA Register - Host to Device command FIS.
1583 */
12fad3f9
TH		 1584 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1585
7d50b60b 1586 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1587 if (is_atapi) {
12fad3f9
TH		 1588 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1589 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1590 }
1da177e4 1591
cc9278ed
TH		 1592 n_elem = 0;
1593 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1594 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1595
cc9278ed
TH		 1596 /*
1597 * Fill in command slot information.
1598 */
7d50b60b 1599 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1600 if (qc->tf.flags & ATA_TFLAG_WRITE)
1601 opts |= AHCI_CMD_WRITE;
1602 if (is_atapi)
4b10e559 1603 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1604
12fad3f9 1605 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1606}
1607
78cd52d0 1608static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1609{
417a1a6d 1610 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 1611 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1612 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1613 struct ata_link *link = NULL;
1614 struct ata_queued_cmd *active_qc;
1615 struct ata_eh_info *active_ehi;
78cd52d0 1616 u32 serror;
1da177e4 1617
7d50b60b
TH		 1618 /* determine active link */
1619 ata_port_for_each_link(link, ap)
1620 if (ata_link_active(link))
1621 break;
1622 if (!link)
1623 link = &ap->link;
1624
1625 active_qc = ata_qc_from_tag(ap, link->active_tag);
1626 active_ehi = &link->eh_info;
1627
1628 /* record irq stat */
1629 ata_ehi_clear_desc(host_ehi);
1630 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1631
78cd52d0 1632 /* AHCI needs SError cleared; otherwise, it might lock up */
da3dbb17 1633 ahci_scr_read(ap, SCR_ERROR, &serror);
78cd52d0 1634 ahci_scr_write(ap, SCR_ERROR, serror);
7d50b60b 1635 host_ehi->serror |= serror;
78cd52d0 1636
41669553 1637 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 1638 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 1639 irq_stat &= ~PORT_IRQ_IF_ERR;
1640
55a61604 1641 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1642 /* If qc is active, charge it; otherwise, the active
1643 * link. There's no active qc on NCQ errors. It will
1644 * be determined by EH by reading log page 10h.
1645 */
1646 if (active_qc)
1647 active_qc->err_mask |= AC_ERR_DEV;
1648 else
1649 active_ehi->err_mask |= AC_ERR_DEV;
1650
417a1a6d 1651 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1652 host_ehi->serror &= ~SERR_INTERNAL;
1653 }
1654
1655 if (irq_stat & PORT_IRQ_UNK_FIS) {
1656 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1657
1658 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1659 active_ehi->action |= ATA_EH_RESET;
7d50b60b
TH		 1660 ata_ehi_push_desc(active_ehi,
1661 "unknown FIS %08x %08x %08x %08x" ,
1662 unk[0], unk[1], unk[2], unk[3]);
1663 }
1664
1665 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1666 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1667 active_ehi->action |= ATA_EH_RESET;
7d50b60b 1668 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 1669 }
78cd52d0
TH		 1670
1671 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b 1672 host_ehi->err_mask |= AC_ERR_HOST_BUS;
cf480626 1673 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1674 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 1675 }
1676
78cd52d0 1677 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b 1678 host_ehi->err_mask |= AC_ERR_ATA_BUS;
cf480626 1679 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1680 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 1681 }
1da177e4 1682
78cd52d0 1683 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 1684 ata_ehi_hotplugged(host_ehi);
1685 ata_ehi_push_desc(host_ehi, "%s",
1686 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 1687 "connection status changed" : "PHY RDY changed");
1688 }
1689
78cd52d0 1690 /* okay, let's hand over to EH */
a72ec4ce 1691
78cd52d0
TH		 1692 if (irq_stat & PORT_IRQ_FREEZE)
1693 ata_port_freeze(ap);
1694 else
1695 ata_port_abort(ap);
1da177e4
LT		 1696}
1697
df69c9c5 1698static void ahci_port_intr(struct ata_port *ap)
1da177e4 1699{
4447d351 1700 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
9af5c9c9 1701 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 1702 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 1703 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 1704 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 1705 u32 status, qc_active;
459ad688 1706 int rc;
1da177e4
LT		 1707
1708 status = readl(port_mmio + PORT_IRQ_STAT);
1709 writel(status, port_mmio + PORT_IRQ_STAT);
1710
b06ce3e5
TH		 1711 /* ignore BAD_PMP while resetting */
1712 if (unlikely(resetting))
1713 status &= ~PORT_IRQ_BAD_PMP;
1714
31556594
KCA		 1715 /* If we are getting PhyRdy, this is
1716 * just a power state change, we should
1717 * clear out this, plus the PhyRdy/Comm
1718 * Wake bits from Serror
1719 */
1720 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1721 (status & PORT_IRQ_PHYRDY)) {
1722 status &= ~PORT_IRQ_PHYRDY;
1723 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1724 }
1725
78cd52d0
TH		 1726 if (unlikely(status & PORT_IRQ_ERROR)) {
1727 ahci_error_intr(ap, status);
1728 return;
1da177e4
LT		 1729 }
1730
2f294968 1731 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 1732 /* If SNotification is available, leave notification
1733 * handling to sata_async_notification(). If not,
1734 * emulate it by snooping SDB FIS RX area.
1735 *
1736 * Snooping FIS RX area is probably cheaper than
1737 * poking SNotification but some constrollers which
1738 * implement SNotification, ICH9 for example, don't
1739 * store AN SDB FIS into receive area.
2f294968 1740 */
5f226c6b 1741 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 1742 sata_async_notification(ap);
5f226c6b
TH		 1743 else {
1744 /* If the 'N' bit in word 0 of the FIS is set,
1745 * we just received asynchronous notification.
1746 * Tell libata about it.
1747 */
1748 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1749 u32 f0 = le32_to_cpu(f[0]);
1750
1751 if (f0 & (1 << 15))
1752 sata_async_notification(ap);
1753 }
2f294968
KCA		 1754 }
1755
7d50b60b
TH		 1756 /* pp->active_link is valid iff any command is in flight */
1757 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 1758 qc_active = readl(port_mmio + PORT_SCR_ACT);
1759 else
1760 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1761
1762 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
b06ce3e5 1763
459ad688
TH		 1764 /* while resetting, invalid completions are expected */
1765 if (unlikely(rc < 0 && !resetting)) {
12fad3f9 1766 ehi->err_mask |= AC_ERR_HSM;
cf480626 1767 ehi->action |= ATA_EH_RESET;
12fad3f9 1768 ata_port_freeze(ap);
1da177e4 1769 }
1da177e4
LT		 1770}
1771
1772static void ahci_irq_clear(struct ata_port *ap)
1773{
1774 /* TODO */
1775}
1776
7d12e780 1777static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1778{
cca3974e 1779 struct ata_host *host = dev_instance;
1da177e4
LT		 1780 struct ahci_host_priv *hpriv;
1781 unsigned int i, handled = 0;
ea6ba10b 1782 void __iomem *mmio;
1da177e4
LT		 1783 u32 irq_stat, irq_ack = 0;
1784
1785 VPRINTK("ENTER\n");
1786
cca3974e 1787 hpriv = host->private_data;
0d5ff566 1788 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1789
1790 /* sigh. 0xffffffff is a valid return from h/w */
1791 irq_stat = readl(mmio + HOST_IRQ_STAT);
1792 irq_stat &= hpriv->port_map;
1793 if (!irq_stat)
1794 return IRQ_NONE;
1795
2dcb407e 1796 spin_lock(&host->lock);
1da177e4 1797
2dcb407e 1798 for (i = 0; i < host->n_ports; i++) {
1da177e4 1799 struct ata_port *ap;
1da177e4 1800
67846b30
JG		 1801 if (!(irq_stat & (1 << i)))
1802 continue;
1803
cca3974e 1804 ap = host->ports[i];
67846b30 1805 if (ap) {
df69c9c5 1806 ahci_port_intr(ap);
67846b30
JG		 1807 VPRINTK("port %u\n", i);
1808 } else {
1809 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1810 if (ata_ratelimit())
cca3974e 1811 dev_printk(KERN_WARNING, host->dev,
a9524a76 1812 "interrupt on disabled port %u\n", i);
1da177e4 1813 }
67846b30
JG		 1814
1815 irq_ack |= (1 << i);
1da177e4
LT		 1816 }
1817
1818 if (irq_ack) {
1819 writel(irq_ack, mmio + HOST_IRQ_STAT);
1820 handled = 1;
1821 }
1822
cca3974e 1823 spin_unlock(&host->lock);
1da177e4
LT		 1824
1825 VPRINTK("EXIT\n");
1826
1827 return IRQ_RETVAL(handled);
1828}
1829
9a3d9eb0 1830static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1831{
1832 struct ata_port *ap = qc->ap;
4447d351 1833 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 1834 struct ahci_port_priv *pp = ap->private_data;
1835
1836 /* Keep track of the currently active link. It will be used
1837 * in completion path to determine whether NCQ phase is in
1838 * progress.
1839 */
1840 pp->active_link = qc->dev->link;
1da177e4 1841
12fad3f9
TH		 1842 if (qc->tf.protocol == ATA_PROT_NCQ)
1843 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1844 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1845 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1846
1847 return 0;
1848}
1849
78cd52d0
TH		 1850static void ahci_freeze(struct ata_port *ap)
1851{
4447d351 1852 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 1853
1854 /* turn IRQ off */
1855 writel(0, port_mmio + PORT_IRQ_MASK);
1856}
1857
1858static void ahci_thaw(struct ata_port *ap)
1859{
0d5ff566 1860 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 1861 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 1862 u32 tmp;
a7384925 1863 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 1864
1865 /* clear IRQ */
1866 tmp = readl(port_mmio + PORT_IRQ_STAT);
1867 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1868 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 1869
1c954a4d
TH		 1870 /* turn IRQ back on */
1871 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 1872}
1873
1874static void ahci_error_handler(struct ata_port *ap)
1875{
b51e9e5d 1876 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1877 /* restart engine */
4447d351
TH		 1878 ahci_stop_engine(ap);
1879 ahci_start_engine(ap);
78cd52d0
TH		 1880 }
1881
1882 /* perform recovery */
7d50b60b
TH		 1883 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1884 ahci_hardreset, ahci_postreset,
1885 sata_pmp_std_prereset, ahci_pmp_softreset,
1886 sata_pmp_std_hardreset, sata_pmp_std_postreset);
78cd52d0
TH		 1887}
1888
ad616ffb
TH		 1889static void ahci_vt8251_error_handler(struct ata_port *ap)
1890{
ad616ffb
TH		 1891 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1892 /* restart engine */
4447d351
TH		 1893 ahci_stop_engine(ap);
1894 ahci_start_engine(ap);
ad616ffb
TH		 1895 }
1896
1897 /* perform recovery */
1898 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1899 ahci_postreset);
1900}
1901
edc93052
TH		 1902static void ahci_p5wdh_error_handler(struct ata_port *ap)
1903{
1904 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1905 /* restart engine */
1906 ahci_stop_engine(ap);
1907 ahci_start_engine(ap);
1908 }
1909
1910 /* perform recovery */
1911 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1912 ahci_postreset);
1913}
1914
78cd52d0
TH		 1915static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1916{
1917 struct ata_port *ap = qc->ap;
1918
d2e75dff
TH		 1919 /* make DMA engine forget about the failed command */
1920 if (qc->flags & ATA_QCFLAG_FAILED)
1921 ahci_kick_engine(ap, 1);
78cd52d0
TH		 1922}
1923
7d50b60b
TH		 1924static void ahci_pmp_attach(struct ata_port *ap)
1925{
1926 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1927 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1928 u32 cmd;
1929
1930 cmd = readl(port_mmio + PORT_CMD);
1931 cmd |= PORT_CMD_PMP;
1932 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1933
1934 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1935 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1936}
1937
1938static void ahci_pmp_detach(struct ata_port *ap)
1939{
1940 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1941 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1942 u32 cmd;
1943
1944 cmd = readl(port_mmio + PORT_CMD);
1945 cmd &= ~PORT_CMD_PMP;
1946 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1947
1948 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1949 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1950}
1951
028a2596
AD		 1952static int ahci_port_resume(struct ata_port *ap)
1953{
1954 ahci_power_up(ap);
1955 ahci_start_port(ap);
1956
7d50b60b
TH		 1957 if (ap->nr_pmp_links)
1958 ahci_pmp_attach(ap);
1959 else
1960 ahci_pmp_detach(ap);
1961
028a2596
AD		 1962 return 0;
1963}
1964
438ac6d5 1965#ifdef CONFIG_PM
c1332875
TH		 1966static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1967{
c1332875
TH		 1968 const char *emsg = NULL;
1969 int rc;
1970
4447d351 1971 rc = ahci_deinit_port(ap, &emsg);
8e16f941 1972 if (rc == 0)
4447d351 1973 ahci_power_down(ap);
8e16f941 1974 else {
c1332875 1975 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 1976 ahci_start_port(ap);
c1332875
TH		 1977 }
1978
1979 return rc;
1980}
1981
c1332875
TH		 1982static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1983{
cca3974e 1984 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1985 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1986 u32 ctl;
1987
3a2d5b70 1988 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 1989 /* AHCI spec rev1.1 section 8.3.3:
1990 * Software must disable interrupts prior to requesting a
1991 * transition of the HBA to D3 state.
1992 */
1993 ctl = readl(mmio + HOST_CTL);
1994 ctl &= ~HOST_IRQ_EN;
1995 writel(ctl, mmio + HOST_CTL);
1996 readl(mmio + HOST_CTL); /* flush */
1997 }
1998
1999 return ata_pci_device_suspend(pdev, mesg);
2000}
2001
2002static int ahci_pci_device_resume(struct pci_dev *pdev)
2003{
cca3974e 2004 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 2005 int rc;
2006
553c4aa6
TH		 2007 rc = ata_pci_device_do_resume(pdev);
2008 if (rc)
2009 return rc;
c1332875
TH		 2010
2011 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 2012 rc = ahci_reset_controller(host);
c1332875
TH		 2013 if (rc)
2014 return rc;
2015
4447d351 2016 ahci_init_controller(host);
c1332875
TH		 2017 }
2018
cca3974e 2019 ata_host_resume(host);
c1332875
TH		 2020
2021 return 0;
2022}
438ac6d5 2023#endif
c1332875 2024
254950cd
TH		 2025static int ahci_port_start(struct ata_port *ap)
2026{
cca3974e 2027 struct device *dev = ap->host->dev;
254950cd 2028 struct ahci_port_priv *pp;
254950cd
TH		 2029 void *mem;
2030 dma_addr_t mem_dma;
254950cd 2031
24dc5f33 2032 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2033 if (!pp)
2034 return -ENOMEM;
254950cd 2035
24dc5f33
TH		 2036 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2037 GFP_KERNEL);
2038 if (!mem)
254950cd 2039 return -ENOMEM;
254950cd
TH		 2040 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2041
2042 /*
2043 * First item in chunk of DMA memory: 32-slot command table,
2044 * 32 bytes each in size
2045 */
2046 pp->cmd_slot = mem;
2047 pp->cmd_slot_dma = mem_dma;
2048
2049 mem += AHCI_CMD_SLOT_SZ;
2050 mem_dma += AHCI_CMD_SLOT_SZ;
2051
2052 /*
2053 * Second item: Received-FIS area
2054 */
2055 pp->rx_fis = mem;
2056 pp->rx_fis_dma = mem_dma;
2057
2058 mem += AHCI_RX_FIS_SZ;
2059 mem_dma += AHCI_RX_FIS_SZ;
2060
2061 /*
2062 * Third item: data area for storing a single command
2063 * and its scatter-gather table
2064 */
2065 pp->cmd_tbl = mem;
2066 pp->cmd_tbl_dma = mem_dma;
2067
a7384925 2068 /*
2dcb407e
JG		 2069 * Save off initial list of interrupts to be enabled.
2070 * This could be changed later
2071 */
a7384925
KCA		 2072 pp->intr_mask = DEF_PORT_IRQ;
2073
254950cd
TH		 2074 ap->private_data = pp;
2075
df69c9c5
JG		 2076 /* engage engines, captain */
2077 return ahci_port_resume(ap);
254950cd
TH		 2078}
2079
2080static void ahci_port_stop(struct ata_port *ap)
2081{
0be0aa98
TH		 2082 const char *emsg = NULL;
2083 int rc;
254950cd 2084
0be0aa98 2085 /* de-initialize port */
4447d351 2086 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2087 if (rc)
2088 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2089}
2090
4447d351 2091static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2092{
1da177e4 2093 int rc;
1da177e4 2094
1da177e4
LT		 2095 if (using_dac &&
2096 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2097 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2098 if (rc) {
2099 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2100 if (rc) {
a9524a76
JG		 2101 dev_printk(KERN_ERR, &pdev->dev,
2102 "64-bit DMA enable failed\n");
1da177e4
LT		 2103 return rc;
2104 }
2105 }
1da177e4
LT		 2106 } else {
2107 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2108 if (rc) {
a9524a76
JG		 2109 dev_printk(KERN_ERR, &pdev->dev,
2110 "32-bit DMA enable failed\n");
1da177e4
LT		 2111 return rc;
2112 }
2113 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2114 if (rc) {
a9524a76
JG		 2115 dev_printk(KERN_ERR, &pdev->dev,
2116 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2117 return rc;
2118 }
2119 }
1da177e4
LT		 2120 return 0;
2121}
2122
4447d351 2123static void ahci_print_info(struct ata_host *host)
1da177e4 2124{
4447d351
TH		 2125 struct ahci_host_priv *hpriv = host->private_data;
2126 struct pci_dev *pdev = to_pci_dev(host->dev);
2127 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2128 u32 vers, cap, impl, speed;
2129 const char *speed_s;
2130 u16 cc;
2131 const char *scc_s;
2132
2133 vers = readl(mmio + HOST_VERSION);
2134 cap = hpriv->cap;
2135 impl = hpriv->port_map;
2136
2137 speed = (cap >> 20) & 0xf;
2138 if (speed == 1)
2139 speed_s = "1.5";
2140 else if (speed == 2)
2141 speed_s = "3";
2142 else
2143 speed_s = "?";
2144
2145 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2146 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2147 scc_s = "IDE";
c9f89475 2148 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2149 scc_s = "SATA";
c9f89475 2150 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2151 scc_s = "RAID";
2152 else
2153 scc_s = "unknown";
2154
a9524a76
JG		 2155 dev_printk(KERN_INFO, &pdev->dev,
2156 "AHCI %02x%02x.%02x%02x "
1da177e4 2157 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2158 ,
1da177e4 2159
2dcb407e
JG		 2160 (vers >> 24) & 0xff,
2161 (vers >> 16) & 0xff,
2162 (vers >> 8) & 0xff,
2163 vers & 0xff,
1da177e4
LT		 2164
2165 ((cap >> 8) & 0x1f) + 1,
2166 (cap & 0x1f) + 1,
2167 speed_s,
2168 impl,
2169 scc_s);
2170
a9524a76
JG		 2171 dev_printk(KERN_INFO, &pdev->dev,
2172 "flags: "
203ef6c4
TH		 2173 "%s%s%s%s%s%s%s"
2174 "%s%s%s%s%s%s%s\n"
2dcb407e 2175 ,
1da177e4
LT		 2176
2177 cap & (1 << 31) ? "64bit " : "",
2178 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2179 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2180 cap & (1 << 28) ? "ilck " : "",
2181 cap & (1 << 27) ? "stag " : "",
2182 cap & (1 << 26) ? "pm " : "",
2183 cap & (1 << 25) ? "led " : "",
2184
2185 cap & (1 << 24) ? "clo " : "",
2186 cap & (1 << 19) ? "nz " : "",
2187 cap & (1 << 18) ? "only " : "",
2188 cap & (1 << 17) ? "pmp " : "",
2189 cap & (1 << 15) ? "pio " : "",
2190 cap & (1 << 14) ? "slum " : "",
2191 cap & (1 << 13) ? "part " : ""
2192 );
2193}
2194
edc93052
TH		 2195/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2196 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2197 * support PMP and the 4726 either directly exports the device
2198 * attached to the first downstream port or acts as a hardware storage
2199 * controller and emulate a single ATA device (can be RAID 0/1 or some
2200 * other configuration).
2201 *
2202 * When there's no device attached to the first downstream port of the
2203 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2204 * configure the 4726. However, ATA emulation of the device is very
2205 * lame. It doesn't send signature D2H Reg FIS after the initial
2206 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2207 *
2208 * The following function works around the problem by always using
2209 * hardreset on the port and not depending on receiving signature FIS
2210 * afterward. If signature FIS isn't received soon, ATA class is
2211 * assumed without follow-up softreset.
2212 */
2213static void ahci_p5wdh_workaround(struct ata_host *host)
2214{
2215 static struct dmi_system_id sysids[] = {
2216 {
2217 .ident = "P5W DH Deluxe",
2218 .matches = {
2219 DMI_MATCH(DMI_SYS_VENDOR,
2220 "ASUSTEK COMPUTER INC"),
2221 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2222 },
2223 },
2224 { }
2225 };
2226 struct pci_dev *pdev = to_pci_dev(host->dev);
2227
2228 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2229 dmi_check_system(sysids)) {
2230 struct ata_port *ap = host->ports[1];
2231
2232 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2233 "Deluxe on-board SIMG4726 workaround\n");
2234
2235 ap->ops = &ahci_p5wdh_ops;
2236 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2237 }
2238}
2239
24dc5f33 2240static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2241{
2242 static int printed_version;
4447d351
TH		 2243 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2244 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2245 struct device *dev = &pdev->dev;
1da177e4 2246 struct ahci_host_priv *hpriv;
4447d351 2247 struct ata_host *host;
837f5f8f 2248 int n_ports, i, rc;
1da177e4
LT		 2249
2250 VPRINTK("ENTER\n");
2251
12fad3f9
TH		 2252 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2253
1da177e4 2254 if (!printed_version++)
a9524a76 2255 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2256
4447d351 2257 /* acquire resources */
24dc5f33 2258 rc = pcim_enable_device(pdev);
1da177e4
LT		 2259 if (rc)
2260 return rc;
2261
dea55137
TH		 2262 /* AHCI controllers often implement SFF compatible interface.
2263 * Grab all PCI BARs just in case.
2264 */
2265 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 2266 if (rc == -EBUSY)
24dc5f33 2267 pcim_pin_device(pdev);
0d5ff566 2268 if (rc)
24dc5f33 2269 return rc;
1da177e4 2270
c4f7792c
TH		 2271 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2272 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2273 u8 map;
2274
2275 /* ICH6s share the same PCI ID for both piix and ahci
2276 * modes. Enabling ahci mode while MAP indicates
2277 * combined mode is a bad idea. Yield to ata_piix.
2278 */
2279 pci_read_config_byte(pdev, ICH_MAP, &map);
2280 if (map & 0x3) {
2281 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2282 "combined mode, can't enable AHCI mode\n");
2283 return -ENODEV;
2284 }
2285 }
2286
24dc5f33
TH		 2287 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2288 if (!hpriv)
2289 return -ENOMEM;
417a1a6d
TH		 2290 hpriv->flags |= (unsigned long)pi.private_data;
2291
2292 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2293 pci_intx(pdev, 1);
1da177e4 2294
4447d351 2295 /* save initial config */
417a1a6d 2296 ahci_save_initial_config(pdev, hpriv);
1da177e4 2297
4447d351 2298 /* prepare host */
274c1fde 2299 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 2300 pi.flags |= ATA_FLAG_NCQ;
1da177e4 2301
7d50b60b
TH		 2302 if (hpriv->cap & HOST_CAP_PMP)
2303 pi.flags |= ATA_FLAG_PMP;
2304
837f5f8f
TH		 2305 /* CAP.NP sometimes indicate the index of the last enabled
2306 * port, at other times, that of the last possible port, so
2307 * determining the maximum port number requires looking at
2308 * both CAP.NP and port_map.
2309 */
2310 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2311
2312 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 2313 if (!host)
2314 return -ENOMEM;
2315 host->iomap = pcim_iomap_table(pdev);
2316 host->private_data = hpriv;
2317
2318 for (i = 0; i < host->n_ports; i++) {
dab632e8
JG		 2319 struct ata_port *ap = host->ports[i];
2320 void __iomem *port_mmio = ahci_port_base(ap);
4447d351 2321
cbcdd875
TH		 2322 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2323 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2324 0x100 + ap->port_no * 0x80, "port");
2325
31556594
KCA		 2326 /* set initial link pm policy */
2327 ap->pm_policy = NOT_AVAILABLE;
2328
dab632e8 2329 /* standard SATA port setup */
203ef6c4 2330 if (hpriv->port_map & (1 << i))
4447d351 2331 ap->ioaddr.cmd_addr = port_mmio;
dab632e8
JG		 2332
2333 /* disabled/not-implemented port */
2334 else
2335 ap->ops = &ata_dummy_port_ops;
4447d351 2336 }
d447df14 2337
edc93052
TH		 2338 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2339 ahci_p5wdh_workaround(host);
2340
4447d351
TH		 2341 /* initialize adapter */
2342 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2343 if (rc)
24dc5f33 2344 return rc;
1da177e4 2345
4447d351
TH		 2346 rc = ahci_reset_controller(host);
2347 if (rc)
2348 return rc;
1da177e4 2349
4447d351
TH		 2350 ahci_init_controller(host);
2351 ahci_print_info(host);
1da177e4 2352
4447d351
TH		 2353 pci_set_master(pdev);
2354 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2355 &ahci_sht);
907f4678 2356}
1da177e4
LT		 2357
2358static int __init ahci_init(void)
2359{
b7887196 2360 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2361}
2362
1da177e4
LT		 2363static void __exit ahci_exit(void)
2364{
2365 pci_unregister_driver(&ahci_pci_driver);
2366}
2367
2368
2369MODULE_AUTHOR("Jeff Garzik");
2370MODULE_DESCRIPTION("AHCI SATA low-level driver");
2371MODULE_LICENSE("GPL");
2372MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2373MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2374
2375module_init(ahci_init);
2376module_exit(ahci_exit);
kernel source for telekom puls (alcatel/mediatek)