[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / xtensa / kernel / pci.c

/*
 * arch/xtensa/kernel/pci.c
 *
 * PCI bios-type initialisation for PCI machines
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (C) 2001-2005 Tensilica Inc.
 *
 * Based largely on work from Cort (ppc/kernel/pci.c)
 * IO functions copied from sparc.
 *
 * Chris Zankel <chris@zankel.net>
 *
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/bootmem.h>

#include <asm/pci-bridge.h>
#include <asm/platform.h>

#undef DEBUG

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

/* PCI Controller */


/*
 * pcibios_alloc_controller
 * pcibios_enable_device
 * pcibios_fixups
 * pcibios_align_resource
 * pcibios_fixup_bus
 * pcibios_setup
 * pci_bus_add_device
 * pci_mmap_page_range
 */

struct pci_controller* pci_ctrl_head;
struct pci_controller** pci_ctrl_tail = &pci_ctrl_head;

static int pci_bus_count;

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
resource_size_t
pcibios_align_resource(void *data, struct resource *res, resource_size_t size,
    		       resource_size_t align)
{
	struct pci_dev *dev = data;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		if (size > 0x100) {
			printk(KERN_ERR "PCI: I/O Region %s/%d too large"
			       " (%ld bytes)\n", pci_name(dev),
			       dev->resource - res, size);
		}

		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	}

	return start;
}

int
pcibios_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for(idx=0; idx<6; idx++) {
		r = &dev->resource[idx];
		if (!r->start && r->end) {
			printk (KERN_ERR "PCI: Device %s not available because "
				"of resource collisions\n", pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (dev->resource[PCI_ROM_RESOURCE].start)
		cmd |= PCI_COMMAND_MEMORY;
	if (cmd != old_cmd) {
		printk("PCI: Enabling device %s (%04x -> %04x)\n",
			pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

struct pci_controller * __init pcibios_alloc_controller(void)
{
	struct pci_controller *pci_ctrl;

	pci_ctrl = (struct pci_controller *)alloc_bootmem(sizeof(*pci_ctrl));
	memset(pci_ctrl, 0, sizeof(struct pci_controller));

	*pci_ctrl_tail = pci_ctrl;
	pci_ctrl_tail = &pci_ctrl->next;

	return pci_ctrl;
}

static int __init pcibios_init(void)
{
	struct pci_controller *pci_ctrl;
	struct pci_bus *bus;
	int next_busno = 0, i;

	printk("PCI: Probing PCI hardware\n");

	/* Scan all of the recorded PCI controllers.  */
	for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
		pci_ctrl->last_busno = 0xff;
		bus = pci_scan_bus(pci_ctrl->first_busno, pci_ctrl->ops,
				   pci_ctrl);
		if (pci_ctrl->io_resource.flags) {
			unsigned long offs;

			offs = (unsigned long)pci_ctrl->io_space.base;
			pci_ctrl->io_resource.start += offs;
			pci_ctrl->io_resource.end += offs;
			bus->resource[0] = &pci_ctrl->io_resource;
		}
		for (i = 0; i < 3; ++i)
			if (pci_ctrl->mem_resources[i].flags)
				bus->resource[i+1] =&pci_ctrl->mem_resources[i];
		pci_ctrl->bus = bus;
		pci_ctrl->last_busno = bus->subordinate;
		if (next_busno <= pci_ctrl->last_busno)
			next_busno = pci_ctrl->last_busno+1;
	}
	pci_bus_count = next_busno;

	return platform_pcibios_fixup();
}

subsys_initcall(pcibios_init);

void __init pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_controller *pci_ctrl = bus->sysdata;
	struct resource *res;
	unsigned long io_offset;
	int i;

	io_offset = (unsigned long)pci_ctrl->io_space.base;
	if (bus->parent == NULL) {
		/* this is a host bridge - fill in its resources */
		pci_ctrl->bus = bus;

		bus->resource[0] = res = &pci_ctrl->io_resource;
		if (!res->flags) {
			if (io_offset)
				printk (KERN_ERR "I/O resource not set for host"
					" bridge %d\n", pci_ctrl->index);
			res->start = 0;
			res->end = IO_SPACE_LIMIT;
			res->flags = IORESOURCE_IO;
		}
		res->start += io_offset;
		res->end += io_offset;

		for (i = 0; i < 3; i++) {
			res = &pci_ctrl->mem_resources[i];
			if (!res->flags) {
				if (i > 0)
					continue;
				printk(KERN_ERR "Memory resource not set for "
				       "host bridge %d\n", pci_ctrl->index);
				res->start = 0;
				res->end = ~0U;
				res->flags = IORESOURCE_MEM;
			}
			bus->resource[i+1] = res;
		}
	} else {
		/* This is a subordinate bridge */
		pci_read_bridge_bases(bus);

		for (i = 0; i < 4; i++) {
			if ((res = bus->resource[i]) == NULL || !res->flags)
				continue;
			if (io_offset && (res->flags & IORESOURCE_IO)) {
				res->start += io_offset;
				res->end += io_offset;
			}
		}
	}
}

char __init *pcibios_setup(char *str)
{
	return str;
}

/* the next one is stolen from the alpha port... */

void __init
pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx=0; idx<6; idx++) {
		r = &dev->resource[idx];
		if (!r->start && r->end) {
			printk(KERN_ERR "PCI: Device %s not available because "
			       "of resource collisions\n", pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		printk("PCI: Enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}

	return 0;
}

#ifdef CONFIG_PROC_FS

/*
 * Return the index of the PCI controller for device pdev.
 */

int
pci_controller_num(struct pci_dev *dev)
{
	struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
	return pci_ctrl->index;
}

#endif /* CONFIG_PROC_FS */

/*
 * Platform support for /proc/bus/pci/X/Y mmap()s,
 * modelled on the sparc64 implementation by Dave Miller.
 *  -- paulus.
 */

/*
 * Adjust vm_pgoff of VMA such that it is the physical page offset
 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
 *
 * Basically, the user finds the base address for his device which he wishes
 * to mmap.  They read the 32-bit value from the config space base register,
 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 *
 * Returns negative error code on failure, zero on success.
 */
static __inline__ int
__pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
		       enum pci_mmap_state mmap_state)
{
	struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
	unsigned long io_offset = 0;
	int i, res_bit;

	if (pci_ctrl == 0)
		return -EINVAL;		/* should never happen */

	/* If memory, add on the PCI bridge address offset */
	if (mmap_state == pci_mmap_mem) {
		res_bit = IORESOURCE_MEM;
	} else {
		io_offset = (unsigned long)pci_ctrl->io_space.base;
		offset += io_offset;
		res_bit = IORESOURCE_IO;
	}

	/*
	 * Check that the offset requested corresponds to one of the
	 * resources of the device.
	 */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		struct resource *rp = &dev->resource[i];
		int flags = rp->flags;

		/* treat ROM as memory (should be already) */
		if (i == PCI_ROM_RESOURCE)
			flags |= IORESOURCE_MEM;

		/* Active and same type? */
		if ((flags & res_bit) == 0)
			continue;

		/* In the range of this resource? */
		if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
			continue;

		/* found it! construct the final physical address */
		if (mmap_state == pci_mmap_io)
			offset += pci_ctrl->io_space.start - io_offset;
		vma->vm_pgoff = offset >> PAGE_SHIFT;
		return 0;
	}

	return -EINVAL;
}

/*
 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 * device mapping.
 */
static __inline__ void
__pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
		      enum pci_mmap_state mmap_state, int write_combine)
{
	int prot = pgprot_val(vma->vm_page_prot);

	/* Set to write-through */
	prot &= ~_PAGE_NO_CACHE;
#if 0
	if (!write_combine)
		prot |= _PAGE_WRITETHRU;
#endif
	vma->vm_page_prot = __pgprot(prot);
}

/*
 * Perform the actual remap of the pages for a PCI device mapping, as
 * appropriate for this architecture.  The region in the process to map
 * is described by vm_start and vm_end members of VMA, the base physical
 * address is found in vm_pgoff.
 * The pci device structure is provided so that architectures may make mapping
 * decisions on a per-device or per-bus basis.
 *
 * Returns a negative error code on failure, zero on success.
 */
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state,
			int write_combine)
{
	int ret;

	ret = __pci_mmap_make_offset(dev, vma, mmap_state);
	if (ret < 0)
		return ret;

	__pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);

	ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
			         vma->vm_end - vma->vm_start,vma->vm_page_prot);

	return ret;
}
Commit	Line	Data
5a0015d6	1	/*
f30c2269	2	* arch/xtensa/kernel/pci.c
5a0015d6 CZ	3	*
	4	* PCI bios-type initialisation for PCI machines
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* Copyright (C) 2001-2005 Tensilica Inc.
	12	*
	13	* Based largely on work from Cort (ppc/kernel/pci.c)
	14	* IO functions copied from sparc.
	15	*
	16	* Chris Zankel <chris@zankel.net>
	17	*
	18	*/
	19
5a0015d6 CZ	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
	22	#include <linux/delay.h>
	23	#include <linux/string.h>
	24	#include <linux/init.h>
	25	#include <linux/sched.h>
	26	#include <linux/errno.h>
	27	#include <linux/bootmem.h>
	28
	29	#include <asm/pci-bridge.h>
	30	#include <asm/platform.h>
	31
	32	#undef DEBUG
	33
	34	#ifdef DEBUG
	35	#define DBG(x...) printk(x)
	36	#else
	37	#define DBG(x...)
	38	#endif
	39
	40	/* PCI Controller */
	41
	42
	43	/*
	44	* pcibios_alloc_controller
	45	* pcibios_enable_device
	46	* pcibios_fixups
	47	* pcibios_align_resource
	48	* pcibios_fixup_bus
	49	* pcibios_setup
	50	* pci_bus_add_device
	51	* pci_mmap_page_range
	52	*/
	53
	54	struct pci_controller* pci_ctrl_head;
	55	struct pci_controller** pci_ctrl_tail = &pci_ctrl_head;
	56
	57	static int pci_bus_count;
	58
5a0015d6 CZ	59	/*
	60	* We need to avoid collisions with `mirrored' VGA ports
	61	* and other strange ISA hardware, so we always want the
	62	* addresses to be allocated in the 0x000-0x0ff region
	63	* modulo 0x400.
	64	*
	65	* Why? Because some silly external IO cards only decode
	66	* the low 10 bits of the IO address. The 0x00-0xff region
	67	* is reserved for motherboard devices that decode all 16
	68	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	69	* but we want to try to avoid allocating at 0x2900-0x2bff
	70	* which might have be mirrored at 0x0100-0x03ff..
	71	*/
b26b2d49	72	resource_size_t
e31dd6e4 GKH	73	pcibios_align_resource(void data, struct resource res, resource_size_t size,
e31dd6e4 GKH	74	resource_size_t align)
5a0015d6 CZ	75	{
5a0015d6 CZ	76	struct pci_dev *dev = data;
b26b2d49	77	resource_size_t start = res->start;
5a0015d6 CZ	78
5a0015d6 CZ	79	if (res->flags & IORESOURCE_IO) {
5a0015d6 CZ	80	if (size > 0x100) {
5a0015d6 CZ	81	printk(KERN_ERR "PCI: I/O Region %s/%d too large"
9ec55a9b	82	" (%ld bytes)\n", pci_name(dev),
5a0015d6 CZ	83	dev->resource - res, size);
	84	}
	85
b26b2d49	86	if (start & 0x300)
5a0015d6	87	start = (start + 0x3ff) & ~0x3ff;
5a0015d6	88	}
b26b2d49 DB	89
b26b2d49 DB	90	return start;
5a0015d6 CZ	91	}
	92
	93	int
	94	pcibios_enable_resources(struct pci_dev *dev, int mask)
	95	{
	96	u16 cmd, old_cmd;
	97	int idx;
	98	struct resource *r;
	99
	100	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	101	old_cmd = cmd;
	102	for(idx=0; idx<6; idx++) {
	103	r = &dev->resource[idx];
	104	if (!r->start && r->end) {
	105	printk (KERN_ERR "PCI: Device %s not available because "
9ec55a9b	106	"of resource collisions\n", pci_name(dev));
5a0015d6 CZ	107	return -EINVAL;
	108	}
	109	if (r->flags & IORESOURCE_IO)
	110	cmd \|= PCI_COMMAND_IO;
	111	if (r->flags & IORESOURCE_MEM)
	112	cmd \|= PCI_COMMAND_MEMORY;
	113	}
	114	if (dev->resource[PCI_ROM_RESOURCE].start)
	115	cmd \|= PCI_COMMAND_MEMORY;
	116	if (cmd != old_cmd) {
	117	printk("PCI: Enabling device %s (%04x -> %04x)\n",
9ec55a9b	118	pci_name(dev), old_cmd, cmd);
5a0015d6 CZ	119	pci_write_config_word(dev, PCI_COMMAND, cmd);
	120	}
	121	return 0;
	122	}
	123
	124	struct pci_controller * __init pcibios_alloc_controller(void)
	125	{
	126	struct pci_controller *pci_ctrl;
	127
	128	pci_ctrl = (struct pci_controller )alloc_bootmem(sizeof(pci_ctrl));
	129	memset(pci_ctrl, 0, sizeof(struct pci_controller));
	130
	131	*pci_ctrl_tail = pci_ctrl;
	132	pci_ctrl_tail = &pci_ctrl->next;
	133
	134	return pci_ctrl;
	135	}
	136
	137	static int __init pcibios_init(void)
	138	{
	139	struct pci_controller *pci_ctrl;
	140	struct pci_bus *bus;
	141	int next_busno = 0, i;
	142
	143	printk("PCI: Probing PCI hardware\n");
	144
	145	/* Scan all of the recorded PCI controllers. */
	146	for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
	147	pci_ctrl->last_busno = 0xff;
	148	bus = pci_scan_bus(pci_ctrl->first_busno, pci_ctrl->ops,
	149	pci_ctrl);
	150	if (pci_ctrl->io_resource.flags) {
	151	unsigned long offs;
	152
	153	offs = (unsigned long)pci_ctrl->io_space.base;
	154	pci_ctrl->io_resource.start += offs;
	155	pci_ctrl->io_resource.end += offs;
	156	bus->resource[0] = &pci_ctrl->io_resource;
	157	}
	158	for (i = 0; i < 3; ++i)
	159	if (pci_ctrl->mem_resources[i].flags)
	160	bus->resource[i+1] =&pci_ctrl->mem_resources[i];
	161	pci_ctrl->bus = bus;
	162	pci_ctrl->last_busno = bus->subordinate;
	163	if (next_busno <= pci_ctrl->last_busno)
	164	next_busno = pci_ctrl->last_busno+1;
	165	}
	166	pci_bus_count = next_busno;
	167
	168	return platform_pcibios_fixup();
	169	}
	170
	171	subsys_initcall(pcibios_init);
	172
	173	void __init pcibios_fixup_bus(struct pci_bus *bus)
	174	{
	175	struct pci_controller *pci_ctrl = bus->sysdata;
	176	struct resource *res;
	177	unsigned long io_offset;
	178	int i;
	179
	180	io_offset = (unsigned long)pci_ctrl->io_space.base;
	181	if (bus->parent == NULL) {
	182	/* this is a host bridge - fill in its resources */
183	pci_ctrl->bus = bus;
184
185	bus->resource[0] = res = &pci_ctrl->io_resource;
186	if (!res->flags) {
187	if (io_offset)
188	printk (KERN_ERR "I/O resource not set for host"
189	" bridge %d\n", pci_ctrl->index);
190	res->start = 0;
191	res->end = IO_SPACE_LIMIT;
192	res->flags = IORESOURCE_IO;
193	}
194	res->start += io_offset;
195	res->end += io_offset;
196
197	for (i = 0; i < 3; i++) {
198	res = &pci_ctrl->mem_resources[i];
199	if (!res->flags) {
200	if (i > 0)
201	continue;
202	printk(KERN_ERR "Memory resource not set for "
203	"host bridge %d\n", pci_ctrl->index);
204	res->start = 0;
205	res->end = ~0U;
206	res->flags = IORESOURCE_MEM;
207	}
208	bus->resource[i+1] = res;
209	}
210	} else {
211	/* This is a subordinate bridge */
212	pci_read_bridge_bases(bus);
213
214	for (i = 0; i < 4; i++) {
215	if ((res = bus->resource[i]) == NULL \|\| !res->flags)
216	continue;
217	if (io_offset && (res->flags & IORESOURCE_IO)) {
218	res->start += io_offset;
219	res->end += io_offset;
220	}
221	}
222	}
223	}
224
225	char __init pcibios_setup(char str)
226	{
227	return str;
228	}
229
230	/* the next one is stolen from the alpha port... */
231
232	void __init
233	pcibios_update_irq(struct pci_dev *dev, int irq)
234	{
235	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
236	}
237
238	int pcibios_enable_device(struct pci_dev *dev, int mask)
239	{
240	u16 cmd, old_cmd;
241	int idx;
242	struct resource *r;
243
244	pci_read_config_word(dev, PCI_COMMAND, &cmd);
245	old_cmd = cmd;
246	for (idx=0; idx<6; idx++) {
247	r = &dev->resource[idx];
248	if (!r->start && r->end) {
249	printk(KERN_ERR "PCI: Device %s not available because "
9ec55a9b	250	"of resource collisions\n", pci_name(dev));
5a0015d6 CZ	251	return -EINVAL;
	252	}
	253	if (r->flags & IORESOURCE_IO)
	254	cmd \|= PCI_COMMAND_IO;
	255	if (r->flags & IORESOURCE_MEM)
	256	cmd \|= PCI_COMMAND_MEMORY;
	257	}
	258	if (cmd != old_cmd) {
	259	printk("PCI: Enabling device %s (%04x -> %04x)\n",
9ec55a9b	260	pci_name(dev), old_cmd, cmd);
5a0015d6 CZ	261	pci_write_config_word(dev, PCI_COMMAND, cmd);
	262	}
	263
	264	return 0;
	265	}
	266
	267	#ifdef CONFIG_PROC_FS
	268
	269	/*
	270	* Return the index of the PCI controller for device pdev.
	271	*/
	272
	273	int
	274	pci_controller_num(struct pci_dev *dev)
	275	{
	276	struct pci_controller pci_ctrl = (struct pci_controller) dev->sysdata;
	277	return pci_ctrl->index;
	278	}
	279
	280	#endif /* CONFIG_PROC_FS */
	281
5a0015d6 CZ	282	/*
	283	* Platform support for /proc/bus/pci/X/Y mmap()s,
	284	* modelled on the sparc64 implementation by Dave Miller.
	285	* -- paulus.
	286	*/
	287
	288	/*
	289	* Adjust vm_pgoff of VMA such that it is the physical page offset
	290	* corresponding to the 32-bit pci bus offset for DEV requested by the user.
	291	*
	292	* Basically, the user finds the base address for his device which he wishes
	293	* to mmap. They read the 32-bit value from the config space base register,
	294	* add whatever PAGE_SIZE multiple offset they wish, and feed this into the
	295	* offset parameter of mmap on /proc/bus/pci/XXX for that device.
	296	*
	297	* Returns negative error code on failure, zero on success.
	298	*/
	299	static __inline__ int
	300	__pci_mmap_make_offset(struct pci_dev dev, struct vm_area_struct vma,
	301	enum pci_mmap_state mmap_state)
	302	{
	303	struct pci_controller pci_ctrl = (struct pci_controller) dev->sysdata;
	304	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
	305	unsigned long io_offset = 0;
	306	int i, res_bit;
	307
	308	if (pci_ctrl == 0)
	309	return -EINVAL; /* should never happen */
	310
	311	/* If memory, add on the PCI bridge address offset */
	312	if (mmap_state == pci_mmap_mem) {
	313	res_bit = IORESOURCE_MEM;
	314	} else {
	315	io_offset = (unsigned long)pci_ctrl->io_space.base;
	316	offset += io_offset;
	317	res_bit = IORESOURCE_IO;
	318	}
	319
	320	/*
	321	* Check that the offset requested corresponds to one of the
	322	* resources of the device.
	323	*/
	324	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
	325	struct resource *rp = &dev->resource[i];
	326	int flags = rp->flags;
	327
	328	/* treat ROM as memory (should be already) */
	329	if (i == PCI_ROM_RESOURCE)
	330	flags \|= IORESOURCE_MEM;
	331
	332	/* Active and same type? */
	333	if ((flags & res_bit) == 0)
	334	continue;
	335
	336	/* In the range of this resource? */
	337	if (offset < (rp->start & PAGE_MASK) \|\| offset > rp->end)
	338	continue;
	339
	340	/* found it! construct the final physical address */
	341	if (mmap_state == pci_mmap_io)
	342	offset += pci_ctrl->io_space.start - io_offset;
	343	vma->vm_pgoff = offset >> PAGE_SHIFT;
	344	return 0;
	345	}
346
347	return -EINVAL;
348	}
349
5a0015d6 CZ	350	/*
	351	* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
	352	* device mapping.
	353	*/
	354	static __inline__ void
	355	__pci_mmap_set_pgprot(struct pci_dev dev, struct vm_area_struct vma,
	356	enum pci_mmap_state mmap_state, int write_combine)
	357	{
	358	int prot = pgprot_val(vma->vm_page_prot);
	359
	360	/* Set to write-through */
	361	prot &= ~_PAGE_NO_CACHE;
	362	#if 0
	363	if (!write_combine)
	364	prot \|= _PAGE_WRITETHRU;
	365	#endif
	366	vma->vm_page_prot = __pgprot(prot);
	367	}
	368
	369	/*
	370	* Perform the actual remap of the pages for a PCI device mapping, as
	371	* appropriate for this architecture. The region in the process to map
	372	* is described by vm_start and vm_end members of VMA, the base physical
	373	* address is found in vm_pgoff.
	374	* The pci device structure is provided so that architectures may make mapping
	375	* decisions on a per-device or per-bus basis.
	376	*
	377	* Returns a negative error code on failure, zero on success.
	378	*/
	379	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	380	enum pci_mmap_state mmap_state,
	381	int write_combine)
	382	{
	383	int ret;
	384
	385	ret = __pci_mmap_make_offset(dev, vma, mmap_state);
	386	if (ret < 0)
	387	return ret;
	388
5a0015d6 CZ	389	__pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
5a0015d6 CZ	390
288a60cf CZ	391	ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
288a60cf CZ	392	vma->vm_end - vma->vm_start,vma->vm_page_prot);
5a0015d6 CZ	393
	394	return ret;
	395	}