[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86_64 / kernel / suspend.c

/*
 * Suspend support specific for i386.
 *
 * Distribute under GPLv2
 *
 * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
 */

#include <linux/smp.h>
#include <linux/suspend.h>
#include <asm/proto.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mtrr.h>

/* References to section boundaries */
extern const void __nosave_begin, __nosave_end;

struct saved_context saved_context;

unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx;
unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi;
unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11;
unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15;
unsigned long saved_context_eflags;

void __save_processor_state(struct saved_context *ctxt)
{
	kernel_fpu_begin();

	/*
	 * descriptor tables
	 */
	asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
	asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
	asm volatile ("str %0"  : "=m" (ctxt->tr));

	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
	/*
	 * segment registers
	 */
	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));

	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
	mtrr_save_fixed_ranges(NULL);

	/*
	 * control registers 
	 */
	rdmsrl(MSR_EFER, ctxt->efer);
	asm volatile ("movq %%cr0, %0" : "=r" (ctxt->cr0));
	asm volatile ("movq %%cr2, %0" : "=r" (ctxt->cr2));
	asm volatile ("movq %%cr3, %0" : "=r" (ctxt->cr3));
	asm volatile ("movq %%cr4, %0" : "=r" (ctxt->cr4));
	asm volatile ("movq %%cr8, %0" : "=r" (ctxt->cr8));
}

void save_processor_state(void)
{
	__save_processor_state(&saved_context);
}

static void do_fpu_end(void)
{
	/*
	 * Restore FPU regs if necessary
	 */
	kernel_fpu_end();
}

void __restore_processor_state(struct saved_context *ctxt)
{
	/*
	 * control registers
	 */
	wrmsrl(MSR_EFER, ctxt->efer);
	asm volatile ("movq %0, %%cr8" :: "r" (ctxt->cr8));
	asm volatile ("movq %0, %%cr4" :: "r" (ctxt->cr4));
	asm volatile ("movq %0, %%cr3" :: "r" (ctxt->cr3));
	asm volatile ("movq %0, %%cr2" :: "r" (ctxt->cr2));
	asm volatile ("movq %0, %%cr0" :: "r" (ctxt->cr0));

	/*
	 * now restore the descriptor tables to their proper values
	 * ltr is done i fix_processor_context().
	 */
	asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
	asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));

	/*
	 * segment registers
	 */
	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	load_gs_index(ctxt->gs);
	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));

	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);

	fix_processor_context();

	do_fpu_end();
	mtrr_ap_init();
}

void restore_processor_state(void)
{
	__restore_processor_state(&saved_context);
}

void fix_processor_context(void)
{
	int cpu = smp_processor_id();
	struct tss_struct *t = &per_cpu(init_tss, cpu);

	set_tss_desc(cpu,t);	/* This just modifies memory; should not be neccessary. But... This is neccessary, because 386 hardware has concept of busy TSS or some similar stupidity. */

	cpu_gdt(cpu)[GDT_ENTRY_TSS].type = 9;

	syscall_init();                         /* This sets MSR_*STAR and related */
	load_TR_desc();				/* This does ltr */
	load_LDT(&current->active_mm->context);	/* This does lldt */

	/*
	 * Now maybe reload the debug registers
	 */
	if (current->thread.debugreg7){
                loaddebug(&current->thread, 0);
                loaddebug(&current->thread, 1);
                loaddebug(&current->thread, 2);
                loaddebug(&current->thread, 3);
                /* no 4 and 5 */
                loaddebug(&current->thread, 6);
                loaddebug(&current->thread, 7);
	}

}

#ifdef CONFIG_SOFTWARE_SUSPEND
/* Defined in arch/x86_64/kernel/suspend_asm.S */
extern int restore_image(void);

pgd_t *temp_level4_pgt;

static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
{
	long i, j;

	i = pud_index(address);
	pud = pud + i;
	for (; i < PTRS_PER_PUD; pud++, i++) {
		unsigned long paddr;
		pmd_t *pmd;

		paddr = address + i*PUD_SIZE;
		if (paddr >= end)
			break;

		pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
		if (!pmd)
			return -ENOMEM;
		set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
		for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
			unsigned long pe;

			if (paddr >= end)
				break;
			pe = _PAGE_NX | _PAGE_PSE | _KERNPG_TABLE | paddr;
			pe &= __supported_pte_mask;
			set_pmd(pmd, __pmd(pe));
		}
	}
	return 0;
}

static int set_up_temporary_mappings(void)
{
	unsigned long start, end, next;
	int error;

	temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
	if (!temp_level4_pgt)
		return -ENOMEM;

	/* It is safe to reuse the original kernel mapping */
	set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
		init_level4_pgt[pgd_index(__START_KERNEL_map)]);

	/* Set up the direct mapping from scratch */
	start = (unsigned long)pfn_to_kaddr(0);
	end = (unsigned long)pfn_to_kaddr(end_pfn);

	for (; start < end; start = next) {
		pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC);
		if (!pud)
			return -ENOMEM;
		next = start + PGDIR_SIZE;
		if (next > end)
			next = end;
		if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
			return error;
		set_pgd(temp_level4_pgt + pgd_index(start),
			mk_kernel_pgd(__pa(pud)));
	}
	return 0;
}

int swsusp_arch_resume(void)
{
	int error;

	/* We have got enough memory and from now on we cannot recover */
	if ((error = set_up_temporary_mappings()))
		return error;
	restore_image();
	return 0;
}

/*
 *	pfn_is_nosave - check if given pfn is in the 'nosave' section
 */

int pfn_is_nosave(unsigned long pfn)
{
	unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
	unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
	return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
}
#endif /* CONFIG_SOFTWARE_SUSPEND */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Suspend support specific for i386.
	3	*
	4	* Distribute under GPLv2
	5	*
	6	* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
	7	* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
	8	*/
	9
55679edb	10	#include <linux/smp.h>
1da177e4	11	#include <linux/suspend.h>
1da177e4	12	#include <asm/proto.h>
3dd08325 RW	13	#include <asm/page.h>
3dd08325 RW	14	#include <asm/pgtable.h>
3ebad590	15	#include <asm/mtrr.h>
1da177e4	16
49c3df6a VG	17	/* References to section boundaries */
	18	extern const void __nosave_begin, __nosave_end;
	19
1da177e4 LT	20	struct saved_context saved_context;
	21
	22	unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx;
	23	unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi;
	24	unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11;
	25	unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15;
	26	unsigned long saved_context_eflags;
	27
	28	void __save_processor_state(struct saved_context *ctxt)
	29	{
	30	kernel_fpu_begin();
	31
	32	/*
	33	* descriptor tables
	34	*/
	35	asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
	36	asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
1da177e4 LT	37	asm volatile ("str %0" : "=m" (ctxt->tr));
	38
	39	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
1da177e4 LT	40	/*
	41	* segment registers
	42	*/
	43	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	44	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	45	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	46	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	47	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
	48
	49	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	50	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	51	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
3ebad590	52	mtrr_save_fixed_ranges(NULL);
1da177e4 LT	53
	54	/*
	55	* control registers
	56	*/
3c321bce	57	rdmsrl(MSR_EFER, ctxt->efer);
1da177e4 LT	58	asm volatile ("movq %%cr0, %0" : "=r" (ctxt->cr0));
	59	asm volatile ("movq %%cr2, %0" : "=r" (ctxt->cr2));
	60	asm volatile ("movq %%cr3, %0" : "=r" (ctxt->cr3));
	61	asm volatile ("movq %%cr4, %0" : "=r" (ctxt->cr4));
8d783b3e	62	asm volatile ("movq %%cr8, %0" : "=r" (ctxt->cr8));
1da177e4 LT	63	}
	64
	65	void save_processor_state(void)
	66	{
	67	__save_processor_state(&saved_context);
	68	}
	69
08967f94	70	static void do_fpu_end(void)
1da177e4	71	{
08967f94 SL	72	/*
	73	* Restore FPU regs if necessary
	74	*/
	75	kernel_fpu_end();
1da177e4 LT	76	}
	77
	78	void __restore_processor_state(struct saved_context *ctxt)
	79	{
	80	/*
	81	* control registers
	82	*/
3c321bce	83	wrmsrl(MSR_EFER, ctxt->efer);
8d783b3e	84	asm volatile ("movq %0, %%cr8" :: "r" (ctxt->cr8));
1da177e4 LT	85	asm volatile ("movq %0, %%cr4" :: "r" (ctxt->cr4));
	86	asm volatile ("movq %0, %%cr3" :: "r" (ctxt->cr3));
	87	asm volatile ("movq %0, %%cr2" :: "r" (ctxt->cr2));
	88	asm volatile ("movq %0, %%cr0" :: "r" (ctxt->cr0));
	89
8d783b3e PM	90	/*
	91	* now restore the descriptor tables to their proper values
	92	* ltr is done i fix_processor_context().
	93	*/
	94	asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
	95	asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));
	96
1da177e4 LT	97	/*
	98	* segment registers
	99	*/
	100	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	101	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	102	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	103	load_gs_index(ctxt->gs);
	104	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
	105
	106	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	107	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	108	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
	109
1da177e4 LT	110	fix_processor_context();
	111
	112	do_fpu_end();
3b520b23	113	mtrr_ap_init();
1da177e4 LT	114	}
	115
	116	void restore_processor_state(void)
	117	{
	118	__restore_processor_state(&saved_context);
	119	}
	120
	121	void fix_processor_context(void)
	122	{
	123	int cpu = smp_processor_id();
	124	struct tss_struct *t = &per_cpu(init_tss, cpu);
	125
	126	set_tss_desc(cpu,t); /* This just modifies memory; should not be neccessary. But... This is neccessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
	127
c11efdf9	128	cpu_gdt(cpu)[GDT_ENTRY_TSS].type = 9;
1da177e4 LT	129
	130	syscall_init(); /* This sets MSR_STAR and related /
	131	load_TR_desc(); /* This does ltr */
	132	load_LDT(&current->active_mm->context); /* This does lldt */
	133
	134	/*
	135	* Now maybe reload the debug registers
	136	*/
	137	if (current->thread.debugreg7){
	138	loaddebug(&current->thread, 0);
	139	loaddebug(&current->thread, 1);
	140	loaddebug(&current->thread, 2);
	141	loaddebug(&current->thread, 3);
	142	/* no 4 and 5 */
	143	loaddebug(&current->thread, 6);
	144	loaddebug(&current->thread, 7);
	145	}
	146
	147	}
	148
3dd08325 RW	149	#ifdef CONFIG_SOFTWARE_SUSPEND
	150	/* Defined in arch/x86_64/kernel/suspend_asm.S */
	151	extern int restore_image(void);
1da177e4	152
3dd08325 RW	153	pgd_t *temp_level4_pgt;
3dd08325 RW	154
2c1b4a5c	155	static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
3dd08325 RW	156	{
	157	long i, j;
	158
	159	i = pud_index(address);
	160	pud = pud + i;
	161	for (; i < PTRS_PER_PUD; pud++, i++) {
	162	unsigned long paddr;
	163	pmd_t *pmd;
	164
	165	paddr = address + i*PUD_SIZE;
	166	if (paddr >= end)
	167	break;
	168
2c1b4a5c RW	169	pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
	170	if (!pmd)
	171	return -ENOMEM;
3dd08325 RW	172	set_pud(pud, __pud(__pa(pmd) \| _KERNPG_TABLE));
	173	for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
	174	unsigned long pe;
	175
	176	if (paddr >= end)
	177	break;
	178	pe = _PAGE_NX \| _PAGE_PSE \| _KERNPG_TABLE \| paddr;
	179	pe &= __supported_pte_mask;
	180	set_pmd(pmd, __pmd(pe));
	181	}
	182	}
2c1b4a5c	183	return 0;
3dd08325 RW	184	}
3dd08325 RW	185
2c1b4a5c	186	static int set_up_temporary_mappings(void)
3dd08325 RW	187	{
3dd08325 RW	188	unsigned long start, end, next;
2c1b4a5c	189	int error;
3dd08325	190
2c1b4a5c RW	191	temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
	192	if (!temp_level4_pgt)
	193	return -ENOMEM;
3dd08325 RW	194
	195	/* It is safe to reuse the original kernel mapping */
	196	set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
	197	init_level4_pgt[pgd_index(__START_KERNEL_map)]);
	198
	199	/* Set up the direct mapping from scratch */
	200	start = (unsigned long)pfn_to_kaddr(0);
	201	end = (unsigned long)pfn_to_kaddr(end_pfn);
	202
	203	for (; start < end; start = next) {
2c1b4a5c RW	204	pud_t pud = (pud_t )get_safe_page(GFP_ATOMIC);
	205	if (!pud)
	206	return -ENOMEM;
3dd08325 RW	207	next = start + PGDIR_SIZE;
	208	if (next > end)
	209	next = end;
2c1b4a5c RW	210	if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
2c1b4a5c RW	211	return error;
3dd08325 RW	212	set_pgd(temp_level4_pgt + pgd_index(start),
	213	mk_kernel_pgd(__pa(pud)));
	214	}
2c1b4a5c	215	return 0;
3dd08325 RW	216	}
	217
	218	int swsusp_arch_resume(void)
	219	{
2c1b4a5c	220	int error;
3dd08325	221
3dd08325	222	/* We have got enough memory and from now on we cannot recover */
2c1b4a5c RW	223	if ((error = set_up_temporary_mappings()))
2c1b4a5c RW	224	return error;
3dd08325 RW	225	restore_image();
	226	return 0;
	227	}
49c3df6a VG	228
	229	/*
	230	* pfn_is_nosave - check if given pfn is in the 'nosave' section
	231	*/
	232
	233	int pfn_is_nosave(unsigned long pfn)
	234	{
	235	unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
	236	unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
	237	return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
	238	}
3dd08325	239	#endif /* CONFIG_SOFTWARE_SUSPEND */