projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] vt: Remove VT-specific declarations and definitions from tty.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86_64 / kernel / setup.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/x86-64/kernel/setup.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 *
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
1da177e4
LT		 8 */
9
10/*
11 * This file handles the architecture-dependent parts of initialization
12 */
13
14#include <linux/errno.h>
15#include <linux/sched.h>
16#include <linux/kernel.h>
17#include <linux/mm.h>
18#include <linux/stddef.h>
19#include <linux/unistd.h>
20#include <linux/ptrace.h>
21#include <linux/slab.h>
22#include <linux/user.h>
23#include <linux/a.out.h>
24#include <linux/tty.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/initrd.h>
29#include <linux/highmem.h>
30#include <linux/bootmem.h>
31#include <linux/module.h>
32#include <asm/processor.h>
33#include <linux/console.h>
34#include <linux/seq_file.h>
aac04b32 35#include <linux/crash_dump.h>
1da177e4
LT		 36#include <linux/root_dev.h>
37#include <linux/pci.h>
38#include <linux/acpi.h>
39#include <linux/kallsyms.h>
40#include <linux/edd.h>
bbfceef4 41#include <linux/mmzone.h>
5f5609df 42#include <linux/kexec.h>
95235ca2 43#include <linux/cpufreq.h>
e9928674 44#include <linux/dmi.h>
17a941d8 45#include <linux/dma-mapping.h>
681558fd 46#include <linux/ctype.h>
bbfceef4 47
1da177e4
LT		 48#include <asm/mtrr.h>
49#include <asm/uaccess.h>
50#include <asm/system.h>
51#include <asm/io.h>
52#include <asm/smp.h>
53#include <asm/msr.h>
54#include <asm/desc.h>
55#include <video/edid.h>
56#include <asm/e820.h>
57#include <asm/dma.h>
58#include <asm/mpspec.h>
59#include <asm/mmu_context.h>
60#include <asm/bootsetup.h>
61#include <asm/proto.h>
62#include <asm/setup.h>
63#include <asm/mach_apic.h>
64#include <asm/numa.h>
2bc0414e 65#include <asm/sections.h>
f2d3efed 66#include <asm/dmi.h>
1da177e4
LT		 67
68/*
69 * Machine setup..
70 */
71
6c231b7b 72struct cpuinfo_x86 boot_cpu_data __read_mostly;
2ee60e17 73EXPORT_SYMBOL(boot_cpu_data);
1da177e4
LT		 74
75unsigned long mmu_cr4_features;
76
77int acpi_disabled;
78EXPORT_SYMBOL(acpi_disabled);
888ba6c6 79#ifdef CONFIG_ACPI
1da177e4
LT		 80extern int __initdata acpi_ht;
81extern acpi_interrupt_flags acpi_sci_flags;
82int __initdata acpi_force = 0;
83#endif
84
85int acpi_numa __initdata;
86
1da177e4
LT		 87/* Boot loader ID as an integer, for the benefit of proc_dointvec */
88int bootloader_type;
89
90unsigned long saved_video_mode;
91
f2d3efed
AK		 92/*
93 * Early DMI memory
94 */
95int dmi_alloc_index;
96char dmi_alloc_data[DMI_MAX_DATA];
97
1da177e4
LT		 98/*
99 * Setup options
100 */
1da177e4 101struct screen_info screen_info;
2ee60e17 102EXPORT_SYMBOL(screen_info);
1da177e4
LT		 103struct sys_desc_table_struct {
104 unsigned short length;
105 unsigned char table[0];
106};
107
108struct edid_info edid_info;
ba70710e 109EXPORT_SYMBOL_GPL(edid_info);
1da177e4
LT		 110struct e820map e820;
111
112extern int root_mountflags;
1da177e4
LT		 113
114char command_line[COMMAND_LINE_SIZE];
115
116struct resource standard_io_resources[] = {
117 { .name = "dma1", .start = 0x00, .end = 0x1f,
118 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
119 { .name = "pic1", .start = 0x20, .end = 0x21,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
121 { .name = "timer0", .start = 0x40, .end = 0x43,
122 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
123 { .name = "timer1", .start = 0x50, .end = 0x53,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "keyboard", .start = 0x60, .end = 0x6f,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "pic2", .start = 0xa0, .end = 0xa1,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
131 { .name = "dma2", .start = 0xc0, .end = 0xdf,
132 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
133 { .name = "fpu", .start = 0xf0, .end = 0xff,
134 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
135};
136
137#define STANDARD_IO_RESOURCES \
138 (sizeof standard_io_resources / sizeof standard_io_resources[0])
139
140#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
141
142struct resource data_resource = {
143 .name = "Kernel data",
144 .start = 0,
145 .end = 0,
146 .flags = IORESOURCE_RAM,
147};
148struct resource code_resource = {
149 .name = "Kernel code",
150 .start = 0,
151 .end = 0,
152 .flags = IORESOURCE_RAM,
153};
154
155#define IORESOURCE_ROM (IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM)
156
157static struct resource system_rom_resource = {
158 .name = "System ROM",
159 .start = 0xf0000,
160 .end = 0xfffff,
161 .flags = IORESOURCE_ROM,
162};
163
164static struct resource extension_rom_resource = {
165 .name = "Extension ROM",
166 .start = 0xe0000,
167 .end = 0xeffff,
168 .flags = IORESOURCE_ROM,
169};
170
171static struct resource adapter_rom_resources[] = {
172 { .name = "Adapter ROM", .start = 0xc8000, .end = 0,
173 .flags = IORESOURCE_ROM },
174 { .name = "Adapter ROM", .start = 0, .end = 0,
175 .flags = IORESOURCE_ROM },
176 { .name = "Adapter ROM", .start = 0, .end = 0,
177 .flags = IORESOURCE_ROM },
178 { .name = "Adapter ROM", .start = 0, .end = 0,
179 .flags = IORESOURCE_ROM },
180 { .name = "Adapter ROM", .start = 0, .end = 0,
181 .flags = IORESOURCE_ROM },
182 { .name = "Adapter ROM", .start = 0, .end = 0,
183 .flags = IORESOURCE_ROM }
184};
185
186#define ADAPTER_ROM_RESOURCES \
187 (sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
188
189static struct resource video_rom_resource = {
190 .name = "Video ROM",
191 .start = 0xc0000,
192 .end = 0xc7fff,
193 .flags = IORESOURCE_ROM,
194};
195
196static struct resource video_ram_resource = {
197 .name = "Video RAM area",
198 .start = 0xa0000,
199 .end = 0xbffff,
200 .flags = IORESOURCE_RAM,
201};
202
203#define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
204
205static int __init romchecksum(unsigned char *rom, unsigned long length)
206{
207 unsigned char *p, sum = 0;
208
209 for (p = rom; p < rom + length; p++)
210 sum += *p;
211 return sum == 0;
212}
213
214static void __init probe_roms(void)
215{
216 unsigned long start, length, upper;
217 unsigned char *rom;
218 int i;
219
220 /* video rom */
221 upper = adapter_rom_resources[0].start;
222 for (start = video_rom_resource.start; start < upper; start += 2048) {
223 rom = isa_bus_to_virt(start);
224 if (!romsignature(rom))
225 continue;
226
227 video_rom_resource.start = start;
228
229 /* 0 < length <= 0x7f * 512, historically */
230 length = rom[2] * 512;
231
232 /* if checksum okay, trust length byte */
233 if (length && romchecksum(rom, length))
234 video_rom_resource.end = start + length - 1;
235
236 request_resource(&iomem_resource, &video_rom_resource);
237 break;
238 }
239
240 start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
241 if (start < upper)
242 start = upper;
243
244 /* system rom */
245 request_resource(&iomem_resource, &system_rom_resource);
246 upper = system_rom_resource.start;
247
248 /* check for extension rom (ignore length byte!) */
249 rom = isa_bus_to_virt(extension_rom_resource.start);
250 if (romsignature(rom)) {
251 length = extension_rom_resource.end - extension_rom_resource.start + 1;
252 if (romchecksum(rom, length)) {
253 request_resource(&iomem_resource, &extension_rom_resource);
254 upper = extension_rom_resource.start;
255 }
256 }
257
258 /* check for adapter roms on 2k boundaries */
259 for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
260 rom = isa_bus_to_virt(start);
261 if (!romsignature(rom))
262 continue;
263
264 /* 0 < length <= 0x7f * 512, historically */
265 length = rom[2] * 512;
266
267 /* but accept any length that fits if checksum okay */
268 if (!length || start + length > upper || !romchecksum(rom, length))
269 continue;
270
271 adapter_rom_resources[i].start = start;
272 adapter_rom_resources[i].end = start + length - 1;
273 request_resource(&iomem_resource, &adapter_rom_resources[i]);
274
275 start = adapter_rom_resources[i++].end & ~2047UL;
276 }
277}
278
681558fd
AK		 279/* Check for full argument with no trailing characters */
280static int fullarg(char *p, char *arg)
281{
282 int l = strlen(arg);
283 return !memcmp(p, arg, l) && (p[l] == 0 || isspace(p[l]));
284}
285
1da177e4
LT		 286static __init void parse_cmdline_early (char ** cmdline_p)
287{
288 char c = ' ', *to = command_line, *from = COMMAND_LINE;
289 int len = 0;
69cda7b1 290 int userdef = 0;
1da177e4 291
1da177e4
LT		 292 for (;;) {
293 if (c != ' ')
294 goto next_char;
295
296#ifdef CONFIG_SMP
297 /*
298 * If the BIOS enumerates physical processors before logical,
299 * maxcpus=N at enumeration-time can be used to disable HT.
300 */
301 else if (!memcmp(from, "maxcpus=", 8)) {
302 extern unsigned int maxcpus;
303
304 maxcpus = simple_strtoul(from + 8, NULL, 0);
305 }
306#endif
888ba6c6 307#ifdef CONFIG_ACPI
1da177e4 308 /* "acpi=off" disables both ACPI table parsing and interpreter init */
681558fd 309 if (fullarg(from,"acpi=off"))
1da177e4
LT		 310 disable_acpi();
311
681558fd 312 if (fullarg(from, "acpi=force")) {
1da177e4
LT		 313 /* add later when we do DMI horrors: */
314 acpi_force = 1;
315 acpi_disabled = 0;
316 }
317
318 /* acpi=ht just means: do ACPI MADT parsing
319 at bootup, but don't enable the full ACPI interpreter */
681558fd 320 if (fullarg(from, "acpi=ht")) {
1da177e4
LT		 321 if (!acpi_force)
322 disable_acpi();
323 acpi_ht = 1;
324 }
681558fd 325 else if (fullarg(from, "pci=noacpi"))
1da177e4 326 acpi_disable_pci();
681558fd 327 else if (fullarg(from, "acpi=noirq"))
1da177e4
LT		 328 acpi_noirq_set();
329
681558fd 330 else if (fullarg(from, "acpi_sci=edge"))
1da177e4 331 acpi_sci_flags.trigger = 1;
681558fd 332 else if (fullarg(from, "acpi_sci=level"))
1da177e4 333 acpi_sci_flags.trigger = 3;
681558fd 334 else if (fullarg(from, "acpi_sci=high"))
1da177e4 335 acpi_sci_flags.polarity = 1;
681558fd 336 else if (fullarg(from, "acpi_sci=low"))
1da177e4
LT		 337 acpi_sci_flags.polarity = 3;
338
339 /* acpi=strict disables out-of-spec workarounds */
681558fd 340 else if (fullarg(from, "acpi=strict")) {
1da177e4
LT		 341 acpi_strict = 1;
342 }
22999244 343#ifdef CONFIG_X86_IO_APIC
681558fd 344 else if (fullarg(from, "acpi_skip_timer_override"))
22999244
AK		 345 acpi_skip_timer_override = 1;
346#endif
1da177e4
LT		 347#endif
348
681558fd 349 if (fullarg(from, "disable_timer_pin_1"))
66759a01 350 disable_timer_pin_1 = 1;
681558fd 351 if (fullarg(from, "enable_timer_pin_1"))
66759a01
CE		 352 disable_timer_pin_1 = -1;
353
d1530d82
AK		 354 if (fullarg(from, "nolapic") || fullarg(from, "disableapic")) {
355 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1da177e4 356 disable_apic = 1;
d1530d82 357 }
1da177e4 358
681558fd 359 if (fullarg(from, "noapic"))
1da177e4
LT		 360 skip_ioapic_setup = 1;
361
681558fd 362 if (fullarg(from,"apic")) {
1da177e4
LT		 363 skip_ioapic_setup = 0;
364 ioapic_force = 1;
365 }
366
367 if (!memcmp(from, "mem=", 4))
368 parse_memopt(from+4, &from);
369
69cda7b1
AM		 370 if (!memcmp(from, "memmap=", 7)) {
371 /* exactmap option is for used defined memory */
372 if (!memcmp(from+7, "exactmap", 8)) {
373#ifdef CONFIG_CRASH_DUMP
374 /* If we are doing a crash dump, we
375 * still need to know the real mem
376 * size before original memory map is
377 * reset.
378 */
379 saved_max_pfn = e820_end_of_ram();
380#endif
381 from += 8+7;
382 end_pfn_map = 0;
383 e820.nr_map = 0;
384 userdef = 1;
385 }
386 else {
387 parse_memmapopt(from+7, &from);
388 userdef = 1;
389 }
390 }
391
2b97690f 392#ifdef CONFIG_NUMA
1da177e4
LT		 393 if (!memcmp(from, "numa=", 5))
394 numa_setup(from+5);
395#endif
396
1da177e4
LT		 397 if (!memcmp(from,"iommu=",6)) {
398 iommu_setup(from+6);
399 }
1da177e4 400
681558fd 401 if (fullarg(from,"oops=panic"))
1da177e4
LT		 402 panic_on_oops = 1;
403
404 if (!memcmp(from, "noexec=", 7))
405 nonx_setup(from + 7);
406
5f5609df
EB		 407#ifdef CONFIG_KEXEC
408 /* crashkernel=size@addr specifies the location to reserve for
409 * a crash kernel. By reserving this memory we guarantee
410 * that linux never set's it up as a DMA target.
411 * Useful for holding code to do something appropriate
412 * after a kernel panic.
413 */
414 else if (!memcmp(from, "crashkernel=", 12)) {
415 unsigned long size, base;
416 size = memparse(from+12, &from);
417 if (*from == '@') {
418 base = memparse(from+1, &from);
419 /* FIXME: Do I want a sanity check
420 * to validate the memory range?
421 */
422 crashk_res.start = base;
423 crashk_res.end = base + size - 1;
424 }
425 }
426#endif
427
aac04b32
VG		 428#ifdef CONFIG_PROC_VMCORE
429 /* elfcorehdr= specifies the location of elf core header
430 * stored by the crashed kernel. This option will be passed
431 * by kexec loader to the capture kernel.
432 */
433 else if(!memcmp(from, "elfcorehdr=", 11))
434 elfcorehdr_addr = memparse(from+11, &from);
435#endif
e2c03888 436
d5176123 437#ifdef CONFIG_HOTPLUG_CPU
e2c03888
AK		 438 else if (!memcmp(from, "additional_cpus=", 16))
439 setup_additional_cpus(from+16);
440#endif
441
1da177e4
LT		 442 next_char:
443 c = *(from++);
444 if (!c)
445 break;
446 if (COMMAND_LINE_SIZE <= ++len)
447 break;
448 *(to++) = c;
449 }
69cda7b1
AM		 450 if (userdef) {
451 printk(KERN_INFO "user-defined physical RAM map:\n");
452 e820_print_map("user");
453 }
1da177e4
LT		 454 *to = '\0';
455 *cmdline_p = command_line;
456}
457
2b97690f 458#ifndef CONFIG_NUMA
bbfceef4
MT		 459static void __init
460contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
1da177e4 461{
bbfceef4
MT		 462 unsigned long bootmap_size, bootmap;
463
bbfceef4
MT		 464 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
465 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
466 if (bootmap == -1L)
467 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
468 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
469 e820_bootmem_free(NODE_DATA(0), 0, end_pfn << PAGE_SHIFT);
470 reserve_bootmem(bootmap, bootmap_size);
1da177e4
LT		 471}
472#endif
473
1da177e4
LT		 474#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
475struct edd edd;
476#ifdef CONFIG_EDD_MODULE
477EXPORT_SYMBOL(edd);
478#endif
479/**
480 * copy_edd() - Copy the BIOS EDD information
481 * from boot_params into a safe place.
482 *
483 */
484static inline void copy_edd(void)
485{
486 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
487 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
488 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
489 edd.edd_info_nr = EDD_NR;
490}
491#else
492static inline void copy_edd(void)
493{
494}
495#endif
496
497#define EBDA_ADDR_POINTER 0x40E
ac71d12c
AK		 498
499unsigned __initdata ebda_addr;
500unsigned __initdata ebda_size;
501
502static void discover_ebda(void)
1da177e4 503{
ac71d12c 504 /*
1da177e4
LT		 505 * there is a real-mode segmented pointer pointing to the
506 * 4K EBDA area at 0x40E
507 */
ac71d12c
AK		 508 ebda_addr = *(unsigned short *)EBDA_ADDR_POINTER;
509 ebda_addr <<= 4;
510
511 ebda_size = *(unsigned short *)(unsigned long)ebda_addr;
512
513 /* Round EBDA up to pages */
514 if (ebda_size == 0)
515 ebda_size = 1;
516 ebda_size <<= 10;
517 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
518 if (ebda_size > 64*1024)
519 ebda_size = 64*1024;
1da177e4
LT		 520}
521
522void __init setup_arch(char **cmdline_p)
523{
1da177e4
LT		 524 unsigned long kernel_end;
525
526 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
1da177e4
LT		 527 screen_info = SCREEN_INFO;
528 edid_info = EDID_INFO;
529 saved_video_mode = SAVED_VIDEO_MODE;
530 bootloader_type = LOADER_TYPE;
531
532#ifdef CONFIG_BLK_DEV_RAM
533 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
534 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
535 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
536#endif
537 setup_memory_region();
538 copy_edd();
539
540 if (!MOUNT_ROOT_RDONLY)
541 root_mountflags &= ~MS_RDONLY;
542 init_mm.start_code = (unsigned long) &_text;
543 init_mm.end_code = (unsigned long) &_etext;
544 init_mm.end_data = (unsigned long) &_edata;
545 init_mm.brk = (unsigned long) &_end;
546
547 code_resource.start = virt_to_phys(&_text);
548 code_resource.end = virt_to_phys(&_etext)-1;
549 data_resource.start = virt_to_phys(&_etext);
550 data_resource.end = virt_to_phys(&_edata)-1;
551
552 parse_cmdline_early(cmdline_p);
553
554 early_identify_cpu(&boot_cpu_data);
555
556 /*
557 * partially used pages are not usable - thus
558 * we are rounding upwards:
559 */
560 end_pfn = e820_end_of_ram();
1f50249e 561 num_physpages = end_pfn; /* for pfn_valid */
1da177e4
LT		 562
563 check_efer();
564
ac71d12c
AK		 565 discover_ebda();
566
1da177e4
LT		 567 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
568
f2d3efed
AK		 569 dmi_scan_machine();
570
f6c2e333
SS		 571 zap_low_mappings(0);
572
888ba6c6 573#ifdef CONFIG_ACPI
1da177e4
LT		 574 /*
575 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
576 * Call this early for SRAT node setup.
577 */
578 acpi_boot_table_init();
579#endif
580
581#ifdef CONFIG_ACPI_NUMA
582 /*
583 * Parse SRAT to discover nodes.
584 */
585 acpi_numa_init();
586#endif
587
2b97690f 588#ifdef CONFIG_NUMA
1da177e4
LT		 589 numa_initmem_init(0, end_pfn);
590#else
bbfceef4 591 contig_initmem_init(0, end_pfn);
1da177e4
LT		 592#endif
593
594 /* Reserve direct mapping */
595 reserve_bootmem_generic(table_start << PAGE_SHIFT,
596 (table_end - table_start) << PAGE_SHIFT);
597
598 /* reserve kernel */
599 kernel_end = round_up(__pa_symbol(&_end),PAGE_SIZE);
600 reserve_bootmem_generic(HIGH_MEMORY, kernel_end - HIGH_MEMORY);
601
602 /*
603 * reserve physical page 0 - it's a special BIOS page on many boxes,
604 * enabling clean reboots, SMP operation, laptop functions.
605 */
606 reserve_bootmem_generic(0, PAGE_SIZE);
607
608 /* reserve ebda region */
ac71d12c
AK		 609 if (ebda_addr)
610 reserve_bootmem_generic(ebda_addr, ebda_size);
1da177e4
LT		 611
612#ifdef CONFIG_SMP
613 /*
614 * But first pinch a few for the stack/trampoline stuff
615 * FIXME: Don't need the extra page at 4K, but need to fix
616 * trampoline before removing it. (see the GDT stuff)
617 */
618 reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
619
620 /* Reserve SMP trampoline */
621 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
622#endif
623
624#ifdef CONFIG_ACPI_SLEEP
625 /*
626 * Reserve low memory region for sleep support.
627 */
628 acpi_reserve_bootmem();
629#endif
630#ifdef CONFIG_X86_LOCAL_APIC
631 /*
632 * Find and reserve possible boot-time SMP configuration:
633 */
634 find_smp_config();
635#endif
636#ifdef CONFIG_BLK_DEV_INITRD
637 if (LOADER_TYPE && INITRD_START) {
638 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
639 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
640 initrd_start =
641 INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
642 initrd_end = initrd_start+INITRD_SIZE;
643 }
644 else {
645 printk(KERN_ERR "initrd extends beyond end of memory "
646 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
647 (unsigned long)(INITRD_START + INITRD_SIZE),
648 (unsigned long)(end_pfn << PAGE_SHIFT));
649 initrd_start = 0;
650 }
651 }
652#endif
5f5609df
EB		 653#ifdef CONFIG_KEXEC
654 if (crashk_res.start != crashk_res.end) {
00212fef 655 reserve_bootmem_generic(crashk_res.start,
5f5609df
EB		 656 crashk_res.end - crashk_res.start + 1);
657 }
658#endif
0d317fb7 659
1da177e4
LT		 660 paging_init();
661
662 check_ioapic();
663
51f62e18
AR		 664 /*
665 * set this early, so we dont allocate cpu0
666 * if MADT list doesnt list BSP first
667 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
668 */
669 cpu_set(0, cpu_present_map);
888ba6c6 670#ifdef CONFIG_ACPI
1da177e4
LT		 671 /*
672 * Read APIC and some other early information from ACPI tables.
673 */
674 acpi_boot_init();
675#endif
676
05b3cbd8
RT		 677 init_cpu_to_node();
678
1da177e4
LT		 679#ifdef CONFIG_X86_LOCAL_APIC
680 /*
681 * get boot-time SMP configuration:
682 */
683 if (smp_found_config)
684 get_smp_config();
685 init_apic_mappings();
686#endif
687
688 /*
689 * Request address space for all standard RAM and ROM resources
690 * and also for regions reported as reserved by the e820.
691 */
692 probe_roms();
693 e820_reserve_resources();
694
695 request_resource(&iomem_resource, &video_ram_resource);
696
697 {
698 unsigned i;
699 /* request I/O space for devices used on all i[345]86 PCs */
700 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
701 request_resource(&ioport_resource, &standard_io_resources[i]);
702 }
703
a1e97782 704 e820_setup_gap();
1da177e4 705
1da177e4
LT		 706#ifdef CONFIG_VT
707#if defined(CONFIG_VGA_CONSOLE)
708 conswitchp = &vga_con;
709#elif defined(CONFIG_DUMMY_CONSOLE)
710 conswitchp = &dummy_con;
711#endif
712#endif
713}
714
e6982c67 715static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
1da177e4
LT		 716{
717 unsigned int *v;
718
ebfcaa96 719 if (c->extended_cpuid_level < 0x80000004)
1da177e4
LT		 720 return 0;
721
722 v = (unsigned int *) c->x86_model_id;
723 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
724 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
725 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
726 c->x86_model_id[48] = 0;
727 return 1;
728}
729
730
e6982c67 731static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
1da177e4
LT		 732{
733 unsigned int n, dummy, eax, ebx, ecx, edx;
734
ebfcaa96 735 n = c->extended_cpuid_level;
1da177e4
LT		 736
737 if (n >= 0x80000005) {
738 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
739 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
740 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
741 c->x86_cache_size=(ecx>>24)+(edx>>24);
742 /* On K8 L1 TLB is inclusive, so don't count it */
743 c->x86_tlbsize = 0;
744 }
745
746 if (n >= 0x80000006) {
747 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
748 ecx = cpuid_ecx(0x80000006);
749 c->x86_cache_size = ecx >> 16;
750 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
751
752 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
753 c->x86_cache_size, ecx & 0xFF);
754 }
755
756 if (n >= 0x80000007)
757 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
758 if (n >= 0x80000008) {
759 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
760 c->x86_virt_bits = (eax >> 8) & 0xff;
761 c->x86_phys_bits = eax & 0xff;
762 }
763}
764
3f098c26
AK		 765#ifdef CONFIG_NUMA
766static int nearby_node(int apicid)
767{
768 int i;
769 for (i = apicid - 1; i >= 0; i--) {
770 int node = apicid_to_node[i];
771 if (node != NUMA_NO_NODE && node_online(node))
772 return node;
773 }
774 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
775 int node = apicid_to_node[i];
776 if (node != NUMA_NO_NODE && node_online(node))
777 return node;
778 }
779 return first_node(node_online_map); /* Shouldn't happen */
780}
781#endif
782
63518644
AK		 783/*
784 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
785 * Assumes number of cores is a power of two.
786 */
787static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
788{
789#ifdef CONFIG_SMP
b41e2939 790 unsigned bits;
3f098c26 791#ifdef CONFIG_NUMA
f3fa8ebc 792 int cpu = smp_processor_id();
3f098c26 793 int node = 0;
60c1bc82 794 unsigned apicid = hard_smp_processor_id();
3f098c26 795#endif
faee9a5d 796 unsigned ecx = cpuid_ecx(0x80000008);
b41e2939 797
faee9a5d 798 c->x86_max_cores = (ecx & 0xff) + 1;
b41e2939 799
faee9a5d
AK		 800 /* CPU telling us the core id bits shift? */
801 bits = (ecx >> 12) & 0xF;
802
803 /* Otherwise recompute */
804 if (bits == 0) {
805 while ((1 << bits) < c->x86_max_cores)
806 bits++;
807 }
b41e2939
AK		 808
809 /* Low order bits define the core id (index of core in socket) */
f3fa8ebc 810 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
b41e2939 811 /* Convert the APIC ID into the socket ID */
f3fa8ebc 812 c->phys_proc_id = phys_pkg_id(bits);
63518644
AK		 813
814#ifdef CONFIG_NUMA
f3fa8ebc 815 node = c->phys_proc_id;
3f098c26
AK		 816 if (apicid_to_node[apicid] != NUMA_NO_NODE)
817 node = apicid_to_node[apicid];
818 if (!node_online(node)) {
819 /* Two possibilities here:
820 - The CPU is missing memory and no node was created.
821 In that case try picking one from a nearby CPU
822 - The APIC IDs differ from the HyperTransport node IDs
823 which the K8 northbridge parsing fills in.
824 Assume they are all increased by a constant offset,
825 but in the same order as the HT nodeids.
826 If that doesn't result in a usable node fall back to the
827 path for the previous case. */
f3fa8ebc 828 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
3f098c26
AK		 829 if (ht_nodeid >= 0 &&
830 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
831 node = apicid_to_node[ht_nodeid];
832 /* Pick a nearby node */
833 if (!node_online(node))
834 node = nearby_node(apicid);
835 }
69d81fcd 836 numa_set_node(cpu, node);
3f098c26 837
e42f9437 838 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
63518644 839#endif
63518644
AK		 840#endif
841}
1da177e4 842
e42f9437 843static void __init init_amd(struct cpuinfo_x86 *c)
1da177e4 844{
7bcd3f34 845 unsigned level;
1da177e4 846
bc5e8fdf
LT		 847#ifdef CONFIG_SMP
848 unsigned long value;
849
7d318d77
AK		 850 /*
851 * Disable TLB flush filter by setting HWCR.FFDIS on K8
852 * bit 6 of msr C001_0015
853 *
854 * Errata 63 for SH-B3 steppings
855 * Errata 122 for all steppings (F+ have it disabled by default)
856 */
857 if (c->x86 == 15) {
858 rdmsrl(MSR_K8_HWCR, value);
859 value |= 1 << 6;
860 wrmsrl(MSR_K8_HWCR, value);
861 }
bc5e8fdf
LT		 862#endif
863
1da177e4
LT		 864 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
865 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
866 clear_bit(0*32+31, &c->x86_capability);
867
7bcd3f34
AK		 868 /* On C+ stepping K8 rep microcode works well for copy/memset */
869 level = cpuid_eax(1);
870 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
871 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
872
18bd057b
AK		 873 /* Enable workaround for FXSAVE leak */
874 if (c->x86 >= 6)
875 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
876
e42f9437
RS		 877 level = get_model_name(c);
878 if (!level) {
1da177e4
LT		 879 switch (c->x86) {
880 case 15:
881 /* Should distinguish Models here, but this is only
882 a fallback anyways. */
883 strcpy(c->x86_model_id, "Hammer");
884 break;
885 }
886 }
887 display_cacheinfo(c);
888
130951cc
AK		 889 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
890 if (c->x86_power & (1<<8))
891 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
892
faee9a5d
AK		 893 /* Multi core CPU? */
894 if (c->extended_cpuid_level >= 0x80000008)
63518644 895 amd_detect_cmp(c);
1da177e4 896
240cd6a8
AK		 897 /* Fix cpuid4 emulation for more */
898 num_cache_leaves = 3;
1da177e4
LT		 899}
900
e6982c67 901static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1da177e4
LT		 902{
903#ifdef CONFIG_SMP
904 u32 eax, ebx, ecx, edx;
94605eff 905 int index_msb, core_bits;
94605eff
SS		 906
907 cpuid(1, &eax, &ebx, &ecx, &edx);
908
94605eff 909
e42f9437 910 if (!cpu_has(c, X86_FEATURE_HT))
1da177e4 911 return;
e42f9437
RS		 912 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
913 goto out;
1da177e4 914
1da177e4 915 smp_num_siblings = (ebx & 0xff0000) >> 16;
94605eff 916
1da177e4
LT		 917 if (smp_num_siblings == 1) {
918 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
94605eff
SS		 919 } else if (smp_num_siblings > 1 ) {
920
1da177e4
LT		 921 if (smp_num_siblings > NR_CPUS) {
922 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
923 smp_num_siblings = 1;
924 return;
925 }
94605eff
SS		 926
927 index_msb = get_count_order(smp_num_siblings);
f3fa8ebc 928 c->phys_proc_id = phys_pkg_id(index_msb);
3dd9d514 929
94605eff 930 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
3dd9d514 931
94605eff
SS		 932 index_msb = get_count_order(smp_num_siblings) ;
933
934 core_bits = get_count_order(c->x86_max_cores);
3dd9d514 935
f3fa8ebc 936 c->cpu_core_id = phys_pkg_id(index_msb) &
94605eff 937 ((1 << core_bits) - 1);
1da177e4 938 }
e42f9437
RS		 939out:
940 if ((c->x86_max_cores * smp_num_siblings) > 1) {
941 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
942 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
943 }
944
1da177e4
LT		 945#endif
946}
947
3dd9d514
AK		 948/*
949 * find out the number of processor cores on the die
950 */
e6982c67 951static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514 952{
2bbc419f 953 unsigned int eax, t;
3dd9d514
AK		 954
955 if (c->cpuid_level < 4)
956 return 1;
957
2bbc419f 958 cpuid_count(4, 0, &eax, &t, &t, &t);
3dd9d514
AK		 959
960 if (eax & 0x1f)
961 return ((eax >> 26) + 1);
962 else
963 return 1;
964}
965
df0cc26b
AK		 966static void srat_detect_node(void)
967{
968#ifdef CONFIG_NUMA
ddea7be0 969 unsigned node;
df0cc26b 970 int cpu = smp_processor_id();
e42f9437 971 int apicid = hard_smp_processor_id();
df0cc26b
AK		 972
973 /* Don't do the funky fallback heuristics the AMD version employs
974 for now. */
e42f9437 975 node = apicid_to_node[apicid];
df0cc26b 976 if (node == NUMA_NO_NODE)
0d015324 977 node = first_node(node_online_map);
69d81fcd 978 numa_set_node(cpu, node);
df0cc26b
AK		 979
980 if (acpi_numa > 0)
e42f9437 981 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
df0cc26b
AK		 982#endif
983}
984
e6982c67 985static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4
LT		 986{
987 /* Cache sizes */
988 unsigned n;
989
990 init_intel_cacheinfo(c);
0080e667
VP		 991 if (c->cpuid_level > 9 ) {
992 unsigned eax = cpuid_eax(10);
993 /* Check for version and the number of counters */
994 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
995 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
996 }
997
ebfcaa96 998 n = c->extended_cpuid_level;
1da177e4
LT		 999 if (n >= 0x80000008) {
1000 unsigned eax = cpuid_eax(0x80000008);
1001 c->x86_virt_bits = (eax >> 8) & 0xff;
1002 c->x86_phys_bits = eax & 0xff;
af9c142d
SL		 1003 /* CPUID workaround for Intel 0F34 CPU */
1004 if (c->x86_vendor == X86_VENDOR_INTEL &&
1005 c->x86 == 0xF && c->x86_model == 0x3 &&
1006 c->x86_mask == 0x4)
1007 c->x86_phys_bits = 36;
1da177e4
LT		 1008 }
1009
1010 if (c->x86 == 15)
1011 c->x86_cache_alignment = c->x86_clflush_size * 2;
39b3a791
AK		 1012 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
1013 (c->x86 == 0x6 && c->x86_model >= 0x0e))
c29601e9 1014 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
c818a181 1015 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
94605eff 1016 c->x86_max_cores = intel_num_cpu_cores(c);
df0cc26b
AK		 1017
1018 srat_detect_node();
1da177e4
LT		 1019}
1020
672289e9 1021static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1da177e4
LT		 1022{
1023 char *v = c->x86_vendor_id;
1024
1025 if (!strcmp(v, "AuthenticAMD"))
1026 c->x86_vendor = X86_VENDOR_AMD;
1027 else if (!strcmp(v, "GenuineIntel"))
1028 c->x86_vendor = X86_VENDOR_INTEL;
1029 else
1030 c->x86_vendor = X86_VENDOR_UNKNOWN;
1031}
1032
1033struct cpu_model_info {
1034 int vendor;
1035 int family;
1036 char *model_names[16];
1037};
1038
1039/* Do some early cpuid on the boot CPU to get some parameter that are
1040 needed before check_bugs. Everything advanced is in identify_cpu
1041 below. */
e6982c67 1042void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 1043{
1044 u32 tfms;
1045
1046 c->loops_per_jiffy = loops_per_jiffy;
1047 c->x86_cache_size = -1;
1048 c->x86_vendor = X86_VENDOR_UNKNOWN;
1049 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1050 c->x86_vendor_id[0] = '\0'; /* Unset */
1051 c->x86_model_id[0] = '\0'; /* Unset */
1052 c->x86_clflush_size = 64;
1053 c->x86_cache_alignment = c->x86_clflush_size;
94605eff 1054 c->x86_max_cores = 1;
ebfcaa96 1055 c->extended_cpuid_level = 0;
1da177e4
LT		 1056 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1057
1058 /* Get vendor name */
1059 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1060 (unsigned int *)&c->x86_vendor_id[0],
1061 (unsigned int *)&c->x86_vendor_id[8],
1062 (unsigned int *)&c->x86_vendor_id[4]);
1063
1064 get_cpu_vendor(c);
1065
1066 /* Initialize the standard set of capabilities */
1067 /* Note that the vendor-specific code below might override */
1068
1069 /* Intel-defined flags: level 0x00000001 */
1070 if (c->cpuid_level >= 0x00000001) {
1071 __u32 misc;
1072 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1073 &c->x86_capability[0]);
1074 c->x86 = (tfms >> 8) & 0xf;
1075 c->x86_model = (tfms >> 4) & 0xf;
1076 c->x86_mask = tfms & 0xf;
f5f786d0 1077 if (c->x86 == 0xf)
1da177e4 1078 c->x86 += (tfms >> 20) & 0xff;
f5f786d0 1079 if (c->x86 >= 0x6)
1da177e4 1080 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1da177e4
LT		 1081 if (c->x86_capability[0] & (1<<19))
1082 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1da177e4
LT		 1083 } else {
1084 /* Have CPUID level 0 only - unheard of */
1085 c->x86 = 4;
1086 }
a158608b
AK		 1087
1088#ifdef CONFIG_SMP
f3fa8ebc 1089 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
a158608b 1090#endif
1da177e4
LT		 1091}
1092
1093/*
1094 * This does the hard work of actually picking apart the CPU stuff...
1095 */
e6982c67 1096void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 1097{
1098 int i;
1099 u32 xlvl;
1100
1101 early_identify_cpu(c);
1102
1103 /* AMD-defined flags: level 0x80000001 */
1104 xlvl = cpuid_eax(0x80000000);
ebfcaa96 1105 c->extended_cpuid_level = xlvl;
1da177e4
LT		 1106 if ((xlvl & 0xffff0000) == 0x80000000) {
1107 if (xlvl >= 0x80000001) {
1108 c->x86_capability[1] = cpuid_edx(0x80000001);
5b7abc6f 1109 c->x86_capability[6] = cpuid_ecx(0x80000001);
1da177e4
LT		 1110 }
1111 if (xlvl >= 0x80000004)
1112 get_model_name(c); /* Default name */
1113 }
1114
1115 /* Transmeta-defined flags: level 0x80860001 */
1116 xlvl = cpuid_eax(0x80860000);
1117 if ((xlvl & 0xffff0000) == 0x80860000) {
1118 /* Don't set x86_cpuid_level here for now to not confuse. */
1119 if (xlvl >= 0x80860001)
1120 c->x86_capability[2] = cpuid_edx(0x80860001);
1121 }
1122
1e9f28fa
SS		 1123 c->apicid = phys_pkg_id(0);
1124
1da177e4
LT		 1125 /*
1126 * Vendor-specific initialization. In this section we
1127 * canonicalize the feature flags, meaning if there are
1128 * features a certain CPU supports which CPUID doesn't
1129 * tell us, CPUID claiming incorrect flags, or other bugs,
1130 * we handle them here.
1131 *
1132 * At the end of this section, c->x86_capability better
1133 * indicate the features this CPU genuinely supports!
1134 */
1135 switch (c->x86_vendor) {
1136 case X86_VENDOR_AMD:
1137 init_amd(c);
1138 break;
1139
1140 case X86_VENDOR_INTEL:
1141 init_intel(c);
1142 break;
1143
1144 case X86_VENDOR_UNKNOWN:
1145 default:
1146 display_cacheinfo(c);
1147 break;
1148 }
1149
1150 select_idle_routine(c);
1151 detect_ht(c);
1da177e4
LT		 1152
1153 /*
1154 * On SMP, boot_cpu_data holds the common feature set between
1155 * all CPUs; so make sure that we indicate which features are
1156 * common between the CPUs. The first time this routine gets
1157 * executed, c == &boot_cpu_data.
1158 */
1159 if (c != &boot_cpu_data) {
1160 /* AND the already accumulated flags with these */
1161 for (i = 0 ; i < NCAPINTS ; i++)
1162 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1163 }
1164
1165#ifdef CONFIG_X86_MCE
1166 mcheck_init(c);
1167#endif
3b520b23
SL		 1168 if (c == &boot_cpu_data)
1169 mtrr_bp_init();
1170 else
1171 mtrr_ap_init();
1da177e4 1172#ifdef CONFIG_NUMA
3019e8eb 1173 numa_add_cpu(smp_processor_id());
1da177e4
LT		 1174#endif
1175}
1176
1177
e6982c67 1178void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1da177e4
LT		 1179{
1180 if (c->x86_model_id[0])
1181 printk("%s", c->x86_model_id);
1182
1183 if (c->x86_mask || c->cpuid_level >= 0)
1184 printk(" stepping %02x\n", c->x86_mask);
1185 else
1186 printk("\n");
1187}
1188
1189/*
1190 * Get CPU information for use by the procfs.
1191 */
1192
1193static int show_cpuinfo(struct seq_file *m, void *v)
1194{
1195 struct cpuinfo_x86 *c = v;
1196
1197 /*
1198 * These flag bits must match the definitions in <asm/cpufeature.h>.
1199 * NULL means this bit is undefined or reserved; either way it doesn't
1200 * have meaning as far as Linux is concerned. Note that it's important
1201 * to realize there is a difference between this table and CPUID -- if
1202 * applications want to get the raw CPUID data, they should access
1203 * /dev/cpu/<cpu_nr>/cpuid instead.
1204 */
1205 static char *x86_cap_flags[] = {
1206 /* Intel-defined */
1207 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1208 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1209 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1210 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
1211
1212 /* AMD-defined */
3c3b73b6 1213 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1214 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1215 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
7b0e8501 1216 NULL, "fxsr_opt", NULL, "rdtscp", NULL, "lm", "3dnowext", "3dnow",
1da177e4
LT		 1217
1218 /* Transmeta-defined */
1219 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1220 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1221 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1222 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1223
1224 /* Other (Linux-defined) */
622dcaf9 1225 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
c29601e9 1226 "constant_tsc", NULL, NULL,
d167a518 1227 "up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1228 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1229 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1230
1231 /* Intel-defined (#2) */
9d95dd84 1232 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1da177e4
LT		 1233 "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
1234 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1235 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1236
5b7abc6f
PA		 1237 /* VIA/Cyrix/Centaur-defined */
1238 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1239 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1240 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1241 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1242
1da177e4 1243 /* AMD-defined (#2) */
3f98bc49 1244 "lahf_lm", "cmp_legacy", "svm", NULL, "cr8_legacy", NULL, NULL, NULL,
1da177e4
LT		 1245 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1246 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
5b7abc6f 1247 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1248 };
1249 static char *x86_power_flags[] = {
1250 "ts", /* temperature sensor */
1251 "fid", /* frequency id control */
1252 "vid", /* voltage id control */
1253 "ttp", /* thermal trip */
1254 "tm",
3f98bc49
AK		 1255 "stc",
1256 NULL,
39b3a791 1257 /* nothing */ /* constant_tsc - moved to flags */
1da177e4
LT		 1258 };
1259
1260
1261#ifdef CONFIG_SMP
1262 if (!cpu_online(c-cpu_data))
1263 return 0;
1264#endif
1265
1266 seq_printf(m,"processor\t: %u\n"
1267 "vendor_id\t: %s\n"
1268 "cpu family\t: %d\n"
1269 "model\t\t: %d\n"
1270 "model name\t: %s\n",
1271 (unsigned)(c-cpu_data),
1272 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1273 c->x86,
1274 (int)c->x86_model,
1275 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1276
1277 if (c->x86_mask || c->cpuid_level >= 0)
1278 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1279 else
1280 seq_printf(m, "stepping\t: unknown\n");
1281
1282 if (cpu_has(c,X86_FEATURE_TSC)) {
95235ca2
VP		 1283 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1284 if (!freq)
1285 freq = cpu_khz;
1da177e4 1286 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
95235ca2 1287 freq / 1000, (freq % 1000));
1da177e4
LT		 1288 }
1289
1290 /* Cache size */
1291 if (c->x86_cache_size >= 0)
1292 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1293
1294#ifdef CONFIG_SMP
94605eff 1295 if (smp_num_siblings * c->x86_max_cores > 1) {
db468681 1296 int cpu = c - cpu_data;
f3fa8ebc 1297 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
94605eff 1298 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
f3fa8ebc 1299 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
94605eff 1300 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
db468681 1301 }
1da177e4
LT		 1302#endif
1303
1304 seq_printf(m,
1305 "fpu\t\t: yes\n"
1306 "fpu_exception\t: yes\n"
1307 "cpuid level\t: %d\n"
1308 "wp\t\t: yes\n"
1309 "flags\t\t:",
1310 c->cpuid_level);
1311
1312 {
1313 int i;
1314 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
3d1712c9 1315 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1da177e4
LT		 1316 seq_printf(m, " %s", x86_cap_flags[i]);
1317 }
1318
1319 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1320 c->loops_per_jiffy/(500000/HZ),
1321 (c->loops_per_jiffy/(5000/HZ)) % 100);
1322
1323 if (c->x86_tlbsize > 0)
1324 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1325 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1326 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1327
1328 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1329 c->x86_phys_bits, c->x86_virt_bits);
1330
1331 seq_printf(m, "power management:");
1332 {
1333 unsigned i;
1334 for (i = 0; i < 32; i++)
1335 if (c->x86_power & (1 << i)) {
3f98bc49
AK		 1336 if (i < ARRAY_SIZE(x86_power_flags) &&
1337 x86_power_flags[i])
1338 seq_printf(m, "%s%s",
1339 x86_power_flags[i][0]?" ":"",
1340 x86_power_flags[i]);
1da177e4
LT		 1341 else
1342 seq_printf(m, " [%d]", i);
1343 }
1344 }
1da177e4 1345
d31ddaa1 1346 seq_printf(m, "\n\n");
1da177e4
LT		 1347
1348 return 0;
1349}
1350
1351static void *c_start(struct seq_file *m, loff_t *pos)
1352{
1353 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1354}
1355
1356static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1357{
1358 ++*pos;
1359 return c_start(m, pos);
1360}
1361
1362static void c_stop(struct seq_file *m, void *v)
1363{
1364}
1365
1366struct seq_operations cpuinfo_op = {
1367 .start =c_start,
1368 .next = c_next,
1369 .stop = c_stop,
1370 .show = show_cpuinfo,
1371};
e9928674 1372
9c63f873 1373#if defined(CONFIG_INPUT_PCSPKR) || defined(CONFIG_INPUT_PCSPKR_MODULE)
160bd18e
MP		 1374#include <linux/platform_device.h>
1375static __init int add_pcspkr(void)
1376{
1377 struct platform_device *pd;
1378 int ret;
1379
1380 pd = platform_device_alloc("pcspkr", -1);
1381 if (!pd)
1382 return -ENOMEM;
1383
1384 ret = platform_device_add(pd);
1385 if (ret)
1386 platform_device_put(pd);
1387
1388 return ret;
1389}
1390device_initcall(add_pcspkr);
1391#endif
kernel source for telekom puls (alcatel/mediatek)