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[CPUFREQ] Move PMBASE reading away and do it only once at initialization time
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86_64 / kernel / setup.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/x86-64/kernel/setup.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 *
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
8 *
9 * $Id$
10 */
11
12/*
13 * This file handles the architecture-dependent parts of initialization
14 */
15
16#include <linux/errno.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/stddef.h>
21#include <linux/unistd.h>
22#include <linux/ptrace.h>
23#include <linux/slab.h>
24#include <linux/user.h>
25#include <linux/a.out.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/delay.h>
29#include <linux/config.h>
30#include <linux/init.h>
31#include <linux/initrd.h>
32#include <linux/highmem.h>
33#include <linux/bootmem.h>
34#include <linux/module.h>
35#include <asm/processor.h>
36#include <linux/console.h>
37#include <linux/seq_file.h>
38#include <linux/root_dev.h>
39#include <linux/pci.h>
40#include <linux/acpi.h>
41#include <linux/kallsyms.h>
42#include <linux/edd.h>
bbfceef4 43#include <linux/mmzone.h>
5f5609df 44#include <linux/kexec.h>
bbfceef4 45
1da177e4
LT		 46#include <asm/mtrr.h>
47#include <asm/uaccess.h>
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/smp.h>
51#include <asm/msr.h>
52#include <asm/desc.h>
53#include <video/edid.h>
54#include <asm/e820.h>
55#include <asm/dma.h>
56#include <asm/mpspec.h>
57#include <asm/mmu_context.h>
58#include <asm/bootsetup.h>
59#include <asm/proto.h>
60#include <asm/setup.h>
61#include <asm/mach_apic.h>
62#include <asm/numa.h>
2bc0414e 63#include <asm/sections.h>
1da177e4
LT		 64
65/*
66 * Machine setup..
67 */
68
6c231b7b 69struct cpuinfo_x86 boot_cpu_data __read_mostly;
1da177e4
LT		 70
71unsigned long mmu_cr4_features;
72
73int acpi_disabled;
74EXPORT_SYMBOL(acpi_disabled);
888ba6c6 75#ifdef CONFIG_ACPI
1da177e4
LT		 76extern int __initdata acpi_ht;
77extern acpi_interrupt_flags acpi_sci_flags;
78int __initdata acpi_force = 0;
79#endif
80
81int acpi_numa __initdata;
82
1da177e4
LT		 83/* Boot loader ID as an integer, for the benefit of proc_dointvec */
84int bootloader_type;
85
86unsigned long saved_video_mode;
87
88#ifdef CONFIG_SWIOTLB
89int swiotlb;
90EXPORT_SYMBOL(swiotlb);
91#endif
92
93/*
94 * Setup options
95 */
96struct drive_info_struct { char dummy[32]; } drive_info;
97struct screen_info screen_info;
98struct sys_desc_table_struct {
99 unsigned short length;
100 unsigned char table[0];
101};
102
103struct edid_info edid_info;
104struct e820map e820;
105
106extern int root_mountflags;
1da177e4
LT		 107
108char command_line[COMMAND_LINE_SIZE];
109
110struct resource standard_io_resources[] = {
111 { .name = "dma1", .start = 0x00, .end = 0x1f,
112 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
113 { .name = "pic1", .start = 0x20, .end = 0x21,
114 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
115 { .name = "timer0", .start = 0x40, .end = 0x43,
116 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
117 { .name = "timer1", .start = 0x50, .end = 0x53,
118 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
119 { .name = "keyboard", .start = 0x60, .end = 0x6f,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
121 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
122 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
123 { .name = "pic2", .start = 0xa0, .end = 0xa1,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "dma2", .start = 0xc0, .end = 0xdf,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "fpu", .start = 0xf0, .end = 0xff,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
129};
130
131#define STANDARD_IO_RESOURCES \
132 (sizeof standard_io_resources / sizeof standard_io_resources[0])
133
134#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
135
136struct resource data_resource = {
137 .name = "Kernel data",
138 .start = 0,
139 .end = 0,
140 .flags = IORESOURCE_RAM,
141};
142struct resource code_resource = {
143 .name = "Kernel code",
144 .start = 0,
145 .end = 0,
146 .flags = IORESOURCE_RAM,
147};
148
149#define IORESOURCE_ROM (IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM)
150
151static struct resource system_rom_resource = {
152 .name = "System ROM",
153 .start = 0xf0000,
154 .end = 0xfffff,
155 .flags = IORESOURCE_ROM,
156};
157
158static struct resource extension_rom_resource = {
159 .name = "Extension ROM",
160 .start = 0xe0000,
161 .end = 0xeffff,
162 .flags = IORESOURCE_ROM,
163};
164
165static struct resource adapter_rom_resources[] = {
166 { .name = "Adapter ROM", .start = 0xc8000, .end = 0,
167 .flags = IORESOURCE_ROM },
168 { .name = "Adapter ROM", .start = 0, .end = 0,
169 .flags = IORESOURCE_ROM },
170 { .name = "Adapter ROM", .start = 0, .end = 0,
171 .flags = IORESOURCE_ROM },
172 { .name = "Adapter ROM", .start = 0, .end = 0,
173 .flags = IORESOURCE_ROM },
174 { .name = "Adapter ROM", .start = 0, .end = 0,
175 .flags = IORESOURCE_ROM },
176 { .name = "Adapter ROM", .start = 0, .end = 0,
177 .flags = IORESOURCE_ROM }
178};
179
180#define ADAPTER_ROM_RESOURCES \
181 (sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
182
183static struct resource video_rom_resource = {
184 .name = "Video ROM",
185 .start = 0xc0000,
186 .end = 0xc7fff,
187 .flags = IORESOURCE_ROM,
188};
189
190static struct resource video_ram_resource = {
191 .name = "Video RAM area",
192 .start = 0xa0000,
193 .end = 0xbffff,
194 .flags = IORESOURCE_RAM,
195};
196
197#define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
198
199static int __init romchecksum(unsigned char *rom, unsigned long length)
200{
201 unsigned char *p, sum = 0;
202
203 for (p = rom; p < rom + length; p++)
204 sum += *p;
205 return sum == 0;
206}
207
208static void __init probe_roms(void)
209{
210 unsigned long start, length, upper;
211 unsigned char *rom;
212 int i;
213
214 /* video rom */
215 upper = adapter_rom_resources[0].start;
216 for (start = video_rom_resource.start; start < upper; start += 2048) {
217 rom = isa_bus_to_virt(start);
218 if (!romsignature(rom))
219 continue;
220
221 video_rom_resource.start = start;
222
223 /* 0 < length <= 0x7f * 512, historically */
224 length = rom[2] * 512;
225
226 /* if checksum okay, trust length byte */
227 if (length && romchecksum(rom, length))
228 video_rom_resource.end = start + length - 1;
229
230 request_resource(&iomem_resource, &video_rom_resource);
231 break;
232 }
233
234 start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
235 if (start < upper)
236 start = upper;
237
238 /* system rom */
239 request_resource(&iomem_resource, &system_rom_resource);
240 upper = system_rom_resource.start;
241
242 /* check for extension rom (ignore length byte!) */
243 rom = isa_bus_to_virt(extension_rom_resource.start);
244 if (romsignature(rom)) {
245 length = extension_rom_resource.end - extension_rom_resource.start + 1;
246 if (romchecksum(rom, length)) {
247 request_resource(&iomem_resource, &extension_rom_resource);
248 upper = extension_rom_resource.start;
249 }
250 }
251
252 /* check for adapter roms on 2k boundaries */
253 for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
254 rom = isa_bus_to_virt(start);
255 if (!romsignature(rom))
256 continue;
257
258 /* 0 < length <= 0x7f * 512, historically */
259 length = rom[2] * 512;
260
261 /* but accept any length that fits if checksum okay */
262 if (!length || start + length > upper || !romchecksum(rom, length))
263 continue;
264
265 adapter_rom_resources[i].start = start;
266 adapter_rom_resources[i].end = start + length - 1;
267 request_resource(&iomem_resource, &adapter_rom_resources[i]);
268
269 start = adapter_rom_resources[i++].end & ~2047UL;
270 }
271}
272
273static __init void parse_cmdline_early (char ** cmdline_p)
274{
275 char c = ' ', *to = command_line, *from = COMMAND_LINE;
276 int len = 0;
277
278 /* Save unparsed command line copy for /proc/cmdline */
279 memcpy(saved_command_line, COMMAND_LINE, COMMAND_LINE_SIZE);
280 saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
281
282 for (;;) {
283 if (c != ' ')
284 goto next_char;
285
286#ifdef CONFIG_SMP
287 /*
288 * If the BIOS enumerates physical processors before logical,
289 * maxcpus=N at enumeration-time can be used to disable HT.
290 */
291 else if (!memcmp(from, "maxcpus=", 8)) {
292 extern unsigned int maxcpus;
293
294 maxcpus = simple_strtoul(from + 8, NULL, 0);
295 }
296#endif
888ba6c6 297#ifdef CONFIG_ACPI
1da177e4
LT		 298 /* "acpi=off" disables both ACPI table parsing and interpreter init */
299 if (!memcmp(from, "acpi=off", 8))
300 disable_acpi();
301
302 if (!memcmp(from, "acpi=force", 10)) {
303 /* add later when we do DMI horrors: */
304 acpi_force = 1;
305 acpi_disabled = 0;
306 }
307
308 /* acpi=ht just means: do ACPI MADT parsing
309 at bootup, but don't enable the full ACPI interpreter */
310 if (!memcmp(from, "acpi=ht", 7)) {
311 if (!acpi_force)
312 disable_acpi();
313 acpi_ht = 1;
314 }
315 else if (!memcmp(from, "pci=noacpi", 10))
316 acpi_disable_pci();
317 else if (!memcmp(from, "acpi=noirq", 10))
318 acpi_noirq_set();
319
320 else if (!memcmp(from, "acpi_sci=edge", 13))
321 acpi_sci_flags.trigger = 1;
322 else if (!memcmp(from, "acpi_sci=level", 14))
323 acpi_sci_flags.trigger = 3;
324 else if (!memcmp(from, "acpi_sci=high", 13))
325 acpi_sci_flags.polarity = 1;
326 else if (!memcmp(from, "acpi_sci=low", 12))
327 acpi_sci_flags.polarity = 3;
328
329 /* acpi=strict disables out-of-spec workarounds */
330 else if (!memcmp(from, "acpi=strict", 11)) {
331 acpi_strict = 1;
332 }
22999244
AK		 333#ifdef CONFIG_X86_IO_APIC
334 else if (!memcmp(from, "acpi_skip_timer_override", 24))
335 acpi_skip_timer_override = 1;
336#endif
1da177e4
LT		 337#endif
338
66759a01
CE		 339 if (!memcmp(from, "disable_timer_pin_1", 19))
340 disable_timer_pin_1 = 1;
341 if (!memcmp(from, "enable_timer_pin_1", 18))
342 disable_timer_pin_1 = -1;
343
1da177e4
LT		 344 if (!memcmp(from, "nolapic", 7) ||
345 !memcmp(from, "disableapic", 11))
346 disable_apic = 1;
347
348 if (!memcmp(from, "noapic", 6))
349 skip_ioapic_setup = 1;
350
351 if (!memcmp(from, "apic", 4)) {
352 skip_ioapic_setup = 0;
353 ioapic_force = 1;
354 }
355
356 if (!memcmp(from, "mem=", 4))
357 parse_memopt(from+4, &from);
358
2b97690f 359#ifdef CONFIG_NUMA
1da177e4
LT		 360 if (!memcmp(from, "numa=", 5))
361 numa_setup(from+5);
362#endif
363
364#ifdef CONFIG_GART_IOMMU
365 if (!memcmp(from,"iommu=",6)) {
366 iommu_setup(from+6);
367 }
368#endif
369
370 if (!memcmp(from,"oops=panic", 10))
371 panic_on_oops = 1;
372
373 if (!memcmp(from, "noexec=", 7))
374 nonx_setup(from + 7);
375
5f5609df
EB		 376#ifdef CONFIG_KEXEC
377 /* crashkernel=size@addr specifies the location to reserve for
378 * a crash kernel. By reserving this memory we guarantee
379 * that linux never set's it up as a DMA target.
380 * Useful for holding code to do something appropriate
381 * after a kernel panic.
382 */
383 else if (!memcmp(from, "crashkernel=", 12)) {
384 unsigned long size, base;
385 size = memparse(from+12, &from);
386 if (*from == '@') {
387 base = memparse(from+1, &from);
388 /* FIXME: Do I want a sanity check
389 * to validate the memory range?
390 */
391 crashk_res.start = base;
392 crashk_res.end = base + size - 1;
393 }
394 }
395#endif
396
1da177e4
LT		 397 next_char:
398 c = *(from++);
399 if (!c)
400 break;
401 if (COMMAND_LINE_SIZE <= ++len)
402 break;
403 *(to++) = c;
404 }
405 *to = '\0';
406 *cmdline_p = command_line;
407}
408
2b97690f 409#ifndef CONFIG_NUMA
bbfceef4
MT		 410static void __init
411contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
1da177e4 412{
bbfceef4
MT		 413 unsigned long bootmap_size, bootmap;
414
bbfceef4
MT		 415 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
416 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
417 if (bootmap == -1L)
418 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
419 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
420 e820_bootmem_free(NODE_DATA(0), 0, end_pfn << PAGE_SHIFT);
421 reserve_bootmem(bootmap, bootmap_size);
1da177e4
LT		 422}
423#endif
424
425/* Use inline assembly to define this because the nops are defined
426 as inline assembly strings in the include files and we cannot
427 get them easily into strings. */
428asm("\t.data\nk8nops: "
429 K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6
430 K8_NOP7 K8_NOP8);
431
432extern unsigned char k8nops[];
433static unsigned char *k8_nops[ASM_NOP_MAX+1] = {
434 NULL,
435 k8nops,
436 k8nops + 1,
437 k8nops + 1 + 2,
438 k8nops + 1 + 2 + 3,
439 k8nops + 1 + 2 + 3 + 4,
440 k8nops + 1 + 2 + 3 + 4 + 5,
441 k8nops + 1 + 2 + 3 + 4 + 5 + 6,
442 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
443};
444
445/* Replace instructions with better alternatives for this CPU type.
446
447 This runs before SMP is initialized to avoid SMP problems with
448 self modifying code. This implies that assymetric systems where
449 APs have less capabilities than the boot processor are not handled.
450 In this case boot with "noreplacement". */
451void apply_alternatives(void *start, void *end)
452{
453 struct alt_instr *a;
454 int diff, i, k;
455 for (a = start; (void *)a < end; a++) {
456 if (!boot_cpu_has(a->cpuid))
457 continue;
458
459 BUG_ON(a->replacementlen > a->instrlen);
460 __inline_memcpy(a->instr, a->replacement, a->replacementlen);
461 diff = a->instrlen - a->replacementlen;
462
463 /* Pad the rest with nops */
464 for (i = a->replacementlen; diff > 0; diff -= k, i += k) {
465 k = diff;
466 if (k > ASM_NOP_MAX)
467 k = ASM_NOP_MAX;
468 __inline_memcpy(a->instr + i, k8_nops[k], k);
469 }
470 }
471}
472
473static int no_replacement __initdata = 0;
474
475void __init alternative_instructions(void)
476{
477 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
478 if (no_replacement)
479 return;
480 apply_alternatives(__alt_instructions, __alt_instructions_end);
481}
482
483static int __init noreplacement_setup(char *s)
484{
485 no_replacement = 1;
486 return 0;
487}
488
489__setup("noreplacement", noreplacement_setup);
490
491#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
492struct edd edd;
493#ifdef CONFIG_EDD_MODULE
494EXPORT_SYMBOL(edd);
495#endif
496/**
497 * copy_edd() - Copy the BIOS EDD information
498 * from boot_params into a safe place.
499 *
500 */
501static inline void copy_edd(void)
502{
503 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
504 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
505 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
506 edd.edd_info_nr = EDD_NR;
507}
508#else
509static inline void copy_edd(void)
510{
511}
512#endif
513
514#define EBDA_ADDR_POINTER 0x40E
515static void __init reserve_ebda_region(void)
516{
517 unsigned int addr;
518 /**
519 * there is a real-mode segmented pointer pointing to the
520 * 4K EBDA area at 0x40E
521 */
522 addr = *(unsigned short *)phys_to_virt(EBDA_ADDR_POINTER);
523 addr <<= 4;
524 if (addr)
525 reserve_bootmem_generic(addr, PAGE_SIZE);
526}
527
528void __init setup_arch(char **cmdline_p)
529{
1da177e4
LT		 530 unsigned long kernel_end;
531
532 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
533 drive_info = DRIVE_INFO;
534 screen_info = SCREEN_INFO;
535 edid_info = EDID_INFO;
536 saved_video_mode = SAVED_VIDEO_MODE;
537 bootloader_type = LOADER_TYPE;
538
539#ifdef CONFIG_BLK_DEV_RAM
540 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
541 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
542 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
543#endif
544 setup_memory_region();
545 copy_edd();
546
547 if (!MOUNT_ROOT_RDONLY)
548 root_mountflags &= ~MS_RDONLY;
549 init_mm.start_code = (unsigned long) &_text;
550 init_mm.end_code = (unsigned long) &_etext;
551 init_mm.end_data = (unsigned long) &_edata;
552 init_mm.brk = (unsigned long) &_end;
553
554 code_resource.start = virt_to_phys(&_text);
555 code_resource.end = virt_to_phys(&_etext)-1;
556 data_resource.start = virt_to_phys(&_etext);
557 data_resource.end = virt_to_phys(&_edata)-1;
558
559 parse_cmdline_early(cmdline_p);
560
561 early_identify_cpu(&boot_cpu_data);
562
563 /*
564 * partially used pages are not usable - thus
565 * we are rounding upwards:
566 */
567 end_pfn = e820_end_of_ram();
568
569 check_efer();
570
571 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
572
f6c2e333
SS		 573 zap_low_mappings(0);
574
888ba6c6 575#ifdef CONFIG_ACPI
1da177e4
LT		 576 /*
577 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
578 * Call this early for SRAT node setup.
579 */
580 acpi_boot_table_init();
581#endif
582
583#ifdef CONFIG_ACPI_NUMA
584 /*
585 * Parse SRAT to discover nodes.
586 */
587 acpi_numa_init();
588#endif
589
2b97690f 590#ifdef CONFIG_NUMA
1da177e4
LT		 591 numa_initmem_init(0, end_pfn);
592#else
bbfceef4 593 contig_initmem_init(0, end_pfn);
1da177e4
LT		 594#endif
595
596 /* Reserve direct mapping */
597 reserve_bootmem_generic(table_start << PAGE_SHIFT,
598 (table_end - table_start) << PAGE_SHIFT);
599
600 /* reserve kernel */
601 kernel_end = round_up(__pa_symbol(&_end),PAGE_SIZE);
602 reserve_bootmem_generic(HIGH_MEMORY, kernel_end - HIGH_MEMORY);
603
604 /*
605 * reserve physical page 0 - it's a special BIOS page on many boxes,
606 * enabling clean reboots, SMP operation, laptop functions.
607 */
608 reserve_bootmem_generic(0, PAGE_SIZE);
609
610 /* reserve ebda region */
611 reserve_ebda_region();
612
613#ifdef CONFIG_SMP
614 /*
615 * But first pinch a few for the stack/trampoline stuff
616 * FIXME: Don't need the extra page at 4K, but need to fix
617 * trampoline before removing it. (see the GDT stuff)
618 */
619 reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
620
621 /* Reserve SMP trampoline */
622 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
623#endif
624
625#ifdef CONFIG_ACPI_SLEEP
626 /*
627 * Reserve low memory region for sleep support.
628 */
629 acpi_reserve_bootmem();
630#endif
631#ifdef CONFIG_X86_LOCAL_APIC
632 /*
633 * Find and reserve possible boot-time SMP configuration:
634 */
635 find_smp_config();
636#endif
637#ifdef CONFIG_BLK_DEV_INITRD
638 if (LOADER_TYPE && INITRD_START) {
639 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
640 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
641 initrd_start =
642 INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
643 initrd_end = initrd_start+INITRD_SIZE;
644 }
645 else {
646 printk(KERN_ERR "initrd extends beyond end of memory "
647 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
648 (unsigned long)(INITRD_START + INITRD_SIZE),
649 (unsigned long)(end_pfn << PAGE_SHIFT));
650 initrd_start = 0;
651 }
652 }
653#endif
5f5609df
EB		 654#ifdef CONFIG_KEXEC
655 if (crashk_res.start != crashk_res.end) {
656 reserve_bootmem(crashk_res.start,
657 crashk_res.end - crashk_res.start + 1);
658 }
659#endif
0d317fb7 660
1da177e4
LT		 661 paging_init();
662
663 check_ioapic();
664
888ba6c6 665#ifdef CONFIG_ACPI
1da177e4
LT		 666 /*
667 * Read APIC and some other early information from ACPI tables.
668 */
669 acpi_boot_init();
670#endif
671
672#ifdef CONFIG_X86_LOCAL_APIC
673 /*
674 * get boot-time SMP configuration:
675 */
676 if (smp_found_config)
677 get_smp_config();
678 init_apic_mappings();
679#endif
680
681 /*
682 * Request address space for all standard RAM and ROM resources
683 * and also for regions reported as reserved by the e820.
684 */
685 probe_roms();
686 e820_reserve_resources();
687
688 request_resource(&iomem_resource, &video_ram_resource);
689
690 {
691 unsigned i;
692 /* request I/O space for devices used on all i[345]86 PCs */
693 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
694 request_resource(&ioport_resource, &standard_io_resources[i]);
695 }
696
a1e97782 697 e820_setup_gap();
1da177e4
LT		 698
699#ifdef CONFIG_GART_IOMMU
700 iommu_hole_init();
701#endif
702
703#ifdef CONFIG_VT
704#if defined(CONFIG_VGA_CONSOLE)
705 conswitchp = &vga_con;
706#elif defined(CONFIG_DUMMY_CONSOLE)
707 conswitchp = &dummy_con;
708#endif
709#endif
710}
711
e6982c67 712static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
1da177e4
LT		 713{
714 unsigned int *v;
715
ebfcaa96 716 if (c->extended_cpuid_level < 0x80000004)
1da177e4
LT		 717 return 0;
718
719 v = (unsigned int *) c->x86_model_id;
720 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
721 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
722 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
723 c->x86_model_id[48] = 0;
724 return 1;
725}
726
727
e6982c67 728static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
1da177e4
LT		 729{
730 unsigned int n, dummy, eax, ebx, ecx, edx;
731
ebfcaa96 732 n = c->extended_cpuid_level;
1da177e4
LT		 733
734 if (n >= 0x80000005) {
735 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
736 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
737 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
738 c->x86_cache_size=(ecx>>24)+(edx>>24);
739 /* On K8 L1 TLB is inclusive, so don't count it */
740 c->x86_tlbsize = 0;
741 }
742
743 if (n >= 0x80000006) {
744 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
745 ecx = cpuid_ecx(0x80000006);
746 c->x86_cache_size = ecx >> 16;
747 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
748
749 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
750 c->x86_cache_size, ecx & 0xFF);
751 }
752
753 if (n >= 0x80000007)
754 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
755 if (n >= 0x80000008) {
756 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
757 c->x86_virt_bits = (eax >> 8) & 0xff;
758 c->x86_phys_bits = eax & 0xff;
759 }
760}
761
3f098c26
AK		 762#ifdef CONFIG_NUMA
763static int nearby_node(int apicid)
764{
765 int i;
766 for (i = apicid - 1; i >= 0; i--) {
767 int node = apicid_to_node[i];
768 if (node != NUMA_NO_NODE && node_online(node))
769 return node;
770 }
771 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
772 int node = apicid_to_node[i];
773 if (node != NUMA_NO_NODE && node_online(node))
774 return node;
775 }
776 return first_node(node_online_map); /* Shouldn't happen */
777}
778#endif
779
63518644
AK		 780/*
781 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
782 * Assumes number of cores is a power of two.
783 */
784static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
785{
786#ifdef CONFIG_SMP
2942283e 787 int cpu = smp_processor_id();
b41e2939 788 unsigned bits;
3f098c26
AK		 789#ifdef CONFIG_NUMA
790 int node = 0;
0b07e984 791 unsigned apicid = phys_proc_id[cpu];
3f098c26 792#endif
b41e2939
AK		 793
794 bits = 0;
94605eff 795 while ((1 << bits) < c->x86_max_cores)
b41e2939
AK		 796 bits++;
797
798 /* Low order bits define the core id (index of core in socket) */
799 cpu_core_id[cpu] = phys_proc_id[cpu] & ((1 << bits)-1);
800 /* Convert the APIC ID into the socket ID */
801 phys_proc_id[cpu] >>= bits;
63518644
AK		 802
803#ifdef CONFIG_NUMA
3f098c26
AK		 804 node = phys_proc_id[cpu];
805 if (apicid_to_node[apicid] != NUMA_NO_NODE)
806 node = apicid_to_node[apicid];
807 if (!node_online(node)) {
808 /* Two possibilities here:
809 - The CPU is missing memory and no node was created.
810 In that case try picking one from a nearby CPU
811 - The APIC IDs differ from the HyperTransport node IDs
812 which the K8 northbridge parsing fills in.
813 Assume they are all increased by a constant offset,
814 but in the same order as the HT nodeids.
815 If that doesn't result in a usable node fall back to the
816 path for the previous case. */
817 int ht_nodeid = apicid - (phys_proc_id[0] << bits);
818 if (ht_nodeid >= 0 &&
819 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
820 node = apicid_to_node[ht_nodeid];
821 /* Pick a nearby node */
822 if (!node_online(node))
823 node = nearby_node(apicid);
824 }
69d81fcd 825 numa_set_node(cpu, node);
3f098c26
AK		 826
827 printk(KERN_INFO "CPU %d(%d) -> Node %d -> Core %d\n",
94605eff 828 cpu, c->x86_max_cores, node, cpu_core_id[cpu]);
63518644 829#endif
63518644
AK		 830#endif
831}
1da177e4
LT		 832
833static int __init init_amd(struct cpuinfo_x86 *c)
834{
835 int r;
836 int level;
1da177e4 837
bc5e8fdf
LT		 838#ifdef CONFIG_SMP
839 unsigned long value;
840
7d318d77
AK		 841 /*
842 * Disable TLB flush filter by setting HWCR.FFDIS on K8
843 * bit 6 of msr C001_0015
844 *
845 * Errata 63 for SH-B3 steppings
846 * Errata 122 for all steppings (F+ have it disabled by default)
847 */
848 if (c->x86 == 15) {
849 rdmsrl(MSR_K8_HWCR, value);
850 value |= 1 << 6;
851 wrmsrl(MSR_K8_HWCR, value);
852 }
bc5e8fdf
LT		 853#endif
854
1da177e4
LT		 855 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
856 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
857 clear_bit(0*32+31, &c->x86_capability);
858
859 /* C-stepping K8? */
860 level = cpuid_eax(1);
861 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
862 set_bit(X86_FEATURE_K8_C, &c->x86_capability);
863
864 r = get_model_name(c);
865 if (!r) {
866 switch (c->x86) {
867 case 15:
868 /* Should distinguish Models here, but this is only
869 a fallback anyways. */
870 strcpy(c->x86_model_id, "Hammer");
871 break;
872 }
873 }
874 display_cacheinfo(c);
875
ebfcaa96 876 if (c->extended_cpuid_level >= 0x80000008) {
94605eff
SS		 877 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
878 if (c->x86_max_cores & (c->x86_max_cores - 1))
879 c->x86_max_cores = 1;
1da177e4 880
63518644 881 amd_detect_cmp(c);
1da177e4
LT		 882 }
883
884 return r;
885}
886
e6982c67 887static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1da177e4
LT		 888{
889#ifdef CONFIG_SMP
890 u32 eax, ebx, ecx, edx;
94605eff 891 int index_msb, core_bits;
1da177e4 892 int cpu = smp_processor_id();
94605eff
SS		 893
894 cpuid(1, &eax, &ebx, &ecx, &edx);
895
896 c->apicid = phys_pkg_id(0);
897
63518644 898 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
1da177e4
LT		 899 return;
900
1da177e4 901 smp_num_siblings = (ebx & 0xff0000) >> 16;
94605eff 902
1da177e4
LT		 903 if (smp_num_siblings == 1) {
904 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
94605eff
SS		 905 } else if (smp_num_siblings > 1 ) {
906
1da177e4
LT		 907 if (smp_num_siblings > NR_CPUS) {
908 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
909 smp_num_siblings = 1;
910 return;
911 }
94605eff
SS		 912
913 index_msb = get_count_order(smp_num_siblings);
1da177e4 914 phys_proc_id[cpu] = phys_pkg_id(index_msb);
94605eff 915
1da177e4
LT		 916 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
917 phys_proc_id[cpu]);
3dd9d514 918
94605eff 919 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
3dd9d514 920
94605eff
SS		 921 index_msb = get_count_order(smp_num_siblings) ;
922
923 core_bits = get_count_order(c->x86_max_cores);
3dd9d514 924
94605eff
SS		 925 cpu_core_id[cpu] = phys_pkg_id(index_msb) &
926 ((1 << core_bits) - 1);
3dd9d514 927
94605eff 928 if (c->x86_max_cores > 1)
3dd9d514
AK		 929 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
930 cpu_core_id[cpu]);
1da177e4
LT		 931 }
932#endif
933}
934
3dd9d514
AK		 935/*
936 * find out the number of processor cores on the die
937 */
e6982c67 938static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514
AK		 939{
940 unsigned int eax;
941
942 if (c->cpuid_level < 4)
943 return 1;
944
945 __asm__("cpuid"
946 : "=a" (eax)
947 : "0" (4), "c" (0)
948 : "bx", "dx");
949
950 if (eax & 0x1f)
951 return ((eax >> 26) + 1);
952 else
953 return 1;
954}
955
df0cc26b
AK		 956static void srat_detect_node(void)
957{
958#ifdef CONFIG_NUMA
ddea7be0 959 unsigned node;
df0cc26b
AK		 960 int cpu = smp_processor_id();
961
962 /* Don't do the funky fallback heuristics the AMD version employs
963 for now. */
ddea7be0 964 node = apicid_to_node[hard_smp_processor_id()];
df0cc26b
AK		 965 if (node == NUMA_NO_NODE)
966 node = 0;
69d81fcd 967 numa_set_node(cpu, node);
df0cc26b
AK		 968
969 if (acpi_numa > 0)
970 printk(KERN_INFO "CPU %d -> Node %d\n", cpu, node);
971#endif
972}
973
e6982c67 974static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4
LT		 975{
976 /* Cache sizes */
977 unsigned n;
978
979 init_intel_cacheinfo(c);
ebfcaa96 980 n = c->extended_cpuid_level;
1da177e4
LT		 981 if (n >= 0x80000008) {
982 unsigned eax = cpuid_eax(0x80000008);
983 c->x86_virt_bits = (eax >> 8) & 0xff;
984 c->x86_phys_bits = eax & 0xff;
af9c142d
SL		 985 /* CPUID workaround for Intel 0F34 CPU */
986 if (c->x86_vendor == X86_VENDOR_INTEL &&
987 c->x86 == 0xF && c->x86_model == 0x3 &&
988 c->x86_mask == 0x4)
989 c->x86_phys_bits = 36;
1da177e4
LT		 990 }
991
992 if (c->x86 == 15)
993 c->x86_cache_alignment = c->x86_clflush_size * 2;
c29601e9
AK		 994 if (c->x86 >= 15)
995 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
94605eff 996 c->x86_max_cores = intel_num_cpu_cores(c);
df0cc26b
AK		 997
998 srat_detect_node();
1da177e4
LT		 999}
1000
672289e9 1001static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1da177e4
LT		 1002{
1003 char *v = c->x86_vendor_id;
1004
1005 if (!strcmp(v, "AuthenticAMD"))
1006 c->x86_vendor = X86_VENDOR_AMD;
1007 else if (!strcmp(v, "GenuineIntel"))
1008 c->x86_vendor = X86_VENDOR_INTEL;
1009 else
1010 c->x86_vendor = X86_VENDOR_UNKNOWN;
1011}
1012
1013struct cpu_model_info {
1014 int vendor;
1015 int family;
1016 char *model_names[16];
1017};
1018
1019/* Do some early cpuid on the boot CPU to get some parameter that are
1020 needed before check_bugs. Everything advanced is in identify_cpu
1021 below. */
e6982c67 1022void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 1023{
1024 u32 tfms;
1025
1026 c->loops_per_jiffy = loops_per_jiffy;
1027 c->x86_cache_size = -1;
1028 c->x86_vendor = X86_VENDOR_UNKNOWN;
1029 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1030 c->x86_vendor_id[0] = '\0'; /* Unset */
1031 c->x86_model_id[0] = '\0'; /* Unset */
1032 c->x86_clflush_size = 64;
1033 c->x86_cache_alignment = c->x86_clflush_size;
94605eff 1034 c->x86_max_cores = 1;
ebfcaa96 1035 c->extended_cpuid_level = 0;
1da177e4
LT		 1036 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1037
1038 /* Get vendor name */
1039 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1040 (unsigned int *)&c->x86_vendor_id[0],
1041 (unsigned int *)&c->x86_vendor_id[8],
1042 (unsigned int *)&c->x86_vendor_id[4]);
1043
1044 get_cpu_vendor(c);
1045
1046 /* Initialize the standard set of capabilities */
1047 /* Note that the vendor-specific code below might override */
1048
1049 /* Intel-defined flags: level 0x00000001 */
1050 if (c->cpuid_level >= 0x00000001) {
1051 __u32 misc;
1052 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1053 &c->x86_capability[0]);
1054 c->x86 = (tfms >> 8) & 0xf;
1055 c->x86_model = (tfms >> 4) & 0xf;
1056 c->x86_mask = tfms & 0xf;
f5f786d0 1057 if (c->x86 == 0xf)
1da177e4 1058 c->x86 += (tfms >> 20) & 0xff;
f5f786d0 1059 if (c->x86 >= 0x6)
1da177e4 1060 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1da177e4
LT		 1061 if (c->x86_capability[0] & (1<<19))
1062 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1da177e4
LT		 1063 } else {
1064 /* Have CPUID level 0 only - unheard of */
1065 c->x86 = 4;
1066 }
a158608b
AK		 1067
1068#ifdef CONFIG_SMP
b41e2939 1069 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
a158608b 1070#endif
1da177e4
LT		 1071}
1072
1073/*
1074 * This does the hard work of actually picking apart the CPU stuff...
1075 */
e6982c67 1076void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 1077{
1078 int i;
1079 u32 xlvl;
1080
1081 early_identify_cpu(c);
1082
1083 /* AMD-defined flags: level 0x80000001 */
1084 xlvl = cpuid_eax(0x80000000);
ebfcaa96 1085 c->extended_cpuid_level = xlvl;
1da177e4
LT		 1086 if ((xlvl & 0xffff0000) == 0x80000000) {
1087 if (xlvl >= 0x80000001) {
1088 c->x86_capability[1] = cpuid_edx(0x80000001);
5b7abc6f 1089 c->x86_capability[6] = cpuid_ecx(0x80000001);
1da177e4
LT		 1090 }
1091 if (xlvl >= 0x80000004)
1092 get_model_name(c); /* Default name */
1093 }
1094
1095 /* Transmeta-defined flags: level 0x80860001 */
1096 xlvl = cpuid_eax(0x80860000);
1097 if ((xlvl & 0xffff0000) == 0x80860000) {
1098 /* Don't set x86_cpuid_level here for now to not confuse. */
1099 if (xlvl >= 0x80860001)
1100 c->x86_capability[2] = cpuid_edx(0x80860001);
1101 }
1102
1103 /*
1104 * Vendor-specific initialization. In this section we
1105 * canonicalize the feature flags, meaning if there are
1106 * features a certain CPU supports which CPUID doesn't
1107 * tell us, CPUID claiming incorrect flags, or other bugs,
1108 * we handle them here.
1109 *
1110 * At the end of this section, c->x86_capability better
1111 * indicate the features this CPU genuinely supports!
1112 */
1113 switch (c->x86_vendor) {
1114 case X86_VENDOR_AMD:
1115 init_amd(c);
1116 break;
1117
1118 case X86_VENDOR_INTEL:
1119 init_intel(c);
1120 break;
1121
1122 case X86_VENDOR_UNKNOWN:
1123 default:
1124 display_cacheinfo(c);
1125 break;
1126 }
1127
1128 select_idle_routine(c);
1129 detect_ht(c);
1da177e4
LT		 1130
1131 /*
1132 * On SMP, boot_cpu_data holds the common feature set between
1133 * all CPUs; so make sure that we indicate which features are
1134 * common between the CPUs. The first time this routine gets
1135 * executed, c == &boot_cpu_data.
1136 */
1137 if (c != &boot_cpu_data) {
1138 /* AND the already accumulated flags with these */
1139 for (i = 0 ; i < NCAPINTS ; i++)
1140 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1141 }
1142
1143#ifdef CONFIG_X86_MCE
1144 mcheck_init(c);
1145#endif
3b520b23
SL		 1146 if (c == &boot_cpu_data)
1147 mtrr_bp_init();
1148 else
1149 mtrr_ap_init();
1da177e4 1150#ifdef CONFIG_NUMA
3019e8eb 1151 numa_add_cpu(smp_processor_id());
1da177e4
LT		 1152#endif
1153}
1154
1155
e6982c67 1156void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1da177e4
LT		 1157{
1158 if (c->x86_model_id[0])
1159 printk("%s", c->x86_model_id);
1160
1161 if (c->x86_mask || c->cpuid_level >= 0)
1162 printk(" stepping %02x\n", c->x86_mask);
1163 else
1164 printk("\n");
1165}
1166
1167/*
1168 * Get CPU information for use by the procfs.
1169 */
1170
1171static int show_cpuinfo(struct seq_file *m, void *v)
1172{
1173 struct cpuinfo_x86 *c = v;
1174
1175 /*
1176 * These flag bits must match the definitions in <asm/cpufeature.h>.
1177 * NULL means this bit is undefined or reserved; either way it doesn't
1178 * have meaning as far as Linux is concerned. Note that it's important
1179 * to realize there is a difference between this table and CPUID -- if
1180 * applications want to get the raw CPUID data, they should access
1181 * /dev/cpu/<cpu_nr>/cpuid instead.
1182 */
1183 static char *x86_cap_flags[] = {
1184 /* Intel-defined */
1185 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1186 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1187 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1188 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
1189
1190 /* AMD-defined */
3c3b73b6 1191 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1192 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1194 NULL, "fxsr_opt", NULL, NULL, NULL, "lm", "3dnowext", "3dnow",
1195
1196 /* Transmeta-defined */
1197 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1198 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1199 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1200 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1201
1202 /* Other (Linux-defined) */
622dcaf9 1203 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
c29601e9 1204 "constant_tsc", NULL, NULL,
1da177e4
LT		 1205 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1206 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1207 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1208
1209 /* Intel-defined (#2) */
daedb82d 1210 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", NULL, "est",
1da177e4
LT		 1211 "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
1212 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1213 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1214
5b7abc6f
PA		 1215 /* VIA/Cyrix/Centaur-defined */
1216 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1217 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1218 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1219 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1220
1da177e4
LT		 1221 /* AMD-defined (#2) */
1222 "lahf_lm", "cmp_legacy", NULL, NULL, NULL, NULL, NULL, NULL,
1223 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1224 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
5b7abc6f 1225 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1226 };
1227 static char *x86_power_flags[] = {
1228 "ts", /* temperature sensor */
1229 "fid", /* frequency id control */
1230 "vid", /* voltage id control */
1231 "ttp", /* thermal trip */
1232 "tm",
1233 "stc"
1234 };
1235
1236
1237#ifdef CONFIG_SMP
1238 if (!cpu_online(c-cpu_data))
1239 return 0;
1240#endif
1241
1242 seq_printf(m,"processor\t: %u\n"
1243 "vendor_id\t: %s\n"
1244 "cpu family\t: %d\n"
1245 "model\t\t: %d\n"
1246 "model name\t: %s\n",
1247 (unsigned)(c-cpu_data),
1248 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1249 c->x86,
1250 (int)c->x86_model,
1251 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1252
1253 if (c->x86_mask || c->cpuid_level >= 0)
1254 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1255 else
1256 seq_printf(m, "stepping\t: unknown\n");
1257
1258 if (cpu_has(c,X86_FEATURE_TSC)) {
1259 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1260 cpu_khz / 1000, (cpu_khz % 1000));
1261 }
1262
1263 /* Cache size */
1264 if (c->x86_cache_size >= 0)
1265 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1266
1267#ifdef CONFIG_SMP
94605eff 1268 if (smp_num_siblings * c->x86_max_cores > 1) {
db468681
AK		 1269 int cpu = c - cpu_data;
1270 seq_printf(m, "physical id\t: %d\n", phys_proc_id[cpu]);
94605eff 1271 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
d31ddaa1 1272 seq_printf(m, "core id\t\t: %d\n", cpu_core_id[cpu]);
94605eff 1273 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
db468681 1274 }
1da177e4
LT		 1275#endif
1276
1277 seq_printf(m,
1278 "fpu\t\t: yes\n"
1279 "fpu_exception\t: yes\n"
1280 "cpuid level\t: %d\n"
1281 "wp\t\t: yes\n"
1282 "flags\t\t:",
1283 c->cpuid_level);
1284
1285 {
1286 int i;
1287 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1288 if ( test_bit(i, &c->x86_capability) &&
1289 x86_cap_flags[i] != NULL )
1290 seq_printf(m, " %s", x86_cap_flags[i]);
1291 }
1292
1293 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1294 c->loops_per_jiffy/(500000/HZ),
1295 (c->loops_per_jiffy/(5000/HZ)) % 100);
1296
1297 if (c->x86_tlbsize > 0)
1298 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1299 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1300 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1301
1302 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1303 c->x86_phys_bits, c->x86_virt_bits);
1304
1305 seq_printf(m, "power management:");
1306 {
1307 unsigned i;
1308 for (i = 0; i < 32; i++)
1309 if (c->x86_power & (1 << i)) {
1310 if (i < ARRAY_SIZE(x86_power_flags))
1311 seq_printf(m, " %s", x86_power_flags[i]);
1312 else
1313 seq_printf(m, " [%d]", i);
1314 }
1315 }
1da177e4 1316
d31ddaa1 1317 seq_printf(m, "\n\n");
1da177e4
LT		 1318
1319 return 0;
1320}
1321
1322static void *c_start(struct seq_file *m, loff_t *pos)
1323{
1324 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1325}
1326
1327static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1328{
1329 ++*pos;
1330 return c_start(m, pos);
1331}
1332
1333static void c_stop(struct seq_file *m, void *v)
1334{
1335}
1336
1337struct seq_operations cpuinfo_op = {
1338 .start =c_start,
1339 .next = c_next,
1340 .stop = c_stop,
1341 .show = show_cpuinfo,
1342};
kernel source for telekom puls (alcatel/mediatek)