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[PATCH] x86_64: Move cpu_present/possible_map parsing earlier
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86_64 / kernel / setup.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/x86-64/kernel/setup.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 *
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
8 *
9 * $Id$
10 */
11
12/*
13 * This file handles the architecture-dependent parts of initialization
14 */
15
16#include <linux/errno.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/stddef.h>
21#include <linux/unistd.h>
22#include <linux/ptrace.h>
23#include <linux/slab.h>
24#include <linux/user.h>
25#include <linux/a.out.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/delay.h>
29#include <linux/config.h>
30#include <linux/init.h>
31#include <linux/initrd.h>
32#include <linux/highmem.h>
33#include <linux/bootmem.h>
34#include <linux/module.h>
35#include <asm/processor.h>
36#include <linux/console.h>
37#include <linux/seq_file.h>
38#include <linux/root_dev.h>
39#include <linux/pci.h>
40#include <linux/acpi.h>
41#include <linux/kallsyms.h>
42#include <linux/edd.h>
bbfceef4 43#include <linux/mmzone.h>
5f5609df 44#include <linux/kexec.h>
bbfceef4 45
1da177e4
LT		 46#include <asm/mtrr.h>
47#include <asm/uaccess.h>
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/smp.h>
51#include <asm/msr.h>
52#include <asm/desc.h>
53#include <video/edid.h>
54#include <asm/e820.h>
55#include <asm/dma.h>
56#include <asm/mpspec.h>
57#include <asm/mmu_context.h>
58#include <asm/bootsetup.h>
59#include <asm/proto.h>
60#include <asm/setup.h>
61#include <asm/mach_apic.h>
62#include <asm/numa.h>
63
64/*
65 * Machine setup..
66 */
67
68struct cpuinfo_x86 boot_cpu_data;
69
70unsigned long mmu_cr4_features;
71
72int acpi_disabled;
73EXPORT_SYMBOL(acpi_disabled);
74#ifdef CONFIG_ACPI_BOOT
75extern int __initdata acpi_ht;
76extern acpi_interrupt_flags acpi_sci_flags;
77int __initdata acpi_force = 0;
78#endif
79
80int acpi_numa __initdata;
81
1da177e4
LT		 82/* Boot loader ID as an integer, for the benefit of proc_dointvec */
83int bootloader_type;
84
85unsigned long saved_video_mode;
86
87#ifdef CONFIG_SWIOTLB
88int swiotlb;
89EXPORT_SYMBOL(swiotlb);
90#endif
91
92/*
93 * Setup options
94 */
95struct drive_info_struct { char dummy[32]; } drive_info;
96struct screen_info screen_info;
97struct sys_desc_table_struct {
98 unsigned short length;
99 unsigned char table[0];
100};
101
102struct edid_info edid_info;
103struct e820map e820;
104
105extern int root_mountflags;
106extern char _text, _etext, _edata, _end;
107
108char command_line[COMMAND_LINE_SIZE];
109
110struct resource standard_io_resources[] = {
111 { .name = "dma1", .start = 0x00, .end = 0x1f,
112 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
113 { .name = "pic1", .start = 0x20, .end = 0x21,
114 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
115 { .name = "timer0", .start = 0x40, .end = 0x43,
116 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
117 { .name = "timer1", .start = 0x50, .end = 0x53,
118 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
119 { .name = "keyboard", .start = 0x60, .end = 0x6f,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
121 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
122 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
123 { .name = "pic2", .start = 0xa0, .end = 0xa1,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "dma2", .start = 0xc0, .end = 0xdf,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "fpu", .start = 0xf0, .end = 0xff,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
129};
130
131#define STANDARD_IO_RESOURCES \
132 (sizeof standard_io_resources / sizeof standard_io_resources[0])
133
134#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
135
136struct resource data_resource = {
137 .name = "Kernel data",
138 .start = 0,
139 .end = 0,
140 .flags = IORESOURCE_RAM,
141};
142struct resource code_resource = {
143 .name = "Kernel code",
144 .start = 0,
145 .end = 0,
146 .flags = IORESOURCE_RAM,
147};
148
149#define IORESOURCE_ROM (IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM)
150
151static struct resource system_rom_resource = {
152 .name = "System ROM",
153 .start = 0xf0000,
154 .end = 0xfffff,
155 .flags = IORESOURCE_ROM,
156};
157
158static struct resource extension_rom_resource = {
159 .name = "Extension ROM",
160 .start = 0xe0000,
161 .end = 0xeffff,
162 .flags = IORESOURCE_ROM,
163};
164
165static struct resource adapter_rom_resources[] = {
166 { .name = "Adapter ROM", .start = 0xc8000, .end = 0,
167 .flags = IORESOURCE_ROM },
168 { .name = "Adapter ROM", .start = 0, .end = 0,
169 .flags = IORESOURCE_ROM },
170 { .name = "Adapter ROM", .start = 0, .end = 0,
171 .flags = IORESOURCE_ROM },
172 { .name = "Adapter ROM", .start = 0, .end = 0,
173 .flags = IORESOURCE_ROM },
174 { .name = "Adapter ROM", .start = 0, .end = 0,
175 .flags = IORESOURCE_ROM },
176 { .name = "Adapter ROM", .start = 0, .end = 0,
177 .flags = IORESOURCE_ROM }
178};
179
180#define ADAPTER_ROM_RESOURCES \
181 (sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
182
183static struct resource video_rom_resource = {
184 .name = "Video ROM",
185 .start = 0xc0000,
186 .end = 0xc7fff,
187 .flags = IORESOURCE_ROM,
188};
189
190static struct resource video_ram_resource = {
191 .name = "Video RAM area",
192 .start = 0xa0000,
193 .end = 0xbffff,
194 .flags = IORESOURCE_RAM,
195};
196
197#define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
198
199static int __init romchecksum(unsigned char *rom, unsigned long length)
200{
201 unsigned char *p, sum = 0;
202
203 for (p = rom; p < rom + length; p++)
204 sum += *p;
205 return sum == 0;
206}
207
208static void __init probe_roms(void)
209{
210 unsigned long start, length, upper;
211 unsigned char *rom;
212 int i;
213
214 /* video rom */
215 upper = adapter_rom_resources[0].start;
216 for (start = video_rom_resource.start; start < upper; start += 2048) {
217 rom = isa_bus_to_virt(start);
218 if (!romsignature(rom))
219 continue;
220
221 video_rom_resource.start = start;
222
223 /* 0 < length <= 0x7f * 512, historically */
224 length = rom[2] * 512;
225
226 /* if checksum okay, trust length byte */
227 if (length && romchecksum(rom, length))
228 video_rom_resource.end = start + length - 1;
229
230 request_resource(&iomem_resource, &video_rom_resource);
231 break;
232 }
233
234 start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
235 if (start < upper)
236 start = upper;
237
238 /* system rom */
239 request_resource(&iomem_resource, &system_rom_resource);
240 upper = system_rom_resource.start;
241
242 /* check for extension rom (ignore length byte!) */
243 rom = isa_bus_to_virt(extension_rom_resource.start);
244 if (romsignature(rom)) {
245 length = extension_rom_resource.end - extension_rom_resource.start + 1;
246 if (romchecksum(rom, length)) {
247 request_resource(&iomem_resource, &extension_rom_resource);
248 upper = extension_rom_resource.start;
249 }
250 }
251
252 /* check for adapter roms on 2k boundaries */
253 for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
254 rom = isa_bus_to_virt(start);
255 if (!romsignature(rom))
256 continue;
257
258 /* 0 < length <= 0x7f * 512, historically */
259 length = rom[2] * 512;
260
261 /* but accept any length that fits if checksum okay */
262 if (!length || start + length > upper || !romchecksum(rom, length))
263 continue;
264
265 adapter_rom_resources[i].start = start;
266 adapter_rom_resources[i].end = start + length - 1;
267 request_resource(&iomem_resource, &adapter_rom_resources[i]);
268
269 start = adapter_rom_resources[i++].end & ~2047UL;
270 }
271}
272
273static __init void parse_cmdline_early (char ** cmdline_p)
274{
275 char c = ' ', *to = command_line, *from = COMMAND_LINE;
276 int len = 0;
277
278 /* Save unparsed command line copy for /proc/cmdline */
279 memcpy(saved_command_line, COMMAND_LINE, COMMAND_LINE_SIZE);
280 saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
281
282 for (;;) {
283 if (c != ' ')
284 goto next_char;
285
286#ifdef CONFIG_SMP
287 /*
288 * If the BIOS enumerates physical processors before logical,
289 * maxcpus=N at enumeration-time can be used to disable HT.
290 */
291 else if (!memcmp(from, "maxcpus=", 8)) {
292 extern unsigned int maxcpus;
293
294 maxcpus = simple_strtoul(from + 8, NULL, 0);
295 }
296#endif
297#ifdef CONFIG_ACPI_BOOT
298 /* "acpi=off" disables both ACPI table parsing and interpreter init */
299 if (!memcmp(from, "acpi=off", 8))
300 disable_acpi();
301
302 if (!memcmp(from, "acpi=force", 10)) {
303 /* add later when we do DMI horrors: */
304 acpi_force = 1;
305 acpi_disabled = 0;
306 }
307
308 /* acpi=ht just means: do ACPI MADT parsing
309 at bootup, but don't enable the full ACPI interpreter */
310 if (!memcmp(from, "acpi=ht", 7)) {
311 if (!acpi_force)
312 disable_acpi();
313 acpi_ht = 1;
314 }
315 else if (!memcmp(from, "pci=noacpi", 10))
316 acpi_disable_pci();
317 else if (!memcmp(from, "acpi=noirq", 10))
318 acpi_noirq_set();
319
320 else if (!memcmp(from, "acpi_sci=edge", 13))
321 acpi_sci_flags.trigger = 1;
322 else if (!memcmp(from, "acpi_sci=level", 14))
323 acpi_sci_flags.trigger = 3;
324 else if (!memcmp(from, "acpi_sci=high", 13))
325 acpi_sci_flags.polarity = 1;
326 else if (!memcmp(from, "acpi_sci=low", 12))
327 acpi_sci_flags.polarity = 3;
328
329 /* acpi=strict disables out-of-spec workarounds */
330 else if (!memcmp(from, "acpi=strict", 11)) {
331 acpi_strict = 1;
332 }
22999244
AK		 333#ifdef CONFIG_X86_IO_APIC
334 else if (!memcmp(from, "acpi_skip_timer_override", 24))
335 acpi_skip_timer_override = 1;
336#endif
1da177e4
LT		 337#endif
338
339 if (!memcmp(from, "nolapic", 7) ||
340 !memcmp(from, "disableapic", 11))
341 disable_apic = 1;
342
343 if (!memcmp(from, "noapic", 6))
344 skip_ioapic_setup = 1;
345
346 if (!memcmp(from, "apic", 4)) {
347 skip_ioapic_setup = 0;
348 ioapic_force = 1;
349 }
350
351 if (!memcmp(from, "mem=", 4))
352 parse_memopt(from+4, &from);
353
2b97690f 354#ifdef CONFIG_NUMA
1da177e4
LT		 355 if (!memcmp(from, "numa=", 5))
356 numa_setup(from+5);
357#endif
358
359#ifdef CONFIG_GART_IOMMU
360 if (!memcmp(from,"iommu=",6)) {
361 iommu_setup(from+6);
362 }
363#endif
364
365 if (!memcmp(from,"oops=panic", 10))
366 panic_on_oops = 1;
367
368 if (!memcmp(from, "noexec=", 7))
369 nonx_setup(from + 7);
370
5f5609df
EB		 371#ifdef CONFIG_KEXEC
372 /* crashkernel=size@addr specifies the location to reserve for
373 * a crash kernel. By reserving this memory we guarantee
374 * that linux never set's it up as a DMA target.
375 * Useful for holding code to do something appropriate
376 * after a kernel panic.
377 */
378 else if (!memcmp(from, "crashkernel=", 12)) {
379 unsigned long size, base;
380 size = memparse(from+12, &from);
381 if (*from == '@') {
382 base = memparse(from+1, &from);
383 /* FIXME: Do I want a sanity check
384 * to validate the memory range?
385 */
386 crashk_res.start = base;
387 crashk_res.end = base + size - 1;
388 }
389 }
390#endif
391
1da177e4
LT		 392 next_char:
393 c = *(from++);
394 if (!c)
395 break;
396 if (COMMAND_LINE_SIZE <= ++len)
397 break;
398 *(to++) = c;
399 }
400 *to = '\0';
401 *cmdline_p = command_line;
402}
403
2b97690f 404#ifndef CONFIG_NUMA
bbfceef4
MT		 405static void __init
406contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
1da177e4 407{
bbfceef4
MT		 408 unsigned long bootmap_size, bootmap;
409
410 memory_present(0, start_pfn, end_pfn);
411 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
412 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
413 if (bootmap == -1L)
414 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
415 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
416 e820_bootmem_free(NODE_DATA(0), 0, end_pfn << PAGE_SHIFT);
417 reserve_bootmem(bootmap, bootmap_size);
1da177e4
LT		 418}
419#endif
420
421/* Use inline assembly to define this because the nops are defined
422 as inline assembly strings in the include files and we cannot
423 get them easily into strings. */
424asm("\t.data\nk8nops: "
425 K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6
426 K8_NOP7 K8_NOP8);
427
428extern unsigned char k8nops[];
429static unsigned char *k8_nops[ASM_NOP_MAX+1] = {
430 NULL,
431 k8nops,
432 k8nops + 1,
433 k8nops + 1 + 2,
434 k8nops + 1 + 2 + 3,
435 k8nops + 1 + 2 + 3 + 4,
436 k8nops + 1 + 2 + 3 + 4 + 5,
437 k8nops + 1 + 2 + 3 + 4 + 5 + 6,
438 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
439};
440
441/* Replace instructions with better alternatives for this CPU type.
442
443 This runs before SMP is initialized to avoid SMP problems with
444 self modifying code. This implies that assymetric systems where
445 APs have less capabilities than the boot processor are not handled.
446 In this case boot with "noreplacement". */
447void apply_alternatives(void *start, void *end)
448{
449 struct alt_instr *a;
450 int diff, i, k;
451 for (a = start; (void *)a < end; a++) {
452 if (!boot_cpu_has(a->cpuid))
453 continue;
454
455 BUG_ON(a->replacementlen > a->instrlen);
456 __inline_memcpy(a->instr, a->replacement, a->replacementlen);
457 diff = a->instrlen - a->replacementlen;
458
459 /* Pad the rest with nops */
460 for (i = a->replacementlen; diff > 0; diff -= k, i += k) {
461 k = diff;
462 if (k > ASM_NOP_MAX)
463 k = ASM_NOP_MAX;
464 __inline_memcpy(a->instr + i, k8_nops[k], k);
465 }
466 }
467}
468
469static int no_replacement __initdata = 0;
470
471void __init alternative_instructions(void)
472{
473 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
474 if (no_replacement)
475 return;
476 apply_alternatives(__alt_instructions, __alt_instructions_end);
477}
478
479static int __init noreplacement_setup(char *s)
480{
481 no_replacement = 1;
482 return 0;
483}
484
485__setup("noreplacement", noreplacement_setup);
486
487#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
488struct edd edd;
489#ifdef CONFIG_EDD_MODULE
490EXPORT_SYMBOL(edd);
491#endif
492/**
493 * copy_edd() - Copy the BIOS EDD information
494 * from boot_params into a safe place.
495 *
496 */
497static inline void copy_edd(void)
498{
499 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
500 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
501 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
502 edd.edd_info_nr = EDD_NR;
503}
504#else
505static inline void copy_edd(void)
506{
507}
508#endif
509
510#define EBDA_ADDR_POINTER 0x40E
511static void __init reserve_ebda_region(void)
512{
513 unsigned int addr;
514 /**
515 * there is a real-mode segmented pointer pointing to the
516 * 4K EBDA area at 0x40E
517 */
518 addr = *(unsigned short *)phys_to_virt(EBDA_ADDR_POINTER);
519 addr <<= 4;
520 if (addr)
521 reserve_bootmem_generic(addr, PAGE_SIZE);
522}
523
524void __init setup_arch(char **cmdline_p)
525{
1da177e4
LT		 526 unsigned long kernel_end;
527
528 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
529 drive_info = DRIVE_INFO;
530 screen_info = SCREEN_INFO;
531 edid_info = EDID_INFO;
532 saved_video_mode = SAVED_VIDEO_MODE;
533 bootloader_type = LOADER_TYPE;
534
535#ifdef CONFIG_BLK_DEV_RAM
536 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
537 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
538 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
539#endif
540 setup_memory_region();
541 copy_edd();
542
543 if (!MOUNT_ROOT_RDONLY)
544 root_mountflags &= ~MS_RDONLY;
545 init_mm.start_code = (unsigned long) &_text;
546 init_mm.end_code = (unsigned long) &_etext;
547 init_mm.end_data = (unsigned long) &_edata;
548 init_mm.brk = (unsigned long) &_end;
549
550 code_resource.start = virt_to_phys(&_text);
551 code_resource.end = virt_to_phys(&_etext)-1;
552 data_resource.start = virt_to_phys(&_etext);
553 data_resource.end = virt_to_phys(&_edata)-1;
554
555 parse_cmdline_early(cmdline_p);
556
557 early_identify_cpu(&boot_cpu_data);
558
559 /*
560 * partially used pages are not usable - thus
561 * we are rounding upwards:
562 */
563 end_pfn = e820_end_of_ram();
564
565 check_efer();
566
567 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
568
569#ifdef CONFIG_ACPI_BOOT
570 /*
571 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
572 * Call this early for SRAT node setup.
573 */
574 acpi_boot_table_init();
575#endif
576
577#ifdef CONFIG_ACPI_NUMA
578 /*
579 * Parse SRAT to discover nodes.
580 */
581 acpi_numa_init();
582#endif
583
2b97690f 584#ifdef CONFIG_NUMA
1da177e4
LT		 585 numa_initmem_init(0, end_pfn);
586#else
bbfceef4 587 contig_initmem_init(0, end_pfn);
1da177e4
LT		 588#endif
589
590 /* Reserve direct mapping */
591 reserve_bootmem_generic(table_start << PAGE_SHIFT,
592 (table_end - table_start) << PAGE_SHIFT);
593
594 /* reserve kernel */
595 kernel_end = round_up(__pa_symbol(&_end),PAGE_SIZE);
596 reserve_bootmem_generic(HIGH_MEMORY, kernel_end - HIGH_MEMORY);
597
598 /*
599 * reserve physical page 0 - it's a special BIOS page on many boxes,
600 * enabling clean reboots, SMP operation, laptop functions.
601 */
602 reserve_bootmem_generic(0, PAGE_SIZE);
603
604 /* reserve ebda region */
605 reserve_ebda_region();
606
607#ifdef CONFIG_SMP
608 /*
609 * But first pinch a few for the stack/trampoline stuff
610 * FIXME: Don't need the extra page at 4K, but need to fix
611 * trampoline before removing it. (see the GDT stuff)
612 */
613 reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
614
615 /* Reserve SMP trampoline */
616 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
617#endif
618
619#ifdef CONFIG_ACPI_SLEEP
620 /*
621 * Reserve low memory region for sleep support.
622 */
623 acpi_reserve_bootmem();
624#endif
625#ifdef CONFIG_X86_LOCAL_APIC
626 /*
627 * Find and reserve possible boot-time SMP configuration:
628 */
629 find_smp_config();
630#endif
631#ifdef CONFIG_BLK_DEV_INITRD
632 if (LOADER_TYPE && INITRD_START) {
633 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
634 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
635 initrd_start =
636 INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
637 initrd_end = initrd_start+INITRD_SIZE;
638 }
639 else {
640 printk(KERN_ERR "initrd extends beyond end of memory "
641 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
642 (unsigned long)(INITRD_START + INITRD_SIZE),
643 (unsigned long)(end_pfn << PAGE_SHIFT));
644 initrd_start = 0;
645 }
646 }
647#endif
bbfceef4
MT		 648
649 sparse_init();
5f5609df
EB		 650
651#ifdef CONFIG_KEXEC
652 if (crashk_res.start != crashk_res.end) {
653 reserve_bootmem(crashk_res.start,
654 crashk_res.end - crashk_res.start + 1);
655 }
656#endif
1da177e4
LT		 657 paging_init();
658
659 check_ioapic();
660
661#ifdef CONFIG_ACPI_BOOT
662 /*
663 * Read APIC and some other early information from ACPI tables.
664 */
665 acpi_boot_init();
666#endif
667
668#ifdef CONFIG_X86_LOCAL_APIC
669 /*
670 * get boot-time SMP configuration:
671 */
672 if (smp_found_config)
673 get_smp_config();
674 init_apic_mappings();
675#endif
676
677 /*
678 * Request address space for all standard RAM and ROM resources
679 * and also for regions reported as reserved by the e820.
680 */
681 probe_roms();
682 e820_reserve_resources();
683
684 request_resource(&iomem_resource, &video_ram_resource);
685
686 {
687 unsigned i;
688 /* request I/O space for devices used on all i[345]86 PCs */
689 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
690 request_resource(&ioport_resource, &standard_io_resources[i]);
691 }
692
a1e97782 693 e820_setup_gap();
1da177e4
LT		 694
695#ifdef CONFIG_GART_IOMMU
696 iommu_hole_init();
697#endif
698
699#ifdef CONFIG_VT
700#if defined(CONFIG_VGA_CONSOLE)
701 conswitchp = &vga_con;
702#elif defined(CONFIG_DUMMY_CONSOLE)
703 conswitchp = &dummy_con;
704#endif
705#endif
706}
707
e6982c67 708static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
1da177e4
LT		 709{
710 unsigned int *v;
711
ebfcaa96 712 if (c->extended_cpuid_level < 0x80000004)
1da177e4
LT		 713 return 0;
714
715 v = (unsigned int *) c->x86_model_id;
716 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
717 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
718 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
719 c->x86_model_id[48] = 0;
720 return 1;
721}
722
723
e6982c67 724static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
1da177e4
LT		 725{
726 unsigned int n, dummy, eax, ebx, ecx, edx;
727
ebfcaa96 728 n = c->extended_cpuid_level;
1da177e4
LT		 729
730 if (n >= 0x80000005) {
731 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
732 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
733 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
734 c->x86_cache_size=(ecx>>24)+(edx>>24);
735 /* On K8 L1 TLB is inclusive, so don't count it */
736 c->x86_tlbsize = 0;
737 }
738
739 if (n >= 0x80000006) {
740 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
741 ecx = cpuid_ecx(0x80000006);
742 c->x86_cache_size = ecx >> 16;
743 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
744
745 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
746 c->x86_cache_size, ecx & 0xFF);
747 }
748
749 if (n >= 0x80000007)
750 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
751 if (n >= 0x80000008) {
752 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
753 c->x86_virt_bits = (eax >> 8) & 0xff;
754 c->x86_phys_bits = eax & 0xff;
755 }
756}
757
63518644
AK		 758/*
759 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
760 * Assumes number of cores is a power of two.
761 */
762static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
763{
764#ifdef CONFIG_SMP
2942283e 765 int cpu = smp_processor_id();
63518644 766 int node = 0;
b41e2939 767 unsigned bits;
63518644
AK		 768 if (c->x86_num_cores == 1)
769 return;
b41e2939
AK		 770
771 bits = 0;
772 while ((1 << bits) < c->x86_num_cores)
773 bits++;
774
775 /* Low order bits define the core id (index of core in socket) */
776 cpu_core_id[cpu] = phys_proc_id[cpu] & ((1 << bits)-1);
777 /* Convert the APIC ID into the socket ID */
778 phys_proc_id[cpu] >>= bits;
63518644
AK		 779
780#ifdef CONFIG_NUMA
781 /* When an ACPI SRAT table is available use the mappings from SRAT
782 instead. */
783 if (acpi_numa <= 0) {
b41e2939 784 node = phys_proc_id[cpu];
63518644
AK		 785 if (!node_online(node))
786 node = first_node(node_online_map);
787 cpu_to_node[cpu] = node;
788 } else {
789 node = cpu_to_node[cpu];
790 }
791#endif
a158608b 792
63518644
AK		 793 printk(KERN_INFO "CPU %d(%d) -> Node %d -> Core %d\n",
794 cpu, c->x86_num_cores, node, cpu_core_id[cpu]);
795#endif
796}
1da177e4
LT		 797
798static int __init init_amd(struct cpuinfo_x86 *c)
799{
800 int r;
801 int level;
1da177e4
LT		 802
803 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
804 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
805 clear_bit(0*32+31, &c->x86_capability);
806
807 /* C-stepping K8? */
808 level = cpuid_eax(1);
809 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
810 set_bit(X86_FEATURE_K8_C, &c->x86_capability);
811
812 r = get_model_name(c);
813 if (!r) {
814 switch (c->x86) {
815 case 15:
816 /* Should distinguish Models here, but this is only
817 a fallback anyways. */
818 strcpy(c->x86_model_id, "Hammer");
819 break;
820 }
821 }
822 display_cacheinfo(c);
823
ebfcaa96 824 if (c->extended_cpuid_level >= 0x80000008) {
1da177e4
LT		 825 c->x86_num_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
826 if (c->x86_num_cores & (c->x86_num_cores - 1))
827 c->x86_num_cores = 1;
828
63518644 829 amd_detect_cmp(c);
1da177e4
LT		 830 }
831
832 return r;
833}
834
e6982c67 835static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1da177e4
LT		 836{
837#ifdef CONFIG_SMP
838 u32 eax, ebx, ecx, edx;
3dd9d514 839 int index_msb, tmp;
1da177e4
LT		 840 int cpu = smp_processor_id();
841
63518644 842 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
1da177e4
LT		 843 return;
844
845 cpuid(1, &eax, &ebx, &ecx, &edx);
846 smp_num_siblings = (ebx & 0xff0000) >> 16;
847
848 if (smp_num_siblings == 1) {
849 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
850 } else if (smp_num_siblings > 1) {
1da177e4
LT		 851 index_msb = 31;
852 /*
853 * At this point we only support two siblings per
854 * processor package.
855 */
856 if (smp_num_siblings > NR_CPUS) {
857 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
858 smp_num_siblings = 1;
859 return;
860 }
861 tmp = smp_num_siblings;
1da177e4
LT		 862 while ((tmp & 0x80000000 ) == 0) {
863 tmp <<=1 ;
864 index_msb--;
865 }
3dd9d514 866 if (smp_num_siblings & (smp_num_siblings - 1))
1da177e4
LT		 867 index_msb++;
868 phys_proc_id[cpu] = phys_pkg_id(index_msb);
869
870 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
871 phys_proc_id[cpu]);
3dd9d514
AK		 872
873 smp_num_siblings = smp_num_siblings / c->x86_num_cores;
874
875 tmp = smp_num_siblings;
876 index_msb = 31;
877 while ((tmp & 0x80000000) == 0) {
878 tmp <<=1 ;
879 index_msb--;
880 }
881 if (smp_num_siblings & (smp_num_siblings - 1))
882 index_msb++;
883
884 cpu_core_id[cpu] = phys_pkg_id(index_msb);
885
886 if (c->x86_num_cores > 1)
887 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
888 cpu_core_id[cpu]);
1da177e4
LT		 889 }
890#endif
891}
892
3dd9d514
AK		 893/*
894 * find out the number of processor cores on the die
895 */
e6982c67 896static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514
AK		 897{
898 unsigned int eax;
899
900 if (c->cpuid_level < 4)
901 return 1;
902
903 __asm__("cpuid"
904 : "=a" (eax)
905 : "0" (4), "c" (0)
906 : "bx", "dx");
907
908 if (eax & 0x1f)
909 return ((eax >> 26) + 1);
910 else
911 return 1;
912}
913
e6982c67 914static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4
LT		 915{
916 /* Cache sizes */
917 unsigned n;
918
919 init_intel_cacheinfo(c);
ebfcaa96 920 n = c->extended_cpuid_level;
1da177e4
LT		 921 if (n >= 0x80000008) {
922 unsigned eax = cpuid_eax(0x80000008);
923 c->x86_virt_bits = (eax >> 8) & 0xff;
924 c->x86_phys_bits = eax & 0xff;
925 }
926
927 if (c->x86 == 15)
928 c->x86_cache_alignment = c->x86_clflush_size * 2;
c29601e9
AK		 929 if (c->x86 >= 15)
930 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
3dd9d514 931 c->x86_num_cores = intel_num_cpu_cores(c);
1da177e4
LT		 932}
933
e6982c67 934void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1da177e4
LT		 935{
936 char *v = c->x86_vendor_id;
937
938 if (!strcmp(v, "AuthenticAMD"))
939 c->x86_vendor = X86_VENDOR_AMD;
940 else if (!strcmp(v, "GenuineIntel"))
941 c->x86_vendor = X86_VENDOR_INTEL;
942 else
943 c->x86_vendor = X86_VENDOR_UNKNOWN;
944}
945
946struct cpu_model_info {
947 int vendor;
948 int family;
949 char *model_names[16];
950};
951
952/* Do some early cpuid on the boot CPU to get some parameter that are
953 needed before check_bugs. Everything advanced is in identify_cpu
954 below. */
e6982c67 955void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 956{
957 u32 tfms;
958
959 c->loops_per_jiffy = loops_per_jiffy;
960 c->x86_cache_size = -1;
961 c->x86_vendor = X86_VENDOR_UNKNOWN;
962 c->x86_model = c->x86_mask = 0; /* So far unknown... */
963 c->x86_vendor_id[0] = '\0'; /* Unset */
964 c->x86_model_id[0] = '\0'; /* Unset */
965 c->x86_clflush_size = 64;
966 c->x86_cache_alignment = c->x86_clflush_size;
967 c->x86_num_cores = 1;
ebfcaa96 968 c->extended_cpuid_level = 0;
1da177e4
LT		 969 memset(&c->x86_capability, 0, sizeof c->x86_capability);
970
971 /* Get vendor name */
972 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
973 (unsigned int *)&c->x86_vendor_id[0],
974 (unsigned int *)&c->x86_vendor_id[8],
975 (unsigned int *)&c->x86_vendor_id[4]);
976
977 get_cpu_vendor(c);
978
979 /* Initialize the standard set of capabilities */
980 /* Note that the vendor-specific code below might override */
981
982 /* Intel-defined flags: level 0x00000001 */
983 if (c->cpuid_level >= 0x00000001) {
984 __u32 misc;
985 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
986 &c->x86_capability[0]);
987 c->x86 = (tfms >> 8) & 0xf;
988 c->x86_model = (tfms >> 4) & 0xf;
989 c->x86_mask = tfms & 0xf;
990 if (c->x86 == 0xf) {
991 c->x86 += (tfms >> 20) & 0xff;
992 c->x86_model += ((tfms >> 16) & 0xF) << 4;
993 }
994 if (c->x86_capability[0] & (1<<19))
995 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1da177e4
LT		 996 } else {
997 /* Have CPUID level 0 only - unheard of */
998 c->x86 = 4;
999 }
a158608b
AK		 1000
1001#ifdef CONFIG_SMP
b41e2939 1002 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
a158608b 1003#endif
1da177e4
LT		 1004}
1005
1006/*
1007 * This does the hard work of actually picking apart the CPU stuff...
1008 */
e6982c67 1009void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 1010{
1011 int i;
1012 u32 xlvl;
1013
1014 early_identify_cpu(c);
1015
1016 /* AMD-defined flags: level 0x80000001 */
1017 xlvl = cpuid_eax(0x80000000);
ebfcaa96 1018 c->extended_cpuid_level = xlvl;
1da177e4
LT		 1019 if ((xlvl & 0xffff0000) == 0x80000000) {
1020 if (xlvl >= 0x80000001) {
1021 c->x86_capability[1] = cpuid_edx(0x80000001);
5b7abc6f 1022 c->x86_capability[6] = cpuid_ecx(0x80000001);
1da177e4
LT		 1023 }
1024 if (xlvl >= 0x80000004)
1025 get_model_name(c); /* Default name */
1026 }
1027
1028 /* Transmeta-defined flags: level 0x80860001 */
1029 xlvl = cpuid_eax(0x80860000);
1030 if ((xlvl & 0xffff0000) == 0x80860000) {
1031 /* Don't set x86_cpuid_level here for now to not confuse. */
1032 if (xlvl >= 0x80860001)
1033 c->x86_capability[2] = cpuid_edx(0x80860001);
1034 }
1035
1036 /*
1037 * Vendor-specific initialization. In this section we
1038 * canonicalize the feature flags, meaning if there are
1039 * features a certain CPU supports which CPUID doesn't
1040 * tell us, CPUID claiming incorrect flags, or other bugs,
1041 * we handle them here.
1042 *
1043 * At the end of this section, c->x86_capability better
1044 * indicate the features this CPU genuinely supports!
1045 */
1046 switch (c->x86_vendor) {
1047 case X86_VENDOR_AMD:
1048 init_amd(c);
1049 break;
1050
1051 case X86_VENDOR_INTEL:
1052 init_intel(c);
1053 break;
1054
1055 case X86_VENDOR_UNKNOWN:
1056 default:
1057 display_cacheinfo(c);
1058 break;
1059 }
1060
1061 select_idle_routine(c);
1062 detect_ht(c);
1da177e4
LT		 1063
1064 /*
1065 * On SMP, boot_cpu_data holds the common feature set between
1066 * all CPUs; so make sure that we indicate which features are
1067 * common between the CPUs. The first time this routine gets
1068 * executed, c == &boot_cpu_data.
1069 */
1070 if (c != &boot_cpu_data) {
1071 /* AND the already accumulated flags with these */
1072 for (i = 0 ; i < NCAPINTS ; i++)
1073 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1074 }
1075
1076#ifdef CONFIG_X86_MCE
1077 mcheck_init(c);
1078#endif
3b520b23
SL		 1079 if (c == &boot_cpu_data)
1080 mtrr_bp_init();
1081 else
1082 mtrr_ap_init();
1da177e4
LT		 1083#ifdef CONFIG_NUMA
1084 if (c != &boot_cpu_data)
1085 numa_add_cpu(c - cpu_data);
1086#endif
1087}
1088
1089
e6982c67 1090void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1da177e4
LT		 1091{
1092 if (c->x86_model_id[0])
1093 printk("%s", c->x86_model_id);
1094
1095 if (c->x86_mask || c->cpuid_level >= 0)
1096 printk(" stepping %02x\n", c->x86_mask);
1097 else
1098 printk("\n");
1099}
1100
1101/*
1102 * Get CPU information for use by the procfs.
1103 */
1104
1105static int show_cpuinfo(struct seq_file *m, void *v)
1106{
1107 struct cpuinfo_x86 *c = v;
1108
1109 /*
1110 * These flag bits must match the definitions in <asm/cpufeature.h>.
1111 * NULL means this bit is undefined or reserved; either way it doesn't
1112 * have meaning as far as Linux is concerned. Note that it's important
1113 * to realize there is a difference between this table and CPUID -- if
1114 * applications want to get the raw CPUID data, they should access
1115 * /dev/cpu/<cpu_nr>/cpuid instead.
1116 */
1117 static char *x86_cap_flags[] = {
1118 /* Intel-defined */
1119 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1120 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1121 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1122 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
1123
1124 /* AMD-defined */
3c3b73b6 1125 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1126 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1127 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1128 NULL, "fxsr_opt", NULL, NULL, NULL, "lm", "3dnowext", "3dnow",
1129
1130 /* Transmeta-defined */
1131 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1135
1136 /* Other (Linux-defined) */
622dcaf9 1137 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
c29601e9 1138 "constant_tsc", NULL, NULL,
1da177e4
LT		 1139 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1141 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1142
1143 /* Intel-defined (#2) */
1144 "pni", NULL, NULL, "monitor", "ds_cpl", NULL, NULL, "est",
1145 "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
1146 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1147 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1148
5b7abc6f
PA		 1149 /* VIA/Cyrix/Centaur-defined */
1150 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1151 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1154
1da177e4
LT		 1155 /* AMD-defined (#2) */
1156 "lahf_lm", "cmp_legacy", NULL, NULL, NULL, NULL, NULL, NULL,
1157 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1158 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
5b7abc6f 1159 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1160 };
1161 static char *x86_power_flags[] = {
1162 "ts", /* temperature sensor */
1163 "fid", /* frequency id control */
1164 "vid", /* voltage id control */
1165 "ttp", /* thermal trip */
1166 "tm",
1167 "stc"
1168 };
1169
1170
1171#ifdef CONFIG_SMP
1172 if (!cpu_online(c-cpu_data))
1173 return 0;
1174#endif
1175
1176 seq_printf(m,"processor\t: %u\n"
1177 "vendor_id\t: %s\n"
1178 "cpu family\t: %d\n"
1179 "model\t\t: %d\n"
1180 "model name\t: %s\n",
1181 (unsigned)(c-cpu_data),
1182 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1183 c->x86,
1184 (int)c->x86_model,
1185 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1186
1187 if (c->x86_mask || c->cpuid_level >= 0)
1188 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1189 else
1190 seq_printf(m, "stepping\t: unknown\n");
1191
1192 if (cpu_has(c,X86_FEATURE_TSC)) {
1193 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1194 cpu_khz / 1000, (cpu_khz % 1000));
1195 }
1196
1197 /* Cache size */
1198 if (c->x86_cache_size >= 0)
1199 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1200
1201#ifdef CONFIG_SMP
db468681
AK		 1202 if (smp_num_siblings * c->x86_num_cores > 1) {
1203 int cpu = c - cpu_data;
1204 seq_printf(m, "physical id\t: %d\n", phys_proc_id[cpu]);
1205 seq_printf(m, "siblings\t: %d\n",
1206 c->x86_num_cores * smp_num_siblings);
d31ddaa1
SS		 1207 seq_printf(m, "core id\t\t: %d\n", cpu_core_id[cpu]);
1208 seq_printf(m, "cpu cores\t: %d\n", c->x86_num_cores);
db468681 1209 }
1da177e4
LT		 1210#endif
1211
1212 seq_printf(m,
1213 "fpu\t\t: yes\n"
1214 "fpu_exception\t: yes\n"
1215 "cpuid level\t: %d\n"
1216 "wp\t\t: yes\n"
1217 "flags\t\t:",
1218 c->cpuid_level);
1219
1220 {
1221 int i;
1222 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1223 if ( test_bit(i, &c->x86_capability) &&
1224 x86_cap_flags[i] != NULL )
1225 seq_printf(m, " %s", x86_cap_flags[i]);
1226 }
1227
1228 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1229 c->loops_per_jiffy/(500000/HZ),
1230 (c->loops_per_jiffy/(5000/HZ)) % 100);
1231
1232 if (c->x86_tlbsize > 0)
1233 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1234 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1235 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1236
1237 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1238 c->x86_phys_bits, c->x86_virt_bits);
1239
1240 seq_printf(m, "power management:");
1241 {
1242 unsigned i;
1243 for (i = 0; i < 32; i++)
1244 if (c->x86_power & (1 << i)) {
1245 if (i < ARRAY_SIZE(x86_power_flags))
1246 seq_printf(m, " %s", x86_power_flags[i]);
1247 else
1248 seq_printf(m, " [%d]", i);
1249 }
1250 }
1da177e4 1251
d31ddaa1 1252 seq_printf(m, "\n\n");
1da177e4
LT		 1253
1254 return 0;
1255}
1256
1257static void *c_start(struct seq_file *m, loff_t *pos)
1258{
1259 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1260}
1261
1262static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1263{
1264 ++*pos;
1265 return c_start(m, pos);
1266}
1267
1268static void c_stop(struct seq_file *m, void *v)
1269{
1270}
1271
1272struct seq_operations cpuinfo_op = {
1273 .start =c_start,
1274 .next = c_next,
1275 .stop = c_stop,
1276 .show = show_cpuinfo,
1277};
kernel source for telekom puls (alcatel/mediatek)