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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/config.h> | |
30 | #include <linux/smp_lock.h> | |
31 | #include <linux/mc146818rtc.h> | |
32 | #include <linux/acpi.h> | |
33 | #include <linux/sysdev.h> | |
34 | ||
35 | #include <asm/io.h> | |
36 | #include <asm/smp.h> | |
37 | #include <asm/desc.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/mach_apic.h> | |
40 | ||
41 | #define __apicdebuginit __init | |
42 | ||
43 | int sis_apic_bug; /* not actually supported, dummy for compile */ | |
44 | ||
45 | static DEFINE_SPINLOCK(ioapic_lock); | |
46 | ||
47 | /* | |
48 | * # of IRQ routing registers | |
49 | */ | |
50 | int nr_ioapic_registers[MAX_IO_APICS]; | |
51 | ||
52 | /* | |
53 | * Rough estimation of how many shared IRQs there are, can | |
54 | * be changed anytime. | |
55 | */ | |
56 | #define MAX_PLUS_SHARED_IRQS NR_IRQS | |
57 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) | |
58 | ||
59 | /* | |
60 | * This is performance-critical, we want to do it O(1) | |
61 | * | |
62 | * the indexing order of this array favors 1:1 mappings | |
63 | * between pins and IRQs. | |
64 | */ | |
65 | ||
66 | static struct irq_pin_list { | |
67 | short apic, pin, next; | |
68 | } irq_2_pin[PIN_MAP_SIZE]; | |
69 | ||
70 | int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1}; | |
71 | #ifdef CONFIG_PCI_MSI | |
72 | #define vector_to_irq(vector) \ | |
73 | (platform_legacy_irq(vector) ? vector : vector_irq[vector]) | |
74 | #else | |
75 | #define vector_to_irq(vector) (vector) | |
76 | #endif | |
77 | ||
78 | /* | |
79 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
80 | * shared ISA-space IRQs, so we have to support them. We are super | |
81 | * fast in the common case, and fast for shared ISA-space IRQs. | |
82 | */ | |
83 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
84 | { | |
85 | static int first_free_entry = NR_IRQS; | |
86 | struct irq_pin_list *entry = irq_2_pin + irq; | |
87 | ||
88 | while (entry->next) | |
89 | entry = irq_2_pin + entry->next; | |
90 | ||
91 | if (entry->pin != -1) { | |
92 | entry->next = first_free_entry; | |
93 | entry = irq_2_pin + entry->next; | |
94 | if (++first_free_entry >= PIN_MAP_SIZE) | |
95 | panic("io_apic.c: whoops"); | |
96 | } | |
97 | entry->apic = apic; | |
98 | entry->pin = pin; | |
99 | } | |
100 | ||
101 | #define __DO_ACTION(R, ACTION, FINAL) \ | |
102 | \ | |
103 | { \ | |
104 | int pin; \ | |
105 | struct irq_pin_list *entry = irq_2_pin + irq; \ | |
106 | \ | |
107 | for (;;) { \ | |
108 | unsigned int reg; \ | |
109 | pin = entry->pin; \ | |
110 | if (pin == -1) \ | |
111 | break; \ | |
112 | reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ | |
113 | reg ACTION; \ | |
114 | io_apic_modify(entry->apic, reg); \ | |
115 | if (!entry->next) \ | |
116 | break; \ | |
117 | entry = irq_2_pin + entry->next; \ | |
118 | } \ | |
119 | FINAL; \ | |
120 | } | |
121 | ||
122 | #define DO_ACTION(name,R,ACTION, FINAL) \ | |
123 | \ | |
124 | static void name##_IO_APIC_irq (unsigned int irq) \ | |
125 | __DO_ACTION(R, ACTION, FINAL) | |
126 | ||
127 | DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) ) | |
128 | /* mask = 1 */ | |
129 | DO_ACTION( __unmask, 0, &= 0xfffeffff, ) | |
130 | /* mask = 0 */ | |
131 | ||
132 | static void mask_IO_APIC_irq (unsigned int irq) | |
133 | { | |
134 | unsigned long flags; | |
135 | ||
136 | spin_lock_irqsave(&ioapic_lock, flags); | |
137 | __mask_IO_APIC_irq(irq); | |
138 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
139 | } | |
140 | ||
141 | static void unmask_IO_APIC_irq (unsigned int irq) | |
142 | { | |
143 | unsigned long flags; | |
144 | ||
145 | spin_lock_irqsave(&ioapic_lock, flags); | |
146 | __unmask_IO_APIC_irq(irq); | |
147 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
148 | } | |
149 | ||
150 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
151 | { | |
152 | struct IO_APIC_route_entry entry; | |
153 | unsigned long flags; | |
154 | ||
155 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
156 | spin_lock_irqsave(&ioapic_lock, flags); | |
157 | *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin); | |
158 | *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin); | |
159 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
160 | if (entry.delivery_mode == dest_SMI) | |
161 | return; | |
162 | /* | |
163 | * Disable it in the IO-APIC irq-routing table: | |
164 | */ | |
165 | memset(&entry, 0, sizeof(entry)); | |
166 | entry.mask = 1; | |
167 | spin_lock_irqsave(&ioapic_lock, flags); | |
168 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0)); | |
169 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1)); | |
170 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
171 | } | |
172 | ||
173 | static void clear_IO_APIC (void) | |
174 | { | |
175 | int apic, pin; | |
176 | ||
177 | for (apic = 0; apic < nr_ioapics; apic++) | |
178 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
179 | clear_IO_APIC_pin(apic, pin); | |
180 | } | |
181 | ||
182 | /* | |
183 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
184 | * specific CPU-side IRQs. | |
185 | */ | |
186 | ||
187 | #define MAX_PIRQS 8 | |
188 | static int pirq_entries [MAX_PIRQS]; | |
189 | static int pirqs_enabled; | |
190 | int skip_ioapic_setup; | |
191 | int ioapic_force; | |
192 | ||
193 | /* dummy parsing: see setup.c */ | |
194 | ||
195 | static int __init disable_ioapic_setup(char *str) | |
196 | { | |
197 | skip_ioapic_setup = 1; | |
198 | return 1; | |
199 | } | |
200 | ||
201 | static int __init enable_ioapic_setup(char *str) | |
202 | { | |
203 | ioapic_force = 1; | |
204 | skip_ioapic_setup = 0; | |
205 | return 1; | |
206 | } | |
207 | ||
208 | __setup("noapic", disable_ioapic_setup); | |
209 | __setup("apic", enable_ioapic_setup); | |
210 | ||
211 | #include <asm/pci-direct.h> | |
212 | #include <linux/pci_ids.h> | |
213 | #include <linux/pci.h> | |
214 | ||
215 | /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC | |
216 | off. Check for an Nvidia or VIA PCI bridge and turn it off. | |
217 | Use pci direct infrastructure because this runs before the PCI subsystem. | |
218 | ||
219 | Can be overwritten with "apic" | |
220 | ||
221 | And another hack to disable the IOMMU on VIA chipsets. | |
222 | ||
223 | Kludge-O-Rama. */ | |
224 | void __init check_ioapic(void) | |
225 | { | |
226 | int num,slot,func; | |
227 | if (ioapic_force) | |
228 | return; | |
229 | ||
230 | /* Poor man's PCI discovery */ | |
231 | for (num = 0; num < 32; num++) { | |
232 | for (slot = 0; slot < 32; slot++) { | |
233 | for (func = 0; func < 8; func++) { | |
234 | u32 class; | |
235 | u32 vendor; | |
236 | u8 type; | |
237 | class = read_pci_config(num,slot,func, | |
238 | PCI_CLASS_REVISION); | |
239 | if (class == 0xffffffff) | |
240 | break; | |
241 | ||
242 | if ((class >> 16) != PCI_CLASS_BRIDGE_PCI) | |
243 | continue; | |
244 | ||
245 | vendor = read_pci_config(num, slot, func, | |
246 | PCI_VENDOR_ID); | |
247 | vendor &= 0xffff; | |
248 | switch (vendor) { | |
249 | case PCI_VENDOR_ID_VIA: | |
250 | #ifdef CONFIG_GART_IOMMU | |
251 | if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) || | |
252 | force_iommu) && | |
253 | !iommu_aperture_allowed) { | |
254 | printk(KERN_INFO | |
255 | "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n"); | |
256 | iommu_aperture_disabled = 1; | |
257 | } | |
258 | #endif | |
259 | return; | |
260 | case PCI_VENDOR_ID_NVIDIA: | |
261 | #ifdef CONFIG_ACPI | |
262 | /* All timer overrides on Nvidia | |
263 | seem to be wrong. Skip them. */ | |
264 | acpi_skip_timer_override = 1; | |
265 | printk(KERN_INFO | |
266 | "Nvidia board detected. Ignoring ACPI timer override.\n"); | |
267 | #endif | |
268 | /* RED-PEN skip them on mptables too? */ | |
269 | return; | |
270 | } | |
271 | ||
272 | /* No multi-function device? */ | |
273 | type = read_pci_config_byte(num,slot,func, | |
274 | PCI_HEADER_TYPE); | |
275 | if (!(type & 0x80)) | |
276 | break; | |
277 | } | |
278 | } | |
279 | } | |
280 | } | |
281 | ||
282 | static int __init ioapic_pirq_setup(char *str) | |
283 | { | |
284 | int i, max; | |
285 | int ints[MAX_PIRQS+1]; | |
286 | ||
287 | get_options(str, ARRAY_SIZE(ints), ints); | |
288 | ||
289 | for (i = 0; i < MAX_PIRQS; i++) | |
290 | pirq_entries[i] = -1; | |
291 | ||
292 | pirqs_enabled = 1; | |
293 | apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n"); | |
294 | max = MAX_PIRQS; | |
295 | if (ints[0] < MAX_PIRQS) | |
296 | max = ints[0]; | |
297 | ||
298 | for (i = 0; i < max; i++) { | |
299 | apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
300 | /* | |
301 | * PIRQs are mapped upside down, usually. | |
302 | */ | |
303 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
304 | } | |
305 | return 1; | |
306 | } | |
307 | ||
308 | __setup("pirq=", ioapic_pirq_setup); | |
309 | ||
310 | /* | |
311 | * Find the IRQ entry number of a certain pin. | |
312 | */ | |
313 | static int find_irq_entry(int apic, int pin, int type) | |
314 | { | |
315 | int i; | |
316 | ||
317 | for (i = 0; i < mp_irq_entries; i++) | |
318 | if (mp_irqs[i].mpc_irqtype == type && | |
319 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || | |
320 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && | |
321 | mp_irqs[i].mpc_dstirq == pin) | |
322 | return i; | |
323 | ||
324 | return -1; | |
325 | } | |
326 | ||
327 | /* | |
328 | * Find the pin to which IRQ[irq] (ISA) is connected | |
329 | */ | |
330 | static int __init find_isa_irq_pin(int irq, int type) | |
331 | { | |
332 | int i; | |
333 | ||
334 | for (i = 0; i < mp_irq_entries; i++) { | |
335 | int lbus = mp_irqs[i].mpc_srcbus; | |
336 | ||
337 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || | |
338 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || | |
339 | mp_bus_id_to_type[lbus] == MP_BUS_MCA) && | |
340 | (mp_irqs[i].mpc_irqtype == type) && | |
341 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
342 | ||
343 | return mp_irqs[i].mpc_dstirq; | |
344 | } | |
345 | return -1; | |
346 | } | |
347 | ||
348 | /* | |
349 | * Find a specific PCI IRQ entry. | |
350 | * Not an __init, possibly needed by modules | |
351 | */ | |
352 | static int pin_2_irq(int idx, int apic, int pin); | |
353 | ||
354 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
355 | { | |
356 | int apic, i, best_guess = -1; | |
357 | ||
358 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
359 | bus, slot, pin); | |
360 | if (mp_bus_id_to_pci_bus[bus] == -1) { | |
361 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
362 | return -1; | |
363 | } | |
364 | for (i = 0; i < mp_irq_entries; i++) { | |
365 | int lbus = mp_irqs[i].mpc_srcbus; | |
366 | ||
367 | for (apic = 0; apic < nr_ioapics; apic++) | |
368 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || | |
369 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) | |
370 | break; | |
371 | ||
372 | if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) && | |
373 | !mp_irqs[i].mpc_irqtype && | |
374 | (bus == lbus) && | |
375 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { | |
376 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); | |
377 | ||
378 | if (!(apic || IO_APIC_IRQ(irq))) | |
379 | continue; | |
380 | ||
381 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) | |
382 | return irq; | |
383 | /* | |
384 | * Use the first all-but-pin matching entry as a | |
385 | * best-guess fuzzy result for broken mptables. | |
386 | */ | |
387 | if (best_guess < 0) | |
388 | best_guess = irq; | |
389 | } | |
390 | } | |
391 | return best_guess; | |
392 | } | |
393 | ||
394 | /* | |
395 | * EISA Edge/Level control register, ELCR | |
396 | */ | |
397 | static int EISA_ELCR(unsigned int irq) | |
398 | { | |
399 | if (irq < 16) { | |
400 | unsigned int port = 0x4d0 + (irq >> 3); | |
401 | return (inb(port) >> (irq & 7)) & 1; | |
402 | } | |
403 | apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq); | |
404 | return 0; | |
405 | } | |
406 | ||
407 | /* EISA interrupts are always polarity zero and can be edge or level | |
408 | * trigger depending on the ELCR value. If an interrupt is listed as | |
409 | * EISA conforming in the MP table, that means its trigger type must | |
410 | * be read in from the ELCR */ | |
411 | ||
412 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) | |
413 | #define default_EISA_polarity(idx) (0) | |
414 | ||
415 | /* ISA interrupts are always polarity zero edge triggered, | |
416 | * when listed as conforming in the MP table. */ | |
417 | ||
418 | #define default_ISA_trigger(idx) (0) | |
419 | #define default_ISA_polarity(idx) (0) | |
420 | ||
421 | /* PCI interrupts are always polarity one level triggered, | |
422 | * when listed as conforming in the MP table. */ | |
423 | ||
424 | #define default_PCI_trigger(idx) (1) | |
425 | #define default_PCI_polarity(idx) (1) | |
426 | ||
427 | /* MCA interrupts are always polarity zero level triggered, | |
428 | * when listed as conforming in the MP table. */ | |
429 | ||
430 | #define default_MCA_trigger(idx) (1) | |
431 | #define default_MCA_polarity(idx) (0) | |
432 | ||
433 | static int __init MPBIOS_polarity(int idx) | |
434 | { | |
435 | int bus = mp_irqs[idx].mpc_srcbus; | |
436 | int polarity; | |
437 | ||
438 | /* | |
439 | * Determine IRQ line polarity (high active or low active): | |
440 | */ | |
441 | switch (mp_irqs[idx].mpc_irqflag & 3) | |
442 | { | |
443 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
444 | { | |
445 | switch (mp_bus_id_to_type[bus]) | |
446 | { | |
447 | case MP_BUS_ISA: /* ISA pin */ | |
448 | { | |
449 | polarity = default_ISA_polarity(idx); | |
450 | break; | |
451 | } | |
452 | case MP_BUS_EISA: /* EISA pin */ | |
453 | { | |
454 | polarity = default_EISA_polarity(idx); | |
455 | break; | |
456 | } | |
457 | case MP_BUS_PCI: /* PCI pin */ | |
458 | { | |
459 | polarity = default_PCI_polarity(idx); | |
460 | break; | |
461 | } | |
462 | case MP_BUS_MCA: /* MCA pin */ | |
463 | { | |
464 | polarity = default_MCA_polarity(idx); | |
465 | break; | |
466 | } | |
467 | default: | |
468 | { | |
469 | printk(KERN_WARNING "broken BIOS!!\n"); | |
470 | polarity = 1; | |
471 | break; | |
472 | } | |
473 | } | |
474 | break; | |
475 | } | |
476 | case 1: /* high active */ | |
477 | { | |
478 | polarity = 0; | |
479 | break; | |
480 | } | |
481 | case 2: /* reserved */ | |
482 | { | |
483 | printk(KERN_WARNING "broken BIOS!!\n"); | |
484 | polarity = 1; | |
485 | break; | |
486 | } | |
487 | case 3: /* low active */ | |
488 | { | |
489 | polarity = 1; | |
490 | break; | |
491 | } | |
492 | default: /* invalid */ | |
493 | { | |
494 | printk(KERN_WARNING "broken BIOS!!\n"); | |
495 | polarity = 1; | |
496 | break; | |
497 | } | |
498 | } | |
499 | return polarity; | |
500 | } | |
501 | ||
502 | static int MPBIOS_trigger(int idx) | |
503 | { | |
504 | int bus = mp_irqs[idx].mpc_srcbus; | |
505 | int trigger; | |
506 | ||
507 | /* | |
508 | * Determine IRQ trigger mode (edge or level sensitive): | |
509 | */ | |
510 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) | |
511 | { | |
512 | case 0: /* conforms, ie. bus-type dependent */ | |
513 | { | |
514 | switch (mp_bus_id_to_type[bus]) | |
515 | { | |
516 | case MP_BUS_ISA: /* ISA pin */ | |
517 | { | |
518 | trigger = default_ISA_trigger(idx); | |
519 | break; | |
520 | } | |
521 | case MP_BUS_EISA: /* EISA pin */ | |
522 | { | |
523 | trigger = default_EISA_trigger(idx); | |
524 | break; | |
525 | } | |
526 | case MP_BUS_PCI: /* PCI pin */ | |
527 | { | |
528 | trigger = default_PCI_trigger(idx); | |
529 | break; | |
530 | } | |
531 | case MP_BUS_MCA: /* MCA pin */ | |
532 | { | |
533 | trigger = default_MCA_trigger(idx); | |
534 | break; | |
535 | } | |
536 | default: | |
537 | { | |
538 | printk(KERN_WARNING "broken BIOS!!\n"); | |
539 | trigger = 1; | |
540 | break; | |
541 | } | |
542 | } | |
543 | break; | |
544 | } | |
545 | case 1: /* edge */ | |
546 | { | |
547 | trigger = 0; | |
548 | break; | |
549 | } | |
550 | case 2: /* reserved */ | |
551 | { | |
552 | printk(KERN_WARNING "broken BIOS!!\n"); | |
553 | trigger = 1; | |
554 | break; | |
555 | } | |
556 | case 3: /* level */ | |
557 | { | |
558 | trigger = 1; | |
559 | break; | |
560 | } | |
561 | default: /* invalid */ | |
562 | { | |
563 | printk(KERN_WARNING "broken BIOS!!\n"); | |
564 | trigger = 0; | |
565 | break; | |
566 | } | |
567 | } | |
568 | return trigger; | |
569 | } | |
570 | ||
571 | static inline int irq_polarity(int idx) | |
572 | { | |
573 | return MPBIOS_polarity(idx); | |
574 | } | |
575 | ||
576 | static inline int irq_trigger(int idx) | |
577 | { | |
578 | return MPBIOS_trigger(idx); | |
579 | } | |
580 | ||
581 | static int pin_2_irq(int idx, int apic, int pin) | |
582 | { | |
583 | int irq, i; | |
584 | int bus = mp_irqs[idx].mpc_srcbus; | |
585 | ||
586 | /* | |
587 | * Debugging check, we are in big trouble if this message pops up! | |
588 | */ | |
589 | if (mp_irqs[idx].mpc_dstirq != pin) | |
590 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); | |
591 | ||
592 | switch (mp_bus_id_to_type[bus]) | |
593 | { | |
594 | case MP_BUS_ISA: /* ISA pin */ | |
595 | case MP_BUS_EISA: | |
596 | case MP_BUS_MCA: | |
597 | { | |
598 | irq = mp_irqs[idx].mpc_srcbusirq; | |
599 | break; | |
600 | } | |
601 | case MP_BUS_PCI: /* PCI pin */ | |
602 | { | |
603 | /* | |
604 | * PCI IRQs are mapped in order | |
605 | */ | |
606 | i = irq = 0; | |
607 | while (i < apic) | |
608 | irq += nr_ioapic_registers[i++]; | |
609 | irq += pin; | |
610 | break; | |
611 | } | |
612 | default: | |
613 | { | |
614 | printk(KERN_ERR "unknown bus type %d.\n",bus); | |
615 | irq = 0; | |
616 | break; | |
617 | } | |
618 | } | |
619 | ||
620 | /* | |
621 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
622 | */ | |
623 | if ((pin >= 16) && (pin <= 23)) { | |
624 | if (pirq_entries[pin-16] != -1) { | |
625 | if (!pirq_entries[pin-16]) { | |
626 | apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16); | |
627 | } else { | |
628 | irq = pirq_entries[pin-16]; | |
629 | apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n", | |
630 | pin-16, irq); | |
631 | } | |
632 | } | |
633 | } | |
634 | return irq; | |
635 | } | |
636 | ||
637 | static inline int IO_APIC_irq_trigger(int irq) | |
638 | { | |
639 | int apic, idx, pin; | |
640 | ||
641 | for (apic = 0; apic < nr_ioapics; apic++) { | |
642 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
643 | idx = find_irq_entry(apic,pin,mp_INT); | |
644 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) | |
645 | return irq_trigger(idx); | |
646 | } | |
647 | } | |
648 | /* | |
649 | * nonexistent IRQs are edge default | |
650 | */ | |
651 | return 0; | |
652 | } | |
653 | ||
654 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
655 | u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 }; | |
656 | ||
657 | int assign_irq_vector(int irq) | |
658 | { | |
659 | static int current_vector = FIRST_DEVICE_VECTOR, offset = 0; | |
660 | ||
661 | BUG_ON(irq >= NR_IRQ_VECTORS); | |
662 | if (IO_APIC_VECTOR(irq) > 0) | |
663 | return IO_APIC_VECTOR(irq); | |
664 | next: | |
665 | current_vector += 8; | |
666 | if (current_vector == IA32_SYSCALL_VECTOR) | |
667 | goto next; | |
668 | ||
669 | if (current_vector >= FIRST_SYSTEM_VECTOR) { | |
670 | offset++; | |
671 | if (!(offset%8)) | |
672 | return -ENOSPC; | |
673 | current_vector = FIRST_DEVICE_VECTOR + offset; | |
674 | } | |
675 | ||
676 | vector_irq[current_vector] = irq; | |
677 | if (irq != AUTO_ASSIGN) | |
678 | IO_APIC_VECTOR(irq) = current_vector; | |
679 | ||
680 | return current_vector; | |
681 | } | |
682 | ||
683 | extern void (*interrupt[NR_IRQS])(void); | |
684 | static struct hw_interrupt_type ioapic_level_type; | |
685 | static struct hw_interrupt_type ioapic_edge_type; | |
686 | ||
687 | #define IOAPIC_AUTO -1 | |
688 | #define IOAPIC_EDGE 0 | |
689 | #define IOAPIC_LEVEL 1 | |
690 | ||
691 | static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger) | |
692 | { | |
693 | if (use_pci_vector() && !platform_legacy_irq(irq)) { | |
694 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || | |
695 | trigger == IOAPIC_LEVEL) | |
696 | irq_desc[vector].handler = &ioapic_level_type; | |
697 | else | |
698 | irq_desc[vector].handler = &ioapic_edge_type; | |
699 | set_intr_gate(vector, interrupt[vector]); | |
700 | } else { | |
701 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || | |
702 | trigger == IOAPIC_LEVEL) | |
703 | irq_desc[irq].handler = &ioapic_level_type; | |
704 | else | |
705 | irq_desc[irq].handler = &ioapic_edge_type; | |
706 | set_intr_gate(vector, interrupt[irq]); | |
707 | } | |
708 | } | |
709 | ||
710 | static void __init setup_IO_APIC_irqs(void) | |
711 | { | |
712 | struct IO_APIC_route_entry entry; | |
713 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
714 | unsigned long flags; | |
715 | ||
716 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
717 | ||
718 | for (apic = 0; apic < nr_ioapics; apic++) { | |
719 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
720 | ||
721 | /* | |
722 | * add it to the IO-APIC irq-routing table: | |
723 | */ | |
724 | memset(&entry,0,sizeof(entry)); | |
725 | ||
726 | entry.delivery_mode = INT_DELIVERY_MODE; | |
727 | entry.dest_mode = INT_DEST_MODE; | |
728 | entry.mask = 0; /* enable IRQ */ | |
729 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
730 | ||
731 | idx = find_irq_entry(apic,pin,mp_INT); | |
732 | if (idx == -1) { | |
733 | if (first_notcon) { | |
734 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin); | |
735 | first_notcon = 0; | |
736 | } else | |
737 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin); | |
738 | continue; | |
739 | } | |
740 | ||
741 | entry.trigger = irq_trigger(idx); | |
742 | entry.polarity = irq_polarity(idx); | |
743 | ||
744 | if (irq_trigger(idx)) { | |
745 | entry.trigger = 1; | |
746 | entry.mask = 1; | |
747 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
748 | } | |
749 | ||
750 | irq = pin_2_irq(idx, apic, pin); | |
751 | add_pin_to_irq(irq, apic, pin); | |
752 | ||
753 | if (!apic && !IO_APIC_IRQ(irq)) | |
754 | continue; | |
755 | ||
756 | if (IO_APIC_IRQ(irq)) { | |
757 | vector = assign_irq_vector(irq); | |
758 | entry.vector = vector; | |
759 | ||
760 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
761 | if (!apic && (irq < 16)) | |
762 | disable_8259A_irq(irq); | |
763 | } | |
764 | spin_lock_irqsave(&ioapic_lock, flags); | |
765 | io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); | |
766 | io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); | |
767 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
768 | } | |
769 | } | |
770 | ||
771 | if (!first_notcon) | |
772 | apic_printk(APIC_VERBOSE," not connected.\n"); | |
773 | } | |
774 | ||
775 | /* | |
776 | * Set up the 8259A-master output pin as broadcast to all | |
777 | * CPUs. | |
778 | */ | |
779 | static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector) | |
780 | { | |
781 | struct IO_APIC_route_entry entry; | |
782 | unsigned long flags; | |
783 | ||
784 | memset(&entry,0,sizeof(entry)); | |
785 | ||
786 | disable_8259A_irq(0); | |
787 | ||
788 | /* mask LVT0 */ | |
789 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
790 | ||
791 | /* | |
792 | * We use logical delivery to get the timer IRQ | |
793 | * to the first CPU. | |
794 | */ | |
795 | entry.dest_mode = INT_DEST_MODE; | |
796 | entry.mask = 0; /* unmask IRQ now */ | |
797 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
798 | entry.delivery_mode = INT_DELIVERY_MODE; | |
799 | entry.polarity = 0; | |
800 | entry.trigger = 0; | |
801 | entry.vector = vector; | |
802 | ||
803 | /* | |
804 | * The timer IRQ doesn't have to know that behind the | |
805 | * scene we have a 8259A-master in AEOI mode ... | |
806 | */ | |
807 | irq_desc[0].handler = &ioapic_edge_type; | |
808 | ||
809 | /* | |
810 | * Add it to the IO-APIC irq-routing table: | |
811 | */ | |
812 | spin_lock_irqsave(&ioapic_lock, flags); | |
813 | io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1)); | |
814 | io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0)); | |
815 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
816 | ||
817 | enable_8259A_irq(0); | |
818 | } | |
819 | ||
820 | void __init UNEXPECTED_IO_APIC(void) | |
821 | { | |
822 | } | |
823 | ||
824 | void __apicdebuginit print_IO_APIC(void) | |
825 | { | |
826 | int apic, i; | |
827 | union IO_APIC_reg_00 reg_00; | |
828 | union IO_APIC_reg_01 reg_01; | |
829 | union IO_APIC_reg_02 reg_02; | |
830 | unsigned long flags; | |
831 | ||
832 | if (apic_verbosity == APIC_QUIET) | |
833 | return; | |
834 | ||
835 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
836 | for (i = 0; i < nr_ioapics; i++) | |
837 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
838 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); | |
839 | ||
840 | /* | |
841 | * We are a bit conservative about what we expect. We have to | |
842 | * know about every hardware change ASAP. | |
843 | */ | |
844 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
845 | ||
846 | for (apic = 0; apic < nr_ioapics; apic++) { | |
847 | ||
848 | spin_lock_irqsave(&ioapic_lock, flags); | |
849 | reg_00.raw = io_apic_read(apic, 0); | |
850 | reg_01.raw = io_apic_read(apic, 1); | |
851 | if (reg_01.bits.version >= 0x10) | |
852 | reg_02.raw = io_apic_read(apic, 2); | |
853 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
854 | ||
855 | printk("\n"); | |
856 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); | |
857 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); | |
858 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
859 | if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2) | |
860 | UNEXPECTED_IO_APIC(); | |
861 | ||
862 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); | |
863 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
864 | if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */ | |
865 | (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */ | |
866 | (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */ | |
867 | (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */ | |
868 | (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */ | |
869 | (reg_01.bits.entries != 0x2E) && | |
870 | (reg_01.bits.entries != 0x3F) && | |
871 | (reg_01.bits.entries != 0x03) | |
872 | ) | |
873 | UNEXPECTED_IO_APIC(); | |
874 | ||
875 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
876 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
877 | if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */ | |
878 | (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */ | |
879 | (reg_01.bits.version != 0x10) && /* oldest IO-APICs */ | |
880 | (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */ | |
881 | (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */ | |
882 | (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */ | |
883 | ) | |
884 | UNEXPECTED_IO_APIC(); | |
885 | if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2) | |
886 | UNEXPECTED_IO_APIC(); | |
887 | ||
888 | if (reg_01.bits.version >= 0x10) { | |
889 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
890 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
891 | if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2) | |
892 | UNEXPECTED_IO_APIC(); | |
893 | } | |
894 | ||
895 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
896 | ||
897 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
898 | " Stat Dest Deli Vect: \n"); | |
899 | ||
900 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
901 | struct IO_APIC_route_entry entry; | |
902 | ||
903 | spin_lock_irqsave(&ioapic_lock, flags); | |
904 | *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); | |
905 | *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); | |
906 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
907 | ||
908 | printk(KERN_DEBUG " %02x %03X %02X ", | |
909 | i, | |
910 | entry.dest.logical.logical_dest, | |
911 | entry.dest.physical.physical_dest | |
912 | ); | |
913 | ||
914 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
915 | entry.mask, | |
916 | entry.trigger, | |
917 | entry.irr, | |
918 | entry.polarity, | |
919 | entry.delivery_status, | |
920 | entry.dest_mode, | |
921 | entry.delivery_mode, | |
922 | entry.vector | |
923 | ); | |
924 | } | |
925 | } | |
926 | if (use_pci_vector()) | |
927 | printk(KERN_INFO "Using vector-based indexing\n"); | |
928 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); | |
929 | for (i = 0; i < NR_IRQS; i++) { | |
930 | struct irq_pin_list *entry = irq_2_pin + i; | |
931 | if (entry->pin < 0) | |
932 | continue; | |
933 | if (use_pci_vector() && !platform_legacy_irq(i)) | |
934 | printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i)); | |
935 | else | |
936 | printk(KERN_DEBUG "IRQ%d ", i); | |
937 | for (;;) { | |
938 | printk("-> %d:%d", entry->apic, entry->pin); | |
939 | if (!entry->next) | |
940 | break; | |
941 | entry = irq_2_pin + entry->next; | |
942 | } | |
943 | printk("\n"); | |
944 | } | |
945 | ||
946 | printk(KERN_INFO ".................................... done.\n"); | |
947 | ||
948 | return; | |
949 | } | |
950 | ||
951 | #if 0 | |
952 | ||
953 | static __apicdebuginit void print_APIC_bitfield (int base) | |
954 | { | |
955 | unsigned int v; | |
956 | int i, j; | |
957 | ||
958 | if (apic_verbosity == APIC_QUIET) | |
959 | return; | |
960 | ||
961 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
962 | for (i = 0; i < 8; i++) { | |
963 | v = apic_read(base + i*0x10); | |
964 | for (j = 0; j < 32; j++) { | |
965 | if (v & (1<<j)) | |
966 | printk("1"); | |
967 | else | |
968 | printk("0"); | |
969 | } | |
970 | printk("\n"); | |
971 | } | |
972 | } | |
973 | ||
974 | void __apicdebuginit print_local_APIC(void * dummy) | |
975 | { | |
976 | unsigned int v, ver, maxlvt; | |
977 | ||
978 | if (apic_verbosity == APIC_QUIET) | |
979 | return; | |
980 | ||
981 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
982 | smp_processor_id(), hard_smp_processor_id()); | |
983 | v = apic_read(APIC_ID); | |
984 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); | |
985 | v = apic_read(APIC_LVR); | |
986 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
987 | ver = GET_APIC_VERSION(v); | |
988 | maxlvt = get_maxlvt(); | |
989 | ||
990 | v = apic_read(APIC_TASKPRI); | |
991 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
992 | ||
993 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
994 | v = apic_read(APIC_ARBPRI); | |
995 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
996 | v & APIC_ARBPRI_MASK); | |
997 | v = apic_read(APIC_PROCPRI); | |
998 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
999 | } | |
1000 | ||
1001 | v = apic_read(APIC_EOI); | |
1002 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1003 | v = apic_read(APIC_RRR); | |
1004 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1005 | v = apic_read(APIC_LDR); | |
1006 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1007 | v = apic_read(APIC_DFR); | |
1008 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1009 | v = apic_read(APIC_SPIV); | |
1010 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1011 | ||
1012 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1013 | print_APIC_bitfield(APIC_ISR); | |
1014 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1015 | print_APIC_bitfield(APIC_TMR); | |
1016 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1017 | print_APIC_bitfield(APIC_IRR); | |
1018 | ||
1019 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1020 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1021 | apic_write(APIC_ESR, 0); | |
1022 | v = apic_read(APIC_ESR); | |
1023 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1024 | } | |
1025 | ||
1026 | v = apic_read(APIC_ICR); | |
1027 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1028 | v = apic_read(APIC_ICR2); | |
1029 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1030 | ||
1031 | v = apic_read(APIC_LVTT); | |
1032 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1033 | ||
1034 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1035 | v = apic_read(APIC_LVTPC); | |
1036 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1037 | } | |
1038 | v = apic_read(APIC_LVT0); | |
1039 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1040 | v = apic_read(APIC_LVT1); | |
1041 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1042 | ||
1043 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1044 | v = apic_read(APIC_LVTERR); | |
1045 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1046 | } | |
1047 | ||
1048 | v = apic_read(APIC_TMICT); | |
1049 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1050 | v = apic_read(APIC_TMCCT); | |
1051 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1052 | v = apic_read(APIC_TDCR); | |
1053 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1054 | printk("\n"); | |
1055 | } | |
1056 | ||
1057 | void print_all_local_APICs (void) | |
1058 | { | |
1059 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1060 | } | |
1061 | ||
1062 | void __apicdebuginit print_PIC(void) | |
1063 | { | |
1064 | extern spinlock_t i8259A_lock; | |
1065 | unsigned int v; | |
1066 | unsigned long flags; | |
1067 | ||
1068 | if (apic_verbosity == APIC_QUIET) | |
1069 | return; | |
1070 | ||
1071 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1072 | ||
1073 | spin_lock_irqsave(&i8259A_lock, flags); | |
1074 | ||
1075 | v = inb(0xa1) << 8 | inb(0x21); | |
1076 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1077 | ||
1078 | v = inb(0xa0) << 8 | inb(0x20); | |
1079 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1080 | ||
1081 | outb(0x0b,0xa0); | |
1082 | outb(0x0b,0x20); | |
1083 | v = inb(0xa0) << 8 | inb(0x20); | |
1084 | outb(0x0a,0xa0); | |
1085 | outb(0x0a,0x20); | |
1086 | ||
1087 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1088 | ||
1089 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1090 | ||
1091 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1092 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1093 | } | |
1094 | ||
1095 | #endif /* 0 */ | |
1096 | ||
1097 | static void __init enable_IO_APIC(void) | |
1098 | { | |
1099 | union IO_APIC_reg_01 reg_01; | |
1100 | int i; | |
1101 | unsigned long flags; | |
1102 | ||
1103 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1104 | irq_2_pin[i].pin = -1; | |
1105 | irq_2_pin[i].next = 0; | |
1106 | } | |
1107 | if (!pirqs_enabled) | |
1108 | for (i = 0; i < MAX_PIRQS; i++) | |
1109 | pirq_entries[i] = -1; | |
1110 | ||
1111 | /* | |
1112 | * The number of IO-APIC IRQ registers (== #pins): | |
1113 | */ | |
1114 | for (i = 0; i < nr_ioapics; i++) { | |
1115 | spin_lock_irqsave(&ioapic_lock, flags); | |
1116 | reg_01.raw = io_apic_read(i, 1); | |
1117 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1118 | nr_ioapic_registers[i] = reg_01.bits.entries+1; | |
1119 | } | |
1120 | ||
1121 | /* | |
1122 | * Do not trust the IO-APIC being empty at bootup | |
1123 | */ | |
1124 | clear_IO_APIC(); | |
1125 | } | |
1126 | ||
1127 | /* | |
1128 | * Not an __init, needed by the reboot code | |
1129 | */ | |
1130 | void disable_IO_APIC(void) | |
1131 | { | |
1132 | /* | |
1133 | * Clear the IO-APIC before rebooting: | |
1134 | */ | |
1135 | clear_IO_APIC(); | |
1136 | ||
1137 | disconnect_bsp_APIC(); | |
1138 | } | |
1139 | ||
1140 | /* | |
1141 | * function to set the IO-APIC physical IDs based on the | |
1142 | * values stored in the MPC table. | |
1143 | * | |
1144 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1145 | */ | |
1146 | ||
1147 | static void __init setup_ioapic_ids_from_mpc (void) | |
1148 | { | |
1149 | union IO_APIC_reg_00 reg_00; | |
1150 | int apic; | |
1151 | int i; | |
1152 | unsigned char old_id; | |
1153 | unsigned long flags; | |
1154 | ||
1155 | /* | |
1156 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1157 | */ | |
1158 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1159 | ||
1160 | /* Read the register 0 value */ | |
1161 | spin_lock_irqsave(&ioapic_lock, flags); | |
1162 | reg_00.raw = io_apic_read(apic, 0); | |
1163 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1164 | ||
1165 | old_id = mp_ioapics[apic].mpc_apicid; | |
1166 | ||
1167 | ||
1168 | printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid); | |
1169 | ||
1170 | ||
1171 | /* | |
1172 | * We need to adjust the IRQ routing table | |
1173 | * if the ID changed. | |
1174 | */ | |
1175 | if (old_id != mp_ioapics[apic].mpc_apicid) | |
1176 | for (i = 0; i < mp_irq_entries; i++) | |
1177 | if (mp_irqs[i].mpc_dstapic == old_id) | |
1178 | mp_irqs[i].mpc_dstapic | |
1179 | = mp_ioapics[apic].mpc_apicid; | |
1180 | ||
1181 | /* | |
1182 | * Read the right value from the MPC table and | |
1183 | * write it into the ID register. | |
1184 | */ | |
1185 | apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...", | |
1186 | mp_ioapics[apic].mpc_apicid); | |
1187 | ||
1188 | reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; | |
1189 | spin_lock_irqsave(&ioapic_lock, flags); | |
1190 | io_apic_write(apic, 0, reg_00.raw); | |
1191 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1192 | ||
1193 | /* | |
1194 | * Sanity check | |
1195 | */ | |
1196 | spin_lock_irqsave(&ioapic_lock, flags); | |
1197 | reg_00.raw = io_apic_read(apic, 0); | |
1198 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1199 | if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) | |
1200 | printk("could not set ID!\n"); | |
1201 | else | |
1202 | apic_printk(APIC_VERBOSE," ok.\n"); | |
1203 | } | |
1204 | } | |
1205 | ||
1206 | /* | |
1207 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1208 | * about the timer IRQ. We do the following to work around the situation: | |
1209 | * | |
1210 | * - timer IRQ defaults to IO-APIC IRQ | |
1211 | * - if this function detects that timer IRQs are defunct, then we fall | |
1212 | * back to ISA timer IRQs | |
1213 | */ | |
1214 | static int __init timer_irq_works(void) | |
1215 | { | |
1216 | unsigned long t1 = jiffies; | |
1217 | ||
1218 | local_irq_enable(); | |
1219 | /* Let ten ticks pass... */ | |
1220 | mdelay((10 * 1000) / HZ); | |
1221 | ||
1222 | /* | |
1223 | * Expect a few ticks at least, to be sure some possible | |
1224 | * glue logic does not lock up after one or two first | |
1225 | * ticks in a non-ExtINT mode. Also the local APIC | |
1226 | * might have cached one ExtINT interrupt. Finally, at | |
1227 | * least one tick may be lost due to delays. | |
1228 | */ | |
1229 | ||
1230 | /* jiffies wrap? */ | |
1231 | if (jiffies - t1 > 4) | |
1232 | return 1; | |
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | /* | |
1237 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1238 | * number of pending IRQ events unhandled. These cases are very rare, | |
1239 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1240 | * better to do it this way as thus we do not have to be aware of | |
1241 | * 'pending' interrupts in the IRQ path, except at this point. | |
1242 | */ | |
1243 | /* | |
1244 | * Edge triggered needs to resend any interrupt | |
1245 | * that was delayed but this is now handled in the device | |
1246 | * independent code. | |
1247 | */ | |
1248 | ||
1249 | /* | |
1250 | * Starting up a edge-triggered IO-APIC interrupt is | |
1251 | * nasty - we need to make sure that we get the edge. | |
1252 | * If it is already asserted for some reason, we need | |
1253 | * return 1 to indicate that is was pending. | |
1254 | * | |
1255 | * This is not complete - we should be able to fake | |
1256 | * an edge even if it isn't on the 8259A... | |
1257 | */ | |
1258 | ||
1259 | static unsigned int startup_edge_ioapic_irq(unsigned int irq) | |
1260 | { | |
1261 | int was_pending = 0; | |
1262 | unsigned long flags; | |
1263 | ||
1264 | spin_lock_irqsave(&ioapic_lock, flags); | |
1265 | if (irq < 16) { | |
1266 | disable_8259A_irq(irq); | |
1267 | if (i8259A_irq_pending(irq)) | |
1268 | was_pending = 1; | |
1269 | } | |
1270 | __unmask_IO_APIC_irq(irq); | |
1271 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1272 | ||
1273 | return was_pending; | |
1274 | } | |
1275 | ||
1276 | /* | |
1277 | * Once we have recorded IRQ_PENDING already, we can mask the | |
1278 | * interrupt for real. This prevents IRQ storms from unhandled | |
1279 | * devices. | |
1280 | */ | |
1281 | static void ack_edge_ioapic_irq(unsigned int irq) | |
1282 | { | |
1283 | if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED)) | |
1284 | == (IRQ_PENDING | IRQ_DISABLED)) | |
1285 | mask_IO_APIC_irq(irq); | |
1286 | ack_APIC_irq(); | |
1287 | } | |
1288 | ||
1289 | /* | |
1290 | * Level triggered interrupts can just be masked, | |
1291 | * and shutting down and starting up the interrupt | |
1292 | * is the same as enabling and disabling them -- except | |
1293 | * with a startup need to return a "was pending" value. | |
1294 | * | |
1295 | * Level triggered interrupts are special because we | |
1296 | * do not touch any IO-APIC register while handling | |
1297 | * them. We ack the APIC in the end-IRQ handler, not | |
1298 | * in the start-IRQ-handler. Protection against reentrance | |
1299 | * from the same interrupt is still provided, both by the | |
1300 | * generic IRQ layer and by the fact that an unacked local | |
1301 | * APIC does not accept IRQs. | |
1302 | */ | |
1303 | static unsigned int startup_level_ioapic_irq (unsigned int irq) | |
1304 | { | |
1305 | unmask_IO_APIC_irq(irq); | |
1306 | ||
1307 | return 0; /* don't check for pending */ | |
1308 | } | |
1309 | ||
1310 | static void end_level_ioapic_irq (unsigned int irq) | |
1311 | { | |
1312 | ack_APIC_irq(); | |
1313 | } | |
1314 | ||
1315 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
1316 | { | |
1317 | unsigned long flags; | |
1318 | unsigned int dest; | |
1319 | ||
1320 | dest = cpu_mask_to_apicid(mask); | |
1321 | ||
1322 | /* | |
1323 | * Only the high 8 bits are valid. | |
1324 | */ | |
1325 | dest = SET_APIC_LOGICAL_ID(dest); | |
1326 | ||
1327 | spin_lock_irqsave(&ioapic_lock, flags); | |
1328 | __DO_ACTION(1, = dest, ) | |
1329 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1330 | } | |
1331 | ||
1332 | #ifdef CONFIG_PCI_MSI | |
1333 | static unsigned int startup_edge_ioapic_vector(unsigned int vector) | |
1334 | { | |
1335 | int irq = vector_to_irq(vector); | |
1336 | ||
1337 | return startup_edge_ioapic_irq(irq); | |
1338 | } | |
1339 | ||
1340 | static void ack_edge_ioapic_vector(unsigned int vector) | |
1341 | { | |
1342 | int irq = vector_to_irq(vector); | |
1343 | ||
1344 | ack_edge_ioapic_irq(irq); | |
1345 | } | |
1346 | ||
1347 | static unsigned int startup_level_ioapic_vector (unsigned int vector) | |
1348 | { | |
1349 | int irq = vector_to_irq(vector); | |
1350 | ||
1351 | return startup_level_ioapic_irq (irq); | |
1352 | } | |
1353 | ||
1354 | static void end_level_ioapic_vector (unsigned int vector) | |
1355 | { | |
1356 | int irq = vector_to_irq(vector); | |
1357 | ||
1358 | end_level_ioapic_irq(irq); | |
1359 | } | |
1360 | ||
1361 | static void mask_IO_APIC_vector (unsigned int vector) | |
1362 | { | |
1363 | int irq = vector_to_irq(vector); | |
1364 | ||
1365 | mask_IO_APIC_irq(irq); | |
1366 | } | |
1367 | ||
1368 | static void unmask_IO_APIC_vector (unsigned int vector) | |
1369 | { | |
1370 | int irq = vector_to_irq(vector); | |
1371 | ||
1372 | unmask_IO_APIC_irq(irq); | |
1373 | } | |
1374 | ||
1375 | static void set_ioapic_affinity_vector (unsigned int vector, | |
1376 | cpumask_t cpu_mask) | |
1377 | { | |
1378 | int irq = vector_to_irq(vector); | |
1379 | ||
1380 | set_ioapic_affinity_irq(irq, cpu_mask); | |
1381 | } | |
1382 | #endif | |
1383 | ||
1384 | /* | |
1385 | * Level and edge triggered IO-APIC interrupts need different handling, | |
1386 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
1387 | * handled with the level-triggered descriptor, but that one has slightly | |
1388 | * more overhead. Level-triggered interrupts cannot be handled with the | |
1389 | * edge-triggered handler, without risking IRQ storms and other ugly | |
1390 | * races. | |
1391 | */ | |
1392 | ||
1393 | static struct hw_interrupt_type ioapic_edge_type = { | |
1394 | .typename = "IO-APIC-edge", | |
1395 | .startup = startup_edge_ioapic, | |
1396 | .shutdown = shutdown_edge_ioapic, | |
1397 | .enable = enable_edge_ioapic, | |
1398 | .disable = disable_edge_ioapic, | |
1399 | .ack = ack_edge_ioapic, | |
1400 | .end = end_edge_ioapic, | |
1401 | .set_affinity = set_ioapic_affinity, | |
1402 | }; | |
1403 | ||
1404 | static struct hw_interrupt_type ioapic_level_type = { | |
1405 | .typename = "IO-APIC-level", | |
1406 | .startup = startup_level_ioapic, | |
1407 | .shutdown = shutdown_level_ioapic, | |
1408 | .enable = enable_level_ioapic, | |
1409 | .disable = disable_level_ioapic, | |
1410 | .ack = mask_and_ack_level_ioapic, | |
1411 | .end = end_level_ioapic, | |
1412 | .set_affinity = set_ioapic_affinity, | |
1413 | }; | |
1414 | ||
1415 | static inline void init_IO_APIC_traps(void) | |
1416 | { | |
1417 | int irq; | |
1418 | ||
1419 | /* | |
1420 | * NOTE! The local APIC isn't very good at handling | |
1421 | * multiple interrupts at the same interrupt level. | |
1422 | * As the interrupt level is determined by taking the | |
1423 | * vector number and shifting that right by 4, we | |
1424 | * want to spread these out a bit so that they don't | |
1425 | * all fall in the same interrupt level. | |
1426 | * | |
1427 | * Also, we've got to be careful not to trash gate | |
1428 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1429 | */ | |
1430 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
1431 | int tmp = irq; | |
1432 | if (use_pci_vector()) { | |
1433 | if (!platform_legacy_irq(tmp)) | |
1434 | if ((tmp = vector_to_irq(tmp)) == -1) | |
1435 | continue; | |
1436 | } | |
1437 | if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) { | |
1438 | /* | |
1439 | * Hmm.. We don't have an entry for this, | |
1440 | * so default to an old-fashioned 8259 | |
1441 | * interrupt if we can.. | |
1442 | */ | |
1443 | if (irq < 16) | |
1444 | make_8259A_irq(irq); | |
1445 | else | |
1446 | /* Strange. Oh, well.. */ | |
1447 | irq_desc[irq].handler = &no_irq_type; | |
1448 | } | |
1449 | } | |
1450 | } | |
1451 | ||
1452 | static void enable_lapic_irq (unsigned int irq) | |
1453 | { | |
1454 | unsigned long v; | |
1455 | ||
1456 | v = apic_read(APIC_LVT0); | |
1457 | apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); | |
1458 | } | |
1459 | ||
1460 | static void disable_lapic_irq (unsigned int irq) | |
1461 | { | |
1462 | unsigned long v; | |
1463 | ||
1464 | v = apic_read(APIC_LVT0); | |
1465 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
1466 | } | |
1467 | ||
1468 | static void ack_lapic_irq (unsigned int irq) | |
1469 | { | |
1470 | ack_APIC_irq(); | |
1471 | } | |
1472 | ||
1473 | static void end_lapic_irq (unsigned int i) { /* nothing */ } | |
1474 | ||
1475 | static struct hw_interrupt_type lapic_irq_type = { | |
1476 | .typename = "local-APIC-edge", | |
1477 | .startup = NULL, /* startup_irq() not used for IRQ0 */ | |
1478 | .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */ | |
1479 | .enable = enable_lapic_irq, | |
1480 | .disable = disable_lapic_irq, | |
1481 | .ack = ack_lapic_irq, | |
1482 | .end = end_lapic_irq, | |
1483 | }; | |
1484 | ||
1485 | static void setup_nmi (void) | |
1486 | { | |
1487 | /* | |
1488 | * Dirty trick to enable the NMI watchdog ... | |
1489 | * We put the 8259A master into AEOI mode and | |
1490 | * unmask on all local APICs LVT0 as NMI. | |
1491 | * | |
1492 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
1493 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
1494 | * the NMI handler or the timer interrupt. | |
1495 | */ | |
1496 | printk(KERN_INFO "activating NMI Watchdog ..."); | |
1497 | ||
1498 | enable_NMI_through_LVT0(NULL); | |
1499 | ||
1500 | printk(" done.\n"); | |
1501 | } | |
1502 | ||
1503 | /* | |
1504 | * This looks a bit hackish but it's about the only one way of sending | |
1505 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
1506 | * not support the ExtINT mode, unfortunately. We need to send these | |
1507 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
1508 | * 8259A interrupt line asserted until INTA. --macro | |
1509 | */ | |
1510 | static inline void unlock_ExtINT_logic(void) | |
1511 | { | |
1512 | int pin, i; | |
1513 | struct IO_APIC_route_entry entry0, entry1; | |
1514 | unsigned char save_control, save_freq_select; | |
1515 | unsigned long flags; | |
1516 | ||
1517 | pin = find_isa_irq_pin(8, mp_INT); | |
1518 | if (pin == -1) | |
1519 | return; | |
1520 | ||
1521 | spin_lock_irqsave(&ioapic_lock, flags); | |
1522 | *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin); | |
1523 | *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin); | |
1524 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1525 | clear_IO_APIC_pin(0, pin); | |
1526 | ||
1527 | memset(&entry1, 0, sizeof(entry1)); | |
1528 | ||
1529 | entry1.dest_mode = 0; /* physical delivery */ | |
1530 | entry1.mask = 0; /* unmask IRQ now */ | |
1531 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
1532 | entry1.delivery_mode = dest_ExtINT; | |
1533 | entry1.polarity = entry0.polarity; | |
1534 | entry1.trigger = 0; | |
1535 | entry1.vector = 0; | |
1536 | ||
1537 | spin_lock_irqsave(&ioapic_lock, flags); | |
1538 | io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1)); | |
1539 | io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0)); | |
1540 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1541 | ||
1542 | save_control = CMOS_READ(RTC_CONTROL); | |
1543 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
1544 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
1545 | RTC_FREQ_SELECT); | |
1546 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
1547 | ||
1548 | i = 100; | |
1549 | while (i-- > 0) { | |
1550 | mdelay(10); | |
1551 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
1552 | i -= 10; | |
1553 | } | |
1554 | ||
1555 | CMOS_WRITE(save_control, RTC_CONTROL); | |
1556 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
1557 | clear_IO_APIC_pin(0, pin); | |
1558 | ||
1559 | spin_lock_irqsave(&ioapic_lock, flags); | |
1560 | io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1)); | |
1561 | io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0)); | |
1562 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1563 | } | |
1564 | ||
1565 | /* | |
1566 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
1567 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
1568 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
1569 | * fanatically on his truly buggy board. | |
1570 | */ | |
1571 | static inline void check_timer(void) | |
1572 | { | |
1573 | int pin1, pin2; | |
1574 | int vector; | |
1575 | ||
1576 | /* | |
1577 | * get/set the timer IRQ vector: | |
1578 | */ | |
1579 | disable_8259A_irq(0); | |
1580 | vector = assign_irq_vector(0); | |
1581 | set_intr_gate(vector, interrupt[0]); | |
1582 | ||
1583 | /* | |
1584 | * Subtle, code in do_timer_interrupt() expects an AEOI | |
1585 | * mode for the 8259A whenever interrupts are routed | |
1586 | * through I/O APICs. Also IRQ0 has to be enabled in | |
1587 | * the 8259A which implies the virtual wire has to be | |
1588 | * disabled in the local APIC. | |
1589 | */ | |
1590 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
1591 | init_8259A(1); | |
1592 | enable_8259A_irq(0); | |
1593 | ||
1594 | pin1 = find_isa_irq_pin(0, mp_INT); | |
1595 | pin2 = find_isa_irq_pin(0, mp_ExtINT); | |
1596 | ||
1597 | apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2); | |
1598 | ||
1599 | if (pin1 != -1) { | |
1600 | /* | |
1601 | * Ok, does IRQ0 through the IOAPIC work? | |
1602 | */ | |
1603 | unmask_IO_APIC_irq(0); | |
1604 | if (timer_irq_works()) { | |
1605 | nmi_watchdog_default(); | |
1606 | if (nmi_watchdog == NMI_IO_APIC) { | |
1607 | disable_8259A_irq(0); | |
1608 | setup_nmi(); | |
1609 | enable_8259A_irq(0); | |
1da177e4 LT |
1610 | } |
1611 | return; | |
1612 | } | |
1613 | clear_IO_APIC_pin(0, pin1); | |
1614 | apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n"); | |
1615 | } | |
1616 | ||
1617 | apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); | |
1618 | if (pin2 != -1) { | |
1619 | apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2); | |
1620 | /* | |
1621 | * legacy devices should be connected to IO APIC #0 | |
1622 | */ | |
1623 | setup_ExtINT_IRQ0_pin(pin2, vector); | |
1624 | if (timer_irq_works()) { | |
1625 | printk("works.\n"); | |
1626 | nmi_watchdog_default(); | |
1627 | if (nmi_watchdog == NMI_IO_APIC) { | |
1628 | setup_nmi(); | |
1da177e4 LT |
1629 | } |
1630 | return; | |
1631 | } | |
1632 | /* | |
1633 | * Cleanup, just in case ... | |
1634 | */ | |
1635 | clear_IO_APIC_pin(0, pin2); | |
1636 | } | |
1637 | printk(" failed.\n"); | |
1638 | ||
1639 | if (nmi_watchdog) { | |
1640 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); | |
1641 | nmi_watchdog = 0; | |
1642 | } | |
1643 | ||
1644 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
1645 | ||
1646 | disable_8259A_irq(0); | |
1647 | irq_desc[0].handler = &lapic_irq_type; | |
1648 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ | |
1649 | enable_8259A_irq(0); | |
1650 | ||
1651 | if (timer_irq_works()) { | |
1652 | apic_printk(APIC_QUIET, " works.\n"); | |
1653 | return; | |
1654 | } | |
1655 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); | |
1656 | apic_printk(APIC_VERBOSE," failed.\n"); | |
1657 | ||
1658 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
1659 | ||
1660 | init_8259A(0); | |
1661 | make_8259A_irq(0); | |
1662 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
1663 | ||
1664 | unlock_ExtINT_logic(); | |
1665 | ||
1666 | if (timer_irq_works()) { | |
1667 | apic_printk(APIC_VERBOSE," works.\n"); | |
1668 | return; | |
1669 | } | |
1670 | apic_printk(APIC_VERBOSE," failed :(.\n"); | |
1671 | panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n"); | |
1672 | } | |
1673 | ||
1674 | /* | |
1675 | * | |
1676 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. | |
1677 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. | |
1678 | * Linux doesn't really care, as it's not actually used | |
1679 | * for any interrupt handling anyway. | |
1680 | */ | |
1681 | #define PIC_IRQS (1<<2) | |
1682 | ||
1683 | void __init setup_IO_APIC(void) | |
1684 | { | |
1685 | enable_IO_APIC(); | |
1686 | ||
1687 | if (acpi_ioapic) | |
1688 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ | |
1689 | else | |
1690 | io_apic_irqs = ~PIC_IRQS; | |
1691 | ||
1692 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); | |
1693 | ||
1694 | /* | |
1695 | * Set up the IO-APIC IRQ routing table. | |
1696 | */ | |
1697 | if (!acpi_ioapic) | |
1698 | setup_ioapic_ids_from_mpc(); | |
1699 | sync_Arb_IDs(); | |
1700 | setup_IO_APIC_irqs(); | |
1701 | init_IO_APIC_traps(); | |
1702 | check_timer(); | |
1703 | if (!acpi_ioapic) | |
1704 | print_IO_APIC(); | |
1705 | } | |
1706 | ||
1707 | struct sysfs_ioapic_data { | |
1708 | struct sys_device dev; | |
1709 | struct IO_APIC_route_entry entry[0]; | |
1710 | }; | |
1711 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
1712 | ||
0b9c33a7 | 1713 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
1714 | { |
1715 | struct IO_APIC_route_entry *entry; | |
1716 | struct sysfs_ioapic_data *data; | |
1717 | unsigned long flags; | |
1718 | int i; | |
1719 | ||
1720 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
1721 | entry = data->entry; | |
1722 | spin_lock_irqsave(&ioapic_lock, flags); | |
1723 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) { | |
1724 | *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i); | |
1725 | *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i); | |
1726 | } | |
1727 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1728 | ||
1729 | return 0; | |
1730 | } | |
1731 | ||
1732 | static int ioapic_resume(struct sys_device *dev) | |
1733 | { | |
1734 | struct IO_APIC_route_entry *entry; | |
1735 | struct sysfs_ioapic_data *data; | |
1736 | unsigned long flags; | |
1737 | union IO_APIC_reg_00 reg_00; | |
1738 | int i; | |
1739 | ||
1740 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
1741 | entry = data->entry; | |
1742 | ||
1743 | spin_lock_irqsave(&ioapic_lock, flags); | |
1744 | reg_00.raw = io_apic_read(dev->id, 0); | |
1745 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { | |
1746 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; | |
1747 | io_apic_write(dev->id, 0, reg_00.raw); | |
1748 | } | |
1749 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) { | |
1750 | io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1)); | |
1751 | io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0)); | |
1752 | } | |
1753 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1754 | ||
1755 | return 0; | |
1756 | } | |
1757 | ||
1758 | static struct sysdev_class ioapic_sysdev_class = { | |
1759 | set_kset_name("ioapic"), | |
1760 | .suspend = ioapic_suspend, | |
1761 | .resume = ioapic_resume, | |
1762 | }; | |
1763 | ||
1764 | static int __init ioapic_init_sysfs(void) | |
1765 | { | |
1766 | struct sys_device * dev; | |
1767 | int i, size, error = 0; | |
1768 | ||
1769 | error = sysdev_class_register(&ioapic_sysdev_class); | |
1770 | if (error) | |
1771 | return error; | |
1772 | ||
1773 | for (i = 0; i < nr_ioapics; i++ ) { | |
1774 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1775 | * sizeof(struct IO_APIC_route_entry); | |
1776 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); | |
1777 | if (!mp_ioapic_data[i]) { | |
1778 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
1779 | continue; | |
1780 | } | |
1781 | memset(mp_ioapic_data[i], 0, size); | |
1782 | dev = &mp_ioapic_data[i]->dev; | |
1783 | dev->id = i; | |
1784 | dev->cls = &ioapic_sysdev_class; | |
1785 | error = sysdev_register(dev); | |
1786 | if (error) { | |
1787 | kfree(mp_ioapic_data[i]); | |
1788 | mp_ioapic_data[i] = NULL; | |
1789 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
1790 | continue; | |
1791 | } | |
1792 | } | |
1793 | ||
1794 | return 0; | |
1795 | } | |
1796 | ||
1797 | device_initcall(ioapic_init_sysfs); | |
1798 | ||
1799 | /* -------------------------------------------------------------------------- | |
1800 | ACPI-based IOAPIC Configuration | |
1801 | -------------------------------------------------------------------------- */ | |
1802 | ||
1803 | #ifdef CONFIG_ACPI_BOOT | |
1804 | ||
1805 | #define IO_APIC_MAX_ID 0xFE | |
1806 | ||
1da177e4 LT |
1807 | int __init io_apic_get_version (int ioapic) |
1808 | { | |
1809 | union IO_APIC_reg_01 reg_01; | |
1810 | unsigned long flags; | |
1811 | ||
1812 | spin_lock_irqsave(&ioapic_lock, flags); | |
1813 | reg_01.raw = io_apic_read(ioapic, 1); | |
1814 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1815 | ||
1816 | return reg_01.bits.version; | |
1817 | } | |
1818 | ||
1819 | ||
1820 | int __init io_apic_get_redir_entries (int ioapic) | |
1821 | { | |
1822 | union IO_APIC_reg_01 reg_01; | |
1823 | unsigned long flags; | |
1824 | ||
1825 | spin_lock_irqsave(&ioapic_lock, flags); | |
1826 | reg_01.raw = io_apic_read(ioapic, 1); | |
1827 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1828 | ||
1829 | return reg_01.bits.entries; | |
1830 | } | |
1831 | ||
1832 | ||
1833 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low) | |
1834 | { | |
1835 | struct IO_APIC_route_entry entry; | |
1836 | unsigned long flags; | |
1837 | ||
1838 | if (!IO_APIC_IRQ(irq)) { | |
1839 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
1840 | ioapic); | |
1841 | return -EINVAL; | |
1842 | } | |
1843 | ||
1844 | /* | |
1845 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
1846 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
1847 | * corresponding device driver registers for this IRQ. | |
1848 | */ | |
1849 | ||
1850 | memset(&entry,0,sizeof(entry)); | |
1851 | ||
1852 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1853 | entry.dest_mode = INT_DEST_MODE; | |
1854 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
1855 | entry.trigger = edge_level; | |
1856 | entry.polarity = active_high_low; | |
1857 | entry.mask = 1; /* Disabled (masked) */ | |
1858 | ||
1859 | /* | |
1860 | * IRQs < 16 are already in the irq_2_pin[] map | |
1861 | */ | |
1862 | if (irq >= 16) | |
1863 | add_pin_to_irq(irq, ioapic, pin); | |
1864 | ||
1865 | entry.vector = assign_irq_vector(irq); | |
1866 | ||
1867 | apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> " | |
1868 | "IRQ %d Mode:%i Active:%i)\n", ioapic, | |
1869 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, | |
1870 | edge_level, active_high_low); | |
1871 | ||
1872 | ioapic_register_intr(irq, entry.vector, edge_level); | |
1873 | ||
1874 | if (!ioapic && (irq < 16)) | |
1875 | disable_8259A_irq(irq); | |
1876 | ||
1877 | spin_lock_irqsave(&ioapic_lock, flags); | |
1878 | io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1)); | |
1879 | io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0)); | |
1880 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1881 | ||
1882 | return 0; | |
1883 | } | |
1884 | ||
1885 | #endif /*CONFIG_ACPI_BOOT*/ | |
1886 | ||
1887 | ||
1888 | /* | |
1889 | * This function currently is only a helper for the i386 smp boot process where | |
1890 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
1891 | * so mask in all cases should simply be TARGET_CPUS | |
1892 | */ | |
1893 | void __init setup_ioapic_dest(void) | |
1894 | { | |
1895 | int pin, ioapic, irq, irq_entry; | |
1896 | ||
1897 | if (skip_ioapic_setup == 1) | |
1898 | return; | |
1899 | ||
1900 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
1901 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
1902 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
1903 | if (irq_entry == -1) | |
1904 | continue; | |
1905 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
1906 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
1907 | } | |
1908 | ||
1909 | } | |
1910 | } |