[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86_64 / kernel / apic.c

/*
 *	Local APIC handling, local APIC timers
 *
 *	(c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/smp_lock.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/module.h>

#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/mpspec.h>
#include <asm/pgalloc.h>
#include <asm/mach_apic.h>
#include <asm/nmi.h>
#include <asm/idle.h>
#include <asm/proto.h>
#include <asm/timex.h>
#include <asm/apic.h>

int apic_mapped;
int apic_verbosity;
int apic_runs_main_timer;
int apic_calibrate_pmtmr __initdata;

int disable_apic_timer __initdata;

/*
 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
 * IPIs in place of local APIC timers
 */
static cpumask_t timer_interrupt_broadcast_ipi_mask;

/* Using APIC to generate smp_local_timer_interrupt? */
int using_apic_timer __read_mostly = 0;

static void apic_pm_activate(void);

void enable_NMI_through_LVT0 (void * dummy)
{
	unsigned int v;
	
	v = APIC_DM_NMI;                        /* unmask and set to NMI */
	apic_write(APIC_LVT0, v);
}

int get_maxlvt(void)
{
	unsigned int v, maxlvt;

	v = apic_read(APIC_LVR);
	maxlvt = GET_APIC_MAXLVT(v);
	return maxlvt;
}

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk("unexpected IRQ trap at vector %02x\n", irq);
	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
  	 * But don't ack when the APIC is disabled. -AK
	 */
	if (!disable_apic)
		ack_APIC_irq();
}

void clear_local_APIC(void)
{
	int maxlvt;
	unsigned int v;

	maxlvt = get_maxlvt();

	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
	v = GET_APIC_VERSION(apic_read(APIC_LVR));
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
}

void disconnect_bsp_APIC(int virt_wire_setup)
{
	/* Go back to Virtual Wire compatibility mode */
	unsigned long value;

	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);

	if (!virt_wire_setup) {
		/* For LVT0 make it edge triggered, active high, external and enabled */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}

	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
}

void disable_local_APIC(void)
{
	unsigned int value;

	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
	reg0 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	reg1 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
	if (reg1 != (reg0 ^ APIC_ID_MASK))
		return 0;

	/*
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

void __init sync_Arb_IDs(void)
{
	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
	if (ver >= 0x14)	/* P4 or higher */
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
	apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
				| APIC_DM_INIT);
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
	unsigned int value;

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	value = apic_read(APIC_LVR);

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= APIC_SPIV_FOCUS_DISABLED;
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up the virtual wire mode.
	 */
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
	value = APIC_DM_NMI;
	apic_write(APIC_LVT1, value);
}

void __cpuinit setup_local_APIC (void)
{
	unsigned int value, maxlvt;
	int i, j;

	value = apic_read(APIC_LVR);

	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);

	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
	if (!apic_id_registered())
		BUG();

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
	init_apic_ldr();

	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
	apic_write(APIC_TASKPRI, value);

	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}

	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

	/* We always use processor focus */

	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
	if (!smp_processor_id() && !value) {
		value = APIC_DM_EXTINT;
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	}
	apic_write(APIC_LVT0, value);

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
	apic_write(APIC_LVT1, value);

	{
		unsigned oldvalue;
		maxlvt = get_maxlvt();
		oldvalue = apic_read(APIC_ESR);
		value = ERROR_APIC_VECTOR;      // enables sending errors
		apic_write(APIC_LVTERR, value);
		/*
		 * spec says clear errors after enabling vector.
		 */
		if (maxlvt > 3)
			apic_write(APIC_ESR, 0);
		value = apic_read(APIC_ESR);
		if (value != oldvalue)
			apic_printk(APIC_VERBOSE,
			"ESR value after enabling vector: %08x, after %08x\n",
			oldvalue, value);
	}

	nmi_watchdog_default();
	setup_apic_nmi_watchdog(NULL);
	apic_pm_activate();
}

#ifdef CONFIG_PM

static struct {
	/* 'active' is true if the local APIC was enabled by us and
	   not the BIOS; this signifies that we are also responsible
	   for disabling it before entering apm/acpi suspend */
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;

	if (!apic_pm_state.active)
		return 0;

	apic_pm_state.apic_id = apic_read(APIC_ID);
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
	apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Local APIC handling, local APIC timers
	3	*
	4	* (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
	5	*
	6	* Fixes
	7	* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
	8	* thanks to Eric Gilmore
	9	* and Rolf G. Tews
	10	* for testing these extensively.
	11	* Maciej W. Rozycki : Various updates and fixes.
	12	* Mikael Pettersson : Power Management for UP-APIC.
	13	* Pavel Machek and
	14	* Mikael Pettersson : PM converted to driver model.
	15	*/
	16
1da177e4 LT	17	#include <linux/init.h>
	18
	19	#include <linux/mm.h>
1da177e4 LT	20	#include <linux/delay.h>
	21	#include <linux/bootmem.h>
	22	#include <linux/smp_lock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/mc146818rtc.h>
	25	#include <linux/kernel_stat.h>
	26	#include <linux/sysdev.h>
d25bf7e5	27	#include <linux/module.h>
1da177e4 LT	28
	29	#include <asm/atomic.h>
	30	#include <asm/smp.h>
	31	#include <asm/mtrr.h>
	32	#include <asm/mpspec.h>
	33	#include <asm/pgalloc.h>
	34	#include <asm/mach_apic.h>
75152114	35	#include <asm/nmi.h>
95833c83	36	#include <asm/idle.h>
73dea47f AK	37	#include <asm/proto.h>
73dea47f AK	38	#include <asm/timex.h>
2c8c0e6b	39	#include <asm/apic.h>
1da177e4	40
b7f5e3c7	41	int apic_mapped;
1da177e4	42	int apic_verbosity;
73dea47f	43	int apic_runs_main_timer;
0c3749c4	44	int apic_calibrate_pmtmr __initdata;
1da177e4 LT	45
	46	int disable_apic_timer __initdata;
	47
d25bf7e5 VP	48	/*
	49	* cpu_mask that denotes the CPUs that needs timer interrupt coming in as
	50	* IPIs in place of local APIC timers
	51	*/
	52	static cpumask_t timer_interrupt_broadcast_ipi_mask;
	53
1da177e4	54	/* Using APIC to generate smp_local_timer_interrupt? */
acae9d32	55	int using_apic_timer __read_mostly = 0;
1da177e4	56
1da177e4 LT	57	static void apic_pm_activate(void);
	58
	59	void enable_NMI_through_LVT0 (void * dummy)
	60	{
11a8e778	61	unsigned int v;
1da177e4	62
1da177e4	63	v = APIC_DM_NMI; /* unmask and set to NMI */
11a8e778	64	apic_write(APIC_LVT0, v);
1da177e4 LT	65	}
	66
	67	int get_maxlvt(void)
	68	{
11a8e778	69	unsigned int v, maxlvt;
1da177e4 LT	70
1da177e4 LT	71	v = apic_read(APIC_LVR);
1da177e4 LT	72	maxlvt = GET_APIC_MAXLVT(v);
	73	return maxlvt;
	74	}
	75
3777a959 AK	76	/*
	77	* 'what should we do if we get a hw irq event on an illegal vector'.
	78	* each architecture has to answer this themselves.
	79	*/
	80	void ack_bad_irq(unsigned int irq)
	81	{
	82	printk("unexpected IRQ trap at vector %02x\n", irq);
	83	/*
	84	* Currently unexpected vectors happen only on SMP and APIC.
	85	* We _must_ ack these because every local APIC has only N
	86	* irq slots per priority level, and a 'hanging, unacked' IRQ
	87	* holds up an irq slot - in excessive cases (when multiple
	88	* unexpected vectors occur) that might lock up the APIC
	89	* completely.
	90	* But don't ack when the APIC is disabled. -AK
	91	*/
	92	if (!disable_apic)
	93	ack_APIC_irq();
	94	}
	95
1da177e4 LT	96	void clear_local_APIC(void)
	97	{
	98	int maxlvt;
	99	unsigned int v;
	100
	101	maxlvt = get_maxlvt();
	102
	103	/*
704fc59e	104	* Masking an LVT entry can trigger a local APIC error
1da177e4 LT	105	* if the vector is zero. Mask LVTERR first to prevent this.
	106	*/
	107	if (maxlvt >= 3) {
	108	v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
11a8e778	109	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
1da177e4 LT	110	}
	111	/*
	112	* Careful: we have to set masks only first to deassert
	113	* any level-triggered sources.
	114	*/
	115	v = apic_read(APIC_LVTT);
11a8e778	116	apic_write(APIC_LVTT, v \| APIC_LVT_MASKED);
1da177e4	117	v = apic_read(APIC_LVT0);
11a8e778	118	apic_write(APIC_LVT0, v \| APIC_LVT_MASKED);
1da177e4	119	v = apic_read(APIC_LVT1);
11a8e778	120	apic_write(APIC_LVT1, v \| APIC_LVT_MASKED);
1da177e4 LT	121	if (maxlvt >= 4) {
1da177e4 LT	122	v = apic_read(APIC_LVTPC);
11a8e778	123	apic_write(APIC_LVTPC, v \| APIC_LVT_MASKED);
1da177e4 LT	124	}
	125
	126	/*
	127	* Clean APIC state for other OSs:
	128	*/
11a8e778 AK	129	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	130	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	131	apic_write(APIC_LVT1, APIC_LVT_MASKED);
1da177e4	132	if (maxlvt >= 3)
11a8e778	133	apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1da177e4	134	if (maxlvt >= 4)
11a8e778	135	apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1da177e4	136	v = GET_APIC_VERSION(apic_read(APIC_LVR));
5a40b7c2 AK	137	apic_write(APIC_ESR, 0);
5a40b7c2 AK	138	apic_read(APIC_ESR);
1da177e4 LT	139	}
1da177e4 LT	140
208fb931	141	void disconnect_bsp_APIC(int virt_wire_setup)
1da177e4	142	{
a8fcf1a2 AK	143	/* Go back to Virtual Wire compatibility mode */
a8fcf1a2 AK	144	unsigned long value;
208fb931	145
a8fcf1a2 AK	146	/* For the spurious interrupt use vector F, and enable it */
	147	value = apic_read(APIC_SPIV);
	148	value &= ~APIC_VECTOR_MASK;
	149	value \|= APIC_SPIV_APIC_ENABLED;
	150	value \|= 0xf;
	151	apic_write(APIC_SPIV, value);
	152
	153	if (!virt_wire_setup) {
	154	/* For LVT0 make it edge triggered, active high, external and enabled */
	155	value = apic_read(APIC_LVT0);
	156	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
208fb931	157	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
a8fcf1a2	158	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED );
208fb931	159	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
a8fcf1a2 AK	160	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
	161	apic_write(APIC_LVT0, value);
	162	} else {
	163	/* Disable LVT0 */
	164	apic_write(APIC_LVT0, APIC_LVT_MASKED);
208fb931	165	}
a8fcf1a2 AK	166
	167	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	168	value = apic_read(APIC_LVT1);
	169	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
	170	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
	171	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED);
	172	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
	173	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	174	apic_write(APIC_LVT1, value);
1da177e4 LT	175	}
	176
	177	void disable_local_APIC(void)
	178	{
	179	unsigned int value;
	180
	181	clear_local_APIC();
	182
	183	/*
	184	* Disable APIC (implies clearing of registers
	185	* for 82489DX!).
	186	*/
	187	value = apic_read(APIC_SPIV);
	188	value &= ~APIC_SPIV_APIC_ENABLED;
11a8e778	189	apic_write(APIC_SPIV, value);
1da177e4 LT	190	}
	191
	192	/*
	193	* This is to verify that we're looking at a real local APIC.
	194	* Check these against your board if the CPUs aren't getting
	195	* started for no apparent reason.
	196	*/
	197	int __init verify_local_APIC(void)
	198	{
	199	unsigned int reg0, reg1;
	200
	201	/*
	202	* The version register is read-only in a real APIC.
	203	*/
	204	reg0 = apic_read(APIC_LVR);
	205	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	206	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	207	reg1 = apic_read(APIC_LVR);
	208	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
	209
	210	/*
	211	* The two version reads above should print the same
	212	* numbers. If the second one is different, then we
	213	* poke at a non-APIC.
	214	*/
	215	if (reg1 != reg0)
	216	return 0;
	217
	218	/*
	219	* Check if the version looks reasonably.
	220	*/
	221	reg1 = GET_APIC_VERSION(reg0);
	222	if (reg1 == 0x00 \|\| reg1 == 0xff)
	223	return 0;
	224	reg1 = get_maxlvt();
	225	if (reg1 < 0x02 \|\| reg1 == 0xff)
	226	return 0;
	227
	228	/*
	229	* The ID register is read/write in a real APIC.
	230	*/
	231	reg0 = apic_read(APIC_ID);
	232	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	233	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	234	reg1 = apic_read(APIC_ID);
	235	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	236	apic_write(APIC_ID, reg0);
	237	if (reg1 != (reg0 ^ APIC_ID_MASK))
	238	return 0;
	239
	240	/*
	241	* The next two are just to see if we have sane values.
	242	* They're only really relevant if we're in Virtual Wire
	243	* compatibility mode, but most boxes are anymore.
	244	*/
	245	reg0 = apic_read(APIC_LVT0);
	246	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	247	reg1 = apic_read(APIC_LVT1);
	248	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
	249
	250	return 1;
	251	}
	252
	253	void __init sync_Arb_IDs(void)
254	{
255	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
256	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
257	if (ver >= 0x14) /* P4 or higher */
258	return;
259
260	/*
261	* Wait for idle.
262	*/
263	apic_wait_icr_idle();
264
265	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
11a8e778	266	apic_write(APIC_ICR, APIC_DEST_ALLINC \| APIC_INT_LEVELTRIG
1da177e4 LT	267	\| APIC_DM_INIT);
	268	}
	269
1da177e4 LT	270	/*
	271	* An initial setup of the virtual wire mode.
	272	*/
	273	void __init init_bsp_APIC(void)
	274	{
11a8e778	275	unsigned int value;
1da177e4 LT	276
	277	/*
	278	* Don't do the setup now if we have a SMP BIOS as the
	279	* through-I/O-APIC virtual wire mode might be active.
	280	*/
	281	if (smp_found_config \|\| !cpu_has_apic)
	282	return;
	283
	284	value = apic_read(APIC_LVR);
1da177e4 LT	285
	286	/*
	287	* Do not trust the local APIC being empty at bootup.
	288	*/
	289	clear_local_APIC();
	290
	291	/*
	292	* Enable APIC.
	293	*/
	294	value = apic_read(APIC_SPIV);
	295	value &= ~APIC_VECTOR_MASK;
	296	value \|= APIC_SPIV_APIC_ENABLED;
	297	value \|= APIC_SPIV_FOCUS_DISABLED;
	298	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	299	apic_write(APIC_SPIV, value);
1da177e4 LT	300
	301	/*
	302	* Set up the virtual wire mode.
	303	*/
11a8e778	304	apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4	305	value = APIC_DM_NMI;
11a8e778	306	apic_write(APIC_LVT1, value);
1da177e4 LT	307	}
1da177e4 LT	308
e6982c67	309	void __cpuinit setup_local_APIC (void)
1da177e4	310	{
11a8e778	311	unsigned int value, maxlvt;
da7ed9f9	312	int i, j;
1da177e4	313
1da177e4	314	value = apic_read(APIC_LVR);
1da177e4	315
fe7414a2	316	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
1da177e4 LT	317
	318	/*
	319	* Double-check whether this APIC is really registered.
	320	* This is meaningless in clustered apic mode, so we skip it.
	321	*/
	322	if (!apic_id_registered())
	323	BUG();
	324
	325	/*
	326	* Intel recommends to set DFR, LDR and TPR before enabling
	327	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	328	* document number 292116). So here it goes...
	329	*/
	330	init_apic_ldr();
	331
	332	/*
	333	* Set Task Priority to 'accept all'. We never change this
	334	* later on.
	335	*/
	336	value = apic_read(APIC_TASKPRI);
	337	value &= ~APIC_TPRI_MASK;
11a8e778	338	apic_write(APIC_TASKPRI, value);
1da177e4	339
da7ed9f9 VG	340	/*
	341	* After a crash, we no longer service the interrupts and a pending
	342	* interrupt from previous kernel might still have ISR bit set.
	343	*
	344	* Most probably by now CPU has serviced that pending interrupt and
	345	* it might not have done the ack_APIC_irq() because it thought,
	346	* interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	347	* does not clear the ISR bit and cpu thinks it has already serivced
	348	* the interrupt. Hence a vector might get locked. It was noticed
	349	* for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	350	*/
	351	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
	352	value = apic_read(APIC_ISR + i*0x10);
	353	for (j = 31; j >= 0; j--) {
	354	if (value & (1<<j))
	355	ack_APIC_irq();
	356	}
	357	}
	358
1da177e4 LT	359	/*
	360	* Now that we are all set up, enable the APIC
	361	*/
	362	value = apic_read(APIC_SPIV);
	363	value &= ~APIC_VECTOR_MASK;
	364	/*
	365	* Enable APIC
	366	*/
	367	value \|= APIC_SPIV_APIC_ENABLED;
	368
3f14c746 AK	369	/* We always use processor focus */
3f14c746 AK	370
1da177e4 LT	371	/*
	372	* Set spurious IRQ vector
	373	*/
	374	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	375	apic_write(APIC_SPIV, value);
1da177e4 LT	376
	377	/*
	378	* Set up LVT0, LVT1:
	379	*
	380	* set up through-local-APIC on the BP's LINT0. This is not
	381	* strictly necessary in pure symmetric-IO mode, but sometimes
	382	* we delegate interrupts to the 8259A.
	383	*/
	384	/*
	385	* TODO: set up through-local-APIC from through-I/O-APIC? --macro
	386	*/
	387	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
a8fcf1a2	388	if (!smp_processor_id() && !value) {
1da177e4 LT	389	value = APIC_DM_EXTINT;
	390	apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	391	} else {
	392	value = APIC_DM_EXTINT \| APIC_LVT_MASKED;
	393	apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	394	}
11a8e778	395	apic_write(APIC_LVT0, value);
1da177e4 LT	396
	397	/*
	398	* only the BP should see the LINT1 NMI signal, obviously.
	399	*/
	400	if (!smp_processor_id())
	401	value = APIC_DM_NMI;
	402	else
	403	value = APIC_DM_NMI \| APIC_LVT_MASKED;
11a8e778	404	apic_write(APIC_LVT1, value);
1da177e4	405
61c11341	406	{
1da177e4 LT	407	unsigned oldvalue;
1da177e4 LT	408	maxlvt = get_maxlvt();
1da177e4 LT	409	oldvalue = apic_read(APIC_ESR);
1da177e4 LT	410	value = ERROR_APIC_VECTOR; // enables sending errors
11a8e778	411	apic_write(APIC_LVTERR, value);
1da177e4 LT	412	/*
	413	* spec says clear errors after enabling vector.
	414	*/
	415	if (maxlvt > 3)
	416	apic_write(APIC_ESR, 0);
	417	value = apic_read(APIC_ESR);
	418	if (value != oldvalue)
	419	apic_printk(APIC_VERBOSE,
	420	"ESR value after enabling vector: %08x, after %08x\n",
	421	oldvalue, value);
1da177e4 LT	422	}
	423
	424	nmi_watchdog_default();
f2802e7f	425	setup_apic_nmi_watchdog(NULL);
1da177e4 LT	426	apic_pm_activate();
	427	}
	428
	429	#ifdef CONFIG_PM
	430
	431	static struct {
	432	/* 'active' is true if the local APIC was enabled by us and
	433	not the BIOS; this signifies that we are also responsible
	434	for disabling it before entering apm/acpi suspend */
	435	int active;
	436	/* r/w apic fields */
	437	unsigned int apic_id;
	438	unsigned int apic_taskpri;
	439	unsigned int apic_ldr;
	440	unsigned int apic_dfr;
	441	unsigned int apic_spiv;
	442	unsigned int apic_lvtt;
	443	unsigned int apic_lvtpc;
	444	unsigned int apic_lvt0;
	445	unsigned int apic_lvt1;
	446	unsigned int apic_lvterr;
	447	unsigned int apic_tmict;
	448	unsigned int apic_tdcr;
	449	unsigned int apic_thmr;
	450	} apic_pm_state;
	451
0b9c33a7	452	static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	453	{
	454	unsigned long flags;
	455
	456	if (!apic_pm_state.active)
	457	return 0;
	458
	459	apic_pm_state.apic_id = apic_read(APIC_ID);
	460	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	461	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	462	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	463	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	464	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	465	apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	466	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	467	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	468	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	469	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	470	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
	471	apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);